/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Global Instruction Selector for the RISCV target                           *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_GLOBALISEL_PREDICATE_BITSET
const unsigned MAX_SUBTARGET_PREDICATES = 35;
using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET

#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
  mutable MatcherState State;
  typedef ComplexRendererFns(RISCVInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
  typedef void(RISCVInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
  static RISCVInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
  static RISCVInstructionSelector::CustomRendererFn CustomRenderers[];
  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
  const int64_t *getMatchTable() const override;
  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const std::array<const MachineOperand *, 3> &Operands) const override;
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL

#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
, State(0),
ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT

#ifdef GET_GLOBALISEL_IMPL
// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
  Feature_HasStdExtMBit = 13,
  Feature_HasStdExtMOrZmmulBit = 12,
  Feature_HasStdExtABit = 15,
  Feature_HasStdExtFBit = 4,
  Feature_HasStdExtDBit = 5,
  Feature_HasStdExtZfhminBit = 17,
  Feature_HasStdExtZfhBit = 7,
  Feature_NoStdExtZfhBit = 18,
  Feature_HasStdExtZfhOrZfhminBit = 16,
  Feature_HasStdExtCBit = 9,
  Feature_HasStdExtZbaBit = 25,
  Feature_NotHasStdExtZbaBit = 11,
  Feature_HasStdExtZbbBit = 23,
  Feature_HasStdExtZbcBit = 27,
  Feature_HasStdExtZbsBit = 22,
  Feature_HasStdExtZbkbBit = 24,
  Feature_HasStdExtZbkxBit = 28,
  Feature_HasStdExtZbbOrZbkbBit = 21,
  Feature_HasStdExtZbcOrZbkcBit = 26,
  Feature_HasStdExtZkndBit = 29,
  Feature_HasStdExtZkneBit = 31,
  Feature_HasStdExtZkndOrZkneBit = 30,
  Feature_HasStdExtZknhBit = 32,
  Feature_HasStdExtZksedBit = 33,
  Feature_HasStdExtZkshBit = 34,
  Feature_HasVInstructionsBit = 6,
  Feature_HasVInstructionsAnyFBit = 8,
  Feature_HasVendorXVentanaCondOpsBit = 19,
  Feature_HasVendorXTHeadVdotBit = 20,
  Feature_IsRV64Bit = 3,
  Feature_IsRV32Bit = 2,
  Feature_HasShortForwardBranchOptBit = 0,
  Feature_NoShortForwardBranchOptBit = 1,
  Feature_HasAtomicLdStBit = 14,
  Feature_OptForMinSizeBit = 10,
};

PredicateBitset RISCVInstructionSelector::
computeAvailableModuleFeatures(const RISCVSubtarget *Subtarget) const {
  PredicateBitset Features;
  if (Subtarget->hasStdExtM())
    Features.set(Feature_HasStdExtMBit);
  if (Subtarget->hasStdExtM() || Subtarget->hasStdExtZmmul())
    Features.set(Feature_HasStdExtMOrZmmulBit);
  if (Subtarget->hasStdExtA())
    Features.set(Feature_HasStdExtABit);
  if (Subtarget->hasStdExtF())
    Features.set(Feature_HasStdExtFBit);
  if (Subtarget->hasStdExtD())
    Features.set(Feature_HasStdExtDBit);
  if (Subtarget->hasStdExtZfhmin())
    Features.set(Feature_HasStdExtZfhminBit);
  if (Subtarget->hasStdExtZfh())
    Features.set(Feature_HasStdExtZfhBit);
  if (!Subtarget->hasStdExtZfh())
    Features.set(Feature_NoStdExtZfhBit);
  if (Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZfhmin())
    Features.set(Feature_HasStdExtZfhOrZfhminBit);
  if (Subtarget->hasStdExtC())
    Features.set(Feature_HasStdExtCBit);
  if (Subtarget->hasStdExtZba())
    Features.set(Feature_HasStdExtZbaBit);
  if (!Subtarget->hasStdExtZba())
    Features.set(Feature_NotHasStdExtZbaBit);
  if (Subtarget->hasStdExtZbb())
    Features.set(Feature_HasStdExtZbbBit);
  if (Subtarget->hasStdExtZbc())
    Features.set(Feature_HasStdExtZbcBit);
  if (Subtarget->hasStdExtZbs())
    Features.set(Feature_HasStdExtZbsBit);
  if (Subtarget->hasStdExtZbkb())
    Features.set(Feature_HasStdExtZbkbBit);
  if (Subtarget->hasStdExtZbkx())
    Features.set(Feature_HasStdExtZbkxBit);
  if (Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb())
    Features.set(Feature_HasStdExtZbbOrZbkbBit);
  if (Subtarget->hasStdExtZbc() || Subtarget->hasStdExtZbkc())
    Features.set(Feature_HasStdExtZbcOrZbkcBit);
  if (Subtarget->hasStdExtZknd())
    Features.set(Feature_HasStdExtZkndBit);
  if (Subtarget->hasStdExtZkne())
    Features.set(Feature_HasStdExtZkneBit);
  if (Subtarget->hasStdExtZknd() || Subtarget->hasStdExtZkne())
    Features.set(Feature_HasStdExtZkndOrZkneBit);
  if (Subtarget->hasStdExtZknh())
    Features.set(Feature_HasStdExtZknhBit);
  if (Subtarget->hasStdExtZksed())
    Features.set(Feature_HasStdExtZksedBit);
  if (Subtarget->hasStdExtZksh())
    Features.set(Feature_HasStdExtZkshBit);
  if (Subtarget->hasVInstructions())
    Features.set(Feature_HasVInstructionsBit);
  if (Subtarget->hasVInstructionsAnyF())
    Features.set(Feature_HasVInstructionsAnyFBit);
  if (Subtarget->hasVendorXVentanaCondOps())
    Features.set(Feature_HasVendorXVentanaCondOpsBit);
  if (Subtarget->hasVendorXTHeadVdot())
    Features.set(Feature_HasVendorXTHeadVdotBit);
  if (Subtarget->is64Bit())
    Features.set(Feature_IsRV64Bit);
  if (!Subtarget->is64Bit())
    Features.set(Feature_IsRV32Bit);
  if (Subtarget->hasShortForwardBranchOpt())
    Features.set(Feature_HasShortForwardBranchOptBit);
  if (!Subtarget->hasShortForwardBranchOpt())
    Features.set(Feature_NoShortForwardBranchOptBit);
  if (Subtarget->hasStdExtA() || Subtarget->hasForcedAtomics())
    Features.set(Feature_HasAtomicLdStBit);
  if (MF ? MF->getFunction().hasMinSize() : false)
    Features.set(Feature_OptForMinSizeBit);
  return Features;
}

void RISCVInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
  AvailableFunctionFeatures = computeAvailableFunctionFeatures((const RISCVSubtarget *)&MF.getSubtarget(), &MF);
}
PredicateBitset RISCVInstructionSelector::
computeAvailableFunctionFeatures(const RISCVSubtarget *Subtarget, const MachineFunction *MF) const {
  PredicateBitset Features;
  return Features;
}

// LLT Objects.
enum {
  GILLT_s16,
  GILLT_s32,
  GILLT_s64,
  GILLT_nxv1s1,
  GILLT_nxv1s8,
  GILLT_nxv1s16,
  GILLT_nxv1s32,
  GILLT_nxv1s64,
  GILLT_nxv2s1,
  GILLT_nxv2s8,
  GILLT_nxv2s16,
  GILLT_nxv2s32,
  GILLT_nxv2s64,
  GILLT_nxv4s1,
  GILLT_nxv4s8,
  GILLT_nxv4s16,
  GILLT_nxv4s32,
  GILLT_nxv4s64,
  GILLT_nxv8s1,
  GILLT_nxv8s8,
  GILLT_nxv8s16,
  GILLT_nxv8s32,
  GILLT_nxv8s64,
  GILLT_nxv16s1,
  GILLT_nxv16s8,
  GILLT_nxv16s16,
  GILLT_nxv16s32,
  GILLT_nxv32s1,
  GILLT_nxv32s8,
  GILLT_nxv32s16,
  GILLT_nxv64s1,
  GILLT_nxv64s8,
};
const static size_t NumTypeObjects = 32;
const static LLT TypeObjects[] = {
  LLT::scalar(16),
  LLT::scalar(32),
  LLT::scalar(64),
  LLT::vector(ElementCount::getScalable(1), 1),
  LLT::vector(ElementCount::getScalable(1), 8),
  LLT::vector(ElementCount::getScalable(1), 16),
  LLT::vector(ElementCount::getScalable(1), 32),
  LLT::vector(ElementCount::getScalable(1), 64),
  LLT::vector(ElementCount::getScalable(2), 1),
  LLT::vector(ElementCount::getScalable(2), 8),
  LLT::vector(ElementCount::getScalable(2), 16),
  LLT::vector(ElementCount::getScalable(2), 32),
  LLT::vector(ElementCount::getScalable(2), 64),
  LLT::vector(ElementCount::getScalable(4), 1),
  LLT::vector(ElementCount::getScalable(4), 8),
  LLT::vector(ElementCount::getScalable(4), 16),
  LLT::vector(ElementCount::getScalable(4), 32),
  LLT::vector(ElementCount::getScalable(4), 64),
  LLT::vector(ElementCount::getScalable(8), 1),
  LLT::vector(ElementCount::getScalable(8), 8),
  LLT::vector(ElementCount::getScalable(8), 16),
  LLT::vector(ElementCount::getScalable(8), 32),
  LLT::vector(ElementCount::getScalable(8), 64),
  LLT::vector(ElementCount::getScalable(16), 1),
  LLT::vector(ElementCount::getScalable(16), 8),
  LLT::vector(ElementCount::getScalable(16), 16),
  LLT::vector(ElementCount::getScalable(16), 32),
  LLT::vector(ElementCount::getScalable(32), 1),
  LLT::vector(ElementCount::getScalable(32), 8),
  LLT::vector(ElementCount::getScalable(32), 16),
  LLT::vector(ElementCount::getScalable(64), 1),
  LLT::vector(ElementCount::getScalable(64), 8),
};

// Feature bitsets.
enum {
  GIFBS_Invalid,
  GIFBS_HasStdExtA,
  GIFBS_HasStdExtD,
  GIFBS_HasStdExtF,
  GIFBS_HasStdExtM,
  GIFBS_HasStdExtMOrZmmul,
  GIFBS_HasStdExtZbb,
  GIFBS_HasStdExtZbbOrZbkb,
  GIFBS_HasStdExtZbc,
  GIFBS_HasStdExtZbcOrZbkc,
  GIFBS_HasStdExtZbkx,
  GIFBS_HasStdExtZbs,
  GIFBS_HasStdExtZfh,
  GIFBS_HasStdExtZfhOrZfhmin,
  GIFBS_HasStdExtZknh,
  GIFBS_HasStdExtZksed,
  GIFBS_HasStdExtZksh,
  GIFBS_HasVInstructions,
  GIFBS_HasVInstructionsAnyF,
  GIFBS_IsRV64,
  GIFBS_HasStdExtA_IsRV64,
  GIFBS_HasStdExtD_HasStdExtZfhOrZfhmin,
  GIFBS_HasStdExtD_IsRV32,
  GIFBS_HasStdExtD_IsRV64,
  GIFBS_HasStdExtF_IsRV32,
  GIFBS_HasStdExtZba_IsRV64,
  GIFBS_HasStdExtZbb_IsRV32,
  GIFBS_HasStdExtZbb_IsRV64,
  GIFBS_HasStdExtZbbOrZbkb_IsRV32,
  GIFBS_HasStdExtZbbOrZbkb_IsRV64,
  GIFBS_HasStdExtZknd_IsRV32,
  GIFBS_HasStdExtZknd_IsRV64,
  GIFBS_HasStdExtZkndOrZkne_IsRV64,
  GIFBS_HasStdExtZkne_IsRV32,
  GIFBS_HasStdExtZkne_IsRV64,
  GIFBS_HasStdExtZknh_IsRV32,
  GIFBS_HasStdExtZknh_IsRV64,
  GIFBS_HasVendorXVentanaCondOps_IsRV64,
  GIFBS_IsRV64_NotHasStdExtZba,
  GIFBS_HasStdExtMOrZmmul_IsRV64_NotHasStdExtZba,
};
const static PredicateBitset FeatureBitsets[] {
  {}, // GIFBS_Invalid
  {Feature_HasStdExtABit, },
  {Feature_HasStdExtDBit, },
  {Feature_HasStdExtFBit, },
  {Feature_HasStdExtMBit, },
  {Feature_HasStdExtMOrZmmulBit, },
  {Feature_HasStdExtZbbBit, },
  {Feature_HasStdExtZbbOrZbkbBit, },
  {Feature_HasStdExtZbcBit, },
  {Feature_HasStdExtZbcOrZbkcBit, },
  {Feature_HasStdExtZbkxBit, },
  {Feature_HasStdExtZbsBit, },
  {Feature_HasStdExtZfhBit, },
  {Feature_HasStdExtZfhOrZfhminBit, },
  {Feature_HasStdExtZknhBit, },
  {Feature_HasStdExtZksedBit, },
  {Feature_HasStdExtZkshBit, },
  {Feature_HasVInstructionsBit, },
  {Feature_HasVInstructionsAnyFBit, },
  {Feature_IsRV64Bit, },
  {Feature_HasStdExtABit, Feature_IsRV64Bit, },
  {Feature_HasStdExtDBit, Feature_HasStdExtZfhOrZfhminBit, },
  {Feature_HasStdExtDBit, Feature_IsRV32Bit, },
  {Feature_HasStdExtDBit, Feature_IsRV64Bit, },
  {Feature_HasStdExtFBit, Feature_IsRV32Bit, },
  {Feature_HasStdExtZbaBit, Feature_IsRV64Bit, },
  {Feature_HasStdExtZbbBit, Feature_IsRV32Bit, },
  {Feature_HasStdExtZbbBit, Feature_IsRV64Bit, },
  {Feature_HasStdExtZbbOrZbkbBit, Feature_IsRV32Bit, },
  {Feature_HasStdExtZbbOrZbkbBit, Feature_IsRV64Bit, },
  {Feature_HasStdExtZkndBit, Feature_IsRV32Bit, },
  {Feature_HasStdExtZkndBit, Feature_IsRV64Bit, },
  {Feature_HasStdExtZkndOrZkneBit, Feature_IsRV64Bit, },
  {Feature_HasStdExtZkneBit, Feature_IsRV32Bit, },
  {Feature_HasStdExtZkneBit, Feature_IsRV64Bit, },
  {Feature_HasStdExtZknhBit, Feature_IsRV32Bit, },
  {Feature_HasStdExtZknhBit, Feature_IsRV64Bit, },
  {Feature_HasVendorXVentanaCondOpsBit, Feature_IsRV64Bit, },
  {Feature_IsRV64Bit, Feature_NotHasStdExtZbaBit, },
  {Feature_HasStdExtMOrZmmulBit, Feature_IsRV64Bit, Feature_NotHasStdExtZbaBit, },
};

// ComplexPattern predicates.
enum {
  GICP_Invalid,
};
// See constructor for table contents

// PatFrag predicates.
enum {
  GIPFP_I64_Predicate_BCLRMask = GIPFP_I64_Invalid + 1,
  GIPFP_I64_Predicate_SingleBitSetMask,
  GIPFP_I64_Predicate_byteselect,
  GIPFP_I64_Predicate_c_lui_imm,
  GIPFP_I64_Predicate_immzero,
  GIPFP_I64_Predicate_rnum,
  GIPFP_I64_Predicate_shfl_uimm,
  GIPFP_I64_Predicate_simm10_lsb0000nonzero,
  GIPFP_I64_Predicate_simm12,
  GIPFP_I64_Predicate_simm12_lsb0,
  GIPFP_I64_Predicate_simm12_lsb00000,
  GIPFP_I64_Predicate_simm12_no6,
  GIPFP_I64_Predicate_simm12_plus1,
  GIPFP_I64_Predicate_simm5,
  GIPFP_I64_Predicate_simm5_plus1,
  GIPFP_I64_Predicate_simm5_plus1_nonzero,
  GIPFP_I64_Predicate_simm6,
  GIPFP_I64_Predicate_simm6nonzero,
  GIPFP_I64_Predicate_simm9_lsb0,
  GIPFP_I64_Predicate_u32simm12,
  GIPFP_I64_Predicate_uimm10_lsb00nonzero,
  GIPFP_I64_Predicate_uimm5,
  GIPFP_I64_Predicate_uimm6gt32,
  GIPFP_I64_Predicate_uimm7_lsb00,
  GIPFP_I64_Predicate_uimm8_lsb00,
  GIPFP_I64_Predicate_uimm8_lsb000,
  GIPFP_I64_Predicate_uimm9_lsb000,
  GIPFP_I64_Predicate_uimmlog2xlen,
  GIPFP_I64_Predicate_uimmlog2xlennonzero,
};
bool RISCVInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
  switch (PredicateID) {
  case GIPFP_I64_Predicate_BCLRMask: {
    
  if (Subtarget->is64Bit())
    return !isInt<12>(Imm) && isPowerOf2_64(~Imm);
  return !isInt<12>(Imm) && isPowerOf2_32(~Imm);

    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_SingleBitSetMask: {
    
  if (Subtarget->is64Bit())
    return !isInt<12>(Imm) && isPowerOf2_64(Imm);
  return !isInt<12>(Imm) && isPowerOf2_32(Imm);

    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_byteselect: {
    return isUInt<2>(Imm);
    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_c_lui_imm: {
    return (Imm != 0) &&
                                 (isUInt<5>(Imm) ||
                                  (Imm >= 0xfffe0 && Imm <= 0xfffff));
    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_immzero: {
    return (Imm == 0);
    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_rnum: {
    return (Imm >= 0 && Imm <= 10);
    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_shfl_uimm: {
    
  if (Subtarget->is64Bit())
    return isUInt<5>(Imm);
  return isUInt<4>(Imm);

    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_simm10_lsb0000nonzero: {
    return (Imm != 0) && isShiftedInt<6, 4>(Imm);
    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_simm12: {
    return isInt<12>(Imm);
    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_simm12_lsb0: {
    return isShiftedInt<11, 1>(Imm);
    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_simm12_lsb00000: {
    return isShiftedInt<7, 5>(Imm);
    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_simm12_no6: {
    
  return isInt<12>(Imm) && !isInt<6>(Imm) && isInt<12>(-Imm);
    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_simm12_plus1: {
    return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048;
    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_simm5: {
    return isInt<5>(Imm);
    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_simm5_plus1: {
    return (isInt<5>(Imm) && Imm != -16) || Imm == 16;
    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_simm5_plus1_nonzero: {
    return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16);
    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_simm6: {
    return isInt<6>(Imm);
    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_simm6nonzero: {
    return (Imm != 0) && isInt<6>(Imm);
    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_simm9_lsb0: {
    return isShiftedInt<8, 1>(Imm);
    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_u32simm12: {
    
  return isUInt<32>(Imm) && isInt<12>(SignExtend64<32>(Imm));

    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_uimm10_lsb00nonzero: {
    return isShiftedUInt<8, 2>(Imm) && (Imm != 0);
    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_uimm5: {
    return isUInt<5>(Imm);
    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_uimm6gt32: {
    
  return isUInt<6>(Imm) && Imm > 32;

    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_uimm7_lsb00: {
    return isShiftedUInt<5, 2>(Imm);
    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_uimm8_lsb00: {
    return isShiftedUInt<6, 2>(Imm);
    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_uimm8_lsb000: {
    return isShiftedUInt<5, 3>(Imm);
    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_uimm9_lsb000: {
    return isShiftedUInt<6, 3>(Imm);
    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_uimmlog2xlen: {
    
  if (Subtarget->is64Bit())
    return isUInt<6>(Imm);
  return isUInt<5>(Imm);

    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  case GIPFP_I64_Predicate_uimmlog2xlennonzero: {
    
  if (Subtarget->is64Bit())
    return isUInt<6>(Imm) && (Imm != 0);
  return isUInt<5>(Imm) && (Imm != 0);

    llvm_unreachable("ImmediateCode should have returned");
    return false;
  }
  }
  llvm_unreachable("Unknown predicate");
  return false;
}
bool RISCVInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
  llvm_unreachable("Unknown predicate");
  return false;
}
bool RISCVInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
  llvm_unreachable("Unknown predicate");
  return false;
}
bool RISCVInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const std::array<const MachineOperand *, 3> &Operands) const {
  const MachineFunction &MF = *MI.getParent()->getParent();
  const MachineRegisterInfo &MRI = MF.getRegInfo();
  (void)MRI;
  llvm_unreachable("Unknown predicate");
  return false;
}

RISCVInstructionSelector::ComplexMatcherMemFn
RISCVInstructionSelector::ComplexPredicateFns[] = {
  nullptr, // GICP_Invalid
};

// Custom renderers.
enum {
  GICR_Invalid,
};
RISCVInstructionSelector::CustomRendererFn
RISCVInstructionSelector::CustomRenderers[] = {
  nullptr, // GICR_Invalid
};

bool RISCVInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
  MachineFunction &MF = *I.getParent()->getParent();
  MachineRegisterInfo &MRI = MF.getRegInfo();
  const PredicateBitset AvailableFeatures = getAvailableFeatures();
  NewMIVector OutMIs;
  State.MIs.clear();
  State.MIs.push_back(&I);

  if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
    return true;
  }

  return false;
}

const int64_t *RISCVInstructionSelector::getMatchTable() const {
  constexpr static int64_t MatchTable0[] = {
    GIM_SwitchOpcode, /*MI*/0, /*[*/46, 227, /*)*//*default:*//*Label 73*/ 151124,
    /*TargetOpcode::G_ADD*//*Label 0*/ 186,
    /*TargetOpcode::G_SUB*//*Label 1*/ 2204,
    /*TargetOpcode::G_MUL*//*Label 2*/ 4150,
    /*TargetOpcode::G_SDIV*//*Label 3*/ 6215,
    /*TargetOpcode::G_UDIV*//*Label 4*/ 8165,
    /*TargetOpcode::G_SREM*//*Label 5*/ 10115,
    /*TargetOpcode::G_UREM*//*Label 6*/ 12065, 0, 0,
    /*TargetOpcode::G_AND*//*Label 7*/ 14015,
    /*TargetOpcode::G_OR*//*Label 8*/ 17311,
    /*TargetOpcode::G_XOR*//*Label 9*/ 20137, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    /*TargetOpcode::G_BITCAST*//*Label 10*/ 23069, 0, 0, 0, 0, 0, 0,
    /*TargetOpcode::G_READCYCLECOUNTER*//*Label 11*/ 23170,
    /*TargetOpcode::G_LOAD*//*Label 12*/ 23202, 0, 0, 0, 0, 0,
    /*TargetOpcode::G_STORE*//*Label 13*/ 25953, 0, 0,
    /*TargetOpcode::G_ATOMIC_CMPXCHG*//*Label 14*/ 28588,
    /*TargetOpcode::G_ATOMICRMW_XCHG*//*Label 15*/ 30001,
    /*TargetOpcode::G_ATOMICRMW_ADD*//*Label 16*/ 30706,
    /*TargetOpcode::G_ATOMICRMW_SUB*//*Label 17*/ 31411,
    /*TargetOpcode::G_ATOMICRMW_AND*//*Label 18*/ 32485,
    /*TargetOpcode::G_ATOMICRMW_NAND*//*Label 19*/ 33190,
    /*TargetOpcode::G_ATOMICRMW_OR*//*Label 20*/ 34114,
    /*TargetOpcode::G_ATOMICRMW_XOR*//*Label 21*/ 34819,
    /*TargetOpcode::G_ATOMICRMW_MAX*//*Label 22*/ 35524,
    /*TargetOpcode::G_ATOMICRMW_MIN*//*Label 23*/ 36229,
    /*TargetOpcode::G_ATOMICRMW_UMAX*//*Label 24*/ 36934,
    /*TargetOpcode::G_ATOMICRMW_UMIN*//*Label 25*/ 37639, 0, 0, 0, 0, 0, 0,
    /*TargetOpcode::G_FENCE*//*Label 26*/ 38344, 0, 0, 0,
    /*TargetOpcode::G_INTRINSIC*//*Label 27*/ 38527,
    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 28*/ 40810,
    /*TargetOpcode::G_ANYEXT*//*Label 29*/ 42545, 0, 0, 0, 0, 0,
    /*TargetOpcode::G_SEXT*//*Label 30*/ 44666, 0,
    /*TargetOpcode::G_ZEXT*//*Label 31*/ 46787,
    /*TargetOpcode::G_SHL*//*Label 32*/ 48908,
    /*TargetOpcode::G_LSHR*//*Label 33*/ 50957,
    /*TargetOpcode::G_ASHR*//*Label 34*/ 53006, 0, 0,
    /*TargetOpcode::G_ROTR*//*Label 35*/ 54992, 0,
    /*TargetOpcode::G_ICMP*//*Label 36*/ 55105,
    /*TargetOpcode::G_FCMP*//*Label 37*/ 79640,
    /*TargetOpcode::G_SELECT*//*Label 38*/ 86077, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    /*TargetOpcode::G_UMULH*//*Label 39*/ 87691,
    /*TargetOpcode::G_SMULH*//*Label 40*/ 89641,
    /*TargetOpcode::G_UADDSAT*//*Label 41*/ 91591,
    /*TargetOpcode::G_SADDSAT*//*Label 42*/ 93474,
    /*TargetOpcode::G_USUBSAT*//*Label 43*/ 95357,
    /*TargetOpcode::G_SSUBSAT*//*Label 44*/ 97240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    /*TargetOpcode::G_FADD*//*Label 45*/ 99123,
    /*TargetOpcode::G_FSUB*//*Label 46*/ 100415,
    /*TargetOpcode::G_FMUL*//*Label 47*/ 101707,
    /*TargetOpcode::G_FMA*//*Label 48*/ 102999, 0,
    /*TargetOpcode::G_FDIV*//*Label 49*/ 117622, 0, 0, 0, 0, 0, 0, 0, 0,
    /*TargetOpcode::G_FNEG*//*Label 50*/ 118914,
    /*TargetOpcode::G_FPEXT*//*Label 51*/ 120086,
    /*TargetOpcode::G_FPTRUNC*//*Label 52*/ 120166,
    /*TargetOpcode::G_FPTOSI*//*Label 53*/ 121014,
    /*TargetOpcode::G_FPTOUI*//*Label 54*/ 124044,
    /*TargetOpcode::G_SITOFP*//*Label 55*/ 127074,
    /*TargetOpcode::G_UITOFP*//*Label 56*/ 130147,
    /*TargetOpcode::G_FABS*//*Label 57*/ 133220,
    /*TargetOpcode::G_FCOPYSIGN*//*Label 58*/ 134392, 0, 0,
    /*TargetOpcode::G_FMINNUM*//*Label 59*/ 137154,
    /*TargetOpcode::G_FMAXNUM*//*Label 60*/ 138446, 0, 0, 0, 0, 0, 0,
    /*TargetOpcode::G_SMIN*//*Label 61*/ 139738,
    /*TargetOpcode::G_SMAX*//*Label 62*/ 141688,
    /*TargetOpcode::G_UMIN*//*Label 63*/ 143638,
    /*TargetOpcode::G_UMAX*//*Label 64*/ 145588, 0, 0, 0,
    /*TargetOpcode::G_BR*//*Label 65*/ 147538, 0, 0, 0, 0,
    /*TargetOpcode::G_CTTZ*//*Label 66*/ 147551, 0,
    /*TargetOpcode::G_CTLZ*//*Label 67*/ 147608, 0,
    /*TargetOpcode::G_CTPOP*//*Label 68*/ 147665,
    /*TargetOpcode::G_BSWAP*//*Label 69*/ 147722, 0, 0, 0, 0,
    /*TargetOpcode::G_FSQRT*//*Label 70*/ 147779, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
    /*TargetOpcode::G_STRICT_FMA*//*Label 71*/ 149022,
    /*TargetOpcode::G_STRICT_FSQRT*//*Label 72*/ 150928,
    // Label 0: @186
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 32, /*)*//*default:*//*Label 98*/ 2203,
    /*GILLT_s32*//*Label 74*/ 223,
    /*GILLT_s64*//*Label 75*/ 289, 0,
    /*GILLT_nxv1s8*//*Label 76*/ 355,
    /*GILLT_nxv1s16*//*Label 77*/ 439,
    /*GILLT_nxv1s32*//*Label 78*/ 523,
    /*GILLT_nxv1s64*//*Label 79*/ 607, 0,
    /*GILLT_nxv2s8*//*Label 80*/ 691,
    /*GILLT_nxv2s16*//*Label 81*/ 775,
    /*GILLT_nxv2s32*//*Label 82*/ 859,
    /*GILLT_nxv2s64*//*Label 83*/ 943, 0,
    /*GILLT_nxv4s8*//*Label 84*/ 1027,
    /*GILLT_nxv4s16*//*Label 85*/ 1111,
    /*GILLT_nxv4s32*//*Label 86*/ 1195,
    /*GILLT_nxv4s64*//*Label 87*/ 1279, 0,
    /*GILLT_nxv8s8*//*Label 88*/ 1363,
    /*GILLT_nxv8s16*//*Label 89*/ 1447,
    /*GILLT_nxv8s32*//*Label 90*/ 1531,
    /*GILLT_nxv8s64*//*Label 91*/ 1615, 0,
    /*GILLT_nxv16s8*//*Label 92*/ 1699,
    /*GILLT_nxv16s16*//*Label 93*/ 1783,
    /*GILLT_nxv16s32*//*Label 94*/ 1867, 0,
    /*GILLT_nxv32s8*//*Label 95*/ 1951,
    /*GILLT_nxv32s16*//*Label 96*/ 2035, 0,
    /*GILLT_nxv64s8*//*Label 97*/ 2119,
    // Label 74: @223
    GIM_Try, /*On fail goto*//*Label 99*/ 288,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_Try, /*On fail goto*//*Label 100*/ 274, // Rule ID 59830 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm)  =>  (ADDI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADDI,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59830,
        GIR_Done,
      // Label 100: @274
      GIM_Try, /*On fail goto*//*Label 101*/ 287, // Rule ID 59808 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::ADD,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59808,
        GIR_Done,
      // Label 101: @287
      GIM_Reject,
    // Label 99: @288
    GIM_Reject,
    // Label 75: @289
    GIM_Try, /*On fail goto*//*Label 102*/ 354,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_Try, /*On fail goto*//*Label 103*/ 340, // Rule ID 59829 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm)  =>  (ADDI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADDI,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59829,
        GIR_Done,
      // Label 103: @340
      GIM_Try, /*On fail goto*//*Label 104*/ 353, // Rule ID 59807 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (ADD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::ADD,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59807,
        GIR_Done,
      // Label 104: @353
      GIM_Reject,
    // Label 102: @354
    GIM_Reject,
    // Label 76: @355
    GIM_Try, /*On fail goto*//*Label 105*/ 438,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 106*/ 407, // Rule ID 54937 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVADD_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 54937,
        GIR_Done,
      // Label 106: @407
      GIM_Try, /*On fail goto*//*Label 107*/ 437, // Rule ID 54938 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVADD_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 54938,
        GIR_Done,
      // Label 107: @437
      GIM_Reject,
    // Label 105: @438
    GIM_Reject,
    // Label 77: @439
    GIM_Try, /*On fail goto*//*Label 108*/ 522,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 109*/ 491, // Rule ID 55217 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVADD_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55217,
        GIR_Done,
      // Label 109: @491
      GIM_Try, /*On fail goto*//*Label 110*/ 521, // Rule ID 55218 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVADD_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55218,
        GIR_Done,
      // Label 110: @521
      GIM_Reject,
    // Label 108: @522
    GIM_Reject,
    // Label 78: @523
    GIM_Try, /*On fail goto*//*Label 111*/ 606,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 112*/ 575, // Rule ID 55225 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVADD_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55225,
        GIR_Done,
      // Label 112: @575
      GIM_Try, /*On fail goto*//*Label 113*/ 605, // Rule ID 55226 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVADD_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55226,
        GIR_Done,
      // Label 113: @605
      GIM_Reject,
    // Label 111: @606
    GIM_Reject,
    // Label 79: @607
    GIM_Try, /*On fail goto*//*Label 114*/ 690,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 115*/ 659, // Rule ID 55241 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVADD_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55241,
        GIR_Done,
      // Label 115: @659
      GIM_Try, /*On fail goto*//*Label 116*/ 689, // Rule ID 55242 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVADD_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55242,
        GIR_Done,
      // Label 116: @689
      GIM_Reject,
    // Label 114: @690
    GIM_Reject,
    // Label 80: @691
    GIM_Try, /*On fail goto*//*Label 117*/ 774,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 118*/ 743, // Rule ID 55209 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVADD_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55209,
        GIR_Done,
      // Label 118: @743
      GIM_Try, /*On fail goto*//*Label 119*/ 773, // Rule ID 55210 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVADD_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55210,
        GIR_Done,
      // Label 119: @773
      GIM_Reject,
    // Label 117: @774
    GIM_Reject,
    // Label 81: @775
    GIM_Try, /*On fail goto*//*Label 120*/ 858,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 121*/ 827, // Rule ID 55221 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVADD_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55221,
        GIR_Done,
      // Label 121: @827
      GIM_Try, /*On fail goto*//*Label 122*/ 857, // Rule ID 55222 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVADD_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55222,
        GIR_Done,
      // Label 122: @857
      GIM_Reject,
    // Label 120: @858
    GIM_Reject,
    // Label 82: @859
    GIM_Try, /*On fail goto*//*Label 123*/ 942,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 124*/ 911, // Rule ID 55237 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVADD_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55237,
        GIR_Done,
      // Label 124: @911
      GIM_Try, /*On fail goto*//*Label 125*/ 941, // Rule ID 55238 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVADD_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55238,
        GIR_Done,
      // Label 125: @941
      GIM_Reject,
    // Label 123: @942
    GIM_Reject,
    // Label 83: @943
    GIM_Try, /*On fail goto*//*Label 126*/ 1026,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 127*/ 995, // Rule ID 55281 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVADD_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55281,
        GIR_Done,
      // Label 127: @995
      GIM_Try, /*On fail goto*//*Label 128*/ 1025, // Rule ID 55282 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVADD_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55282,
        GIR_Done,
      // Label 128: @1025
      GIM_Reject,
    // Label 126: @1026
    GIM_Reject,
    // Label 84: @1027
    GIM_Try, /*On fail goto*//*Label 129*/ 1110,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 130*/ 1079, // Rule ID 55213 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVADD_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55213,
        GIR_Done,
      // Label 130: @1079
      GIM_Try, /*On fail goto*//*Label 131*/ 1109, // Rule ID 55214 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVADD_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55214,
        GIR_Done,
      // Label 131: @1109
      GIM_Reject,
    // Label 129: @1110
    GIM_Reject,
    // Label 85: @1111
    GIM_Try, /*On fail goto*//*Label 132*/ 1194,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 133*/ 1163, // Rule ID 55233 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVADD_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55233,
        GIR_Done,
      // Label 133: @1163
      GIM_Try, /*On fail goto*//*Label 134*/ 1193, // Rule ID 55234 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVADD_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55234,
        GIR_Done,
      // Label 134: @1193
      GIM_Reject,
    // Label 132: @1194
    GIM_Reject,
    // Label 86: @1195
    GIM_Try, /*On fail goto*//*Label 135*/ 1278,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 136*/ 1247, // Rule ID 55269 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVADD_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55269,
        GIR_Done,
      // Label 136: @1247
      GIM_Try, /*On fail goto*//*Label 137*/ 1277, // Rule ID 55270 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVADD_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55270,
        GIR_Done,
      // Label 137: @1277
      GIM_Reject,
    // Label 135: @1278
    GIM_Reject,
    // Label 87: @1279
    GIM_Try, /*On fail goto*//*Label 138*/ 1362,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 139*/ 1331, // Rule ID 55285 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVADD_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55285,
        GIR_Done,
      // Label 139: @1331
      GIM_Try, /*On fail goto*//*Label 140*/ 1361, // Rule ID 55286 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVADD_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55286,
        GIR_Done,
      // Label 140: @1361
      GIM_Reject,
    // Label 138: @1362
    GIM_Reject,
    // Label 88: @1363
    GIM_Try, /*On fail goto*//*Label 141*/ 1446,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 142*/ 1415, // Rule ID 55229 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVADD_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55229,
        GIR_Done,
      // Label 142: @1415
      GIM_Try, /*On fail goto*//*Label 143*/ 1445, // Rule ID 55230 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVADD_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55230,
        GIR_Done,
      // Label 143: @1445
      GIM_Reject,
    // Label 141: @1446
    GIM_Reject,
    // Label 89: @1447
    GIM_Try, /*On fail goto*//*Label 144*/ 1530,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 145*/ 1499, // Rule ID 55257 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVADD_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55257,
        GIR_Done,
      // Label 145: @1499
      GIM_Try, /*On fail goto*//*Label 146*/ 1529, // Rule ID 55258 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVADD_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55258,
        GIR_Done,
      // Label 146: @1529
      GIM_Reject,
    // Label 144: @1530
    GIM_Reject,
    // Label 90: @1531
    GIM_Try, /*On fail goto*//*Label 147*/ 1614,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 148*/ 1583, // Rule ID 55273 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVADD_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55273,
        GIR_Done,
      // Label 148: @1583
      GIM_Try, /*On fail goto*//*Label 149*/ 1613, // Rule ID 55274 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVADD_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55274,
        GIR_Done,
      // Label 149: @1613
      GIM_Reject,
    // Label 147: @1614
    GIM_Reject,
    // Label 91: @1615
    GIM_Try, /*On fail goto*//*Label 150*/ 1698,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 151*/ 1667, // Rule ID 55289 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVADD_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55289,
        GIR_Done,
      // Label 151: @1667
      GIM_Try, /*On fail goto*//*Label 152*/ 1697, // Rule ID 55290 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVADD_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55290,
        GIR_Done,
      // Label 152: @1697
      GIM_Reject,
    // Label 150: @1698
    GIM_Reject,
    // Label 92: @1699
    GIM_Try, /*On fail goto*//*Label 153*/ 1782,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 154*/ 1751, // Rule ID 55245 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVADD_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55245,
        GIR_Done,
      // Label 154: @1751
      GIM_Try, /*On fail goto*//*Label 155*/ 1781, // Rule ID 55246 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVADD_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55246,
        GIR_Done,
      // Label 155: @1781
      GIM_Reject,
    // Label 153: @1782
    GIM_Reject,
    // Label 93: @1783
    GIM_Try, /*On fail goto*//*Label 156*/ 1866,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 157*/ 1835, // Rule ID 55261 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVADD_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55261,
        GIR_Done,
      // Label 157: @1835
      GIM_Try, /*On fail goto*//*Label 158*/ 1865, // Rule ID 55262 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVADD_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55262,
        GIR_Done,
      // Label 158: @1865
      GIM_Reject,
    // Label 156: @1866
    GIM_Reject,
    // Label 94: @1867
    GIM_Try, /*On fail goto*//*Label 159*/ 1950,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 160*/ 1919, // Rule ID 55277 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVADD_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55277,
        GIR_Done,
      // Label 160: @1919
      GIM_Try, /*On fail goto*//*Label 161*/ 1949, // Rule ID 55278 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVADD_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55278,
        GIR_Done,
      // Label 161: @1949
      GIM_Reject,
    // Label 159: @1950
    GIM_Reject,
    // Label 95: @1951
    GIM_Try, /*On fail goto*//*Label 162*/ 2034,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 163*/ 2003, // Rule ID 55249 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVADD_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55249,
        GIR_Done,
      // Label 163: @2003
      GIM_Try, /*On fail goto*//*Label 164*/ 2033, // Rule ID 55250 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVADD_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55250,
        GIR_Done,
      // Label 164: @2033
      GIM_Reject,
    // Label 162: @2034
    GIM_Reject,
    // Label 96: @2035
    GIM_Try, /*On fail goto*//*Label 165*/ 2118,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 166*/ 2087, // Rule ID 55265 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVADD_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55265,
        GIR_Done,
      // Label 166: @2087
      GIM_Try, /*On fail goto*//*Label 167*/ 2117, // Rule ID 55266 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVADD_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55266,
        GIR_Done,
      // Label 167: @2117
      GIM_Reject,
    // Label 165: @2118
    GIM_Reject,
    // Label 97: @2119
    GIM_Try, /*On fail goto*//*Label 168*/ 2202,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv64s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 169*/ 2171, // Rule ID 55253 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVADD_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55253,
        GIR_Done,
      // Label 169: @2171
      GIM_Try, /*On fail goto*//*Label 170*/ 2201, // Rule ID 55254 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (add:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVADD_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55254,
        GIR_Done,
      // Label 170: @2201
      GIM_Reject,
    // Label 168: @2202
    GIM_Reject,
    // Label 98: @2203
    GIM_Reject,
    // Label 1: @2204
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 32, /*)*//*default:*//*Label 195*/ 4149,
    /*GILLT_s32*//*Label 171*/ 2241,
    /*GILLT_s64*//*Label 172*/ 2271, 0,
    /*GILLT_nxv1s8*//*Label 173*/ 2301,
    /*GILLT_nxv1s16*//*Label 174*/ 2385,
    /*GILLT_nxv1s32*//*Label 175*/ 2469,
    /*GILLT_nxv1s64*//*Label 176*/ 2553, 0,
    /*GILLT_nxv2s8*//*Label 177*/ 2637,
    /*GILLT_nxv2s16*//*Label 178*/ 2721,
    /*GILLT_nxv2s32*//*Label 179*/ 2805,
    /*GILLT_nxv2s64*//*Label 180*/ 2889, 0,
    /*GILLT_nxv4s8*//*Label 181*/ 2973,
    /*GILLT_nxv4s16*//*Label 182*/ 3057,
    /*GILLT_nxv4s32*//*Label 183*/ 3141,
    /*GILLT_nxv4s64*//*Label 184*/ 3225, 0,
    /*GILLT_nxv8s8*//*Label 185*/ 3309,
    /*GILLT_nxv8s16*//*Label 186*/ 3393,
    /*GILLT_nxv8s32*//*Label 187*/ 3477,
    /*GILLT_nxv8s64*//*Label 188*/ 3561, 0,
    /*GILLT_nxv16s8*//*Label 189*/ 3645,
    /*GILLT_nxv16s16*//*Label 190*/ 3729,
    /*GILLT_nxv16s32*//*Label 191*/ 3813, 0,
    /*GILLT_nxv32s8*//*Label 192*/ 3897,
    /*GILLT_nxv32s16*//*Label 193*/ 3981, 0,
    /*GILLT_nxv64s8*//*Label 194*/ 4065,
    // Label 171: @2241
    GIM_Try, /*On fail goto*//*Label 196*/ 2270, // Rule ID 59852 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
      // (sub:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (SUB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SUB,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 59852,
      GIR_Done,
    // Label 196: @2270
    GIM_Reject,
    // Label 172: @2271
    GIM_Try, /*On fail goto*//*Label 197*/ 2300, // Rule ID 59851 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
      // (sub:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (SUB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SUB,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 59851,
      GIR_Done,
    // Label 197: @2300
    GIM_Reject,
    // Label 173: @2301
    GIM_Try, /*On fail goto*//*Label 198*/ 2384,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 199*/ 2353, // Rule ID 55335 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVSUB_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55335,
        GIR_Done,
      // Label 199: @2353
      GIM_Try, /*On fail goto*//*Label 200*/ 2383, // Rule ID 55336 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVSUB_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55336,
        GIR_Done,
      // Label 200: @2383
      GIM_Reject,
    // Label 198: @2384
    GIM_Reject,
    // Label 174: @2385
    GIM_Try, /*On fail goto*//*Label 201*/ 2468,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 202*/ 2437, // Rule ID 55347 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVSUB_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55347,
        GIR_Done,
      // Label 202: @2437
      GIM_Try, /*On fail goto*//*Label 203*/ 2467, // Rule ID 55348 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVSUB_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55348,
        GIR_Done,
      // Label 203: @2467
      GIM_Reject,
    // Label 201: @2468
    GIM_Reject,
    // Label 175: @2469
    GIM_Try, /*On fail goto*//*Label 204*/ 2552,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 205*/ 2521, // Rule ID 55355 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVSUB_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55355,
        GIR_Done,
      // Label 205: @2521
      GIM_Try, /*On fail goto*//*Label 206*/ 2551, // Rule ID 55356 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVSUB_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55356,
        GIR_Done,
      // Label 206: @2551
      GIM_Reject,
    // Label 204: @2552
    GIM_Reject,
    // Label 176: @2553
    GIM_Try, /*On fail goto*//*Label 207*/ 2636,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 208*/ 2605, // Rule ID 55371 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVSUB_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55371,
        GIR_Done,
      // Label 208: @2605
      GIM_Try, /*On fail goto*//*Label 209*/ 2635, // Rule ID 55372 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVSUB_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55372,
        GIR_Done,
      // Label 209: @2635
      GIM_Reject,
    // Label 207: @2636
    GIM_Reject,
    // Label 177: @2637
    GIM_Try, /*On fail goto*//*Label 210*/ 2720,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 211*/ 2689, // Rule ID 55339 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVSUB_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55339,
        GIR_Done,
      // Label 211: @2689
      GIM_Try, /*On fail goto*//*Label 212*/ 2719, // Rule ID 55340 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVSUB_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55340,
        GIR_Done,
      // Label 212: @2719
      GIM_Reject,
    // Label 210: @2720
    GIM_Reject,
    // Label 178: @2721
    GIM_Try, /*On fail goto*//*Label 213*/ 2804,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 214*/ 2773, // Rule ID 55351 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVSUB_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55351,
        GIR_Done,
      // Label 214: @2773
      GIM_Try, /*On fail goto*//*Label 215*/ 2803, // Rule ID 55352 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVSUB_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55352,
        GIR_Done,
      // Label 215: @2803
      GIM_Reject,
    // Label 213: @2804
    GIM_Reject,
    // Label 179: @2805
    GIM_Try, /*On fail goto*//*Label 216*/ 2888,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 217*/ 2857, // Rule ID 55367 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVSUB_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55367,
        GIR_Done,
      // Label 217: @2857
      GIM_Try, /*On fail goto*//*Label 218*/ 2887, // Rule ID 55368 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVSUB_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55368,
        GIR_Done,
      // Label 218: @2887
      GIM_Reject,
    // Label 216: @2888
    GIM_Reject,
    // Label 180: @2889
    GIM_Try, /*On fail goto*//*Label 219*/ 2972,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 220*/ 2941, // Rule ID 55411 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVSUB_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55411,
        GIR_Done,
      // Label 220: @2941
      GIM_Try, /*On fail goto*//*Label 221*/ 2971, // Rule ID 55412 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVSUB_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55412,
        GIR_Done,
      // Label 221: @2971
      GIM_Reject,
    // Label 219: @2972
    GIM_Reject,
    // Label 181: @2973
    GIM_Try, /*On fail goto*//*Label 222*/ 3056,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 223*/ 3025, // Rule ID 55343 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVSUB_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55343,
        GIR_Done,
      // Label 223: @3025
      GIM_Try, /*On fail goto*//*Label 224*/ 3055, // Rule ID 55344 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVSUB_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55344,
        GIR_Done,
      // Label 224: @3055
      GIM_Reject,
    // Label 222: @3056
    GIM_Reject,
    // Label 182: @3057
    GIM_Try, /*On fail goto*//*Label 225*/ 3140,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 226*/ 3109, // Rule ID 55363 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVSUB_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55363,
        GIR_Done,
      // Label 226: @3109
      GIM_Try, /*On fail goto*//*Label 227*/ 3139, // Rule ID 55364 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVSUB_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55364,
        GIR_Done,
      // Label 227: @3139
      GIM_Reject,
    // Label 225: @3140
    GIM_Reject,
    // Label 183: @3141
    GIM_Try, /*On fail goto*//*Label 228*/ 3224,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 229*/ 3193, // Rule ID 55399 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVSUB_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55399,
        GIR_Done,
      // Label 229: @3193
      GIM_Try, /*On fail goto*//*Label 230*/ 3223, // Rule ID 55400 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVSUB_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55400,
        GIR_Done,
      // Label 230: @3223
      GIM_Reject,
    // Label 228: @3224
    GIM_Reject,
    // Label 184: @3225
    GIM_Try, /*On fail goto*//*Label 231*/ 3308,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 232*/ 3277, // Rule ID 55415 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVSUB_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55415,
        GIR_Done,
      // Label 232: @3277
      GIM_Try, /*On fail goto*//*Label 233*/ 3307, // Rule ID 55416 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVSUB_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55416,
        GIR_Done,
      // Label 233: @3307
      GIM_Reject,
    // Label 231: @3308
    GIM_Reject,
    // Label 185: @3309
    GIM_Try, /*On fail goto*//*Label 234*/ 3392,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 235*/ 3361, // Rule ID 55359 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVSUB_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55359,
        GIR_Done,
      // Label 235: @3361
      GIM_Try, /*On fail goto*//*Label 236*/ 3391, // Rule ID 55360 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVSUB_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55360,
        GIR_Done,
      // Label 236: @3391
      GIM_Reject,
    // Label 234: @3392
    GIM_Reject,
    // Label 186: @3393
    GIM_Try, /*On fail goto*//*Label 237*/ 3476,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 238*/ 3445, // Rule ID 55387 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVSUB_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55387,
        GIR_Done,
      // Label 238: @3445
      GIM_Try, /*On fail goto*//*Label 239*/ 3475, // Rule ID 55388 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVSUB_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55388,
        GIR_Done,
      // Label 239: @3475
      GIM_Reject,
    // Label 237: @3476
    GIM_Reject,
    // Label 187: @3477
    GIM_Try, /*On fail goto*//*Label 240*/ 3560,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 241*/ 3529, // Rule ID 55403 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVSUB_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55403,
        GIR_Done,
      // Label 241: @3529
      GIM_Try, /*On fail goto*//*Label 242*/ 3559, // Rule ID 55404 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVSUB_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55404,
        GIR_Done,
      // Label 242: @3559
      GIM_Reject,
    // Label 240: @3560
    GIM_Reject,
    // Label 188: @3561
    GIM_Try, /*On fail goto*//*Label 243*/ 3644,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 244*/ 3613, // Rule ID 55419 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVSUB_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55419,
        GIR_Done,
      // Label 244: @3613
      GIM_Try, /*On fail goto*//*Label 245*/ 3643, // Rule ID 55420 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVSUB_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55420,
        GIR_Done,
      // Label 245: @3643
      GIM_Reject,
    // Label 243: @3644
    GIM_Reject,
    // Label 189: @3645
    GIM_Try, /*On fail goto*//*Label 246*/ 3728,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 247*/ 3697, // Rule ID 55375 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVSUB_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55375,
        GIR_Done,
      // Label 247: @3697
      GIM_Try, /*On fail goto*//*Label 248*/ 3727, // Rule ID 55376 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVSUB_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55376,
        GIR_Done,
      // Label 248: @3727
      GIM_Reject,
    // Label 246: @3728
    GIM_Reject,
    // Label 190: @3729
    GIM_Try, /*On fail goto*//*Label 249*/ 3812,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 250*/ 3781, // Rule ID 55391 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVSUB_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55391,
        GIR_Done,
      // Label 250: @3781
      GIM_Try, /*On fail goto*//*Label 251*/ 3811, // Rule ID 55392 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVSUB_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55392,
        GIR_Done,
      // Label 251: @3811
      GIM_Reject,
    // Label 249: @3812
    GIM_Reject,
    // Label 191: @3813
    GIM_Try, /*On fail goto*//*Label 252*/ 3896,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 253*/ 3865, // Rule ID 55407 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVSUB_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55407,
        GIR_Done,
      // Label 253: @3865
      GIM_Try, /*On fail goto*//*Label 254*/ 3895, // Rule ID 55408 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVSUB_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55408,
        GIR_Done,
      // Label 254: @3895
      GIM_Reject,
    // Label 252: @3896
    GIM_Reject,
    // Label 192: @3897
    GIM_Try, /*On fail goto*//*Label 255*/ 3980,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 256*/ 3949, // Rule ID 55379 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVSUB_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55379,
        GIR_Done,
      // Label 256: @3949
      GIM_Try, /*On fail goto*//*Label 257*/ 3979, // Rule ID 55380 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVSUB_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55380,
        GIR_Done,
      // Label 257: @3979
      GIM_Reject,
    // Label 255: @3980
    GIM_Reject,
    // Label 193: @3981
    GIM_Try, /*On fail goto*//*Label 258*/ 4064,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 259*/ 4033, // Rule ID 55395 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVSUB_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55395,
        GIR_Done,
      // Label 259: @4033
      GIM_Try, /*On fail goto*//*Label 260*/ 4063, // Rule ID 55396 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVSUB_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55396,
        GIR_Done,
      // Label 260: @4063
      GIM_Reject,
    // Label 258: @4064
    GIM_Reject,
    // Label 194: @4065
    GIM_Try, /*On fail goto*//*Label 261*/ 4148,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv64s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 262*/ 4117, // Rule ID 55383 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVSUB_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55383,
        GIR_Done,
      // Label 262: @4117
      GIM_Try, /*On fail goto*//*Label 263*/ 4147, // Rule ID 55384 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sub:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVSUB_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55384,
        GIR_Done,
      // Label 263: @4147
      GIM_Reject,
    // Label 261: @4148
    GIM_Reject,
    // Label 195: @4149
    GIM_Reject,
    // Label 2: @4150
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 32, /*)*//*default:*//*Label 288*/ 6214,
    /*GILLT_s32*//*Label 264*/ 4187,
    /*GILLT_s64*//*Label 265*/ 4219, 0,
    /*GILLT_nxv1s8*//*Label 266*/ 4366,
    /*GILLT_nxv1s16*//*Label 267*/ 4450,
    /*GILLT_nxv1s32*//*Label 268*/ 4534,
    /*GILLT_nxv1s64*//*Label 269*/ 4618, 0,
    /*GILLT_nxv2s8*//*Label 270*/ 4702,
    /*GILLT_nxv2s16*//*Label 271*/ 4786,
    /*GILLT_nxv2s32*//*Label 272*/ 4870,
    /*GILLT_nxv2s64*//*Label 273*/ 4954, 0,
    /*GILLT_nxv4s8*//*Label 274*/ 5038,
    /*GILLT_nxv4s16*//*Label 275*/ 5122,
    /*GILLT_nxv4s32*//*Label 276*/ 5206,
    /*GILLT_nxv4s64*//*Label 277*/ 5290, 0,
    /*GILLT_nxv8s8*//*Label 278*/ 5374,
    /*GILLT_nxv8s16*//*Label 279*/ 5458,
    /*GILLT_nxv8s32*//*Label 280*/ 5542,
    /*GILLT_nxv8s64*//*Label 281*/ 5626, 0,
    /*GILLT_nxv16s8*//*Label 282*/ 5710,
    /*GILLT_nxv16s16*//*Label 283*/ 5794,
    /*GILLT_nxv16s32*//*Label 284*/ 5878, 0,
    /*GILLT_nxv32s8*//*Label 285*/ 5962,
    /*GILLT_nxv32s16*//*Label 286*/ 6046, 0,
    /*GILLT_nxv64s8*//*Label 287*/ 6130,
    // Label 264: @4187
    GIM_Try, /*On fail goto*//*Label 289*/ 4218, // Rule ID 63267 //
      GIM_CheckFeatures, GIFBS_HasStdExtMOrZmmul,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
      // (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (MUL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MUL,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63267,
      GIR_Done,
    // Label 289: @4218
    GIM_Reject,
    // Label 265: @4219
    GIM_Try, /*On fail goto*//*Label 290*/ 4365,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_Try, /*On fail goto*//*Label 291*/ 4345, // Rule ID 63601 //
        GIM_CheckFeatures, GIFBS_HasStdExtMOrZmmul_IsRV64_NotHasStdExtZba,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294967295,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_AND,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 4294967295,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (mul:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), (and:{ *:[i64] } GPR:{ *:[i64] }:$rs2, 4294967295:{ *:[i64] }))  =>  (MULHU:{ *:[i64] } (SLLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 32:{ *:[i64] }), (SLLI:{ *:[i64] } GPR:{ *:[i64] }:$rs2, 32:{ *:[i64] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::SLLI,
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/2, /*Imm*/32,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLLI,
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/1, /*Imm*/32,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::MULHU,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63601,
        GIR_Done,
      // Label 291: @4345
      GIM_Try, /*On fail goto*//*Label 292*/ 4364, // Rule ID 63266 //
        GIM_CheckFeatures, GIFBS_HasStdExtMOrZmmul,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (mul:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (MUL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MUL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63266,
        GIR_Done,
      // Label 292: @4364
      GIM_Reject,
    // Label 290: @4365
    GIM_Reject,
    // Label 266: @4366
    GIM_Try, /*On fail goto*//*Label 293*/ 4449,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 294*/ 4418, // Rule ID 59501 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVMUL_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59501,
        GIR_Done,
      // Label 294: @4418
      GIM_Try, /*On fail goto*//*Label 295*/ 4448, // Rule ID 59502 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVMUL_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59502,
        GIR_Done,
      // Label 295: @4448
      GIM_Reject,
    // Label 293: @4449
    GIM_Reject,
    // Label 267: @4450
    GIM_Try, /*On fail goto*//*Label 296*/ 4533,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 297*/ 4502, // Rule ID 59513 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVMUL_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59513,
        GIR_Done,
      // Label 297: @4502
      GIM_Try, /*On fail goto*//*Label 298*/ 4532, // Rule ID 59514 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVMUL_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59514,
        GIR_Done,
      // Label 298: @4532
      GIM_Reject,
    // Label 296: @4533
    GIM_Reject,
    // Label 268: @4534
    GIM_Try, /*On fail goto*//*Label 299*/ 4617,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 300*/ 4586, // Rule ID 59521 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVMUL_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59521,
        GIR_Done,
      // Label 300: @4586
      GIM_Try, /*On fail goto*//*Label 301*/ 4616, // Rule ID 59522 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVMUL_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59522,
        GIR_Done,
      // Label 301: @4616
      GIM_Reject,
    // Label 299: @4617
    GIM_Reject,
    // Label 269: @4618
    GIM_Try, /*On fail goto*//*Label 302*/ 4701,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 303*/ 4670, // Rule ID 59537 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVMUL_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59537,
        GIR_Done,
      // Label 303: @4670
      GIM_Try, /*On fail goto*//*Label 304*/ 4700, // Rule ID 59538 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVMUL_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59538,
        GIR_Done,
      // Label 304: @4700
      GIM_Reject,
    // Label 302: @4701
    GIM_Reject,
    // Label 270: @4702
    GIM_Try, /*On fail goto*//*Label 305*/ 4785,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 306*/ 4754, // Rule ID 59505 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVMUL_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59505,
        GIR_Done,
      // Label 306: @4754
      GIM_Try, /*On fail goto*//*Label 307*/ 4784, // Rule ID 59506 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVMUL_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59506,
        GIR_Done,
      // Label 307: @4784
      GIM_Reject,
    // Label 305: @4785
    GIM_Reject,
    // Label 271: @4786
    GIM_Try, /*On fail goto*//*Label 308*/ 4869,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 309*/ 4838, // Rule ID 59517 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVMUL_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59517,
        GIR_Done,
      // Label 309: @4838
      GIM_Try, /*On fail goto*//*Label 310*/ 4868, // Rule ID 59518 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVMUL_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59518,
        GIR_Done,
      // Label 310: @4868
      GIM_Reject,
    // Label 308: @4869
    GIM_Reject,
    // Label 272: @4870
    GIM_Try, /*On fail goto*//*Label 311*/ 4953,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 312*/ 4922, // Rule ID 59533 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVMUL_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59533,
        GIR_Done,
      // Label 312: @4922
      GIM_Try, /*On fail goto*//*Label 313*/ 4952, // Rule ID 59534 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVMUL_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59534,
        GIR_Done,
      // Label 313: @4952
      GIM_Reject,
    // Label 311: @4953
    GIM_Reject,
    // Label 273: @4954
    GIM_Try, /*On fail goto*//*Label 314*/ 5037,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 315*/ 5006, // Rule ID 59577 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVMUL_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59577,
        GIR_Done,
      // Label 315: @5006
      GIM_Try, /*On fail goto*//*Label 316*/ 5036, // Rule ID 59578 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVMUL_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59578,
        GIR_Done,
      // Label 316: @5036
      GIM_Reject,
    // Label 314: @5037
    GIM_Reject,
    // Label 274: @5038
    GIM_Try, /*On fail goto*//*Label 317*/ 5121,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 318*/ 5090, // Rule ID 59509 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVMUL_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59509,
        GIR_Done,
      // Label 318: @5090
      GIM_Try, /*On fail goto*//*Label 319*/ 5120, // Rule ID 59510 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVMUL_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59510,
        GIR_Done,
      // Label 319: @5120
      GIM_Reject,
    // Label 317: @5121
    GIM_Reject,
    // Label 275: @5122
    GIM_Try, /*On fail goto*//*Label 320*/ 5205,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 321*/ 5174, // Rule ID 59529 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVMUL_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59529,
        GIR_Done,
      // Label 321: @5174
      GIM_Try, /*On fail goto*//*Label 322*/ 5204, // Rule ID 59530 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVMUL_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59530,
        GIR_Done,
      // Label 322: @5204
      GIM_Reject,
    // Label 320: @5205
    GIM_Reject,
    // Label 276: @5206
    GIM_Try, /*On fail goto*//*Label 323*/ 5289,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 324*/ 5258, // Rule ID 59565 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVMUL_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59565,
        GIR_Done,
      // Label 324: @5258
      GIM_Try, /*On fail goto*//*Label 325*/ 5288, // Rule ID 59566 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVMUL_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59566,
        GIR_Done,
      // Label 325: @5288
      GIM_Reject,
    // Label 323: @5289
    GIM_Reject,
    // Label 277: @5290
    GIM_Try, /*On fail goto*//*Label 326*/ 5373,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 327*/ 5342, // Rule ID 59581 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVMUL_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59581,
        GIR_Done,
      // Label 327: @5342
      GIM_Try, /*On fail goto*//*Label 328*/ 5372, // Rule ID 59582 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVMUL_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59582,
        GIR_Done,
      // Label 328: @5372
      GIM_Reject,
    // Label 326: @5373
    GIM_Reject,
    // Label 278: @5374
    GIM_Try, /*On fail goto*//*Label 329*/ 5457,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 330*/ 5426, // Rule ID 59525 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVMUL_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59525,
        GIR_Done,
      // Label 330: @5426
      GIM_Try, /*On fail goto*//*Label 331*/ 5456, // Rule ID 59526 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVMUL_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59526,
        GIR_Done,
      // Label 331: @5456
      GIM_Reject,
    // Label 329: @5457
    GIM_Reject,
    // Label 279: @5458
    GIM_Try, /*On fail goto*//*Label 332*/ 5541,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 333*/ 5510, // Rule ID 59553 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVMUL_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59553,
        GIR_Done,
      // Label 333: @5510
      GIM_Try, /*On fail goto*//*Label 334*/ 5540, // Rule ID 59554 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVMUL_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59554,
        GIR_Done,
      // Label 334: @5540
      GIM_Reject,
    // Label 332: @5541
    GIM_Reject,
    // Label 280: @5542
    GIM_Try, /*On fail goto*//*Label 335*/ 5625,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 336*/ 5594, // Rule ID 59569 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVMUL_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59569,
        GIR_Done,
      // Label 336: @5594
      GIM_Try, /*On fail goto*//*Label 337*/ 5624, // Rule ID 59570 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVMUL_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59570,
        GIR_Done,
      // Label 337: @5624
      GIM_Reject,
    // Label 335: @5625
    GIM_Reject,
    // Label 281: @5626
    GIM_Try, /*On fail goto*//*Label 338*/ 5709,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 339*/ 5678, // Rule ID 59585 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVMUL_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59585,
        GIR_Done,
      // Label 339: @5678
      GIM_Try, /*On fail goto*//*Label 340*/ 5708, // Rule ID 59586 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVMUL_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59586,
        GIR_Done,
      // Label 340: @5708
      GIM_Reject,
    // Label 338: @5709
    GIM_Reject,
    // Label 282: @5710
    GIM_Try, /*On fail goto*//*Label 341*/ 5793,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 342*/ 5762, // Rule ID 59541 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVMUL_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59541,
        GIR_Done,
      // Label 342: @5762
      GIM_Try, /*On fail goto*//*Label 343*/ 5792, // Rule ID 59542 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVMUL_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59542,
        GIR_Done,
      // Label 343: @5792
      GIM_Reject,
    // Label 341: @5793
    GIM_Reject,
    // Label 283: @5794
    GIM_Try, /*On fail goto*//*Label 344*/ 5877,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 345*/ 5846, // Rule ID 59557 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVMUL_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59557,
        GIR_Done,
      // Label 345: @5846
      GIM_Try, /*On fail goto*//*Label 346*/ 5876, // Rule ID 59558 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVMUL_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59558,
        GIR_Done,
      // Label 346: @5876
      GIM_Reject,
    // Label 344: @5877
    GIM_Reject,
    // Label 284: @5878
    GIM_Try, /*On fail goto*//*Label 347*/ 5961,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 348*/ 5930, // Rule ID 59573 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVMUL_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59573,
        GIR_Done,
      // Label 348: @5930
      GIM_Try, /*On fail goto*//*Label 349*/ 5960, // Rule ID 59574 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVMUL_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59574,
        GIR_Done,
      // Label 349: @5960
      GIM_Reject,
    // Label 347: @5961
    GIM_Reject,
    // Label 285: @5962
    GIM_Try, /*On fail goto*//*Label 350*/ 6045,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 351*/ 6014, // Rule ID 59545 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVMUL_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59545,
        GIR_Done,
      // Label 351: @6014
      GIM_Try, /*On fail goto*//*Label 352*/ 6044, // Rule ID 59546 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVMUL_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59546,
        GIR_Done,
      // Label 352: @6044
      GIM_Reject,
    // Label 350: @6045
    GIM_Reject,
    // Label 286: @6046
    GIM_Try, /*On fail goto*//*Label 353*/ 6129,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 354*/ 6098, // Rule ID 59561 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVMUL_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59561,
        GIR_Done,
      // Label 354: @6098
      GIM_Try, /*On fail goto*//*Label 355*/ 6128, // Rule ID 59562 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVMUL_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59562,
        GIR_Done,
      // Label 355: @6128
      GIM_Reject,
    // Label 353: @6129
    GIM_Reject,
    // Label 287: @6130
    GIM_Try, /*On fail goto*//*Label 356*/ 6213,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv64s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 357*/ 6182, // Rule ID 59549 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVMUL_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59549,
        GIR_Done,
      // Label 357: @6182
      GIM_Try, /*On fail goto*//*Label 358*/ 6212, // Rule ID 59550 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mul:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVMUL_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMUL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59550,
        GIR_Done,
      // Label 358: @6212
      GIM_Reject,
    // Label 356: @6213
    GIM_Reject,
    // Label 288: @6214
    GIM_Reject,
    // Label 3: @6215
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 32, /*)*//*default:*//*Label 383*/ 8164,
    /*GILLT_s32*//*Label 359*/ 6252,
    /*GILLT_s64*//*Label 360*/ 6284, 0,
    /*GILLT_nxv1s8*//*Label 361*/ 6316,
    /*GILLT_nxv1s16*//*Label 362*/ 6400,
    /*GILLT_nxv1s32*//*Label 363*/ 6484,
    /*GILLT_nxv1s64*//*Label 364*/ 6568, 0,
    /*GILLT_nxv2s8*//*Label 365*/ 6652,
    /*GILLT_nxv2s16*//*Label 366*/ 6736,
    /*GILLT_nxv2s32*//*Label 367*/ 6820,
    /*GILLT_nxv2s64*//*Label 368*/ 6904, 0,
    /*GILLT_nxv4s8*//*Label 369*/ 6988,
    /*GILLT_nxv4s16*//*Label 370*/ 7072,
    /*GILLT_nxv4s32*//*Label 371*/ 7156,
    /*GILLT_nxv4s64*//*Label 372*/ 7240, 0,
    /*GILLT_nxv8s8*//*Label 373*/ 7324,
    /*GILLT_nxv8s16*//*Label 374*/ 7408,
    /*GILLT_nxv8s32*//*Label 375*/ 7492,
    /*GILLT_nxv8s64*//*Label 376*/ 7576, 0,
    /*GILLT_nxv16s8*//*Label 377*/ 7660,
    /*GILLT_nxv16s16*//*Label 378*/ 7744,
    /*GILLT_nxv16s32*//*Label 379*/ 7828, 0,
    /*GILLT_nxv32s8*//*Label 380*/ 7912,
    /*GILLT_nxv32s16*//*Label 381*/ 7996, 0,
    /*GILLT_nxv64s8*//*Label 382*/ 8080,
    // Label 359: @6252
    GIM_Try, /*On fail goto*//*Label 384*/ 6283, // Rule ID 63353 //
      GIM_CheckFeatures, GIFBS_HasStdExtM,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
      // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (DIV:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::DIV,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63353,
      GIR_Done,
    // Label 384: @6283
    GIM_Reject,
    // Label 360: @6284
    GIM_Try, /*On fail goto*//*Label 385*/ 6315, // Rule ID 63352 //
      GIM_CheckFeatures, GIFBS_HasStdExtM,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
      // (sdiv:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (DIV:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::DIV,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63352,
      GIR_Done,
    // Label 385: @6315
    GIM_Reject,
    // Label 361: @6316
    GIM_Try, /*On fail goto*//*Label 386*/ 6399,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 387*/ 6368, // Rule ID 59859 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVDIV_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59859,
        GIR_Done,
      // Label 387: @6368
      GIM_Try, /*On fail goto*//*Label 388*/ 6398, // Rule ID 59860 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVDIV_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59860,
        GIR_Done,
      // Label 388: @6398
      GIM_Reject,
    // Label 386: @6399
    GIM_Reject,
    // Label 362: @6400
    GIM_Try, /*On fail goto*//*Label 389*/ 6483,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 390*/ 6452, // Rule ID 59873 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVDIV_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59873,
        GIR_Done,
      // Label 390: @6452
      GIM_Try, /*On fail goto*//*Label 391*/ 6482, // Rule ID 59874 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVDIV_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59874,
        GIR_Done,
      // Label 391: @6482
      GIM_Reject,
    // Label 389: @6483
    GIM_Reject,
    // Label 363: @6484
    GIM_Try, /*On fail goto*//*Label 392*/ 6567,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 393*/ 6536, // Rule ID 59881 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVDIV_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59881,
        GIR_Done,
      // Label 393: @6536
      GIM_Try, /*On fail goto*//*Label 394*/ 6566, // Rule ID 59882 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVDIV_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59882,
        GIR_Done,
      // Label 394: @6566
      GIM_Reject,
    // Label 392: @6567
    GIM_Reject,
    // Label 364: @6568
    GIM_Try, /*On fail goto*//*Label 395*/ 6651,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 396*/ 6620, // Rule ID 59899 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVDIV_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59899,
        GIR_Done,
      // Label 396: @6620
      GIM_Try, /*On fail goto*//*Label 397*/ 6650, // Rule ID 59900 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVDIV_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59900,
        GIR_Done,
      // Label 397: @6650
      GIM_Reject,
    // Label 395: @6651
    GIM_Reject,
    // Label 365: @6652
    GIM_Try, /*On fail goto*//*Label 398*/ 6735,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 399*/ 6704, // Rule ID 59863 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVDIV_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59863,
        GIR_Done,
      // Label 399: @6704
      GIM_Try, /*On fail goto*//*Label 400*/ 6734, // Rule ID 59864 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVDIV_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59864,
        GIR_Done,
      // Label 400: @6734
      GIM_Reject,
    // Label 398: @6735
    GIM_Reject,
    // Label 366: @6736
    GIM_Try, /*On fail goto*//*Label 401*/ 6819,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 402*/ 6788, // Rule ID 59877 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVDIV_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59877,
        GIR_Done,
      // Label 402: @6788
      GIM_Try, /*On fail goto*//*Label 403*/ 6818, // Rule ID 59878 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVDIV_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59878,
        GIR_Done,
      // Label 403: @6818
      GIM_Reject,
    // Label 401: @6819
    GIM_Reject,
    // Label 367: @6820
    GIM_Try, /*On fail goto*//*Label 404*/ 6903,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 405*/ 6872, // Rule ID 59895 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVDIV_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59895,
        GIR_Done,
      // Label 405: @6872
      GIM_Try, /*On fail goto*//*Label 406*/ 6902, // Rule ID 59896 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVDIV_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59896,
        GIR_Done,
      // Label 406: @6902
      GIM_Reject,
    // Label 404: @6903
    GIM_Reject,
    // Label 368: @6904
    GIM_Try, /*On fail goto*//*Label 407*/ 6987,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 408*/ 6956, // Rule ID 59943 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVDIV_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59943,
        GIR_Done,
      // Label 408: @6956
      GIM_Try, /*On fail goto*//*Label 409*/ 6986, // Rule ID 59944 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVDIV_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59944,
        GIR_Done,
      // Label 409: @6986
      GIM_Reject,
    // Label 407: @6987
    GIM_Reject,
    // Label 369: @6988
    GIM_Try, /*On fail goto*//*Label 410*/ 7071,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 411*/ 7040, // Rule ID 59867 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVDIV_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59867,
        GIR_Done,
      // Label 411: @7040
      GIM_Try, /*On fail goto*//*Label 412*/ 7070, // Rule ID 59868 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVDIV_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59868,
        GIR_Done,
      // Label 412: @7070
      GIM_Reject,
    // Label 410: @7071
    GIM_Reject,
    // Label 370: @7072
    GIM_Try, /*On fail goto*//*Label 413*/ 7155,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 414*/ 7124, // Rule ID 59889 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVDIV_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59889,
        GIR_Done,
      // Label 414: @7124
      GIM_Try, /*On fail goto*//*Label 415*/ 7154, // Rule ID 59890 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVDIV_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59890,
        GIR_Done,
      // Label 415: @7154
      GIM_Reject,
    // Label 413: @7155
    GIM_Reject,
    // Label 371: @7156
    GIM_Try, /*On fail goto*//*Label 416*/ 7239,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 417*/ 7208, // Rule ID 59929 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVDIV_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59929,
        GIR_Done,
      // Label 417: @7208
      GIM_Try, /*On fail goto*//*Label 418*/ 7238, // Rule ID 59930 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVDIV_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59930,
        GIR_Done,
      // Label 418: @7238
      GIM_Reject,
    // Label 416: @7239
    GIM_Reject,
    // Label 372: @7240
    GIM_Try, /*On fail goto*//*Label 419*/ 7323,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 420*/ 7292, // Rule ID 59947 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVDIV_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59947,
        GIR_Done,
      // Label 420: @7292
      GIM_Try, /*On fail goto*//*Label 421*/ 7322, // Rule ID 59948 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVDIV_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59948,
        GIR_Done,
      // Label 421: @7322
      GIM_Reject,
    // Label 419: @7323
    GIM_Reject,
    // Label 373: @7324
    GIM_Try, /*On fail goto*//*Label 422*/ 7407,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 423*/ 7376, // Rule ID 59885 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVDIV_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59885,
        GIR_Done,
      // Label 423: @7376
      GIM_Try, /*On fail goto*//*Label 424*/ 7406, // Rule ID 59886 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVDIV_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59886,
        GIR_Done,
      // Label 424: @7406
      GIM_Reject,
    // Label 422: @7407
    GIM_Reject,
    // Label 374: @7408
    GIM_Try, /*On fail goto*//*Label 425*/ 7491,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 426*/ 7460, // Rule ID 59917 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVDIV_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59917,
        GIR_Done,
      // Label 426: @7460
      GIM_Try, /*On fail goto*//*Label 427*/ 7490, // Rule ID 59918 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVDIV_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59918,
        GIR_Done,
      // Label 427: @7490
      GIM_Reject,
    // Label 425: @7491
    GIM_Reject,
    // Label 375: @7492
    GIM_Try, /*On fail goto*//*Label 428*/ 7575,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 429*/ 7544, // Rule ID 59933 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVDIV_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59933,
        GIR_Done,
      // Label 429: @7544
      GIM_Try, /*On fail goto*//*Label 430*/ 7574, // Rule ID 59934 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVDIV_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59934,
        GIR_Done,
      // Label 430: @7574
      GIM_Reject,
    // Label 428: @7575
    GIM_Reject,
    // Label 376: @7576
    GIM_Try, /*On fail goto*//*Label 431*/ 7659,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 432*/ 7628, // Rule ID 59951 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVDIV_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59951,
        GIR_Done,
      // Label 432: @7628
      GIM_Try, /*On fail goto*//*Label 433*/ 7658, // Rule ID 59952 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVDIV_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59952,
        GIR_Done,
      // Label 433: @7658
      GIM_Reject,
    // Label 431: @7659
    GIM_Reject,
    // Label 377: @7660
    GIM_Try, /*On fail goto*//*Label 434*/ 7743,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 435*/ 7712, // Rule ID 59903 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVDIV_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59903,
        GIR_Done,
      // Label 435: @7712
      GIM_Try, /*On fail goto*//*Label 436*/ 7742, // Rule ID 59904 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVDIV_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59904,
        GIR_Done,
      // Label 436: @7742
      GIM_Reject,
    // Label 434: @7743
    GIM_Reject,
    // Label 378: @7744
    GIM_Try, /*On fail goto*//*Label 437*/ 7827,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 438*/ 7796, // Rule ID 59921 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVDIV_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59921,
        GIR_Done,
      // Label 438: @7796
      GIM_Try, /*On fail goto*//*Label 439*/ 7826, // Rule ID 59922 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVDIV_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59922,
        GIR_Done,
      // Label 439: @7826
      GIM_Reject,
    // Label 437: @7827
    GIM_Reject,
    // Label 379: @7828
    GIM_Try, /*On fail goto*//*Label 440*/ 7911,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 441*/ 7880, // Rule ID 59939 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVDIV_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59939,
        GIR_Done,
      // Label 441: @7880
      GIM_Try, /*On fail goto*//*Label 442*/ 7910, // Rule ID 59940 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVDIV_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59940,
        GIR_Done,
      // Label 442: @7910
      GIM_Reject,
    // Label 440: @7911
    GIM_Reject,
    // Label 380: @7912
    GIM_Try, /*On fail goto*//*Label 443*/ 7995,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 444*/ 7964, // Rule ID 59907 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVDIV_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59907,
        GIR_Done,
      // Label 444: @7964
      GIM_Try, /*On fail goto*//*Label 445*/ 7994, // Rule ID 59908 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVDIV_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59908,
        GIR_Done,
      // Label 445: @7994
      GIM_Reject,
    // Label 443: @7995
    GIM_Reject,
    // Label 381: @7996
    GIM_Try, /*On fail goto*//*Label 446*/ 8079,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 447*/ 8048, // Rule ID 59925 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVDIV_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59925,
        GIR_Done,
      // Label 447: @8048
      GIM_Try, /*On fail goto*//*Label 448*/ 8078, // Rule ID 59926 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVDIV_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59926,
        GIR_Done,
      // Label 448: @8078
      GIM_Reject,
    // Label 446: @8079
    GIM_Reject,
    // Label 382: @8080
    GIM_Try, /*On fail goto*//*Label 449*/ 8163,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv64s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 450*/ 8132, // Rule ID 59911 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVDIV_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59911,
        GIR_Done,
      // Label 450: @8132
      GIM_Try, /*On fail goto*//*Label 451*/ 8162, // Rule ID 59912 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sdiv:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVDIV_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIV_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59912,
        GIR_Done,
      // Label 451: @8162
      GIM_Reject,
    // Label 449: @8163
    GIM_Reject,
    // Label 383: @8164
    GIM_Reject,
    // Label 4: @8165
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 32, /*)*//*default:*//*Label 476*/ 10114,
    /*GILLT_s32*//*Label 452*/ 8202,
    /*GILLT_s64*//*Label 453*/ 8234, 0,
    /*GILLT_nxv1s8*//*Label 454*/ 8266,
    /*GILLT_nxv1s16*//*Label 455*/ 8350,
    /*GILLT_nxv1s32*//*Label 456*/ 8434,
    /*GILLT_nxv1s64*//*Label 457*/ 8518, 0,
    /*GILLT_nxv2s8*//*Label 458*/ 8602,
    /*GILLT_nxv2s16*//*Label 459*/ 8686,
    /*GILLT_nxv2s32*//*Label 460*/ 8770,
    /*GILLT_nxv2s64*//*Label 461*/ 8854, 0,
    /*GILLT_nxv4s8*//*Label 462*/ 8938,
    /*GILLT_nxv4s16*//*Label 463*/ 9022,
    /*GILLT_nxv4s32*//*Label 464*/ 9106,
    /*GILLT_nxv4s64*//*Label 465*/ 9190, 0,
    /*GILLT_nxv8s8*//*Label 466*/ 9274,
    /*GILLT_nxv8s16*//*Label 467*/ 9358,
    /*GILLT_nxv8s32*//*Label 468*/ 9442,
    /*GILLT_nxv8s64*//*Label 469*/ 9526, 0,
    /*GILLT_nxv16s8*//*Label 470*/ 9610,
    /*GILLT_nxv16s16*//*Label 471*/ 9694,
    /*GILLT_nxv16s32*//*Label 472*/ 9778, 0,
    /*GILLT_nxv32s8*//*Label 473*/ 9862,
    /*GILLT_nxv32s16*//*Label 474*/ 9946, 0,
    /*GILLT_nxv64s8*//*Label 475*/ 10030,
    // Label 452: @8202
    GIM_Try, /*On fail goto*//*Label 477*/ 8233, // Rule ID 63375 //
      GIM_CheckFeatures, GIFBS_HasStdExtM,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
      // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (DIVU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::DIVU,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63375,
      GIR_Done,
    // Label 477: @8233
    GIM_Reject,
    // Label 453: @8234
    GIM_Try, /*On fail goto*//*Label 478*/ 8265, // Rule ID 63374 //
      GIM_CheckFeatures, GIFBS_HasStdExtM,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
      // (udiv:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (DIVU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::DIVU,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63374,
      GIR_Done,
    // Label 478: @8265
    GIM_Reject,
    // Label 454: @8266
    GIM_Try, /*On fail goto*//*Label 479*/ 8349,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 480*/ 8318, // Rule ID 59765 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVDIVU_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59765,
        GIR_Done,
      // Label 480: @8318
      GIM_Try, /*On fail goto*//*Label 481*/ 8348, // Rule ID 59766 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVDIVU_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59766,
        GIR_Done,
      // Label 481: @8348
      GIM_Reject,
    // Label 479: @8349
    GIM_Reject,
    // Label 455: @8350
    GIM_Try, /*On fail goto*//*Label 482*/ 8433,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 483*/ 8402, // Rule ID 59777 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVDIVU_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59777,
        GIR_Done,
      // Label 483: @8402
      GIM_Try, /*On fail goto*//*Label 484*/ 8432, // Rule ID 59778 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVDIVU_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59778,
        GIR_Done,
      // Label 484: @8432
      GIM_Reject,
    // Label 482: @8433
    GIM_Reject,
    // Label 456: @8434
    GIM_Try, /*On fail goto*//*Label 485*/ 8517,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 486*/ 8486, // Rule ID 59785 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVDIVU_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59785,
        GIR_Done,
      // Label 486: @8486
      GIM_Try, /*On fail goto*//*Label 487*/ 8516, // Rule ID 59786 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVDIVU_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59786,
        GIR_Done,
      // Label 487: @8516
      GIM_Reject,
    // Label 485: @8517
    GIM_Reject,
    // Label 457: @8518
    GIM_Try, /*On fail goto*//*Label 488*/ 8601,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 489*/ 8570, // Rule ID 59801 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVDIVU_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59801,
        GIR_Done,
      // Label 489: @8570
      GIM_Try, /*On fail goto*//*Label 490*/ 8600, // Rule ID 59802 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVDIVU_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59802,
        GIR_Done,
      // Label 490: @8600
      GIM_Reject,
    // Label 488: @8601
    GIM_Reject,
    // Label 458: @8602
    GIM_Try, /*On fail goto*//*Label 491*/ 8685,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 492*/ 8654, // Rule ID 59769 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVDIVU_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59769,
        GIR_Done,
      // Label 492: @8654
      GIM_Try, /*On fail goto*//*Label 493*/ 8684, // Rule ID 59770 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVDIVU_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59770,
        GIR_Done,
      // Label 493: @8684
      GIM_Reject,
    // Label 491: @8685
    GIM_Reject,
    // Label 459: @8686
    GIM_Try, /*On fail goto*//*Label 494*/ 8769,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 495*/ 8738, // Rule ID 59781 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVDIVU_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59781,
        GIR_Done,
      // Label 495: @8738
      GIM_Try, /*On fail goto*//*Label 496*/ 8768, // Rule ID 59782 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVDIVU_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59782,
        GIR_Done,
      // Label 496: @8768
      GIM_Reject,
    // Label 494: @8769
    GIM_Reject,
    // Label 460: @8770
    GIM_Try, /*On fail goto*//*Label 497*/ 8853,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 498*/ 8822, // Rule ID 59797 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVDIVU_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59797,
        GIR_Done,
      // Label 498: @8822
      GIM_Try, /*On fail goto*//*Label 499*/ 8852, // Rule ID 59798 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVDIVU_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59798,
        GIR_Done,
      // Label 499: @8852
      GIM_Reject,
    // Label 497: @8853
    GIM_Reject,
    // Label 461: @8854
    GIM_Try, /*On fail goto*//*Label 500*/ 8937,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 501*/ 8906, // Rule ID 59845 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVDIVU_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59845,
        GIR_Done,
      // Label 501: @8906
      GIM_Try, /*On fail goto*//*Label 502*/ 8936, // Rule ID 59846 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVDIVU_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59846,
        GIR_Done,
      // Label 502: @8936
      GIM_Reject,
    // Label 500: @8937
    GIM_Reject,
    // Label 462: @8938
    GIM_Try, /*On fail goto*//*Label 503*/ 9021,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 504*/ 8990, // Rule ID 59773 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVDIVU_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59773,
        GIR_Done,
      // Label 504: @8990
      GIM_Try, /*On fail goto*//*Label 505*/ 9020, // Rule ID 59774 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVDIVU_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59774,
        GIR_Done,
      // Label 505: @9020
      GIM_Reject,
    // Label 503: @9021
    GIM_Reject,
    // Label 463: @9022
    GIM_Try, /*On fail goto*//*Label 506*/ 9105,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 507*/ 9074, // Rule ID 59793 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVDIVU_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59793,
        GIR_Done,
      // Label 507: @9074
      GIM_Try, /*On fail goto*//*Label 508*/ 9104, // Rule ID 59794 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVDIVU_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59794,
        GIR_Done,
      // Label 508: @9104
      GIM_Reject,
    // Label 506: @9105
    GIM_Reject,
    // Label 464: @9106
    GIM_Try, /*On fail goto*//*Label 509*/ 9189,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 510*/ 9158, // Rule ID 59833 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVDIVU_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59833,
        GIR_Done,
      // Label 510: @9158
      GIM_Try, /*On fail goto*//*Label 511*/ 9188, // Rule ID 59834 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVDIVU_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59834,
        GIR_Done,
      // Label 511: @9188
      GIM_Reject,
    // Label 509: @9189
    GIM_Reject,
    // Label 465: @9190
    GIM_Try, /*On fail goto*//*Label 512*/ 9273,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 513*/ 9242, // Rule ID 59849 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVDIVU_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59849,
        GIR_Done,
      // Label 513: @9242
      GIM_Try, /*On fail goto*//*Label 514*/ 9272, // Rule ID 59850 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVDIVU_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59850,
        GIR_Done,
      // Label 514: @9272
      GIM_Reject,
    // Label 512: @9273
    GIM_Reject,
    // Label 466: @9274
    GIM_Try, /*On fail goto*//*Label 515*/ 9357,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 516*/ 9326, // Rule ID 59789 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVDIVU_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59789,
        GIR_Done,
      // Label 516: @9326
      GIM_Try, /*On fail goto*//*Label 517*/ 9356, // Rule ID 59790 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVDIVU_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59790,
        GIR_Done,
      // Label 517: @9356
      GIM_Reject,
    // Label 515: @9357
    GIM_Reject,
    // Label 467: @9358
    GIM_Try, /*On fail goto*//*Label 518*/ 9441,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 519*/ 9410, // Rule ID 59819 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVDIVU_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59819,
        GIR_Done,
      // Label 519: @9410
      GIM_Try, /*On fail goto*//*Label 520*/ 9440, // Rule ID 59820 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVDIVU_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59820,
        GIR_Done,
      // Label 520: @9440
      GIM_Reject,
    // Label 518: @9441
    GIM_Reject,
    // Label 468: @9442
    GIM_Try, /*On fail goto*//*Label 521*/ 9525,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 522*/ 9494, // Rule ID 59837 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVDIVU_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59837,
        GIR_Done,
      // Label 522: @9494
      GIM_Try, /*On fail goto*//*Label 523*/ 9524, // Rule ID 59838 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVDIVU_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59838,
        GIR_Done,
      // Label 523: @9524
      GIM_Reject,
    // Label 521: @9525
    GIM_Reject,
    // Label 469: @9526
    GIM_Try, /*On fail goto*//*Label 524*/ 9609,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 525*/ 9578, // Rule ID 59855 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVDIVU_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59855,
        GIR_Done,
      // Label 525: @9578
      GIM_Try, /*On fail goto*//*Label 526*/ 9608, // Rule ID 59856 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVDIVU_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59856,
        GIR_Done,
      // Label 526: @9608
      GIM_Reject,
    // Label 524: @9609
    GIM_Reject,
    // Label 470: @9610
    GIM_Try, /*On fail goto*//*Label 527*/ 9693,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 528*/ 9662, // Rule ID 59805 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVDIVU_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59805,
        GIR_Done,
      // Label 528: @9662
      GIM_Try, /*On fail goto*//*Label 529*/ 9692, // Rule ID 59806 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVDIVU_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59806,
        GIR_Done,
      // Label 529: @9692
      GIM_Reject,
    // Label 527: @9693
    GIM_Reject,
    // Label 471: @9694
    GIM_Try, /*On fail goto*//*Label 530*/ 9777,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 531*/ 9746, // Rule ID 59823 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVDIVU_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59823,
        GIR_Done,
      // Label 531: @9746
      GIM_Try, /*On fail goto*//*Label 532*/ 9776, // Rule ID 59824 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVDIVU_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59824,
        GIR_Done,
      // Label 532: @9776
      GIM_Reject,
    // Label 530: @9777
    GIM_Reject,
    // Label 472: @9778
    GIM_Try, /*On fail goto*//*Label 533*/ 9861,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 534*/ 9830, // Rule ID 59841 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVDIVU_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59841,
        GIR_Done,
      // Label 534: @9830
      GIM_Try, /*On fail goto*//*Label 535*/ 9860, // Rule ID 59842 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVDIVU_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59842,
        GIR_Done,
      // Label 535: @9860
      GIM_Reject,
    // Label 533: @9861
    GIM_Reject,
    // Label 473: @9862
    GIM_Try, /*On fail goto*//*Label 536*/ 9945,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 537*/ 9914, // Rule ID 59811 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVDIVU_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59811,
        GIR_Done,
      // Label 537: @9914
      GIM_Try, /*On fail goto*//*Label 538*/ 9944, // Rule ID 59812 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVDIVU_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59812,
        GIR_Done,
      // Label 538: @9944
      GIM_Reject,
    // Label 536: @9945
    GIM_Reject,
    // Label 474: @9946
    GIM_Try, /*On fail goto*//*Label 539*/ 10029,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 540*/ 9998, // Rule ID 59827 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVDIVU_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59827,
        GIR_Done,
      // Label 540: @9998
      GIM_Try, /*On fail goto*//*Label 541*/ 10028, // Rule ID 59828 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVDIVU_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59828,
        GIR_Done,
      // Label 541: @10028
      GIM_Reject,
    // Label 539: @10029
    GIM_Reject,
    // Label 475: @10030
    GIM_Try, /*On fail goto*//*Label 542*/ 10113,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv64s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 543*/ 10082, // Rule ID 59815 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVDIVU_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59815,
        GIR_Done,
      // Label 543: @10082
      GIM_Try, /*On fail goto*//*Label 544*/ 10112, // Rule ID 59816 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (udiv:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVDIVU_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVDIVU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59816,
        GIR_Done,
      // Label 544: @10112
      GIM_Reject,
    // Label 542: @10113
    GIM_Reject,
    // Label 476: @10114
    GIM_Reject,
    // Label 5: @10115
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 32, /*)*//*default:*//*Label 569*/ 12064,
    /*GILLT_s32*//*Label 545*/ 10152,
    /*GILLT_s64*//*Label 546*/ 10184, 0,
    /*GILLT_nxv1s8*//*Label 547*/ 10216,
    /*GILLT_nxv1s16*//*Label 548*/ 10300,
    /*GILLT_nxv1s32*//*Label 549*/ 10384,
    /*GILLT_nxv1s64*//*Label 550*/ 10468, 0,
    /*GILLT_nxv2s8*//*Label 551*/ 10552,
    /*GILLT_nxv2s16*//*Label 552*/ 10636,
    /*GILLT_nxv2s32*//*Label 553*/ 10720,
    /*GILLT_nxv2s64*//*Label 554*/ 10804, 0,
    /*GILLT_nxv4s8*//*Label 555*/ 10888,
    /*GILLT_nxv4s16*//*Label 556*/ 10972,
    /*GILLT_nxv4s32*//*Label 557*/ 11056,
    /*GILLT_nxv4s64*//*Label 558*/ 11140, 0,
    /*GILLT_nxv8s8*//*Label 559*/ 11224,
    /*GILLT_nxv8s16*//*Label 560*/ 11308,
    /*GILLT_nxv8s32*//*Label 561*/ 11392,
    /*GILLT_nxv8s64*//*Label 562*/ 11476, 0,
    /*GILLT_nxv16s8*//*Label 563*/ 11560,
    /*GILLT_nxv16s16*//*Label 564*/ 11644,
    /*GILLT_nxv16s32*//*Label 565*/ 11728, 0,
    /*GILLT_nxv32s8*//*Label 566*/ 11812,
    /*GILLT_nxv32s16*//*Label 567*/ 11896, 0,
    /*GILLT_nxv64s8*//*Label 568*/ 11980,
    // Label 545: @10152
    GIM_Try, /*On fail goto*//*Label 570*/ 10183, // Rule ID 63395 //
      GIM_CheckFeatures, GIFBS_HasStdExtM,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
      // (srem:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (REM:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::REM,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63395,
      GIR_Done,
    // Label 570: @10183
    GIM_Reject,
    // Label 546: @10184
    GIM_Try, /*On fail goto*//*Label 571*/ 10215, // Rule ID 63394 //
      GIM_CheckFeatures, GIFBS_HasStdExtM,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
      // (srem:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (REM:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::REM,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63394,
      GIR_Done,
    // Label 571: @10215
    GIM_Reject,
    // Label 547: @10216
    GIM_Try, /*On fail goto*//*Label 572*/ 10299,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 573*/ 10268, // Rule ID 60053 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVREM_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60053,
        GIR_Done,
      // Label 573: @10268
      GIM_Try, /*On fail goto*//*Label 574*/ 10298, // Rule ID 60054 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVREM_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60054,
        GIR_Done,
      // Label 574: @10298
      GIM_Reject,
    // Label 572: @10299
    GIM_Reject,
    // Label 548: @10300
    GIM_Try, /*On fail goto*//*Label 575*/ 10383,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 576*/ 10352, // Rule ID 60067 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVREM_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60067,
        GIR_Done,
      // Label 576: @10352
      GIM_Try, /*On fail goto*//*Label 577*/ 10382, // Rule ID 60068 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVREM_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60068,
        GIR_Done,
      // Label 577: @10382
      GIM_Reject,
    // Label 575: @10383
    GIM_Reject,
    // Label 549: @10384
    GIM_Try, /*On fail goto*//*Label 578*/ 10467,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 579*/ 10436, // Rule ID 60075 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVREM_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60075,
        GIR_Done,
      // Label 579: @10436
      GIM_Try, /*On fail goto*//*Label 580*/ 10466, // Rule ID 60076 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVREM_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60076,
        GIR_Done,
      // Label 580: @10466
      GIM_Reject,
    // Label 578: @10467
    GIM_Reject,
    // Label 550: @10468
    GIM_Try, /*On fail goto*//*Label 581*/ 10551,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 582*/ 10520, // Rule ID 60093 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVREM_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60093,
        GIR_Done,
      // Label 582: @10520
      GIM_Try, /*On fail goto*//*Label 583*/ 10550, // Rule ID 60094 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVREM_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60094,
        GIR_Done,
      // Label 583: @10550
      GIM_Reject,
    // Label 581: @10551
    GIM_Reject,
    // Label 551: @10552
    GIM_Try, /*On fail goto*//*Label 584*/ 10635,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 585*/ 10604, // Rule ID 60057 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVREM_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60057,
        GIR_Done,
      // Label 585: @10604
      GIM_Try, /*On fail goto*//*Label 586*/ 10634, // Rule ID 60058 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVREM_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60058,
        GIR_Done,
      // Label 586: @10634
      GIM_Reject,
    // Label 584: @10635
    GIM_Reject,
    // Label 552: @10636
    GIM_Try, /*On fail goto*//*Label 587*/ 10719,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 588*/ 10688, // Rule ID 60071 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVREM_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60071,
        GIR_Done,
      // Label 588: @10688
      GIM_Try, /*On fail goto*//*Label 589*/ 10718, // Rule ID 60072 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVREM_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60072,
        GIR_Done,
      // Label 589: @10718
      GIM_Reject,
    // Label 587: @10719
    GIM_Reject,
    // Label 553: @10720
    GIM_Try, /*On fail goto*//*Label 590*/ 10803,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 591*/ 10772, // Rule ID 60089 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVREM_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60089,
        GIR_Done,
      // Label 591: @10772
      GIM_Try, /*On fail goto*//*Label 592*/ 10802, // Rule ID 60090 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVREM_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60090,
        GIR_Done,
      // Label 592: @10802
      GIM_Reject,
    // Label 590: @10803
    GIM_Reject,
    // Label 554: @10804
    GIM_Try, /*On fail goto*//*Label 593*/ 10887,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 594*/ 10856, // Rule ID 60136 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVREM_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60136,
        GIR_Done,
      // Label 594: @10856
      GIM_Try, /*On fail goto*//*Label 595*/ 10886, // Rule ID 60137 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVREM_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60137,
        GIR_Done,
      // Label 595: @10886
      GIM_Reject,
    // Label 593: @10887
    GIM_Reject,
    // Label 555: @10888
    GIM_Try, /*On fail goto*//*Label 596*/ 10971,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 597*/ 10940, // Rule ID 60061 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVREM_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60061,
        GIR_Done,
      // Label 597: @10940
      GIM_Try, /*On fail goto*//*Label 598*/ 10970, // Rule ID 60062 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVREM_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60062,
        GIR_Done,
      // Label 598: @10970
      GIM_Reject,
    // Label 596: @10971
    GIM_Reject,
    // Label 556: @10972
    GIM_Try, /*On fail goto*//*Label 599*/ 11055,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 600*/ 11024, // Rule ID 60083 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVREM_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60083,
        GIR_Done,
      // Label 600: @11024
      GIM_Try, /*On fail goto*//*Label 601*/ 11054, // Rule ID 60084 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVREM_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60084,
        GIR_Done,
      // Label 601: @11054
      GIM_Reject,
    // Label 599: @11055
    GIM_Reject,
    // Label 557: @11056
    GIM_Try, /*On fail goto*//*Label 602*/ 11139,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 603*/ 11108, // Rule ID 60122 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVREM_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60122,
        GIR_Done,
      // Label 603: @11108
      GIM_Try, /*On fail goto*//*Label 604*/ 11138, // Rule ID 60123 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVREM_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60123,
        GIR_Done,
      // Label 604: @11138
      GIM_Reject,
    // Label 602: @11139
    GIM_Reject,
    // Label 558: @11140
    GIM_Try, /*On fail goto*//*Label 605*/ 11223,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 606*/ 11192, // Rule ID 60140 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVREM_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60140,
        GIR_Done,
      // Label 606: @11192
      GIM_Try, /*On fail goto*//*Label 607*/ 11222, // Rule ID 60141 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVREM_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60141,
        GIR_Done,
      // Label 607: @11222
      GIM_Reject,
    // Label 605: @11223
    GIM_Reject,
    // Label 559: @11224
    GIM_Try, /*On fail goto*//*Label 608*/ 11307,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 609*/ 11276, // Rule ID 60079 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVREM_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60079,
        GIR_Done,
      // Label 609: @11276
      GIM_Try, /*On fail goto*//*Label 610*/ 11306, // Rule ID 60080 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVREM_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60080,
        GIR_Done,
      // Label 610: @11306
      GIM_Reject,
    // Label 608: @11307
    GIM_Reject,
    // Label 560: @11308
    GIM_Try, /*On fail goto*//*Label 611*/ 11391,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 612*/ 11360, // Rule ID 60110 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVREM_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60110,
        GIR_Done,
      // Label 612: @11360
      GIM_Try, /*On fail goto*//*Label 613*/ 11390, // Rule ID 60111 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVREM_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60111,
        GIR_Done,
      // Label 613: @11390
      GIM_Reject,
    // Label 611: @11391
    GIM_Reject,
    // Label 561: @11392
    GIM_Try, /*On fail goto*//*Label 614*/ 11475,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 615*/ 11444, // Rule ID 60126 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVREM_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60126,
        GIR_Done,
      // Label 615: @11444
      GIM_Try, /*On fail goto*//*Label 616*/ 11474, // Rule ID 60127 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVREM_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60127,
        GIR_Done,
      // Label 616: @11474
      GIM_Reject,
    // Label 614: @11475
    GIM_Reject,
    // Label 562: @11476
    GIM_Try, /*On fail goto*//*Label 617*/ 11559,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 618*/ 11528, // Rule ID 60144 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVREM_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60144,
        GIR_Done,
      // Label 618: @11528
      GIM_Try, /*On fail goto*//*Label 619*/ 11558, // Rule ID 60145 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVREM_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60145,
        GIR_Done,
      // Label 619: @11558
      GIM_Reject,
    // Label 617: @11559
    GIM_Reject,
    // Label 563: @11560
    GIM_Try, /*On fail goto*//*Label 620*/ 11643,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 621*/ 11612, // Rule ID 60097 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVREM_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60097,
        GIR_Done,
      // Label 621: @11612
      GIM_Try, /*On fail goto*//*Label 622*/ 11642, // Rule ID 60098 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVREM_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60098,
        GIR_Done,
      // Label 622: @11642
      GIM_Reject,
    // Label 620: @11643
    GIM_Reject,
    // Label 564: @11644
    GIM_Try, /*On fail goto*//*Label 623*/ 11727,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 624*/ 11696, // Rule ID 60114 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVREM_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60114,
        GIR_Done,
      // Label 624: @11696
      GIM_Try, /*On fail goto*//*Label 625*/ 11726, // Rule ID 60115 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVREM_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60115,
        GIR_Done,
      // Label 625: @11726
      GIM_Reject,
    // Label 623: @11727
    GIM_Reject,
    // Label 565: @11728
    GIM_Try, /*On fail goto*//*Label 626*/ 11811,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 627*/ 11780, // Rule ID 60132 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVREM_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60132,
        GIR_Done,
      // Label 627: @11780
      GIM_Try, /*On fail goto*//*Label 628*/ 11810, // Rule ID 60133 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVREM_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60133,
        GIR_Done,
      // Label 628: @11810
      GIM_Reject,
    // Label 626: @11811
    GIM_Reject,
    // Label 566: @11812
    GIM_Try, /*On fail goto*//*Label 629*/ 11895,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 630*/ 11864, // Rule ID 60101 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVREM_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60101,
        GIR_Done,
      // Label 630: @11864
      GIM_Try, /*On fail goto*//*Label 631*/ 11894, // Rule ID 60102 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVREM_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60102,
        GIR_Done,
      // Label 631: @11894
      GIM_Reject,
    // Label 629: @11895
    GIM_Reject,
    // Label 567: @11896
    GIM_Try, /*On fail goto*//*Label 632*/ 11979,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 633*/ 11948, // Rule ID 60118 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVREM_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60118,
        GIR_Done,
      // Label 633: @11948
      GIM_Try, /*On fail goto*//*Label 634*/ 11978, // Rule ID 60119 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVREM_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60119,
        GIR_Done,
      // Label 634: @11978
      GIM_Reject,
    // Label 632: @11979
    GIM_Reject,
    // Label 568: @11980
    GIM_Try, /*On fail goto*//*Label 635*/ 12063,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv64s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 636*/ 12032, // Rule ID 60105 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVREM_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60105,
        GIR_Done,
      // Label 636: @12032
      GIM_Try, /*On fail goto*//*Label 637*/ 12062, // Rule ID 60106 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srem:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVREM_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREM_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60106,
        GIR_Done,
      // Label 637: @12062
      GIM_Reject,
    // Label 635: @12063
    GIM_Reject,
    // Label 569: @12064
    GIM_Reject,
    // Label 6: @12065
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 32, /*)*//*default:*//*Label 662*/ 14014,
    /*GILLT_s32*//*Label 638*/ 12102,
    /*GILLT_s64*//*Label 639*/ 12134, 0,
    /*GILLT_nxv1s8*//*Label 640*/ 12166,
    /*GILLT_nxv1s16*//*Label 641*/ 12250,
    /*GILLT_nxv1s32*//*Label 642*/ 12334,
    /*GILLT_nxv1s64*//*Label 643*/ 12418, 0,
    /*GILLT_nxv2s8*//*Label 644*/ 12502,
    /*GILLT_nxv2s16*//*Label 645*/ 12586,
    /*GILLT_nxv2s32*//*Label 646*/ 12670,
    /*GILLT_nxv2s64*//*Label 647*/ 12754, 0,
    /*GILLT_nxv4s8*//*Label 648*/ 12838,
    /*GILLT_nxv4s16*//*Label 649*/ 12922,
    /*GILLT_nxv4s32*//*Label 650*/ 13006,
    /*GILLT_nxv4s64*//*Label 651*/ 13090, 0,
    /*GILLT_nxv8s8*//*Label 652*/ 13174,
    /*GILLT_nxv8s16*//*Label 653*/ 13258,
    /*GILLT_nxv8s32*//*Label 654*/ 13342,
    /*GILLT_nxv8s64*//*Label 655*/ 13426, 0,
    /*GILLT_nxv16s8*//*Label 656*/ 13510,
    /*GILLT_nxv16s16*//*Label 657*/ 13594,
    /*GILLT_nxv16s32*//*Label 658*/ 13678, 0,
    /*GILLT_nxv32s8*//*Label 659*/ 13762,
    /*GILLT_nxv32s16*//*Label 660*/ 13846, 0,
    /*GILLT_nxv64s8*//*Label 661*/ 13930,
    // Label 638: @12102
    GIM_Try, /*On fail goto*//*Label 663*/ 12133, // Rule ID 63417 //
      GIM_CheckFeatures, GIFBS_HasStdExtM,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
      // (urem:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (REMU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::REMU,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63417,
      GIR_Done,
    // Label 663: @12133
    GIM_Reject,
    // Label 639: @12134
    GIM_Try, /*On fail goto*//*Label 664*/ 12165, // Rule ID 63416 //
      GIM_CheckFeatures, GIFBS_HasStdExtM,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
      // (urem:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (REMU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::REMU,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63416,
      GIR_Done,
    // Label 664: @12165
    GIM_Reject,
    // Label 640: @12166
    GIM_Try, /*On fail goto*//*Label 665*/ 12249,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 666*/ 12218, // Rule ID 59955 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVREMU_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59955,
        GIR_Done,
      // Label 666: @12218
      GIM_Try, /*On fail goto*//*Label 667*/ 12248, // Rule ID 59956 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVREMU_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59956,
        GIR_Done,
      // Label 667: @12248
      GIM_Reject,
    // Label 665: @12249
    GIM_Reject,
    // Label 641: @12250
    GIM_Try, /*On fail goto*//*Label 668*/ 12333,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 669*/ 12302, // Rule ID 59969 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVREMU_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59969,
        GIR_Done,
      // Label 669: @12302
      GIM_Try, /*On fail goto*//*Label 670*/ 12332, // Rule ID 59970 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVREMU_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59970,
        GIR_Done,
      // Label 670: @12332
      GIM_Reject,
    // Label 668: @12333
    GIM_Reject,
    // Label 642: @12334
    GIM_Try, /*On fail goto*//*Label 671*/ 12417,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 672*/ 12386, // Rule ID 59977 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVREMU_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59977,
        GIR_Done,
      // Label 672: @12386
      GIM_Try, /*On fail goto*//*Label 673*/ 12416, // Rule ID 59978 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVREMU_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59978,
        GIR_Done,
      // Label 673: @12416
      GIM_Reject,
    // Label 671: @12417
    GIM_Reject,
    // Label 643: @12418
    GIM_Try, /*On fail goto*//*Label 674*/ 12501,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 675*/ 12470, // Rule ID 59995 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVREMU_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59995,
        GIR_Done,
      // Label 675: @12470
      GIM_Try, /*On fail goto*//*Label 676*/ 12500, // Rule ID 59996 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVREMU_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59996,
        GIR_Done,
      // Label 676: @12500
      GIM_Reject,
    // Label 674: @12501
    GIM_Reject,
    // Label 644: @12502
    GIM_Try, /*On fail goto*//*Label 677*/ 12585,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 678*/ 12554, // Rule ID 59961 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVREMU_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59961,
        GIR_Done,
      // Label 678: @12554
      GIM_Try, /*On fail goto*//*Label 679*/ 12584, // Rule ID 59962 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVREMU_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59962,
        GIR_Done,
      // Label 679: @12584
      GIM_Reject,
    // Label 677: @12585
    GIM_Reject,
    // Label 645: @12586
    GIM_Try, /*On fail goto*//*Label 680*/ 12669,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 681*/ 12638, // Rule ID 59973 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVREMU_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59973,
        GIR_Done,
      // Label 681: @12638
      GIM_Try, /*On fail goto*//*Label 682*/ 12668, // Rule ID 59974 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVREMU_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59974,
        GIR_Done,
      // Label 682: @12668
      GIM_Reject,
    // Label 680: @12669
    GIM_Reject,
    // Label 646: @12670
    GIM_Try, /*On fail goto*//*Label 683*/ 12753,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 684*/ 12722, // Rule ID 59991 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVREMU_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59991,
        GIR_Done,
      // Label 684: @12722
      GIM_Try, /*On fail goto*//*Label 685*/ 12752, // Rule ID 59992 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVREMU_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59992,
        GIR_Done,
      // Label 685: @12752
      GIM_Reject,
    // Label 683: @12753
    GIM_Reject,
    // Label 647: @12754
    GIM_Try, /*On fail goto*//*Label 686*/ 12837,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 687*/ 12806, // Rule ID 60039 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVREMU_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60039,
        GIR_Done,
      // Label 687: @12806
      GIM_Try, /*On fail goto*//*Label 688*/ 12836, // Rule ID 60040 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVREMU_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60040,
        GIR_Done,
      // Label 688: @12836
      GIM_Reject,
    // Label 686: @12837
    GIM_Reject,
    // Label 648: @12838
    GIM_Try, /*On fail goto*//*Label 689*/ 12921,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 690*/ 12890, // Rule ID 59965 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVREMU_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59965,
        GIR_Done,
      // Label 690: @12890
      GIM_Try, /*On fail goto*//*Label 691*/ 12920, // Rule ID 59966 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVREMU_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59966,
        GIR_Done,
      // Label 691: @12920
      GIM_Reject,
    // Label 689: @12921
    GIM_Reject,
    // Label 649: @12922
    GIM_Try, /*On fail goto*//*Label 692*/ 13005,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 693*/ 12974, // Rule ID 59987 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVREMU_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59987,
        GIR_Done,
      // Label 693: @12974
      GIM_Try, /*On fail goto*//*Label 694*/ 13004, // Rule ID 59988 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVREMU_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59988,
        GIR_Done,
      // Label 694: @13004
      GIM_Reject,
    // Label 692: @13005
    GIM_Reject,
    // Label 650: @13006
    GIM_Try, /*On fail goto*//*Label 695*/ 13089,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 696*/ 13058, // Rule ID 60027 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVREMU_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60027,
        GIR_Done,
      // Label 696: @13058
      GIM_Try, /*On fail goto*//*Label 697*/ 13088, // Rule ID 60028 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVREMU_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60028,
        GIR_Done,
      // Label 697: @13088
      GIM_Reject,
    // Label 695: @13089
    GIM_Reject,
    // Label 651: @13090
    GIM_Try, /*On fail goto*//*Label 698*/ 13173,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 699*/ 13142, // Rule ID 60043 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVREMU_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60043,
        GIR_Done,
      // Label 699: @13142
      GIM_Try, /*On fail goto*//*Label 700*/ 13172, // Rule ID 60044 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVREMU_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60044,
        GIR_Done,
      // Label 700: @13172
      GIM_Reject,
    // Label 698: @13173
    GIM_Reject,
    // Label 652: @13174
    GIM_Try, /*On fail goto*//*Label 701*/ 13257,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 702*/ 13226, // Rule ID 59983 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVREMU_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59983,
        GIR_Done,
      // Label 702: @13226
      GIM_Try, /*On fail goto*//*Label 703*/ 13256, // Rule ID 59984 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVREMU_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59984,
        GIR_Done,
      // Label 703: @13256
      GIM_Reject,
    // Label 701: @13257
    GIM_Reject,
    // Label 653: @13258
    GIM_Try, /*On fail goto*//*Label 704*/ 13341,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 705*/ 13310, // Rule ID 60013 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVREMU_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60013,
        GIR_Done,
      // Label 705: @13310
      GIM_Try, /*On fail goto*//*Label 706*/ 13340, // Rule ID 60014 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVREMU_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60014,
        GIR_Done,
      // Label 706: @13340
      GIM_Reject,
    // Label 704: @13341
    GIM_Reject,
    // Label 654: @13342
    GIM_Try, /*On fail goto*//*Label 707*/ 13425,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 708*/ 13394, // Rule ID 60031 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVREMU_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60031,
        GIR_Done,
      // Label 708: @13394
      GIM_Try, /*On fail goto*//*Label 709*/ 13424, // Rule ID 60032 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVREMU_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60032,
        GIR_Done,
      // Label 709: @13424
      GIM_Reject,
    // Label 707: @13425
    GIM_Reject,
    // Label 655: @13426
    GIM_Try, /*On fail goto*//*Label 710*/ 13509,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 711*/ 13478, // Rule ID 60049 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVREMU_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60049,
        GIR_Done,
      // Label 711: @13478
      GIM_Try, /*On fail goto*//*Label 712*/ 13508, // Rule ID 60050 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVREMU_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60050,
        GIR_Done,
      // Label 712: @13508
      GIM_Reject,
    // Label 710: @13509
    GIM_Reject,
    // Label 656: @13510
    GIM_Try, /*On fail goto*//*Label 713*/ 13593,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 714*/ 13562, // Rule ID 59999 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVREMU_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59999,
        GIR_Done,
      // Label 714: @13562
      GIM_Try, /*On fail goto*//*Label 715*/ 13592, // Rule ID 60000 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVREMU_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60000,
        GIR_Done,
      // Label 715: @13592
      GIM_Reject,
    // Label 713: @13593
    GIM_Reject,
    // Label 657: @13594
    GIM_Try, /*On fail goto*//*Label 716*/ 13677,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 717*/ 13646, // Rule ID 60017 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVREMU_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60017,
        GIR_Done,
      // Label 717: @13646
      GIM_Try, /*On fail goto*//*Label 718*/ 13676, // Rule ID 60018 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVREMU_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60018,
        GIR_Done,
      // Label 718: @13676
      GIM_Reject,
    // Label 716: @13677
    GIM_Reject,
    // Label 658: @13678
    GIM_Try, /*On fail goto*//*Label 719*/ 13761,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 720*/ 13730, // Rule ID 60035 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVREMU_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60035,
        GIR_Done,
      // Label 720: @13730
      GIM_Try, /*On fail goto*//*Label 721*/ 13760, // Rule ID 60036 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVREMU_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60036,
        GIR_Done,
      // Label 721: @13760
      GIM_Reject,
    // Label 719: @13761
    GIM_Reject,
    // Label 659: @13762
    GIM_Try, /*On fail goto*//*Label 722*/ 13845,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 723*/ 13814, // Rule ID 60005 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVREMU_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60005,
        GIR_Done,
      // Label 723: @13814
      GIM_Try, /*On fail goto*//*Label 724*/ 13844, // Rule ID 60006 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVREMU_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60006,
        GIR_Done,
      // Label 724: @13844
      GIM_Reject,
    // Label 722: @13845
    GIM_Reject,
    // Label 660: @13846
    GIM_Try, /*On fail goto*//*Label 725*/ 13929,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 726*/ 13898, // Rule ID 60021 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVREMU_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60021,
        GIR_Done,
      // Label 726: @13898
      GIM_Try, /*On fail goto*//*Label 727*/ 13928, // Rule ID 60022 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVREMU_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60022,
        GIR_Done,
      // Label 727: @13928
      GIM_Reject,
    // Label 725: @13929
    GIM_Reject,
    // Label 661: @13930
    GIM_Try, /*On fail goto*//*Label 728*/ 14013,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv64s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 729*/ 13982, // Rule ID 60009 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVREMU_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60009,
        GIR_Done,
      // Label 729: @13982
      GIM_Try, /*On fail goto*//*Label 730*/ 14012, // Rule ID 60010 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (urem:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVREMU_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVREMU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60010,
        GIR_Done,
      // Label 730: @14012
      GIM_Reject,
    // Label 728: @14013
    GIM_Reject,
    // Label 662: @14014
    GIM_Reject,
    // Label 7: @14015
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 32, /*)*//*default:*//*Label 762*/ 17310,
    /*GILLT_s32*//*Label 731*/ 14052,
    /*GILLT_s64*//*Label 732*/ 14422,
    /*GILLT_nxv1s1*//*Label 733*/ 14874,
    /*GILLT_nxv1s8*//*Label 734*/ 14958,
    /*GILLT_nxv1s16*//*Label 735*/ 15042,
    /*GILLT_nxv1s32*//*Label 736*/ 15126,
    /*GILLT_nxv1s64*//*Label 737*/ 15210,
    /*GILLT_nxv2s1*//*Label 738*/ 15294,
    /*GILLT_nxv2s8*//*Label 739*/ 15378,
    /*GILLT_nxv2s16*//*Label 740*/ 15462,
    /*GILLT_nxv2s32*//*Label 741*/ 15546,
    /*GILLT_nxv2s64*//*Label 742*/ 15630,
    /*GILLT_nxv4s1*//*Label 743*/ 15714,
    /*GILLT_nxv4s8*//*Label 744*/ 15798,
    /*GILLT_nxv4s16*//*Label 745*/ 15882,
    /*GILLT_nxv4s32*//*Label 746*/ 15966,
    /*GILLT_nxv4s64*//*Label 747*/ 16050,
    /*GILLT_nxv8s1*//*Label 748*/ 16134,
    /*GILLT_nxv8s8*//*Label 749*/ 16218,
    /*GILLT_nxv8s16*//*Label 750*/ 16302,
    /*GILLT_nxv8s32*//*Label 751*/ 16386,
    /*GILLT_nxv8s64*//*Label 752*/ 16470,
    /*GILLT_nxv16s1*//*Label 753*/ 16554,
    /*GILLT_nxv16s8*//*Label 754*/ 16638,
    /*GILLT_nxv16s16*//*Label 755*/ 16722,
    /*GILLT_nxv16s32*//*Label 756*/ 16806,
    /*GILLT_nxv32s1*//*Label 757*/ 16890,
    /*GILLT_nxv32s8*//*Label 758*/ 16974,
    /*GILLT_nxv32s16*//*Label 759*/ 17058,
    /*GILLT_nxv64s1*//*Label 760*/ 17142,
    /*GILLT_nxv64s8*//*Label 761*/ 17226,
    // Label 731: @14052
    GIM_Try, /*On fail goto*//*Label 763*/ 14421,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_Try, /*On fail goto*//*Label 764*/ 14126, // Rule ID 65470 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbs,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen,
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt), 1:{ *:[i32] })  =>  (BEXTI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::BEXTI,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shamt
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65470,
        GIR_Done,
      // Label 764: @14126
      GIM_Try, /*On fail goto*//*Label 765*/ 14179, // Rule ID 65454 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbs,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ROTL,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (and:{ *:[i32] } (rotl:{ *:[i32] } -2:{ *:[i32] }, GPR:{ *:[i32] }:$rs2), GPR:{ *:[i32] }:$rs1)  =>  (BCLR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::BCLR,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65454,
        GIR_Done,
      // Label 765: @14179
      GIM_Try, /*On fail goto*//*Label 766*/ 14232, // Rule ID 72085 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbbOrZbkb,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (and:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs2, -1:{ *:[i32] }), GPR:{ *:[i32] }:$rs1)  =>  (ANDN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ANDN,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72085,
        GIR_Done,
      // Label 766: @14232
      GIM_Try, /*On fail goto*//*Label 767*/ 14285, // Rule ID 72095 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbs,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ROTL,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (rotl:{ *:[i32] } -2:{ *:[i32] }, GPR:{ *:[i32] }:$rs2))  =>  (BCLR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::BCLR,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72095,
        GIR_Done,
      // Label 767: @14285
      GIM_Try, /*On fail goto*//*Label 768*/ 14338, // Rule ID 65434 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbbOrZbkb,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs2, -1:{ *:[i32] }))  =>  (ANDN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ANDN,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65434,
        GIR_Done,
      // Label 768: @14338
      GIM_Try, /*On fail goto*//*Label 769*/ 14366, // Rule ID 65525 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbb_IsRV32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535,
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs, 65535:{ *:[i32] })  =>  (ZEXT_H_RV32:{ *:[i32] } GPR:{ *:[i32] }:$rs)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ZEXT_H_RV32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65525,
        GIR_Done,
      // Label 769: @14366
      GIM_Try, /*On fail goto*//*Label 770*/ 14403, // Rule ID 59938 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm)  =>  (ANDI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ANDI,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59938,
        GIR_Done,
      // Label 770: @14403
      GIM_Try, /*On fail goto*//*Label 771*/ 14420, // Rule ID 59916 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (AND:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AND,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59916,
        GIR_Done,
      // Label 771: @14420
      GIM_Reject,
    // Label 763: @14421
    GIM_Reject,
    // Label 732: @14422
    GIM_Try, /*On fail goto*//*Label 772*/ 14873,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_Try, /*On fail goto*//*Label 773*/ 14496, // Rule ID 65469 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbs,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_LSHR,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen,
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (and:{ *:[i64] } (srl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt), 1:{ *:[i64] })  =>  (BEXTI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::BEXTI,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shamt
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65469,
        GIR_Done,
      // Label 773: @14496
      GIM_Try, /*On fail goto*//*Label 774*/ 14549, // Rule ID 65453 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbs,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ROTL,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (and:{ *:[i64] } (rotl:{ *:[i64] } -2:{ *:[i64] }, GPR:{ *:[i64] }:$rs2), GPR:{ *:[i64] }:$rs1)  =>  (BCLR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::BCLR,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65453,
        GIR_Done,
      // Label 774: @14549
      GIM_Try, /*On fail goto*//*Label 775*/ 14602, // Rule ID 72084 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbbOrZbkb,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (and:{ *:[i64] } (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs2, -1:{ *:[i64] }), GPR:{ *:[i64] }:$rs1)  =>  (ANDN:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ANDN,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72084,
        GIR_Done,
      // Label 775: @14602
      GIM_Try, /*On fail goto*//*Label 776*/ 14655, // Rule ID 72094 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbs,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ROTL,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckConstantInt, /*MI*/1, /*Op*/1, -2,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (rotl:{ *:[i64] } -2:{ *:[i64] }, GPR:{ *:[i64] }:$rs2))  =>  (BCLR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::BCLR,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72094,
        GIR_Done,
      // Label 776: @14655
      GIM_Try, /*On fail goto*//*Label 777*/ 14708, // Rule ID 65433 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbbOrZbkb,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs2, -1:{ *:[i64] }))  =>  (ANDN:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ANDN,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65433,
        GIR_Done,
      // Label 777: @14708
      GIM_Try, /*On fail goto*//*Label 778*/ 14758, // Rule ID 62198 //
        GIM_CheckFeatures, GIFBS_IsRV64_NotHasStdExtZba,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 4294967295,
        // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] })  =>  (SRLI:{ *:[i64] } (SLLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 32:{ *:[i64] }), 32:{ *:[i64] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLLI,
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/1, /*Imm*/32,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRLI,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
        GIR_AddImm, /*InsnID*/0, /*Imm*/32,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62198,
        GIR_Done,
      // Label 778: @14758
      GIM_Try, /*On fail goto*//*Label 779*/ 14786, // Rule ID 65526 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbb_IsRV64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 65535,
        // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs, 65535:{ *:[i64] })  =>  (ZEXT_H_RV64:{ *:[i64] } GPR:{ *:[i64] }:$rs)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ZEXT_H_RV64,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65526,
        GIR_Done,
      // Label 779: @14786
      GIM_Try, /*On fail goto*//*Label 780*/ 14818, // Rule ID 65592 //
        GIM_CheckFeatures, GIFBS_HasStdExtZba_IsRV64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 4294967295,
        // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs, 4294967295:{ *:[i64] })  =>  (ADD_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs, X0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADD_UW,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65592,
        GIR_Done,
      // Label 780: @14818
      GIM_Try, /*On fail goto*//*Label 781*/ 14855, // Rule ID 59937 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm)  =>  (ANDI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ANDI,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59937,
        GIR_Done,
      // Label 781: @14855
      GIM_Try, /*On fail goto*//*Label 782*/ 14872, // Rule ID 59915 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (AND:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AND,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59915,
        GIR_Done,
      // Label 782: @14872
      GIM_Reject,
    // Label 772: @14873
    GIM_Reject,
    // Label 733: @14874
    GIM_Try, /*On fail goto*//*Label 783*/ 14957,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 784*/ 14926, // Rule ID 61576 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2)  =>  (PseudoVMAND_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAND_MM_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61576,
        GIR_Done,
      // Label 784: @14926
      GIM_Try, /*On fail goto*//*Label 785*/ 14956, // Rule ID 61577 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2)  =>  (PseudoVMAND_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAND_MM_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61577,
        GIR_Done,
      // Label 785: @14956
      GIM_Reject,
    // Label 783: @14957
    GIM_Reject,
    // Label 734: @14958
    GIM_Try, /*On fail goto*//*Label 786*/ 15041,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 787*/ 15010, // Rule ID 56389 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVAND_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56389,
        GIR_Done,
      // Label 787: @15010
      GIM_Try, /*On fail goto*//*Label 788*/ 15040, // Rule ID 56390 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVAND_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56390,
        GIR_Done,
      // Label 788: @15040
      GIM_Reject,
    // Label 786: @15041
    GIM_Reject,
    // Label 735: @15042
    GIM_Try, /*On fail goto*//*Label 789*/ 15125,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 790*/ 15094, // Rule ID 56401 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVAND_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56401,
        GIR_Done,
      // Label 790: @15094
      GIM_Try, /*On fail goto*//*Label 791*/ 15124, // Rule ID 56402 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVAND_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56402,
        GIR_Done,
      // Label 791: @15124
      GIM_Reject,
    // Label 789: @15125
    GIM_Reject,
    // Label 736: @15126
    GIM_Try, /*On fail goto*//*Label 792*/ 15209,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 793*/ 15178, // Rule ID 56409 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVAND_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56409,
        GIR_Done,
      // Label 793: @15178
      GIM_Try, /*On fail goto*//*Label 794*/ 15208, // Rule ID 56410 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVAND_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56410,
        GIR_Done,
      // Label 794: @15208
      GIM_Reject,
    // Label 792: @15209
    GIM_Reject,
    // Label 737: @15210
    GIM_Try, /*On fail goto*//*Label 795*/ 15293,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 796*/ 15262, // Rule ID 56425 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVAND_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56425,
        GIR_Done,
      // Label 796: @15262
      GIM_Try, /*On fail goto*//*Label 797*/ 15292, // Rule ID 56426 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVAND_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56426,
        GIR_Done,
      // Label 797: @15292
      GIM_Reject,
    // Label 795: @15293
    GIM_Reject,
    // Label 738: @15294
    GIM_Try, /*On fail goto*//*Label 798*/ 15377,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 799*/ 15346, // Rule ID 61596 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2)  =>  (PseudoVMAND_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAND_MM_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61596,
        GIR_Done,
      // Label 799: @15346
      GIM_Try, /*On fail goto*//*Label 800*/ 15376, // Rule ID 61597 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2)  =>  (PseudoVMAND_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAND_MM_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61597,
        GIR_Done,
      // Label 800: @15376
      GIM_Reject,
    // Label 798: @15377
    GIM_Reject,
    // Label 739: @15378
    GIM_Try, /*On fail goto*//*Label 801*/ 15461,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 802*/ 15430, // Rule ID 56393 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVAND_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56393,
        GIR_Done,
      // Label 802: @15430
      GIM_Try, /*On fail goto*//*Label 803*/ 15460, // Rule ID 56394 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVAND_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56394,
        GIR_Done,
      // Label 803: @15460
      GIM_Reject,
    // Label 801: @15461
    GIM_Reject,
    // Label 740: @15462
    GIM_Try, /*On fail goto*//*Label 804*/ 15545,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 805*/ 15514, // Rule ID 56405 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVAND_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56405,
        GIR_Done,
      // Label 805: @15514
      GIM_Try, /*On fail goto*//*Label 806*/ 15544, // Rule ID 56406 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVAND_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56406,
        GIR_Done,
      // Label 806: @15544
      GIM_Reject,
    // Label 804: @15545
    GIM_Reject,
    // Label 741: @15546
    GIM_Try, /*On fail goto*//*Label 807*/ 15629,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 808*/ 15598, // Rule ID 56421 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVAND_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56421,
        GIR_Done,
      // Label 808: @15598
      GIM_Try, /*On fail goto*//*Label 809*/ 15628, // Rule ID 56422 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVAND_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56422,
        GIR_Done,
      // Label 809: @15628
      GIM_Reject,
    // Label 807: @15629
    GIM_Reject,
    // Label 742: @15630
    GIM_Try, /*On fail goto*//*Label 810*/ 15713,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 811*/ 15682, // Rule ID 56465 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVAND_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56465,
        GIR_Done,
      // Label 811: @15682
      GIM_Try, /*On fail goto*//*Label 812*/ 15712, // Rule ID 56466 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVAND_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56466,
        GIR_Done,
      // Label 812: @15712
      GIM_Reject,
    // Label 810: @15713
    GIM_Reject,
    // Label 743: @15714
    GIM_Try, /*On fail goto*//*Label 813*/ 15797,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 814*/ 15766, // Rule ID 61616 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2)  =>  (PseudoVMAND_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAND_MM_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61616,
        GIR_Done,
      // Label 814: @15766
      GIM_Try, /*On fail goto*//*Label 815*/ 15796, // Rule ID 61617 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2)  =>  (PseudoVMAND_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAND_MM_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61617,
        GIR_Done,
      // Label 815: @15796
      GIM_Reject,
    // Label 813: @15797
    GIM_Reject,
    // Label 744: @15798
    GIM_Try, /*On fail goto*//*Label 816*/ 15881,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 817*/ 15850, // Rule ID 56397 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVAND_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56397,
        GIR_Done,
      // Label 817: @15850
      GIM_Try, /*On fail goto*//*Label 818*/ 15880, // Rule ID 56398 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVAND_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56398,
        GIR_Done,
      // Label 818: @15880
      GIM_Reject,
    // Label 816: @15881
    GIM_Reject,
    // Label 745: @15882
    GIM_Try, /*On fail goto*//*Label 819*/ 15965,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 820*/ 15934, // Rule ID 56417 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVAND_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56417,
        GIR_Done,
      // Label 820: @15934
      GIM_Try, /*On fail goto*//*Label 821*/ 15964, // Rule ID 56418 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVAND_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56418,
        GIR_Done,
      // Label 821: @15964
      GIM_Reject,
    // Label 819: @15965
    GIM_Reject,
    // Label 746: @15966
    GIM_Try, /*On fail goto*//*Label 822*/ 16049,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 823*/ 16018, // Rule ID 56453 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVAND_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56453,
        GIR_Done,
      // Label 823: @16018
      GIM_Try, /*On fail goto*//*Label 824*/ 16048, // Rule ID 56454 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVAND_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56454,
        GIR_Done,
      // Label 824: @16048
      GIM_Reject,
    // Label 822: @16049
    GIM_Reject,
    // Label 747: @16050
    GIM_Try, /*On fail goto*//*Label 825*/ 16133,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 826*/ 16102, // Rule ID 56469 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVAND_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56469,
        GIR_Done,
      // Label 826: @16102
      GIM_Try, /*On fail goto*//*Label 827*/ 16132, // Rule ID 56470 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVAND_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56470,
        GIR_Done,
      // Label 827: @16132
      GIM_Reject,
    // Label 825: @16133
    GIM_Reject,
    // Label 748: @16134
    GIM_Try, /*On fail goto*//*Label 828*/ 16217,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 829*/ 16186, // Rule ID 61634 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2)  =>  (PseudoVMAND_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAND_MM_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61634,
        GIR_Done,
      // Label 829: @16186
      GIM_Try, /*On fail goto*//*Label 830*/ 16216, // Rule ID 61635 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2)  =>  (PseudoVMAND_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAND_MM_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61635,
        GIR_Done,
      // Label 830: @16216
      GIM_Reject,
    // Label 828: @16217
    GIM_Reject,
    // Label 749: @16218
    GIM_Try, /*On fail goto*//*Label 831*/ 16301,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 832*/ 16270, // Rule ID 56413 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVAND_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56413,
        GIR_Done,
      // Label 832: @16270
      GIM_Try, /*On fail goto*//*Label 833*/ 16300, // Rule ID 56414 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVAND_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56414,
        GIR_Done,
      // Label 833: @16300
      GIM_Reject,
    // Label 831: @16301
    GIM_Reject,
    // Label 750: @16302
    GIM_Try, /*On fail goto*//*Label 834*/ 16385,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 835*/ 16354, // Rule ID 56441 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVAND_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56441,
        GIR_Done,
      // Label 835: @16354
      GIM_Try, /*On fail goto*//*Label 836*/ 16384, // Rule ID 56442 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVAND_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56442,
        GIR_Done,
      // Label 836: @16384
      GIM_Reject,
    // Label 834: @16385
    GIM_Reject,
    // Label 751: @16386
    GIM_Try, /*On fail goto*//*Label 837*/ 16469,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 838*/ 16438, // Rule ID 56457 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVAND_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56457,
        GIR_Done,
      // Label 838: @16438
      GIM_Try, /*On fail goto*//*Label 839*/ 16468, // Rule ID 56458 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVAND_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56458,
        GIR_Done,
      // Label 839: @16468
      GIM_Reject,
    // Label 837: @16469
    GIM_Reject,
    // Label 752: @16470
    GIM_Try, /*On fail goto*//*Label 840*/ 16553,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 841*/ 16522, // Rule ID 56473 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVAND_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56473,
        GIR_Done,
      // Label 841: @16522
      GIM_Try, /*On fail goto*//*Label 842*/ 16552, // Rule ID 56474 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVAND_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56474,
        GIR_Done,
      // Label 842: @16552
      GIM_Reject,
    // Label 840: @16553
    GIM_Reject,
    // Label 753: @16554
    GIM_Try, /*On fail goto*//*Label 843*/ 16637,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 844*/ 16606, // Rule ID 61654 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2)  =>  (PseudoVMAND_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAND_MM_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61654,
        GIR_Done,
      // Label 844: @16606
      GIM_Try, /*On fail goto*//*Label 845*/ 16636, // Rule ID 61655 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2)  =>  (PseudoVMAND_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAND_MM_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61655,
        GIR_Done,
      // Label 845: @16636
      GIM_Reject,
    // Label 843: @16637
    GIM_Reject,
    // Label 754: @16638
    GIM_Try, /*On fail goto*//*Label 846*/ 16721,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 847*/ 16690, // Rule ID 56429 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVAND_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56429,
        GIR_Done,
      // Label 847: @16690
      GIM_Try, /*On fail goto*//*Label 848*/ 16720, // Rule ID 56430 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVAND_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56430,
        GIR_Done,
      // Label 848: @16720
      GIM_Reject,
    // Label 846: @16721
    GIM_Reject,
    // Label 755: @16722
    GIM_Try, /*On fail goto*//*Label 849*/ 16805,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 850*/ 16774, // Rule ID 56445 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVAND_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56445,
        GIR_Done,
      // Label 850: @16774
      GIM_Try, /*On fail goto*//*Label 851*/ 16804, // Rule ID 56446 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVAND_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56446,
        GIR_Done,
      // Label 851: @16804
      GIM_Reject,
    // Label 849: @16805
    GIM_Reject,
    // Label 756: @16806
    GIM_Try, /*On fail goto*//*Label 852*/ 16889,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 853*/ 16858, // Rule ID 56461 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVAND_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56461,
        GIR_Done,
      // Label 853: @16858
      GIM_Try, /*On fail goto*//*Label 854*/ 16888, // Rule ID 56462 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVAND_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56462,
        GIR_Done,
      // Label 854: @16888
      GIM_Reject,
    // Label 852: @16889
    GIM_Reject,
    // Label 757: @16890
    GIM_Try, /*On fail goto*//*Label 855*/ 16973,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 856*/ 16942, // Rule ID 61672 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2)  =>  (PseudoVMAND_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAND_MM_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61672,
        GIR_Done,
      // Label 856: @16942
      GIM_Try, /*On fail goto*//*Label 857*/ 16972, // Rule ID 61673 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2)  =>  (PseudoVMAND_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAND_MM_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61673,
        GIR_Done,
      // Label 857: @16972
      GIM_Reject,
    // Label 855: @16973
    GIM_Reject,
    // Label 758: @16974
    GIM_Try, /*On fail goto*//*Label 858*/ 17057,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 859*/ 17026, // Rule ID 56433 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVAND_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56433,
        GIR_Done,
      // Label 859: @17026
      GIM_Try, /*On fail goto*//*Label 860*/ 17056, // Rule ID 56434 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVAND_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56434,
        GIR_Done,
      // Label 860: @17056
      GIM_Reject,
    // Label 858: @17057
    GIM_Reject,
    // Label 759: @17058
    GIM_Try, /*On fail goto*//*Label 861*/ 17141,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 862*/ 17110, // Rule ID 56449 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVAND_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56449,
        GIR_Done,
      // Label 862: @17110
      GIM_Try, /*On fail goto*//*Label 863*/ 17140, // Rule ID 56450 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVAND_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56450,
        GIR_Done,
      // Label 863: @17140
      GIM_Reject,
    // Label 861: @17141
    GIM_Reject,
    // Label 760: @17142
    GIM_Try, /*On fail goto*//*Label 864*/ 17225,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv64s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 865*/ 17194, // Rule ID 61690 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2)  =>  (PseudoVMAND_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAND_MM_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61690,
        GIR_Done,
      // Label 865: @17194
      GIM_Try, /*On fail goto*//*Label 866*/ 17224, // Rule ID 61691 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2)  =>  (PseudoVMAND_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAND_MM_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61691,
        GIR_Done,
      // Label 866: @17224
      GIM_Reject,
    // Label 864: @17225
    GIM_Reject,
    // Label 761: @17226
    GIM_Try, /*On fail goto*//*Label 867*/ 17309,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv64s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 868*/ 17278, // Rule ID 56437 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVAND_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56437,
        GIR_Done,
      // Label 868: @17278
      GIM_Try, /*On fail goto*//*Label 869*/ 17308, // Rule ID 56438 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (and:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVAND_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVAND_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56438,
        GIR_Done,
      // Label 869: @17308
      GIM_Reject,
    // Label 867: @17309
    GIM_Reject,
    // Label 762: @17310
    GIM_Reject,
    // Label 8: @17311
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 32, /*)*//*default:*//*Label 901*/ 20136,
    /*GILLT_s32*//*Label 870*/ 17348,
    /*GILLT_s64*//*Label 871*/ 17524,
    /*GILLT_nxv1s1*//*Label 872*/ 17700,
    /*GILLT_nxv1s8*//*Label 873*/ 17784,
    /*GILLT_nxv1s16*//*Label 874*/ 17868,
    /*GILLT_nxv1s32*//*Label 875*/ 17952,
    /*GILLT_nxv1s64*//*Label 876*/ 18036,
    /*GILLT_nxv2s1*//*Label 877*/ 18120,
    /*GILLT_nxv2s8*//*Label 878*/ 18204,
    /*GILLT_nxv2s16*//*Label 879*/ 18288,
    /*GILLT_nxv2s32*//*Label 880*/ 18372,
    /*GILLT_nxv2s64*//*Label 881*/ 18456,
    /*GILLT_nxv4s1*//*Label 882*/ 18540,
    /*GILLT_nxv4s8*//*Label 883*/ 18624,
    /*GILLT_nxv4s16*//*Label 884*/ 18708,
    /*GILLT_nxv4s32*//*Label 885*/ 18792,
    /*GILLT_nxv4s64*//*Label 886*/ 18876,
    /*GILLT_nxv8s1*//*Label 887*/ 18960,
    /*GILLT_nxv8s8*//*Label 888*/ 19044,
    /*GILLT_nxv8s16*//*Label 889*/ 19128,
    /*GILLT_nxv8s32*//*Label 890*/ 19212,
    /*GILLT_nxv8s64*//*Label 891*/ 19296,
    /*GILLT_nxv16s1*//*Label 892*/ 19380,
    /*GILLT_nxv16s8*//*Label 893*/ 19464,
    /*GILLT_nxv16s16*//*Label 894*/ 19548,
    /*GILLT_nxv16s32*//*Label 895*/ 19632,
    /*GILLT_nxv32s1*//*Label 896*/ 19716,
    /*GILLT_nxv32s8*//*Label 897*/ 19800,
    /*GILLT_nxv32s16*//*Label 898*/ 19884,
    /*GILLT_nxv64s1*//*Label 899*/ 19968,
    /*GILLT_nxv64s8*//*Label 900*/ 20052,
    // Label 870: @17348
    GIM_Try, /*On fail goto*//*Label 902*/ 17523,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_Try, /*On fail goto*//*Label 903*/ 17415, // Rule ID 72087 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbbOrZbkb,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (or:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs2, -1:{ *:[i32] }), GPR:{ *:[i32] }:$rs1)  =>  (ORN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ORN,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72087,
        GIR_Done,
      // Label 903: @17415
      GIM_Try, /*On fail goto*//*Label 904*/ 17468, // Rule ID 65436 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbbOrZbkb,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs2, -1:{ *:[i32] }))  =>  (ORN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ORN,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65436,
        GIR_Done,
      // Label 904: @17468
      GIM_Try, /*On fail goto*//*Label 905*/ 17505, // Rule ID 59894 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm)  =>  (ORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ORI,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59894,
        GIR_Done,
      // Label 905: @17505
      GIM_Try, /*On fail goto*//*Label 906*/ 17522, // Rule ID 59872 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (OR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::OR,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59872,
        GIR_Done,
      // Label 906: @17522
      GIM_Reject,
    // Label 902: @17523
    GIM_Reject,
    // Label 871: @17524
    GIM_Try, /*On fail goto*//*Label 907*/ 17699,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_Try, /*On fail goto*//*Label 908*/ 17591, // Rule ID 72086 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbbOrZbkb,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (or:{ *:[i64] } (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs2, -1:{ *:[i64] }), GPR:{ *:[i64] }:$rs1)  =>  (ORN:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ORN,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72086,
        GIR_Done,
      // Label 908: @17591
      GIM_Try, /*On fail goto*//*Label 909*/ 17644, // Rule ID 65435 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbbOrZbkb,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs2, -1:{ *:[i64] }))  =>  (ORN:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ORN,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65435,
        GIR_Done,
      // Label 909: @17644
      GIM_Try, /*On fail goto*//*Label 910*/ 17681, // Rule ID 59893 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm)  =>  (ORI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ORI,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59893,
        GIR_Done,
      // Label 910: @17681
      GIM_Try, /*On fail goto*//*Label 911*/ 17698, // Rule ID 59871 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (OR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::OR,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59871,
        GIR_Done,
      // Label 911: @17698
      GIM_Reject,
    // Label 907: @17699
    GIM_Reject,
    // Label 872: @17700
    GIM_Try, /*On fail goto*//*Label 912*/ 17783,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 913*/ 17752, // Rule ID 61578 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2)  =>  (PseudoVMOR_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMOR_MM_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61578,
        GIR_Done,
      // Label 913: @17752
      GIM_Try, /*On fail goto*//*Label 914*/ 17782, // Rule ID 61579 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2)  =>  (PseudoVMOR_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMOR_MM_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61579,
        GIR_Done,
      // Label 914: @17782
      GIM_Reject,
    // Label 912: @17783
    GIM_Reject,
    // Label 873: @17784
    GIM_Try, /*On fail goto*//*Label 915*/ 17867,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 916*/ 17836, // Rule ID 56521 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVOR_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56521,
        GIR_Done,
      // Label 916: @17836
      GIM_Try, /*On fail goto*//*Label 917*/ 17866, // Rule ID 56522 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVOR_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56522,
        GIR_Done,
      // Label 917: @17866
      GIM_Reject,
    // Label 915: @17867
    GIM_Reject,
    // Label 874: @17868
    GIM_Try, /*On fail goto*//*Label 918*/ 17951,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 919*/ 17920, // Rule ID 56533 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVOR_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56533,
        GIR_Done,
      // Label 919: @17920
      GIM_Try, /*On fail goto*//*Label 920*/ 17950, // Rule ID 56534 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVOR_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56534,
        GIR_Done,
      // Label 920: @17950
      GIM_Reject,
    // Label 918: @17951
    GIM_Reject,
    // Label 875: @17952
    GIM_Try, /*On fail goto*//*Label 921*/ 18035,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 922*/ 18004, // Rule ID 56541 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVOR_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56541,
        GIR_Done,
      // Label 922: @18004
      GIM_Try, /*On fail goto*//*Label 923*/ 18034, // Rule ID 56542 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVOR_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56542,
        GIR_Done,
      // Label 923: @18034
      GIM_Reject,
    // Label 921: @18035
    GIM_Reject,
    // Label 876: @18036
    GIM_Try, /*On fail goto*//*Label 924*/ 18119,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 925*/ 18088, // Rule ID 56557 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVOR_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56557,
        GIR_Done,
      // Label 925: @18088
      GIM_Try, /*On fail goto*//*Label 926*/ 18118, // Rule ID 56558 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVOR_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56558,
        GIR_Done,
      // Label 926: @18118
      GIM_Reject,
    // Label 924: @18119
    GIM_Reject,
    // Label 877: @18120
    GIM_Try, /*On fail goto*//*Label 927*/ 18203,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 928*/ 18172, // Rule ID 61598 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2)  =>  (PseudoVMOR_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMOR_MM_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61598,
        GIR_Done,
      // Label 928: @18172
      GIM_Try, /*On fail goto*//*Label 929*/ 18202, // Rule ID 61599 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2)  =>  (PseudoVMOR_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMOR_MM_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61599,
        GIR_Done,
      // Label 929: @18202
      GIM_Reject,
    // Label 927: @18203
    GIM_Reject,
    // Label 878: @18204
    GIM_Try, /*On fail goto*//*Label 930*/ 18287,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 931*/ 18256, // Rule ID 56525 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVOR_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56525,
        GIR_Done,
      // Label 931: @18256
      GIM_Try, /*On fail goto*//*Label 932*/ 18286, // Rule ID 56526 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVOR_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56526,
        GIR_Done,
      // Label 932: @18286
      GIM_Reject,
    // Label 930: @18287
    GIM_Reject,
    // Label 879: @18288
    GIM_Try, /*On fail goto*//*Label 933*/ 18371,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 934*/ 18340, // Rule ID 56537 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVOR_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56537,
        GIR_Done,
      // Label 934: @18340
      GIM_Try, /*On fail goto*//*Label 935*/ 18370, // Rule ID 56538 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVOR_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56538,
        GIR_Done,
      // Label 935: @18370
      GIM_Reject,
    // Label 933: @18371
    GIM_Reject,
    // Label 880: @18372
    GIM_Try, /*On fail goto*//*Label 936*/ 18455,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 937*/ 18424, // Rule ID 56553 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVOR_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56553,
        GIR_Done,
      // Label 937: @18424
      GIM_Try, /*On fail goto*//*Label 938*/ 18454, // Rule ID 56554 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVOR_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56554,
        GIR_Done,
      // Label 938: @18454
      GIM_Reject,
    // Label 936: @18455
    GIM_Reject,
    // Label 881: @18456
    GIM_Try, /*On fail goto*//*Label 939*/ 18539,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 940*/ 18508, // Rule ID 56597 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVOR_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56597,
        GIR_Done,
      // Label 940: @18508
      GIM_Try, /*On fail goto*//*Label 941*/ 18538, // Rule ID 56598 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVOR_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56598,
        GIR_Done,
      // Label 941: @18538
      GIM_Reject,
    // Label 939: @18539
    GIM_Reject,
    // Label 882: @18540
    GIM_Try, /*On fail goto*//*Label 942*/ 18623,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 943*/ 18592, // Rule ID 61618 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2)  =>  (PseudoVMOR_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMOR_MM_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61618,
        GIR_Done,
      // Label 943: @18592
      GIM_Try, /*On fail goto*//*Label 944*/ 18622, // Rule ID 61619 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2)  =>  (PseudoVMOR_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMOR_MM_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61619,
        GIR_Done,
      // Label 944: @18622
      GIM_Reject,
    // Label 942: @18623
    GIM_Reject,
    // Label 883: @18624
    GIM_Try, /*On fail goto*//*Label 945*/ 18707,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 946*/ 18676, // Rule ID 56529 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVOR_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56529,
        GIR_Done,
      // Label 946: @18676
      GIM_Try, /*On fail goto*//*Label 947*/ 18706, // Rule ID 56530 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVOR_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56530,
        GIR_Done,
      // Label 947: @18706
      GIM_Reject,
    // Label 945: @18707
    GIM_Reject,
    // Label 884: @18708
    GIM_Try, /*On fail goto*//*Label 948*/ 18791,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 949*/ 18760, // Rule ID 56549 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVOR_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56549,
        GIR_Done,
      // Label 949: @18760
      GIM_Try, /*On fail goto*//*Label 950*/ 18790, // Rule ID 56550 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVOR_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56550,
        GIR_Done,
      // Label 950: @18790
      GIM_Reject,
    // Label 948: @18791
    GIM_Reject,
    // Label 885: @18792
    GIM_Try, /*On fail goto*//*Label 951*/ 18875,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 952*/ 18844, // Rule ID 56585 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVOR_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56585,
        GIR_Done,
      // Label 952: @18844
      GIM_Try, /*On fail goto*//*Label 953*/ 18874, // Rule ID 56586 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVOR_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56586,
        GIR_Done,
      // Label 953: @18874
      GIM_Reject,
    // Label 951: @18875
    GIM_Reject,
    // Label 886: @18876
    GIM_Try, /*On fail goto*//*Label 954*/ 18959,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 955*/ 18928, // Rule ID 56601 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVOR_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56601,
        GIR_Done,
      // Label 955: @18928
      GIM_Try, /*On fail goto*//*Label 956*/ 18958, // Rule ID 56602 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVOR_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56602,
        GIR_Done,
      // Label 956: @18958
      GIM_Reject,
    // Label 954: @18959
    GIM_Reject,
    // Label 887: @18960
    GIM_Try, /*On fail goto*//*Label 957*/ 19043,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 958*/ 19012, // Rule ID 61638 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2)  =>  (PseudoVMOR_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMOR_MM_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61638,
        GIR_Done,
      // Label 958: @19012
      GIM_Try, /*On fail goto*//*Label 959*/ 19042, // Rule ID 61639 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2)  =>  (PseudoVMOR_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMOR_MM_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61639,
        GIR_Done,
      // Label 959: @19042
      GIM_Reject,
    // Label 957: @19043
    GIM_Reject,
    // Label 888: @19044
    GIM_Try, /*On fail goto*//*Label 960*/ 19127,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 961*/ 19096, // Rule ID 56545 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVOR_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56545,
        GIR_Done,
      // Label 961: @19096
      GIM_Try, /*On fail goto*//*Label 962*/ 19126, // Rule ID 56546 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVOR_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56546,
        GIR_Done,
      // Label 962: @19126
      GIM_Reject,
    // Label 960: @19127
    GIM_Reject,
    // Label 889: @19128
    GIM_Try, /*On fail goto*//*Label 963*/ 19211,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 964*/ 19180, // Rule ID 56573 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVOR_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56573,
        GIR_Done,
      // Label 964: @19180
      GIM_Try, /*On fail goto*//*Label 965*/ 19210, // Rule ID 56574 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVOR_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56574,
        GIR_Done,
      // Label 965: @19210
      GIM_Reject,
    // Label 963: @19211
    GIM_Reject,
    // Label 890: @19212
    GIM_Try, /*On fail goto*//*Label 966*/ 19295,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 967*/ 19264, // Rule ID 56589 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVOR_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56589,
        GIR_Done,
      // Label 967: @19264
      GIM_Try, /*On fail goto*//*Label 968*/ 19294, // Rule ID 56590 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVOR_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56590,
        GIR_Done,
      // Label 968: @19294
      GIM_Reject,
    // Label 966: @19295
    GIM_Reject,
    // Label 891: @19296
    GIM_Try, /*On fail goto*//*Label 969*/ 19379,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 970*/ 19348, // Rule ID 56605 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVOR_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56605,
        GIR_Done,
      // Label 970: @19348
      GIM_Try, /*On fail goto*//*Label 971*/ 19378, // Rule ID 56606 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVOR_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56606,
        GIR_Done,
      // Label 971: @19378
      GIM_Reject,
    // Label 969: @19379
    GIM_Reject,
    // Label 892: @19380
    GIM_Try, /*On fail goto*//*Label 972*/ 19463,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 973*/ 19432, // Rule ID 61656 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2)  =>  (PseudoVMOR_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMOR_MM_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61656,
        GIR_Done,
      // Label 973: @19432
      GIM_Try, /*On fail goto*//*Label 974*/ 19462, // Rule ID 61657 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2)  =>  (PseudoVMOR_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMOR_MM_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61657,
        GIR_Done,
      // Label 974: @19462
      GIM_Reject,
    // Label 972: @19463
    GIM_Reject,
    // Label 893: @19464
    GIM_Try, /*On fail goto*//*Label 975*/ 19547,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 976*/ 19516, // Rule ID 56561 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVOR_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56561,
        GIR_Done,
      // Label 976: @19516
      GIM_Try, /*On fail goto*//*Label 977*/ 19546, // Rule ID 56562 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVOR_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56562,
        GIR_Done,
      // Label 977: @19546
      GIM_Reject,
    // Label 975: @19547
    GIM_Reject,
    // Label 894: @19548
    GIM_Try, /*On fail goto*//*Label 978*/ 19631,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 979*/ 19600, // Rule ID 56577 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVOR_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56577,
        GIR_Done,
      // Label 979: @19600
      GIM_Try, /*On fail goto*//*Label 980*/ 19630, // Rule ID 56578 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVOR_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56578,
        GIR_Done,
      // Label 980: @19630
      GIM_Reject,
    // Label 978: @19631
    GIM_Reject,
    // Label 895: @19632
    GIM_Try, /*On fail goto*//*Label 981*/ 19715,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 982*/ 19684, // Rule ID 56593 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVOR_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56593,
        GIR_Done,
      // Label 982: @19684
      GIM_Try, /*On fail goto*//*Label 983*/ 19714, // Rule ID 56594 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVOR_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56594,
        GIR_Done,
      // Label 983: @19714
      GIM_Reject,
    // Label 981: @19715
    GIM_Reject,
    // Label 896: @19716
    GIM_Try, /*On fail goto*//*Label 984*/ 19799,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 985*/ 19768, // Rule ID 61674 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2)  =>  (PseudoVMOR_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMOR_MM_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61674,
        GIR_Done,
      // Label 985: @19768
      GIM_Try, /*On fail goto*//*Label 986*/ 19798, // Rule ID 61675 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2)  =>  (PseudoVMOR_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMOR_MM_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61675,
        GIR_Done,
      // Label 986: @19798
      GIM_Reject,
    // Label 984: @19799
    GIM_Reject,
    // Label 897: @19800
    GIM_Try, /*On fail goto*//*Label 987*/ 19883,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 988*/ 19852, // Rule ID 56565 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVOR_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56565,
        GIR_Done,
      // Label 988: @19852
      GIM_Try, /*On fail goto*//*Label 989*/ 19882, // Rule ID 56566 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVOR_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56566,
        GIR_Done,
      // Label 989: @19882
      GIM_Reject,
    // Label 987: @19883
    GIM_Reject,
    // Label 898: @19884
    GIM_Try, /*On fail goto*//*Label 990*/ 19967,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 991*/ 19936, // Rule ID 56581 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVOR_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56581,
        GIR_Done,
      // Label 991: @19936
      GIM_Try, /*On fail goto*//*Label 992*/ 19966, // Rule ID 56582 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVOR_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56582,
        GIR_Done,
      // Label 992: @19966
      GIM_Reject,
    // Label 990: @19967
    GIM_Reject,
    // Label 899: @19968
    GIM_Try, /*On fail goto*//*Label 993*/ 20051,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv64s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 994*/ 20020, // Rule ID 61692 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2)  =>  (PseudoVMOR_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMOR_MM_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61692,
        GIR_Done,
      // Label 994: @20020
      GIM_Try, /*On fail goto*//*Label 995*/ 20050, // Rule ID 61693 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2)  =>  (PseudoVMOR_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMOR_MM_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61693,
        GIR_Done,
      // Label 995: @20050
      GIM_Reject,
    // Label 993: @20051
    GIM_Reject,
    // Label 900: @20052
    GIM_Try, /*On fail goto*//*Label 996*/ 20135,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv64s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 997*/ 20104, // Rule ID 56569 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVOR_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56569,
        GIR_Done,
      // Label 997: @20104
      GIM_Try, /*On fail goto*//*Label 998*/ 20134, // Rule ID 56570 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (or:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVOR_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVOR_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56570,
        GIR_Done,
      // Label 998: @20134
      GIM_Reject,
    // Label 996: @20135
    GIM_Reject,
    // Label 901: @20136
    GIM_Reject,
    // Label 9: @20137
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 32, /*)*//*default:*//*Label 1030*/ 23068,
    /*GILLT_s32*//*Label 999*/ 20174,
    /*GILLT_s64*//*Label 1000*/ 20403,
    /*GILLT_nxv1s1*//*Label 1001*/ 20632,
    /*GILLT_nxv1s8*//*Label 1002*/ 20716,
    /*GILLT_nxv1s16*//*Label 1003*/ 20800,
    /*GILLT_nxv1s32*//*Label 1004*/ 20884,
    /*GILLT_nxv1s64*//*Label 1005*/ 20968,
    /*GILLT_nxv2s1*//*Label 1006*/ 21052,
    /*GILLT_nxv2s8*//*Label 1007*/ 21136,
    /*GILLT_nxv2s16*//*Label 1008*/ 21220,
    /*GILLT_nxv2s32*//*Label 1009*/ 21304,
    /*GILLT_nxv2s64*//*Label 1010*/ 21388,
    /*GILLT_nxv4s1*//*Label 1011*/ 21472,
    /*GILLT_nxv4s8*//*Label 1012*/ 21556,
    /*GILLT_nxv4s16*//*Label 1013*/ 21640,
    /*GILLT_nxv4s32*//*Label 1014*/ 21724,
    /*GILLT_nxv4s64*//*Label 1015*/ 21808,
    /*GILLT_nxv8s1*//*Label 1016*/ 21892,
    /*GILLT_nxv8s8*//*Label 1017*/ 21976,
    /*GILLT_nxv8s16*//*Label 1018*/ 22060,
    /*GILLT_nxv8s32*//*Label 1019*/ 22144,
    /*GILLT_nxv8s64*//*Label 1020*/ 22228,
    /*GILLT_nxv16s1*//*Label 1021*/ 22312,
    /*GILLT_nxv16s8*//*Label 1022*/ 22396,
    /*GILLT_nxv16s16*//*Label 1023*/ 22480,
    /*GILLT_nxv16s32*//*Label 1024*/ 22564,
    /*GILLT_nxv32s1*//*Label 1025*/ 22648,
    /*GILLT_nxv32s8*//*Label 1026*/ 22732,
    /*GILLT_nxv32s16*//*Label 1027*/ 22816,
    /*GILLT_nxv64s1*//*Label 1028*/ 22900,
    /*GILLT_nxv64s8*//*Label 1029*/ 22984,
    // Label 999: @20174
    GIM_Try, /*On fail goto*//*Label 1031*/ 20402,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1032*/ 20241, // Rule ID 72091 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbbOrZbkb,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }), GPR:{ *:[i32] }:$rs2)  =>  (XNOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XNOR,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72091,
        GIR_Done,
      // Label 1032: @20241
      GIM_Try, /*On fail goto*//*Label 1033*/ 20294, // Rule ID 72089 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbbOrZbkb,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), -1:{ *:[i32] })  =>  (XNOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XNOR,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72089,
        GIR_Done,
      // Label 1033: @20294
      GIM_Try, /*On fail goto*//*Label 1034*/ 20347, // Rule ID 65438 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbbOrZbkb,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs2, -1:{ *:[i32] }))  =>  (XNOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XNOR,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65438,
        GIR_Done,
      // Label 1034: @20347
      GIM_Try, /*On fail goto*//*Label 1035*/ 20384, // Rule ID 59980 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm)  =>  (XORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59980,
        GIR_Done,
      // Label 1035: @20384
      GIM_Try, /*On fail goto*//*Label 1036*/ 20401, // Rule ID 59958 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::XOR,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59958,
        GIR_Done,
      // Label 1036: @20401
      GIM_Reject,
    // Label 1031: @20402
    GIM_Reject,
    // Label 1000: @20403
    GIM_Try, /*On fail goto*//*Label 1037*/ 20631,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1038*/ 20470, // Rule ID 72090 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbbOrZbkb,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }), GPR:{ *:[i64] }:$rs2)  =>  (XNOR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XNOR,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72090,
        GIR_Done,
      // Label 1038: @20470
      GIM_Try, /*On fail goto*//*Label 1039*/ 20523, // Rule ID 72088 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbbOrZbkb,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2), -1:{ *:[i64] })  =>  (XNOR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XNOR,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72088,
        GIR_Done,
      // Label 1039: @20523
      GIM_Try, /*On fail goto*//*Label 1040*/ 20576, // Rule ID 65437 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbbOrZbkb,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_XOR,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, -1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs2, -1:{ *:[i64] }))  =>  (XNOR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XNOR,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65437,
        GIR_Done,
      // Label 1040: @20576
      GIM_Try, /*On fail goto*//*Label 1041*/ 20613, // Rule ID 59979 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm)  =>  (XORI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59979,
        GIR_Done,
      // Label 1041: @20613
      GIM_Try, /*On fail goto*//*Label 1042*/ 20630, // Rule ID 59957 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (XOR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::XOR,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59957,
        GIR_Done,
      // Label 1042: @20630
      GIM_Reject,
    // Label 1037: @20631
    GIM_Reject,
    // Label 1001: @20632
    GIM_Try, /*On fail goto*//*Label 1043*/ 20715,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1044*/ 20684, // Rule ID 61580 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2)  =>  (PseudoVMXOR_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMXOR_MM_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61580,
        GIR_Done,
      // Label 1044: @20684
      GIM_Try, /*On fail goto*//*Label 1045*/ 20714, // Rule ID 61581 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2)  =>  (PseudoVMXOR_MM_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i1] }:$rs1, VR:{ *:[nxv1i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMXOR_MM_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61581,
        GIR_Done,
      // Label 1045: @20714
      GIM_Reject,
    // Label 1043: @20715
    GIM_Reject,
    // Label 1002: @20716
    GIM_Try, /*On fail goto*//*Label 1046*/ 20799,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1047*/ 20768, // Rule ID 56653 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVXOR_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56653,
        GIR_Done,
      // Label 1047: @20768
      GIM_Try, /*On fail goto*//*Label 1048*/ 20798, // Rule ID 56654 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVXOR_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56654,
        GIR_Done,
      // Label 1048: @20798
      GIM_Reject,
    // Label 1046: @20799
    GIM_Reject,
    // Label 1003: @20800
    GIM_Try, /*On fail goto*//*Label 1049*/ 20883,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1050*/ 20852, // Rule ID 56665 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVXOR_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56665,
        GIR_Done,
      // Label 1050: @20852
      GIM_Try, /*On fail goto*//*Label 1051*/ 20882, // Rule ID 56666 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVXOR_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56666,
        GIR_Done,
      // Label 1051: @20882
      GIM_Reject,
    // Label 1049: @20883
    GIM_Reject,
    // Label 1004: @20884
    GIM_Try, /*On fail goto*//*Label 1052*/ 20967,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1053*/ 20936, // Rule ID 56673 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVXOR_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56673,
        GIR_Done,
      // Label 1053: @20936
      GIM_Try, /*On fail goto*//*Label 1054*/ 20966, // Rule ID 56674 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVXOR_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56674,
        GIR_Done,
      // Label 1054: @20966
      GIM_Reject,
    // Label 1052: @20967
    GIM_Reject,
    // Label 1005: @20968
    GIM_Try, /*On fail goto*//*Label 1055*/ 21051,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1056*/ 21020, // Rule ID 56689 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVXOR_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56689,
        GIR_Done,
      // Label 1056: @21020
      GIM_Try, /*On fail goto*//*Label 1057*/ 21050, // Rule ID 56690 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVXOR_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56690,
        GIR_Done,
      // Label 1057: @21050
      GIM_Reject,
    // Label 1055: @21051
    GIM_Reject,
    // Label 1006: @21052
    GIM_Try, /*On fail goto*//*Label 1058*/ 21135,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1059*/ 21104, // Rule ID 61600 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2)  =>  (PseudoVMXOR_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMXOR_MM_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61600,
        GIR_Done,
      // Label 1059: @21104
      GIM_Try, /*On fail goto*//*Label 1060*/ 21134, // Rule ID 61601 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2)  =>  (PseudoVMXOR_MM_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i1] }:$rs1, VR:{ *:[nxv2i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMXOR_MM_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61601,
        GIR_Done,
      // Label 1060: @21134
      GIM_Reject,
    // Label 1058: @21135
    GIM_Reject,
    // Label 1007: @21136
    GIM_Try, /*On fail goto*//*Label 1061*/ 21219,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1062*/ 21188, // Rule ID 56657 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVXOR_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56657,
        GIR_Done,
      // Label 1062: @21188
      GIM_Try, /*On fail goto*//*Label 1063*/ 21218, // Rule ID 56658 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVXOR_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56658,
        GIR_Done,
      // Label 1063: @21218
      GIM_Reject,
    // Label 1061: @21219
    GIM_Reject,
    // Label 1008: @21220
    GIM_Try, /*On fail goto*//*Label 1064*/ 21303,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1065*/ 21272, // Rule ID 56669 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVXOR_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56669,
        GIR_Done,
      // Label 1065: @21272
      GIM_Try, /*On fail goto*//*Label 1066*/ 21302, // Rule ID 56670 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVXOR_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56670,
        GIR_Done,
      // Label 1066: @21302
      GIM_Reject,
    // Label 1064: @21303
    GIM_Reject,
    // Label 1009: @21304
    GIM_Try, /*On fail goto*//*Label 1067*/ 21387,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1068*/ 21356, // Rule ID 56685 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVXOR_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56685,
        GIR_Done,
      // Label 1068: @21356
      GIM_Try, /*On fail goto*//*Label 1069*/ 21386, // Rule ID 56686 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVXOR_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56686,
        GIR_Done,
      // Label 1069: @21386
      GIM_Reject,
    // Label 1067: @21387
    GIM_Reject,
    // Label 1010: @21388
    GIM_Try, /*On fail goto*//*Label 1070*/ 21471,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 1071*/ 21440, // Rule ID 56729 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVXOR_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56729,
        GIR_Done,
      // Label 1071: @21440
      GIM_Try, /*On fail goto*//*Label 1072*/ 21470, // Rule ID 56730 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVXOR_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56730,
        GIR_Done,
      // Label 1072: @21470
      GIM_Reject,
    // Label 1070: @21471
    GIM_Reject,
    // Label 1011: @21472
    GIM_Try, /*On fail goto*//*Label 1073*/ 21555,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1074*/ 21524, // Rule ID 61620 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2)  =>  (PseudoVMXOR_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMXOR_MM_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61620,
        GIR_Done,
      // Label 1074: @21524
      GIM_Try, /*On fail goto*//*Label 1075*/ 21554, // Rule ID 61621 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2)  =>  (PseudoVMXOR_MM_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i1] }:$rs1, VR:{ *:[nxv4i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMXOR_MM_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61621,
        GIR_Done,
      // Label 1075: @21554
      GIM_Reject,
    // Label 1073: @21555
    GIM_Reject,
    // Label 1012: @21556
    GIM_Try, /*On fail goto*//*Label 1076*/ 21639,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1077*/ 21608, // Rule ID 56661 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVXOR_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56661,
        GIR_Done,
      // Label 1077: @21608
      GIM_Try, /*On fail goto*//*Label 1078*/ 21638, // Rule ID 56662 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVXOR_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56662,
        GIR_Done,
      // Label 1078: @21638
      GIM_Reject,
    // Label 1076: @21639
    GIM_Reject,
    // Label 1013: @21640
    GIM_Try, /*On fail goto*//*Label 1079*/ 21723,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1080*/ 21692, // Rule ID 56681 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVXOR_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56681,
        GIR_Done,
      // Label 1080: @21692
      GIM_Try, /*On fail goto*//*Label 1081*/ 21722, // Rule ID 56682 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVXOR_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56682,
        GIR_Done,
      // Label 1081: @21722
      GIM_Reject,
    // Label 1079: @21723
    GIM_Reject,
    // Label 1014: @21724
    GIM_Try, /*On fail goto*//*Label 1082*/ 21807,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 1083*/ 21776, // Rule ID 56717 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVXOR_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56717,
        GIR_Done,
      // Label 1083: @21776
      GIM_Try, /*On fail goto*//*Label 1084*/ 21806, // Rule ID 56718 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVXOR_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56718,
        GIR_Done,
      // Label 1084: @21806
      GIM_Reject,
    // Label 1082: @21807
    GIM_Reject,
    // Label 1015: @21808
    GIM_Try, /*On fail goto*//*Label 1085*/ 21891,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 1086*/ 21860, // Rule ID 56733 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVXOR_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56733,
        GIR_Done,
      // Label 1086: @21860
      GIM_Try, /*On fail goto*//*Label 1087*/ 21890, // Rule ID 56734 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVXOR_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56734,
        GIR_Done,
      // Label 1087: @21890
      GIM_Reject,
    // Label 1085: @21891
    GIM_Reject,
    // Label 1016: @21892
    GIM_Try, /*On fail goto*//*Label 1088*/ 21975,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1089*/ 21944, // Rule ID 61640 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2)  =>  (PseudoVMXOR_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMXOR_MM_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61640,
        GIR_Done,
      // Label 1089: @21944
      GIM_Try, /*On fail goto*//*Label 1090*/ 21974, // Rule ID 61641 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2)  =>  (PseudoVMXOR_MM_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i1] }:$rs1, VR:{ *:[nxv8i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMXOR_MM_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61641,
        GIR_Done,
      // Label 1090: @21974
      GIM_Reject,
    // Label 1088: @21975
    GIM_Reject,
    // Label 1017: @21976
    GIM_Try, /*On fail goto*//*Label 1091*/ 22059,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1092*/ 22028, // Rule ID 56677 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVXOR_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56677,
        GIR_Done,
      // Label 1092: @22028
      GIM_Try, /*On fail goto*//*Label 1093*/ 22058, // Rule ID 56678 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVXOR_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56678,
        GIR_Done,
      // Label 1093: @22058
      GIM_Reject,
    // Label 1091: @22059
    GIM_Reject,
    // Label 1018: @22060
    GIM_Try, /*On fail goto*//*Label 1094*/ 22143,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 1095*/ 22112, // Rule ID 56705 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVXOR_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56705,
        GIR_Done,
      // Label 1095: @22112
      GIM_Try, /*On fail goto*//*Label 1096*/ 22142, // Rule ID 56706 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVXOR_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56706,
        GIR_Done,
      // Label 1096: @22142
      GIM_Reject,
    // Label 1094: @22143
    GIM_Reject,
    // Label 1019: @22144
    GIM_Try, /*On fail goto*//*Label 1097*/ 22227,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 1098*/ 22196, // Rule ID 56721 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVXOR_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56721,
        GIR_Done,
      // Label 1098: @22196
      GIM_Try, /*On fail goto*//*Label 1099*/ 22226, // Rule ID 56722 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVXOR_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56722,
        GIR_Done,
      // Label 1099: @22226
      GIM_Reject,
    // Label 1097: @22227
    GIM_Reject,
    // Label 1020: @22228
    GIM_Try, /*On fail goto*//*Label 1100*/ 22311,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 1101*/ 22280, // Rule ID 56737 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVXOR_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56737,
        GIR_Done,
      // Label 1101: @22280
      GIM_Try, /*On fail goto*//*Label 1102*/ 22310, // Rule ID 56738 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVXOR_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56738,
        GIR_Done,
      // Label 1102: @22310
      GIM_Reject,
    // Label 1100: @22311
    GIM_Reject,
    // Label 1021: @22312
    GIM_Try, /*On fail goto*//*Label 1103*/ 22395,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1104*/ 22364, // Rule ID 61658 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2)  =>  (PseudoVMXOR_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMXOR_MM_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61658,
        GIR_Done,
      // Label 1104: @22364
      GIM_Try, /*On fail goto*//*Label 1105*/ 22394, // Rule ID 61659 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2)  =>  (PseudoVMXOR_MM_M2:{ *:[nxv16i1] } VR:{ *:[nxv16i1] }:$rs1, VR:{ *:[nxv16i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMXOR_MM_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61659,
        GIR_Done,
      // Label 1105: @22394
      GIM_Reject,
    // Label 1103: @22395
    GIM_Reject,
    // Label 1022: @22396
    GIM_Try, /*On fail goto*//*Label 1106*/ 22479,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 1107*/ 22448, // Rule ID 56693 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVXOR_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56693,
        GIR_Done,
      // Label 1107: @22448
      GIM_Try, /*On fail goto*//*Label 1108*/ 22478, // Rule ID 56694 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVXOR_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56694,
        GIR_Done,
      // Label 1108: @22478
      GIM_Reject,
    // Label 1106: @22479
    GIM_Reject,
    // Label 1023: @22480
    GIM_Try, /*On fail goto*//*Label 1109*/ 22563,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 1110*/ 22532, // Rule ID 56709 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVXOR_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56709,
        GIR_Done,
      // Label 1110: @22532
      GIM_Try, /*On fail goto*//*Label 1111*/ 22562, // Rule ID 56710 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVXOR_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56710,
        GIR_Done,
      // Label 1111: @22562
      GIM_Reject,
    // Label 1109: @22563
    GIM_Reject,
    // Label 1024: @22564
    GIM_Try, /*On fail goto*//*Label 1112*/ 22647,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 1113*/ 22616, // Rule ID 56725 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVXOR_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56725,
        GIR_Done,
      // Label 1113: @22616
      GIM_Try, /*On fail goto*//*Label 1114*/ 22646, // Rule ID 56726 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVXOR_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56726,
        GIR_Done,
      // Label 1114: @22646
      GIM_Reject,
    // Label 1112: @22647
    GIM_Reject,
    // Label 1025: @22648
    GIM_Try, /*On fail goto*//*Label 1115*/ 22731,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1116*/ 22700, // Rule ID 61676 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2)  =>  (PseudoVMXOR_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMXOR_MM_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61676,
        GIR_Done,
      // Label 1116: @22700
      GIM_Try, /*On fail goto*//*Label 1117*/ 22730, // Rule ID 61677 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2)  =>  (PseudoVMXOR_MM_M4:{ *:[nxv32i1] } VR:{ *:[nxv32i1] }:$rs1, VR:{ *:[nxv32i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMXOR_MM_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61677,
        GIR_Done,
      // Label 1117: @22730
      GIM_Reject,
    // Label 1115: @22731
    GIM_Reject,
    // Label 1026: @22732
    GIM_Try, /*On fail goto*//*Label 1118*/ 22815,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 1119*/ 22784, // Rule ID 56697 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVXOR_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56697,
        GIR_Done,
      // Label 1119: @22784
      GIM_Try, /*On fail goto*//*Label 1120*/ 22814, // Rule ID 56698 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVXOR_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56698,
        GIR_Done,
      // Label 1120: @22814
      GIM_Reject,
    // Label 1118: @22815
    GIM_Reject,
    // Label 1027: @22816
    GIM_Try, /*On fail goto*//*Label 1121*/ 22899,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 1122*/ 22868, // Rule ID 56713 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVXOR_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56713,
        GIR_Done,
      // Label 1122: @22868
      GIM_Try, /*On fail goto*//*Label 1123*/ 22898, // Rule ID 56714 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVXOR_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56714,
        GIR_Done,
      // Label 1123: @22898
      GIM_Reject,
    // Label 1121: @22899
    GIM_Reject,
    // Label 1028: @22900
    GIM_Try, /*On fail goto*//*Label 1124*/ 22983,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv64s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1125*/ 22952, // Rule ID 61694 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2)  =>  (PseudoVMXOR_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMXOR_MM_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61694,
        GIR_Done,
      // Label 1125: @22952
      GIM_Try, /*On fail goto*//*Label 1126*/ 22982, // Rule ID 61695 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2)  =>  (PseudoVMXOR_MM_M8:{ *:[nxv64i1] } VR:{ *:[nxv64i1] }:$rs1, VR:{ *:[nxv64i1] }:$rs2, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMXOR_MM_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61695,
        GIR_Done,
      // Label 1126: @22982
      GIM_Reject,
    // Label 1124: @22983
    GIM_Reject,
    // Label 1029: @22984
    GIM_Try, /*On fail goto*//*Label 1127*/ 23067,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv64s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 1128*/ 23036, // Rule ID 56701 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVXOR_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56701,
        GIR_Done,
      // Label 1128: @23036
      GIM_Try, /*On fail goto*//*Label 1129*/ 23066, // Rule ID 56702 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (xor:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVXOR_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVXOR_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56702,
        GIR_Done,
      // Label 1129: @23066
      GIM_Reject,
    // Label 1127: @23067
    GIM_Reject,
    // Label 1030: @23068
    GIM_Reject,
    // Label 10: @23069
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1132*/ 23169,
    /*GILLT_s32*//*Label 1130*/ 23077,
    /*GILLT_s64*//*Label 1131*/ 23123,
    // Label 1130: @23077
    GIM_Try, /*On fail goto*//*Label 1133*/ 23122,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 1134*/ 23102, // Rule ID 65241 //
        GIM_CheckFeatures, GIFBS_HasStdExtF_IsRV32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$rs1)  =>  (FMV_W_X:{ *:[f32] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_W_X,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65241,
        GIR_Done,
      // Label 1134: @23102
      GIM_Try, /*On fail goto*//*Label 1135*/ 23121, // Rule ID 65242 //
        GIM_CheckFeatures, GIFBS_HasStdExtF_IsRV32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        // (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$rs1)  =>  (FMV_X_W:{ *:[i32] } FPR32:{ *:[f32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_X_W,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65242,
        GIR_Done,
      // Label 1135: @23121
      GIM_Reject,
    // Label 1133: @23122
    GIM_Reject,
    // Label 1131: @23123
    GIM_Try, /*On fail goto*//*Label 1136*/ 23168,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 1137*/ 23148, // Rule ID 65405 //
        GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (bitconvert:{ *:[f64] } GPR:{ *:[i64] }:$rs1)  =>  (FMV_D_X:{ *:[f64] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_D_X,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65405,
        GIR_Done,
      // Label 1137: @23148
      GIM_Try, /*On fail goto*//*Label 1138*/ 23167, // Rule ID 65406 //
        GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        // (bitconvert:{ *:[i64] } FPR64:{ *:[f64] }:$rs1)  =>  (FMV_X_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_X_D,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65406,
        GIR_Done,
      // Label 1138: @23167
      GIM_Reject,
    // Label 1136: @23168
    GIM_Reject,
    // Label 1132: @23169
    GIM_Reject,
    // Label 11: @23170
    GIM_Try, /*On fail goto*//*Label 1139*/ 23201, // Rule ID 63162 //
      GIM_CheckFeatures, GIFBS_IsRV64,
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      // (readcyclecounter:{ *:[i64] })  =>  (CSRRS:{ *:[i64] } 3072:{ *:[i64] }, X0:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::CSRRS,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_AddImm, /*InsnID*/0, /*Imm*/3072,
      GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63162,
      GIR_Done,
    // Label 1139: @23201
    GIM_Reject,
    // Label 12: @23202
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 32, /*)*//*default:*//*Label 1169*/ 25952,
    /*GILLT_nxv1s1*//*Label 1140*/ 23237,
    /*GILLT_nxv1s8*//*Label 1141*/ 23328,
    /*GILLT_nxv1s16*//*Label 1142*/ 23419,
    /*GILLT_nxv1s32*//*Label 1143*/ 23586,
    /*GILLT_nxv1s64*//*Label 1144*/ 23753,
    /*GILLT_nxv2s1*//*Label 1145*/ 23844,
    /*GILLT_nxv2s8*//*Label 1146*/ 23935,
    /*GILLT_nxv2s16*//*Label 1147*/ 24026,
    /*GILLT_nxv2s32*//*Label 1148*/ 24193,
    /*GILLT_nxv2s64*//*Label 1149*/ 24284,
    /*GILLT_nxv4s1*//*Label 1150*/ 24375,
    /*GILLT_nxv4s8*//*Label 1151*/ 24466,
    /*GILLT_nxv4s16*//*Label 1152*/ 24557,
    /*GILLT_nxv4s32*//*Label 1153*/ 24648,
    /*GILLT_nxv4s64*//*Label 1154*/ 24739,
    /*GILLT_nxv8s1*//*Label 1155*/ 24830,
    /*GILLT_nxv8s8*//*Label 1156*/ 24921,
    /*GILLT_nxv8s16*//*Label 1157*/ 24974,
    /*GILLT_nxv8s32*//*Label 1158*/ 25065,
    /*GILLT_nxv8s64*//*Label 1159*/ 25156,
    /*GILLT_nxv16s1*//*Label 1160*/ 25247,
    /*GILLT_nxv16s8*//*Label 1161*/ 25338,
    /*GILLT_nxv16s16*//*Label 1162*/ 25391,
    /*GILLT_nxv16s32*//*Label 1163*/ 25482,
    /*GILLT_nxv32s1*//*Label 1164*/ 25573,
    /*GILLT_nxv32s8*//*Label 1165*/ 25664,
    /*GILLT_nxv32s16*//*Label 1166*/ 25717,
    /*GILLT_nxv64s1*//*Label 1167*/ 25808,
    /*GILLT_nxv64s8*//*Label 1168*/ 25899,
    // Label 1140: @23237
    GIM_Try, /*On fail goto*//*Label 1170*/ 23327,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1171*/ 23288, // Rule ID 54933 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv1i1] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLM_V_B1:{ *:[nxv1i1] } GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLM_V_B1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 54933,
        GIR_Done,
      // Label 1171: @23288
      GIM_Try, /*On fail goto*//*Label 1172*/ 23326, // Rule ID 54934 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv1i1] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLM_V_B1:{ *:[nxv1i1] } GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLM_V_B1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 54934,
        GIR_Done,
      // Label 1172: @23326
      GIM_Reject,
    // Label 1170: @23327
    GIM_Reject,
    // Label 1141: @23328
    GIM_Try, /*On fail goto*//*Label 1173*/ 23418,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1174*/ 23379, // Rule ID 54925 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv1i8] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLE8_V_MF8:{ *:[nxv1i8] } GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLE8_V_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 54925,
        GIR_Done,
      // Label 1174: @23379
      GIM_Try, /*On fail goto*//*Label 1175*/ 23417, // Rule ID 54926 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv1i8] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLE8_V_MF8:{ *:[nxv1i8] } GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLE8_V_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 54926,
        GIR_Done,
      // Label 1175: @23417
      GIM_Reject,
    // Label 1173: @23418
    GIM_Reject,
    // Label 1142: @23419
    GIM_Try, /*On fail goto*//*Label 1176*/ 23585,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1177*/ 23470, // Rule ID 55053 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv1i16] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLE16_V_MF4:{ *:[nxv1i16] } GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLE16_V_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55053,
        GIR_Done,
      // Label 1177: @23470
      GIM_Try, /*On fail goto*//*Label 1178*/ 23508, // Rule ID 55054 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv1i16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLE16_V_MF4:{ *:[nxv1i16] } GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLE16_V_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55054,
        GIR_Done,
      // Label 1178: @23508
      GIM_Try, /*On fail goto*//*Label 1179*/ 23546, // Rule ID 55065 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv1f16] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLE16_V_MF4:{ *:[nxv1f16] } GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLE16_V_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55065,
        GIR_Done,
      // Label 1179: @23546
      GIM_Try, /*On fail goto*//*Label 1180*/ 23584, // Rule ID 55066 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv1f16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLE16_V_MF4:{ *:[nxv1f16] } GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLE16_V_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55066,
        GIR_Done,
      // Label 1180: @23584
      GIM_Reject,
    // Label 1176: @23585
    GIM_Reject,
    // Label 1143: @23586
    GIM_Try, /*On fail goto*//*Label 1181*/ 23752,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1182*/ 23637, // Rule ID 55061 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv1i32] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLE32_V_MF2:{ *:[nxv1i32] } GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLE32_V_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55061,
        GIR_Done,
      // Label 1182: @23637
      GIM_Try, /*On fail goto*//*Label 1183*/ 23675, // Rule ID 55062 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv1i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLE32_V_MF2:{ *:[nxv1i32] } GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLE32_V_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55062,
        GIR_Done,
      // Label 1183: @23675
      GIM_Try, /*On fail goto*//*Label 1184*/ 23713, // Rule ID 55073 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv1f32] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLE32_V_MF2:{ *:[nxv1f32] } GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLE32_V_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55073,
        GIR_Done,
      // Label 1184: @23713
      GIM_Try, /*On fail goto*//*Label 1185*/ 23751, // Rule ID 55074 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv1f32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLE32_V_MF2:{ *:[nxv1f32] } GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLE32_V_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55074,
        GIR_Done,
      // Label 1185: @23751
      GIM_Reject,
    // Label 1181: @23752
    GIM_Reject,
    // Label 1144: @23753
    GIM_Try, /*On fail goto*//*Label 1186*/ 23843,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1187*/ 23785, // Rule ID 55085 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv1i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL1RE64_V:{ *:[nxv1i64] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL1RE64_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55085,
        GIR_Done,
      // Label 1187: @23785
      GIM_Try, /*On fail goto*//*Label 1188*/ 23804, // Rule ID 55086 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv1i64] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL1RE64_V:{ *:[nxv1i64] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL1RE64_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55086,
        GIR_Done,
      // Label 1188: @23804
      GIM_Try, /*On fail goto*//*Label 1189*/ 23823, // Rule ID 55097 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv1f64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL1RE64_V:{ *:[nxv1f64] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL1RE64_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55097,
        GIR_Done,
      // Label 1189: @23823
      GIM_Try, /*On fail goto*//*Label 1190*/ 23842, // Rule ID 55098 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv1f64] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL1RE64_V:{ *:[nxv1f64] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL1RE64_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55098,
        GIR_Done,
      // Label 1190: @23842
      GIM_Reject,
    // Label 1186: @23843
    GIM_Reject,
    // Label 1145: @23844
    GIM_Try, /*On fail goto*//*Label 1191*/ 23934,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1192*/ 23895, // Rule ID 55185 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv2i1] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLM_V_B2:{ *:[nxv2i1] } GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLM_V_B2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55185,
        GIR_Done,
      // Label 1192: @23895
      GIM_Try, /*On fail goto*//*Label 1193*/ 23933, // Rule ID 55186 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv2i1] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLM_V_B2:{ *:[nxv2i1] } GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLM_V_B2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55186,
        GIR_Done,
      // Label 1193: @23933
      GIM_Reject,
    // Label 1191: @23934
    GIM_Reject,
    // Label 1146: @23935
    GIM_Try, /*On fail goto*//*Label 1194*/ 24025,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1195*/ 23986, // Rule ID 55045 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv2i8] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLE8_V_MF4:{ *:[nxv2i8] } GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLE8_V_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55045,
        GIR_Done,
      // Label 1195: @23986
      GIM_Try, /*On fail goto*//*Label 1196*/ 24024, // Rule ID 55046 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv2i8] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLE8_V_MF4:{ *:[nxv2i8] } GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLE8_V_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55046,
        GIR_Done,
      // Label 1196: @24024
      GIM_Reject,
    // Label 1194: @24025
    GIM_Reject,
    // Label 1147: @24026
    GIM_Try, /*On fail goto*//*Label 1197*/ 24192,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1198*/ 24077, // Rule ID 55057 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv2i16] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLE16_V_MF2:{ *:[nxv2i16] } GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLE16_V_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55057,
        GIR_Done,
      // Label 1198: @24077
      GIM_Try, /*On fail goto*//*Label 1199*/ 24115, // Rule ID 55058 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv2i16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLE16_V_MF2:{ *:[nxv2i16] } GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLE16_V_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55058,
        GIR_Done,
      // Label 1199: @24115
      GIM_Try, /*On fail goto*//*Label 1200*/ 24153, // Rule ID 55069 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv2f16] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLE16_V_MF2:{ *:[nxv2f16] } GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLE16_V_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55069,
        GIR_Done,
      // Label 1200: @24153
      GIM_Try, /*On fail goto*//*Label 1201*/ 24191, // Rule ID 55070 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv2f16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLE16_V_MF2:{ *:[nxv2f16] } GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLE16_V_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55070,
        GIR_Done,
      // Label 1201: @24191
      GIM_Reject,
    // Label 1197: @24192
    GIM_Reject,
    // Label 1148: @24193
    GIM_Try, /*On fail goto*//*Label 1202*/ 24283,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1203*/ 24225, // Rule ID 55081 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv2i32] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL1RE32_V:{ *:[nxv2i32] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL1RE32_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55081,
        GIR_Done,
      // Label 1203: @24225
      GIM_Try, /*On fail goto*//*Label 1204*/ 24244, // Rule ID 55082 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv2i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL1RE32_V:{ *:[nxv2i32] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL1RE32_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55082,
        GIR_Done,
      // Label 1204: @24244
      GIM_Try, /*On fail goto*//*Label 1205*/ 24263, // Rule ID 55093 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv2f32] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL1RE32_V:{ *:[nxv2f32] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL1RE32_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55093,
        GIR_Done,
      // Label 1205: @24263
      GIM_Try, /*On fail goto*//*Label 1206*/ 24282, // Rule ID 55094 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv2f32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL1RE32_V:{ *:[nxv2f32] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL1RE32_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55094,
        GIR_Done,
      // Label 1206: @24282
      GIM_Reject,
    // Label 1202: @24283
    GIM_Reject,
    // Label 1149: @24284
    GIM_Try, /*On fail goto*//*Label 1207*/ 24374,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 1208*/ 24316, // Rule ID 55137 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv2i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL2RE64_V:{ *:[nxv2i64] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL2RE64_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55137,
        GIR_Done,
      // Label 1208: @24316
      GIM_Try, /*On fail goto*//*Label 1209*/ 24335, // Rule ID 55138 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv2i64] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL2RE64_V:{ *:[nxv2i64] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL2RE64_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55138,
        GIR_Done,
      // Label 1209: @24335
      GIM_Try, /*On fail goto*//*Label 1210*/ 24354, // Rule ID 55173 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv2f64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL2RE64_V:{ *:[nxv2f64] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL2RE64_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55173,
        GIR_Done,
      // Label 1210: @24354
      GIM_Try, /*On fail goto*//*Label 1211*/ 24373, // Rule ID 55174 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv2f64] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL2RE64_V:{ *:[nxv2f64] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL2RE64_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55174,
        GIR_Done,
      // Label 1211: @24373
      GIM_Reject,
    // Label 1207: @24374
    GIM_Reject,
    // Label 1150: @24375
    GIM_Try, /*On fail goto*//*Label 1212*/ 24465,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1213*/ 24426, // Rule ID 55189 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv4i1] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLM_V_B4:{ *:[nxv4i1] } GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLM_V_B4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55189,
        GIR_Done,
      // Label 1213: @24426
      GIM_Try, /*On fail goto*//*Label 1214*/ 24464, // Rule ID 55190 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv4i1] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLM_V_B4:{ *:[nxv4i1] } GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLM_V_B4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55190,
        GIR_Done,
      // Label 1214: @24464
      GIM_Reject,
    // Label 1212: @24465
    GIM_Reject,
    // Label 1151: @24466
    GIM_Try, /*On fail goto*//*Label 1215*/ 24556,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1216*/ 24517, // Rule ID 55049 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv4i8] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLE8_V_MF2:{ *:[nxv4i8] } GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLE8_V_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55049,
        GIR_Done,
      // Label 1216: @24517
      GIM_Try, /*On fail goto*//*Label 1217*/ 24555, // Rule ID 55050 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv4i8] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLE8_V_MF2:{ *:[nxv4i8] } GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLE8_V_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55050,
        GIR_Done,
      // Label 1217: @24555
      GIM_Reject,
    // Label 1215: @24556
    GIM_Reject,
    // Label 1152: @24557
    GIM_Try, /*On fail goto*//*Label 1218*/ 24647,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1219*/ 24589, // Rule ID 55077 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv4i16] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL1RE16_V:{ *:[nxv4i16] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL1RE16_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55077,
        GIR_Done,
      // Label 1219: @24589
      GIM_Try, /*On fail goto*//*Label 1220*/ 24608, // Rule ID 55078 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv4i16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL1RE16_V:{ *:[nxv4i16] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL1RE16_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55078,
        GIR_Done,
      // Label 1220: @24608
      GIM_Try, /*On fail goto*//*Label 1221*/ 24627, // Rule ID 55089 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv4f16] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL1RE16_V:{ *:[nxv4f16] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL1RE16_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55089,
        GIR_Done,
      // Label 1221: @24627
      GIM_Try, /*On fail goto*//*Label 1222*/ 24646, // Rule ID 55090 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv4f16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL1RE16_V:{ *:[nxv4f16] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL1RE16_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55090,
        GIR_Done,
      // Label 1222: @24646
      GIM_Reject,
    // Label 1218: @24647
    GIM_Reject,
    // Label 1153: @24648
    GIM_Try, /*On fail goto*//*Label 1223*/ 24738,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 1224*/ 24680, // Rule ID 55125 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv4i32] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL2RE32_V:{ *:[nxv4i32] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL2RE32_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55125,
        GIR_Done,
      // Label 1224: @24680
      GIM_Try, /*On fail goto*//*Label 1225*/ 24699, // Rule ID 55126 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv4i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL2RE32_V:{ *:[nxv4i32] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL2RE32_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55126,
        GIR_Done,
      // Label 1225: @24699
      GIM_Try, /*On fail goto*//*Label 1226*/ 24718, // Rule ID 55161 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv4f32] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL2RE32_V:{ *:[nxv4f32] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL2RE32_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55161,
        GIR_Done,
      // Label 1226: @24718
      GIM_Try, /*On fail goto*//*Label 1227*/ 24737, // Rule ID 55162 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv4f32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL2RE32_V:{ *:[nxv4f32] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL2RE32_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55162,
        GIR_Done,
      // Label 1227: @24737
      GIM_Reject,
    // Label 1223: @24738
    GIM_Reject,
    // Label 1154: @24739
    GIM_Try, /*On fail goto*//*Label 1228*/ 24829,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 1229*/ 24771, // Rule ID 55141 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv4i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL4RE64_V:{ *:[nxv4i64] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL4RE64_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55141,
        GIR_Done,
      // Label 1229: @24771
      GIM_Try, /*On fail goto*//*Label 1230*/ 24790, // Rule ID 55142 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv4i64] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL4RE64_V:{ *:[nxv4i64] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL4RE64_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55142,
        GIR_Done,
      // Label 1230: @24790
      GIM_Try, /*On fail goto*//*Label 1231*/ 24809, // Rule ID 55177 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv4f64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL4RE64_V:{ *:[nxv4f64] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL4RE64_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55177,
        GIR_Done,
      // Label 1231: @24809
      GIM_Try, /*On fail goto*//*Label 1232*/ 24828, // Rule ID 55178 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv4f64] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL4RE64_V:{ *:[nxv4f64] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL4RE64_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55178,
        GIR_Done,
      // Label 1232: @24828
      GIM_Reject,
    // Label 1228: @24829
    GIM_Reject,
    // Label 1155: @24830
    GIM_Try, /*On fail goto*//*Label 1233*/ 24920,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1234*/ 24881, // Rule ID 55193 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv8i1] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLM_V_B8:{ *:[nxv8i1] } GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLM_V_B8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55193,
        GIR_Done,
      // Label 1234: @24881
      GIM_Try, /*On fail goto*//*Label 1235*/ 24919, // Rule ID 55194 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv8i1] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLM_V_B8:{ *:[nxv8i1] } GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLM_V_B8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55194,
        GIR_Done,
      // Label 1235: @24919
      GIM_Reject,
    // Label 1233: @24920
    GIM_Reject,
    // Label 1156: @24921
    GIM_Try, /*On fail goto*//*Label 1236*/ 24973,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1237*/ 24953, // Rule ID 54929 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv8i8] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL1RE8_V:{ *:[nxv8i8] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL1RE8_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 54929,
        GIR_Done,
      // Label 1237: @24953
      GIM_Try, /*On fail goto*//*Label 1238*/ 24972, // Rule ID 54930 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv8i8] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL1RE8_V:{ *:[nxv8i8] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL1RE8_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 54930,
        GIR_Done,
      // Label 1238: @24972
      GIM_Reject,
    // Label 1236: @24973
    GIM_Reject,
    // Label 1157: @24974
    GIM_Try, /*On fail goto*//*Label 1239*/ 25064,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 1240*/ 25006, // Rule ID 55113 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv8i16] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL2RE16_V:{ *:[nxv8i16] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL2RE16_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55113,
        GIR_Done,
      // Label 1240: @25006
      GIM_Try, /*On fail goto*//*Label 1241*/ 25025, // Rule ID 55114 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv8i16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL2RE16_V:{ *:[nxv8i16] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL2RE16_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55114,
        GIR_Done,
      // Label 1241: @25025
      GIM_Try, /*On fail goto*//*Label 1242*/ 25044, // Rule ID 55149 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv8f16] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL2RE16_V:{ *:[nxv8f16] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL2RE16_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55149,
        GIR_Done,
      // Label 1242: @25044
      GIM_Try, /*On fail goto*//*Label 1243*/ 25063, // Rule ID 55150 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv8f16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL2RE16_V:{ *:[nxv8f16] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL2RE16_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55150,
        GIR_Done,
      // Label 1243: @25063
      GIM_Reject,
    // Label 1239: @25064
    GIM_Reject,
    // Label 1158: @25065
    GIM_Try, /*On fail goto*//*Label 1244*/ 25155,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 1245*/ 25097, // Rule ID 55129 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv8i32] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL4RE32_V:{ *:[nxv8i32] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL4RE32_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55129,
        GIR_Done,
      // Label 1245: @25097
      GIM_Try, /*On fail goto*//*Label 1246*/ 25116, // Rule ID 55130 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv8i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL4RE32_V:{ *:[nxv8i32] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL4RE32_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55130,
        GIR_Done,
      // Label 1246: @25116
      GIM_Try, /*On fail goto*//*Label 1247*/ 25135, // Rule ID 55165 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv8f32] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL4RE32_V:{ *:[nxv8f32] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL4RE32_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55165,
        GIR_Done,
      // Label 1247: @25135
      GIM_Try, /*On fail goto*//*Label 1248*/ 25154, // Rule ID 55166 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv8f32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL4RE32_V:{ *:[nxv8f32] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL4RE32_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55166,
        GIR_Done,
      // Label 1248: @25154
      GIM_Reject,
    // Label 1244: @25155
    GIM_Reject,
    // Label 1159: @25156
    GIM_Try, /*On fail goto*//*Label 1249*/ 25246,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 1250*/ 25188, // Rule ID 55145 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv8i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL8RE64_V:{ *:[nxv8i64] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL8RE64_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55145,
        GIR_Done,
      // Label 1250: @25188
      GIM_Try, /*On fail goto*//*Label 1251*/ 25207, // Rule ID 55146 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv8i64] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL8RE64_V:{ *:[nxv8i64] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL8RE64_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55146,
        GIR_Done,
      // Label 1251: @25207
      GIM_Try, /*On fail goto*//*Label 1252*/ 25226, // Rule ID 55181 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv8f64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL8RE64_V:{ *:[nxv8f64] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL8RE64_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55181,
        GIR_Done,
      // Label 1252: @25226
      GIM_Try, /*On fail goto*//*Label 1253*/ 25245, // Rule ID 55182 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv8f64] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL8RE64_V:{ *:[nxv8f64] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL8RE64_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55182,
        GIR_Done,
      // Label 1253: @25245
      GIM_Reject,
    // Label 1249: @25246
    GIM_Reject,
    // Label 1160: @25247
    GIM_Try, /*On fail goto*//*Label 1254*/ 25337,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1255*/ 25298, // Rule ID 55197 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv16i1] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLM_V_B16:{ *:[nxv16i1] } GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLM_V_B16,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55197,
        GIR_Done,
      // Label 1255: @25298
      GIM_Try, /*On fail goto*//*Label 1256*/ 25336, // Rule ID 55198 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv16i1] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLM_V_B16:{ *:[nxv16i1] } GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLM_V_B16,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55198,
        GIR_Done,
      // Label 1256: @25336
      GIM_Reject,
    // Label 1254: @25337
    GIM_Reject,
    // Label 1161: @25338
    GIM_Try, /*On fail goto*//*Label 1257*/ 25390,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 1258*/ 25370, // Rule ID 55101 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv16i8] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL2RE8_V:{ *:[nxv16i8] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL2RE8_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55101,
        GIR_Done,
      // Label 1258: @25370
      GIM_Try, /*On fail goto*//*Label 1259*/ 25389, // Rule ID 55102 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv16i8] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL2RE8_V:{ *:[nxv16i8] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL2RE8_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55102,
        GIR_Done,
      // Label 1259: @25389
      GIM_Reject,
    // Label 1257: @25390
    GIM_Reject,
    // Label 1162: @25391
    GIM_Try, /*On fail goto*//*Label 1260*/ 25481,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 1261*/ 25423, // Rule ID 55117 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv16i16] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL4RE16_V:{ *:[nxv16i16] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL4RE16_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55117,
        GIR_Done,
      // Label 1261: @25423
      GIM_Try, /*On fail goto*//*Label 1262*/ 25442, // Rule ID 55118 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv16i16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL4RE16_V:{ *:[nxv16i16] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL4RE16_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55118,
        GIR_Done,
      // Label 1262: @25442
      GIM_Try, /*On fail goto*//*Label 1263*/ 25461, // Rule ID 55153 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv16f16] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL4RE16_V:{ *:[nxv16f16] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL4RE16_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55153,
        GIR_Done,
      // Label 1263: @25461
      GIM_Try, /*On fail goto*//*Label 1264*/ 25480, // Rule ID 55154 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv16f16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL4RE16_V:{ *:[nxv16f16] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL4RE16_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55154,
        GIR_Done,
      // Label 1264: @25480
      GIM_Reject,
    // Label 1260: @25481
    GIM_Reject,
    // Label 1163: @25482
    GIM_Try, /*On fail goto*//*Label 1265*/ 25572,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 1266*/ 25514, // Rule ID 55133 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv16i32] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL8RE32_V:{ *:[nxv16i32] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL8RE32_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55133,
        GIR_Done,
      // Label 1266: @25514
      GIM_Try, /*On fail goto*//*Label 1267*/ 25533, // Rule ID 55134 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv16i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL8RE32_V:{ *:[nxv16i32] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL8RE32_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55134,
        GIR_Done,
      // Label 1267: @25533
      GIM_Try, /*On fail goto*//*Label 1268*/ 25552, // Rule ID 55169 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv16f32] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL8RE32_V:{ *:[nxv16f32] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL8RE32_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55169,
        GIR_Done,
      // Label 1268: @25552
      GIM_Try, /*On fail goto*//*Label 1269*/ 25571, // Rule ID 55170 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv16f32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL8RE32_V:{ *:[nxv16f32] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL8RE32_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55170,
        GIR_Done,
      // Label 1269: @25571
      GIM_Reject,
    // Label 1265: @25572
    GIM_Reject,
    // Label 1164: @25573
    GIM_Try, /*On fail goto*//*Label 1270*/ 25663,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1271*/ 25624, // Rule ID 55201 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv32i1] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLM_V_B32:{ *:[nxv32i1] } GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLM_V_B32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55201,
        GIR_Done,
      // Label 1271: @25624
      GIM_Try, /*On fail goto*//*Label 1272*/ 25662, // Rule ID 55202 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv32i1] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLM_V_B32:{ *:[nxv32i1] } GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLM_V_B32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55202,
        GIR_Done,
      // Label 1272: @25662
      GIM_Reject,
    // Label 1270: @25663
    GIM_Reject,
    // Label 1165: @25664
    GIM_Try, /*On fail goto*//*Label 1273*/ 25716,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 1274*/ 25696, // Rule ID 55105 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv32i8] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL4RE8_V:{ *:[nxv32i8] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL4RE8_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55105,
        GIR_Done,
      // Label 1274: @25696
      GIM_Try, /*On fail goto*//*Label 1275*/ 25715, // Rule ID 55106 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv32i8] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL4RE8_V:{ *:[nxv32i8] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL4RE8_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55106,
        GIR_Done,
      // Label 1275: @25715
      GIM_Reject,
    // Label 1273: @25716
    GIM_Reject,
    // Label 1166: @25717
    GIM_Try, /*On fail goto*//*Label 1276*/ 25807,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 1277*/ 25749, // Rule ID 55121 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv32i16] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL8RE16_V:{ *:[nxv32i16] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL8RE16_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55121,
        GIR_Done,
      // Label 1277: @25749
      GIM_Try, /*On fail goto*//*Label 1278*/ 25768, // Rule ID 55122 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv32i16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL8RE16_V:{ *:[nxv32i16] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL8RE16_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55122,
        GIR_Done,
      // Label 1278: @25768
      GIM_Try, /*On fail goto*//*Label 1279*/ 25787, // Rule ID 55157 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv32f16] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL8RE16_V:{ *:[nxv32f16] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL8RE16_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55157,
        GIR_Done,
      // Label 1279: @25787
      GIM_Try, /*On fail goto*//*Label 1280*/ 25806, // Rule ID 55158 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv32f16] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL8RE16_V:{ *:[nxv32f16] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL8RE16_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55158,
        GIR_Done,
      // Label 1280: @25806
      GIM_Reject,
    // Label 1276: @25807
    GIM_Reject,
    // Label 1167: @25808
    GIM_Try, /*On fail goto*//*Label 1281*/ 25898,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1282*/ 25859, // Rule ID 55205 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv64i1] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLM_V_B64:{ *:[nxv64i1] } GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLM_V_B64,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55205,
        GIR_Done,
      // Label 1282: @25859
      GIM_Try, /*On fail goto*//*Label 1283*/ 25897, // Rule ID 55206 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv64i1] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (PseudoVLM_V_B64:{ *:[nxv64i1] } GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVLM_V_B64,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55206,
        GIR_Done,
      // Label 1283: @25897
      GIM_Reject,
    // Label 1281: @25898
    GIM_Reject,
    // Label 1168: @25899
    GIM_Try, /*On fail goto*//*Label 1284*/ 25951,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 1285*/ 25931, // Rule ID 55109 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv64i8] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL8RE8_V:{ *:[nxv64i8] } GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL8RE8_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55109,
        GIR_Done,
      // Label 1285: @25931
      GIM_Try, /*On fail goto*//*Label 1286*/ 25950, // Rule ID 55110 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (ld:{ *:[nxv64i8] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (VL8RE8_V:{ *:[nxv64i8] } GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VL8RE8_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55110,
        GIR_Done,
      // Label 1286: @25950
      GIM_Reject,
    // Label 1284: @25951
    GIM_Reject,
    // Label 1169: @25952
    GIM_Reject,
    // Label 13: @25953
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 32, /*)*//*default:*//*Label 1316*/ 28587,
    /*GILLT_nxv1s1*//*Label 1287*/ 25988,
    /*GILLT_nxv1s8*//*Label 1288*/ 26075,
    /*GILLT_nxv1s16*//*Label 1289*/ 26162,
    /*GILLT_nxv1s32*//*Label 1290*/ 26325,
    /*GILLT_nxv1s64*//*Label 1291*/ 26488,
    /*GILLT_nxv2s1*//*Label 1292*/ 26575,
    /*GILLT_nxv2s8*//*Label 1293*/ 26662,
    /*GILLT_nxv2s16*//*Label 1294*/ 26749,
    /*GILLT_nxv2s32*//*Label 1295*/ 26912,
    /*GILLT_nxv2s64*//*Label 1296*/ 26999,
    /*GILLT_nxv4s1*//*Label 1297*/ 27086,
    /*GILLT_nxv4s8*//*Label 1298*/ 27173,
    /*GILLT_nxv4s16*//*Label 1299*/ 27260,
    /*GILLT_nxv4s32*//*Label 1300*/ 27347,
    /*GILLT_nxv4s64*//*Label 1301*/ 27434,
    /*GILLT_nxv8s1*//*Label 1302*/ 27521,
    /*GILLT_nxv8s8*//*Label 1303*/ 27608,
    /*GILLT_nxv8s16*//*Label 1304*/ 27657,
    /*GILLT_nxv8s32*//*Label 1305*/ 27744,
    /*GILLT_nxv8s64*//*Label 1306*/ 27831,
    /*GILLT_nxv16s1*//*Label 1307*/ 27918,
    /*GILLT_nxv16s8*//*Label 1308*/ 28005,
    /*GILLT_nxv16s16*//*Label 1309*/ 28054,
    /*GILLT_nxv16s32*//*Label 1310*/ 28141,
    /*GILLT_nxv32s1*//*Label 1311*/ 28228,
    /*GILLT_nxv32s8*//*Label 1312*/ 28315,
    /*GILLT_nxv32s16*//*Label 1313*/ 28364,
    /*GILLT_nxv64s1*//*Label 1314*/ 28451,
    /*GILLT_nxv64s8*//*Label 1315*/ 28538,
    // Label 1287: @25988
    GIM_Try, /*On fail goto*//*Label 1317*/ 26074,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1318*/ 26035, // Rule ID 54935 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv1i1:{ *:[nxv1i1] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSM_V_B1 VR:{ *:[nxv1i1] }:$rs2, GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSM_V_B1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 54935,
        GIR_Done,
      // Label 1318: @26035
      GIM_Try, /*On fail goto*//*Label 1319*/ 26073, // Rule ID 54936 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv1i1:{ *:[nxv1i1] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSM_V_B1 VR:{ *:[nxv1i1] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSM_V_B1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 54936,
        GIR_Done,
      // Label 1319: @26073
      GIM_Reject,
    // Label 1317: @26074
    GIM_Reject,
    // Label 1288: @26075
    GIM_Try, /*On fail goto*//*Label 1320*/ 26161,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1321*/ 26122, // Rule ID 54927 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv1i8:{ *:[nxv1i8] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSE8_V_MF8 VR:{ *:[nxv1i8] }:$rs2, GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSE8_V_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 54927,
        GIR_Done,
      // Label 1321: @26122
      GIM_Try, /*On fail goto*//*Label 1322*/ 26160, // Rule ID 54928 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv1i8:{ *:[nxv1i8] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSE8_V_MF8 VR:{ *:[nxv1i8] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSE8_V_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 54928,
        GIR_Done,
      // Label 1322: @26160
      GIM_Reject,
    // Label 1320: @26161
    GIM_Reject,
    // Label 1289: @26162
    GIM_Try, /*On fail goto*//*Label 1323*/ 26324,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1324*/ 26209, // Rule ID 55055 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv1i16:{ *:[nxv1i16] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSE16_V_MF4 VR:{ *:[nxv1i16] }:$rs2, GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSE16_V_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55055,
        GIR_Done,
      // Label 1324: @26209
      GIM_Try, /*On fail goto*//*Label 1325*/ 26247, // Rule ID 55056 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv1i16:{ *:[nxv1i16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSE16_V_MF4 VR:{ *:[nxv1i16] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSE16_V_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55056,
        GIR_Done,
      // Label 1325: @26247
      GIM_Try, /*On fail goto*//*Label 1326*/ 26285, // Rule ID 55067 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv1f16:{ *:[nxv1f16] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSE16_V_MF4 VR:{ *:[nxv1f16] }:$rs2, GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSE16_V_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55067,
        GIR_Done,
      // Label 1326: @26285
      GIM_Try, /*On fail goto*//*Label 1327*/ 26323, // Rule ID 55068 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv1f16:{ *:[nxv1f16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSE16_V_MF4 VR:{ *:[nxv1f16] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSE16_V_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55068,
        GIR_Done,
      // Label 1327: @26323
      GIM_Reject,
    // Label 1323: @26324
    GIM_Reject,
    // Label 1290: @26325
    GIM_Try, /*On fail goto*//*Label 1328*/ 26487,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1329*/ 26372, // Rule ID 55063 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv1i32:{ *:[nxv1i32] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSE32_V_MF2 VR:{ *:[nxv1i32] }:$rs2, GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSE32_V_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55063,
        GIR_Done,
      // Label 1329: @26372
      GIM_Try, /*On fail goto*//*Label 1330*/ 26410, // Rule ID 55064 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv1i32:{ *:[nxv1i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSE32_V_MF2 VR:{ *:[nxv1i32] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSE32_V_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55064,
        GIR_Done,
      // Label 1330: @26410
      GIM_Try, /*On fail goto*//*Label 1331*/ 26448, // Rule ID 55075 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv1f32:{ *:[nxv1f32] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSE32_V_MF2 VR:{ *:[nxv1f32] }:$rs2, GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSE32_V_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55075,
        GIR_Done,
      // Label 1331: @26448
      GIM_Try, /*On fail goto*//*Label 1332*/ 26486, // Rule ID 55076 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv1f32:{ *:[nxv1f32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSE32_V_MF2 VR:{ *:[nxv1f32] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSE32_V_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55076,
        GIR_Done,
      // Label 1332: @26486
      GIM_Reject,
    // Label 1328: @26487
    GIM_Reject,
    // Label 1291: @26488
    GIM_Try, /*On fail goto*//*Label 1333*/ 26574,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1334*/ 26516, // Rule ID 55087 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv1i64:{ *:[nxv1i64] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS1R_V VR:{ *:[nxv1i64] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS1R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55087,
        GIR_Done,
      // Label 1334: @26516
      GIM_Try, /*On fail goto*//*Label 1335*/ 26535, // Rule ID 55088 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv1i64:{ *:[nxv1i64] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS1R_V VR:{ *:[nxv1i64] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS1R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55088,
        GIR_Done,
      // Label 1335: @26535
      GIM_Try, /*On fail goto*//*Label 1336*/ 26554, // Rule ID 55099 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv1f64:{ *:[nxv1f64] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS1R_V VR:{ *:[nxv1f64] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS1R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55099,
        GIR_Done,
      // Label 1336: @26554
      GIM_Try, /*On fail goto*//*Label 1337*/ 26573, // Rule ID 55100 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv1f64:{ *:[nxv1f64] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS1R_V VR:{ *:[nxv1f64] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS1R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55100,
        GIR_Done,
      // Label 1337: @26573
      GIM_Reject,
    // Label 1333: @26574
    GIM_Reject,
    // Label 1292: @26575
    GIM_Try, /*On fail goto*//*Label 1338*/ 26661,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1339*/ 26622, // Rule ID 55187 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv2i1:{ *:[nxv2i1] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSM_V_B2 VR:{ *:[nxv2i1] }:$rs2, GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSM_V_B2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55187,
        GIR_Done,
      // Label 1339: @26622
      GIM_Try, /*On fail goto*//*Label 1340*/ 26660, // Rule ID 55188 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv2i1:{ *:[nxv2i1] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSM_V_B2 VR:{ *:[nxv2i1] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSM_V_B2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55188,
        GIR_Done,
      // Label 1340: @26660
      GIM_Reject,
    // Label 1338: @26661
    GIM_Reject,
    // Label 1293: @26662
    GIM_Try, /*On fail goto*//*Label 1341*/ 26748,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1342*/ 26709, // Rule ID 55047 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv2i8:{ *:[nxv2i8] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSE8_V_MF4 VR:{ *:[nxv2i8] }:$rs2, GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSE8_V_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55047,
        GIR_Done,
      // Label 1342: @26709
      GIM_Try, /*On fail goto*//*Label 1343*/ 26747, // Rule ID 55048 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv2i8:{ *:[nxv2i8] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSE8_V_MF4 VR:{ *:[nxv2i8] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSE8_V_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55048,
        GIR_Done,
      // Label 1343: @26747
      GIM_Reject,
    // Label 1341: @26748
    GIM_Reject,
    // Label 1294: @26749
    GIM_Try, /*On fail goto*//*Label 1344*/ 26911,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1345*/ 26796, // Rule ID 55059 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv2i16:{ *:[nxv2i16] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSE16_V_MF2 VR:{ *:[nxv2i16] }:$rs2, GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSE16_V_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55059,
        GIR_Done,
      // Label 1345: @26796
      GIM_Try, /*On fail goto*//*Label 1346*/ 26834, // Rule ID 55060 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv2i16:{ *:[nxv2i16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSE16_V_MF2 VR:{ *:[nxv2i16] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSE16_V_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55060,
        GIR_Done,
      // Label 1346: @26834
      GIM_Try, /*On fail goto*//*Label 1347*/ 26872, // Rule ID 55071 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv2f16:{ *:[nxv2f16] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSE16_V_MF2 VR:{ *:[nxv2f16] }:$rs2, GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSE16_V_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55071,
        GIR_Done,
      // Label 1347: @26872
      GIM_Try, /*On fail goto*//*Label 1348*/ 26910, // Rule ID 55072 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv2f16:{ *:[nxv2f16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSE16_V_MF2 VR:{ *:[nxv2f16] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSE16_V_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55072,
        GIR_Done,
      // Label 1348: @26910
      GIM_Reject,
    // Label 1344: @26911
    GIM_Reject,
    // Label 1295: @26912
    GIM_Try, /*On fail goto*//*Label 1349*/ 26998,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1350*/ 26940, // Rule ID 55083 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv2i32:{ *:[nxv2i32] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS1R_V VR:{ *:[nxv2i32] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS1R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55083,
        GIR_Done,
      // Label 1350: @26940
      GIM_Try, /*On fail goto*//*Label 1351*/ 26959, // Rule ID 55084 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv2i32:{ *:[nxv2i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS1R_V VR:{ *:[nxv2i32] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS1R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55084,
        GIR_Done,
      // Label 1351: @26959
      GIM_Try, /*On fail goto*//*Label 1352*/ 26978, // Rule ID 55095 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv2f32:{ *:[nxv2f32] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS1R_V VR:{ *:[nxv2f32] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS1R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55095,
        GIR_Done,
      // Label 1352: @26978
      GIM_Try, /*On fail goto*//*Label 1353*/ 26997, // Rule ID 55096 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv2f32:{ *:[nxv2f32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS1R_V VR:{ *:[nxv2f32] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS1R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55096,
        GIR_Done,
      // Label 1353: @26997
      GIM_Reject,
    // Label 1349: @26998
    GIM_Reject,
    // Label 1296: @26999
    GIM_Try, /*On fail goto*//*Label 1354*/ 27085,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1355*/ 27027, // Rule ID 55139 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv2i64:{ *:[nxv2i64] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS2R_V VRM2:{ *:[nxv2i64] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS2R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55139,
        GIR_Done,
      // Label 1355: @27027
      GIM_Try, /*On fail goto*//*Label 1356*/ 27046, // Rule ID 55140 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv2i64:{ *:[nxv2i64] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS2R_V VRM2:{ *:[nxv2i64] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS2R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55140,
        GIR_Done,
      // Label 1356: @27046
      GIM_Try, /*On fail goto*//*Label 1357*/ 27065, // Rule ID 55175 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv2f64:{ *:[nxv2f64] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS2R_V VRM2:{ *:[nxv2f64] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS2R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55175,
        GIR_Done,
      // Label 1357: @27065
      GIM_Try, /*On fail goto*//*Label 1358*/ 27084, // Rule ID 55176 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv2f64:{ *:[nxv2f64] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS2R_V VRM2:{ *:[nxv2f64] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS2R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55176,
        GIR_Done,
      // Label 1358: @27084
      GIM_Reject,
    // Label 1354: @27085
    GIM_Reject,
    // Label 1297: @27086
    GIM_Try, /*On fail goto*//*Label 1359*/ 27172,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1360*/ 27133, // Rule ID 55191 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv4i1:{ *:[nxv4i1] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSM_V_B4 VR:{ *:[nxv4i1] }:$rs2, GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSM_V_B4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55191,
        GIR_Done,
      // Label 1360: @27133
      GIM_Try, /*On fail goto*//*Label 1361*/ 27171, // Rule ID 55192 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv4i1:{ *:[nxv4i1] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSM_V_B4 VR:{ *:[nxv4i1] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSM_V_B4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55192,
        GIR_Done,
      // Label 1361: @27171
      GIM_Reject,
    // Label 1359: @27172
    GIM_Reject,
    // Label 1298: @27173
    GIM_Try, /*On fail goto*//*Label 1362*/ 27259,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1363*/ 27220, // Rule ID 55051 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv4i8:{ *:[nxv4i8] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSE8_V_MF2 VR:{ *:[nxv4i8] }:$rs2, GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSE8_V_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55051,
        GIR_Done,
      // Label 1363: @27220
      GIM_Try, /*On fail goto*//*Label 1364*/ 27258, // Rule ID 55052 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv4i8:{ *:[nxv4i8] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSE8_V_MF2 VR:{ *:[nxv4i8] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSE8_V_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55052,
        GIR_Done,
      // Label 1364: @27258
      GIM_Reject,
    // Label 1362: @27259
    GIM_Reject,
    // Label 1299: @27260
    GIM_Try, /*On fail goto*//*Label 1365*/ 27346,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1366*/ 27288, // Rule ID 55079 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv4i16:{ *:[nxv4i16] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS1R_V VR:{ *:[nxv4i16] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS1R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55079,
        GIR_Done,
      // Label 1366: @27288
      GIM_Try, /*On fail goto*//*Label 1367*/ 27307, // Rule ID 55080 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv4i16:{ *:[nxv4i16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS1R_V VR:{ *:[nxv4i16] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS1R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55080,
        GIR_Done,
      // Label 1367: @27307
      GIM_Try, /*On fail goto*//*Label 1368*/ 27326, // Rule ID 55091 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv4f16:{ *:[nxv4f16] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS1R_V VR:{ *:[nxv4f16] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS1R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55091,
        GIR_Done,
      // Label 1368: @27326
      GIM_Try, /*On fail goto*//*Label 1369*/ 27345, // Rule ID 55092 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv4f16:{ *:[nxv4f16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS1R_V VR:{ *:[nxv4f16] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS1R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55092,
        GIR_Done,
      // Label 1369: @27345
      GIM_Reject,
    // Label 1365: @27346
    GIM_Reject,
    // Label 1300: @27347
    GIM_Try, /*On fail goto*//*Label 1370*/ 27433,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1371*/ 27375, // Rule ID 55127 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv4i32:{ *:[nxv4i32] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS2R_V VRM2:{ *:[nxv4i32] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS2R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55127,
        GIR_Done,
      // Label 1371: @27375
      GIM_Try, /*On fail goto*//*Label 1372*/ 27394, // Rule ID 55128 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv4i32:{ *:[nxv4i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS2R_V VRM2:{ *:[nxv4i32] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS2R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55128,
        GIR_Done,
      // Label 1372: @27394
      GIM_Try, /*On fail goto*//*Label 1373*/ 27413, // Rule ID 55163 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv4f32:{ *:[nxv4f32] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS2R_V VRM2:{ *:[nxv4f32] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS2R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55163,
        GIR_Done,
      // Label 1373: @27413
      GIM_Try, /*On fail goto*//*Label 1374*/ 27432, // Rule ID 55164 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv4f32:{ *:[nxv4f32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS2R_V VRM2:{ *:[nxv4f32] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS2R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55164,
        GIR_Done,
      // Label 1374: @27432
      GIM_Reject,
    // Label 1370: @27433
    GIM_Reject,
    // Label 1301: @27434
    GIM_Try, /*On fail goto*//*Label 1375*/ 27520,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1376*/ 27462, // Rule ID 55143 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv4i64:{ *:[nxv4i64] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS4R_V VRM4:{ *:[nxv4i64] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS4R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55143,
        GIR_Done,
      // Label 1376: @27462
      GIM_Try, /*On fail goto*//*Label 1377*/ 27481, // Rule ID 55144 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv4i64:{ *:[nxv4i64] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS4R_V VRM4:{ *:[nxv4i64] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS4R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55144,
        GIR_Done,
      // Label 1377: @27481
      GIM_Try, /*On fail goto*//*Label 1378*/ 27500, // Rule ID 55179 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv4f64:{ *:[nxv4f64] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS4R_V VRM4:{ *:[nxv4f64] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS4R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55179,
        GIR_Done,
      // Label 1378: @27500
      GIM_Try, /*On fail goto*//*Label 1379*/ 27519, // Rule ID 55180 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv4f64:{ *:[nxv4f64] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS4R_V VRM4:{ *:[nxv4f64] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS4R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55180,
        GIR_Done,
      // Label 1379: @27519
      GIM_Reject,
    // Label 1375: @27520
    GIM_Reject,
    // Label 1302: @27521
    GIM_Try, /*On fail goto*//*Label 1380*/ 27607,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1381*/ 27568, // Rule ID 55195 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv8i1:{ *:[nxv8i1] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSM_V_B8 VR:{ *:[nxv8i1] }:$rs2, GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSM_V_B8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55195,
        GIR_Done,
      // Label 1381: @27568
      GIM_Try, /*On fail goto*//*Label 1382*/ 27606, // Rule ID 55196 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv8i1:{ *:[nxv8i1] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSM_V_B8 VR:{ *:[nxv8i1] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSM_V_B8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55196,
        GIR_Done,
      // Label 1382: @27606
      GIM_Reject,
    // Label 1380: @27607
    GIM_Reject,
    // Label 1303: @27608
    GIM_Try, /*On fail goto*//*Label 1383*/ 27656,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1384*/ 27636, // Rule ID 54931 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv8i8:{ *:[nxv8i8] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS1R_V VR:{ *:[nxv8i8] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS1R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 54931,
        GIR_Done,
      // Label 1384: @27636
      GIM_Try, /*On fail goto*//*Label 1385*/ 27655, // Rule ID 54932 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv8i8:{ *:[nxv8i8] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS1R_V VR:{ *:[nxv8i8] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS1R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 54932,
        GIR_Done,
      // Label 1385: @27655
      GIM_Reject,
    // Label 1383: @27656
    GIM_Reject,
    // Label 1304: @27657
    GIM_Try, /*On fail goto*//*Label 1386*/ 27743,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1387*/ 27685, // Rule ID 55115 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv8i16:{ *:[nxv8i16] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS2R_V VRM2:{ *:[nxv8i16] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS2R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55115,
        GIR_Done,
      // Label 1387: @27685
      GIM_Try, /*On fail goto*//*Label 1388*/ 27704, // Rule ID 55116 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv8i16:{ *:[nxv8i16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS2R_V VRM2:{ *:[nxv8i16] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS2R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55116,
        GIR_Done,
      // Label 1388: @27704
      GIM_Try, /*On fail goto*//*Label 1389*/ 27723, // Rule ID 55151 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv8f16:{ *:[nxv8f16] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS2R_V VRM2:{ *:[nxv8f16] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS2R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55151,
        GIR_Done,
      // Label 1389: @27723
      GIM_Try, /*On fail goto*//*Label 1390*/ 27742, // Rule ID 55152 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv8f16:{ *:[nxv8f16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS2R_V VRM2:{ *:[nxv8f16] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS2R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55152,
        GIR_Done,
      // Label 1390: @27742
      GIM_Reject,
    // Label 1386: @27743
    GIM_Reject,
    // Label 1305: @27744
    GIM_Try, /*On fail goto*//*Label 1391*/ 27830,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1392*/ 27772, // Rule ID 55131 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv8i32:{ *:[nxv8i32] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS4R_V VRM4:{ *:[nxv8i32] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS4R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55131,
        GIR_Done,
      // Label 1392: @27772
      GIM_Try, /*On fail goto*//*Label 1393*/ 27791, // Rule ID 55132 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv8i32:{ *:[nxv8i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS4R_V VRM4:{ *:[nxv8i32] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS4R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55132,
        GIR_Done,
      // Label 1393: @27791
      GIM_Try, /*On fail goto*//*Label 1394*/ 27810, // Rule ID 55167 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv8f32:{ *:[nxv8f32] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS4R_V VRM4:{ *:[nxv8f32] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS4R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55167,
        GIR_Done,
      // Label 1394: @27810
      GIM_Try, /*On fail goto*//*Label 1395*/ 27829, // Rule ID 55168 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv8f32:{ *:[nxv8f32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS4R_V VRM4:{ *:[nxv8f32] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS4R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55168,
        GIR_Done,
      // Label 1395: @27829
      GIM_Reject,
    // Label 1391: @27830
    GIM_Reject,
    // Label 1306: @27831
    GIM_Try, /*On fail goto*//*Label 1396*/ 27917,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1397*/ 27859, // Rule ID 55147 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv8i64:{ *:[nxv8i64] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS8R_V VRM8:{ *:[nxv8i64] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS8R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55147,
        GIR_Done,
      // Label 1397: @27859
      GIM_Try, /*On fail goto*//*Label 1398*/ 27878, // Rule ID 55148 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv8i64:{ *:[nxv8i64] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS8R_V VRM8:{ *:[nxv8i64] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS8R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55148,
        GIR_Done,
      // Label 1398: @27878
      GIM_Try, /*On fail goto*//*Label 1399*/ 27897, // Rule ID 55183 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv8f64:{ *:[nxv8f64] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS8R_V VRM8:{ *:[nxv8f64] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS8R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55183,
        GIR_Done,
      // Label 1399: @27897
      GIM_Try, /*On fail goto*//*Label 1400*/ 27916, // Rule ID 55184 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv8f64:{ *:[nxv8f64] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS8R_V VRM8:{ *:[nxv8f64] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS8R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55184,
        GIR_Done,
      // Label 1400: @27916
      GIM_Reject,
    // Label 1396: @27917
    GIM_Reject,
    // Label 1307: @27918
    GIM_Try, /*On fail goto*//*Label 1401*/ 28004,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1402*/ 27965, // Rule ID 55199 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv16i1:{ *:[nxv16i1] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSM_V_B16 VR:{ *:[nxv16i1] }:$rs2, GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSM_V_B16,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55199,
        GIR_Done,
      // Label 1402: @27965
      GIM_Try, /*On fail goto*//*Label 1403*/ 28003, // Rule ID 55200 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv16i1:{ *:[nxv16i1] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSM_V_B16 VR:{ *:[nxv16i1] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSM_V_B16,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55200,
        GIR_Done,
      // Label 1403: @28003
      GIM_Reject,
    // Label 1401: @28004
    GIM_Reject,
    // Label 1308: @28005
    GIM_Try, /*On fail goto*//*Label 1404*/ 28053,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1405*/ 28033, // Rule ID 55103 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv16i8:{ *:[nxv16i8] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS2R_V VRM2:{ *:[nxv16i8] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS2R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55103,
        GIR_Done,
      // Label 1405: @28033
      GIM_Try, /*On fail goto*//*Label 1406*/ 28052, // Rule ID 55104 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv16i8:{ *:[nxv16i8] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS2R_V VRM2:{ *:[nxv16i8] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS2R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55104,
        GIR_Done,
      // Label 1406: @28052
      GIM_Reject,
    // Label 1404: @28053
    GIM_Reject,
    // Label 1309: @28054
    GIM_Try, /*On fail goto*//*Label 1407*/ 28140,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1408*/ 28082, // Rule ID 55119 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv16i16:{ *:[nxv16i16] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS4R_V VRM4:{ *:[nxv16i16] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS4R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55119,
        GIR_Done,
      // Label 1408: @28082
      GIM_Try, /*On fail goto*//*Label 1409*/ 28101, // Rule ID 55120 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv16i16:{ *:[nxv16i16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS4R_V VRM4:{ *:[nxv16i16] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS4R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55120,
        GIR_Done,
      // Label 1409: @28101
      GIM_Try, /*On fail goto*//*Label 1410*/ 28120, // Rule ID 55155 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv16f16:{ *:[nxv16f16] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS4R_V VRM4:{ *:[nxv16f16] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS4R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55155,
        GIR_Done,
      // Label 1410: @28120
      GIM_Try, /*On fail goto*//*Label 1411*/ 28139, // Rule ID 55156 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv16f16:{ *:[nxv16f16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS4R_V VRM4:{ *:[nxv16f16] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS4R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55156,
        GIR_Done,
      // Label 1411: @28139
      GIM_Reject,
    // Label 1407: @28140
    GIM_Reject,
    // Label 1310: @28141
    GIM_Try, /*On fail goto*//*Label 1412*/ 28227,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1413*/ 28169, // Rule ID 55135 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv16i32:{ *:[nxv16i32] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS8R_V VRM8:{ *:[nxv16i32] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS8R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55135,
        GIR_Done,
      // Label 1413: @28169
      GIM_Try, /*On fail goto*//*Label 1414*/ 28188, // Rule ID 55136 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv16i32:{ *:[nxv16i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS8R_V VRM8:{ *:[nxv16i32] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS8R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55136,
        GIR_Done,
      // Label 1414: @28188
      GIM_Try, /*On fail goto*//*Label 1415*/ 28207, // Rule ID 55171 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv16f32:{ *:[nxv16f32] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS8R_V VRM8:{ *:[nxv16f32] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS8R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55171,
        GIR_Done,
      // Label 1415: @28207
      GIM_Try, /*On fail goto*//*Label 1416*/ 28226, // Rule ID 55172 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv16f32:{ *:[nxv16f32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS8R_V VRM8:{ *:[nxv16f32] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS8R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55172,
        GIR_Done,
      // Label 1416: @28226
      GIM_Reject,
    // Label 1412: @28227
    GIM_Reject,
    // Label 1311: @28228
    GIM_Try, /*On fail goto*//*Label 1417*/ 28314,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1418*/ 28275, // Rule ID 55203 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv32i1:{ *:[nxv32i1] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSM_V_B32 VR:{ *:[nxv32i1] }:$rs2, GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSM_V_B32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55203,
        GIR_Done,
      // Label 1418: @28275
      GIM_Try, /*On fail goto*//*Label 1419*/ 28313, // Rule ID 55204 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv32i1:{ *:[nxv32i1] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSM_V_B32 VR:{ *:[nxv32i1] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSM_V_B32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55204,
        GIR_Done,
      // Label 1419: @28313
      GIM_Reject,
    // Label 1417: @28314
    GIM_Reject,
    // Label 1312: @28315
    GIM_Try, /*On fail goto*//*Label 1420*/ 28363,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1421*/ 28343, // Rule ID 55107 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv32i8:{ *:[nxv32i8] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS4R_V VRM4:{ *:[nxv32i8] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS4R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55107,
        GIR_Done,
      // Label 1421: @28343
      GIM_Try, /*On fail goto*//*Label 1422*/ 28362, // Rule ID 55108 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv32i8:{ *:[nxv32i8] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS4R_V VRM4:{ *:[nxv32i8] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS4R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55108,
        GIR_Done,
      // Label 1422: @28362
      GIM_Reject,
    // Label 1420: @28363
    GIM_Reject,
    // Label 1313: @28364
    GIM_Try, /*On fail goto*//*Label 1423*/ 28450,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1424*/ 28392, // Rule ID 55123 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv32i16:{ *:[nxv32i16] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS8R_V VRM8:{ *:[nxv32i16] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS8R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55123,
        GIR_Done,
      // Label 1424: @28392
      GIM_Try, /*On fail goto*//*Label 1425*/ 28411, // Rule ID 55124 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv32i16:{ *:[nxv32i16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS8R_V VRM8:{ *:[nxv32i16] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS8R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55124,
        GIR_Done,
      // Label 1425: @28411
      GIM_Try, /*On fail goto*//*Label 1426*/ 28430, // Rule ID 55159 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv32f16:{ *:[nxv32f16] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS8R_V VRM8:{ *:[nxv32f16] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS8R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55159,
        GIR_Done,
      // Label 1426: @28430
      GIM_Try, /*On fail goto*//*Label 1427*/ 28449, // Rule ID 55160 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv32f16:{ *:[nxv32f16] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS8R_V VRM8:{ *:[nxv32f16] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS8R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55160,
        GIR_Done,
      // Label 1427: @28449
      GIM_Reject,
    // Label 1423: @28450
    GIM_Reject,
    // Label 1314: @28451
    GIM_Try, /*On fail goto*//*Label 1428*/ 28537,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1429*/ 28498, // Rule ID 55207 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv64i1:{ *:[nxv64i1] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSM_V_B64 VR:{ *:[nxv64i1] }:$rs2, GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, 0:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSM_V_B64,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55207,
        GIR_Done,
      // Label 1429: @28498
      GIM_Try, /*On fail goto*//*Label 1430*/ 28536, // Rule ID 55208 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv64i1:{ *:[nxv64i1] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (PseudoVSM_V_B64 VR:{ *:[nxv64i1] }:$rs2, GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSM_V_B64,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55208,
        GIR_Done,
      // Label 1430: @28536
      GIM_Reject,
    // Label 1428: @28537
    GIM_Reject,
    // Label 1315: @28538
    GIM_Try, /*On fail goto*//*Label 1431*/ 28586,
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
      GIM_Try, /*On fail goto*//*Label 1432*/ 28566, // Rule ID 55111 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv64i8:{ *:[nxv64i8] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS8R_V VRM8:{ *:[nxv64i8] }:$rs2, GPR:{ *:[i64] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS8R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55111,
        GIR_Done,
      // Label 1432: @28566
      GIM_Try, /*On fail goto*//*Label 1433*/ 28585, // Rule ID 55112 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        // (st nxv64i8:{ *:[nxv64i8] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (VS8R_V VRM8:{ *:[nxv64i8] }:$rs2, GPR:{ *:[i32] }:$rs1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::VS8R_V,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55112,
        GIR_Done,
      // Label 1433: @28585
      GIM_Reject,
    // Label 1431: @28586
    GIM_Reject,
    // Label 1316: @28587
    GIM_Reject,
    // Label 14: @28588
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1436*/ 30000,
    /*GILLT_s32*//*Label 1434*/ 28596,
    /*GILLT_s64*//*Label 1435*/ 29298,
    // Label 1434: @28596
    GIM_Try, /*On fail goto*//*Label 1437*/ 29297,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 1438*/ 28675, // Rule ID 65016 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_monotonic>>  =>  (PseudoCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 2:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoCmpXchg32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // new
        GIR_AddImm, /*InsnID*/0, /*Imm*/2,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65016,
        GIR_Done,
      // Label 1438: @28675
      GIM_Try, /*On fail goto*//*Label 1439*/ 28744, // Rule ID 65018 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_acquire>>  =>  (PseudoCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 4:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoCmpXchg32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // new
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65018,
        GIR_Done,
      // Label 1439: @28744
      GIM_Try, /*On fail goto*//*Label 1440*/ 28813, // Rule ID 65020 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_release>>  =>  (PseudoCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 5:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoCmpXchg32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // new
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65020,
        GIR_Done,
      // Label 1440: @28813
      GIM_Try, /*On fail goto*//*Label 1441*/ 28882, // Rule ID 65022 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_acq_rel>>  =>  (PseudoCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 6:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoCmpXchg32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // new
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65022,
        GIR_Done,
      // Label 1441: @28882
      GIM_Try, /*On fail goto*//*Label 1442*/ 28951, // Rule ID 65024 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_seq_cst>>  =>  (PseudoCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 7:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoCmpXchg32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // new
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65024,
        GIR_Done,
      // Label 1442: @28951
      GIM_Try, /*On fail goto*//*Label 1443*/ 29020, // Rule ID 65135 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_monotonic>>  =>  (PseudoCmpXchg64:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 2:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoCmpXchg64,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // new
        GIR_AddImm, /*InsnID*/0, /*Imm*/2,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65135,
        GIR_Done,
      // Label 1443: @29020
      GIM_Try, /*On fail goto*//*Label 1444*/ 29089, // Rule ID 65137 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_acquire>>  =>  (PseudoCmpXchg64:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 4:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoCmpXchg64,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // new
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65137,
        GIR_Done,
      // Label 1444: @29089
      GIM_Try, /*On fail goto*//*Label 1445*/ 29158, // Rule ID 65139 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_release>>  =>  (PseudoCmpXchg64:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 5:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoCmpXchg64,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // new
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65139,
        GIR_Done,
      // Label 1445: @29158
      GIM_Try, /*On fail goto*//*Label 1446*/ 29227, // Rule ID 65141 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_acq_rel>>  =>  (PseudoCmpXchg64:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 6:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoCmpXchg64,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // new
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65141,
        GIR_Done,
      // Label 1446: @29227
      GIM_Try, /*On fail goto*//*Label 1447*/ 29296, // Rule ID 65143 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_seq_cst>>  =>  (PseudoCmpXchg64:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 7:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoCmpXchg64,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // new
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65143,
        GIR_Done,
      // Label 1447: @29296
      GIM_Reject,
    // Label 1437: @29297
    GIM_Reject,
    // Label 1435: @29298
    GIM_Try, /*On fail goto*//*Label 1448*/ 29999,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 1449*/ 29377, // Rule ID 65015 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_monotonic>>  =>  (PseudoCmpXchg32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new, 2:{ *:[i64] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoCmpXchg32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // new
        GIR_AddImm, /*InsnID*/0, /*Imm*/2,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65015,
        GIR_Done,
      // Label 1449: @29377
      GIM_Try, /*On fail goto*//*Label 1450*/ 29446, // Rule ID 65017 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_acquire>>  =>  (PseudoCmpXchg32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new, 4:{ *:[i64] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoCmpXchg32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // new
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65017,
        GIR_Done,
      // Label 1450: @29446
      GIM_Try, /*On fail goto*//*Label 1451*/ 29515, // Rule ID 65019 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_release>>  =>  (PseudoCmpXchg32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new, 5:{ *:[i64] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoCmpXchg32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // new
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65019,
        GIR_Done,
      // Label 1451: @29515
      GIM_Try, /*On fail goto*//*Label 1452*/ 29584, // Rule ID 65021 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_acq_rel>>  =>  (PseudoCmpXchg32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new, 6:{ *:[i64] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoCmpXchg32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // new
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65021,
        GIR_Done,
      // Label 1452: @29584
      GIM_Try, /*On fail goto*//*Label 1453*/ 29653, // Rule ID 65023 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_seq_cst>>  =>  (PseudoCmpXchg32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new, 7:{ *:[i64] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoCmpXchg32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // new
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65023,
        GIR_Done,
      // Label 1453: @29653
      GIM_Try, /*On fail goto*//*Label 1454*/ 29722, // Rule ID 65134 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_monotonic>>  =>  (PseudoCmpXchg64:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new, 2:{ *:[i64] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoCmpXchg64,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // new
        GIR_AddImm, /*InsnID*/0, /*Imm*/2,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65134,
        GIR_Done,
      // Label 1454: @29722
      GIM_Try, /*On fail goto*//*Label 1455*/ 29791, // Rule ID 65136 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_acquire>>  =>  (PseudoCmpXchg64:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new, 4:{ *:[i64] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoCmpXchg64,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // new
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65136,
        GIR_Done,
      // Label 1455: @29791
      GIM_Try, /*On fail goto*//*Label 1456*/ 29860, // Rule ID 65138 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_release>>  =>  (PseudoCmpXchg64:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new, 5:{ *:[i64] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoCmpXchg64,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // new
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65138,
        GIR_Done,
      // Label 1456: @29860
      GIM_Try, /*On fail goto*//*Label 1457*/ 29929, // Rule ID 65140 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_acq_rel>>  =>  (PseudoCmpXchg64:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new, 6:{ *:[i64] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoCmpXchg64,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // new
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65140,
        GIR_Done,
      // Label 1457: @29929
      GIM_Try, /*On fail goto*//*Label 1458*/ 29998, // Rule ID 65142 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_seq_cst>>  =>  (PseudoCmpXchg64:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new, 7:{ *:[i64] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoCmpXchg64,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // new
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65142,
        GIR_Done,
      // Label 1458: @29998
      GIM_Reject,
    // Label 1448: @29999
    GIM_Reject,
    // Label 1436: @30000
    GIM_Reject,
    // Label 15: @30001
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1461*/ 30705,
    /*GILLT_s32*//*Label 1459*/ 30009,
    /*GILLT_s64*//*Label 1460*/ 30357,
    // Label 1459: @30009
    GIM_Try, /*On fail goto*//*Label 1462*/ 30356,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 1463*/ 30049, // Rule ID 63951 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_monotonic>>  =>  (AMOSWAP_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63951,
        GIR_Done,
      // Label 1463: @30049
      GIM_Try, /*On fail goto*//*Label 1464*/ 30083, // Rule ID 63971 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_acquire>>  =>  (AMOSWAP_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63971,
        GIR_Done,
      // Label 1464: @30083
      GIM_Try, /*On fail goto*//*Label 1465*/ 30117, // Rule ID 63993 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_release>>  =>  (AMOSWAP_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63993,
        GIR_Done,
      // Label 1465: @30117
      GIM_Try, /*On fail goto*//*Label 1466*/ 30151, // Rule ID 64015 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_acq_rel>>  =>  (AMOSWAP_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64015,
        GIR_Done,
      // Label 1466: @30151
      GIM_Try, /*On fail goto*//*Label 1467*/ 30185, // Rule ID 64037 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_seq_cst>>  =>  (AMOSWAP_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64037,
        GIR_Done,
      // Label 1467: @30185
      GIM_Try, /*On fail goto*//*Label 1468*/ 30219, // Rule ID 65027 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_monotonic>>  =>  (AMOSWAP_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65027,
        GIR_Done,
      // Label 1468: @30219
      GIM_Try, /*On fail goto*//*Label 1469*/ 30253, // Rule ID 65029 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_acquire>>  =>  (AMOSWAP_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65029,
        GIR_Done,
      // Label 1469: @30253
      GIM_Try, /*On fail goto*//*Label 1470*/ 30287, // Rule ID 65031 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_release>>  =>  (AMOSWAP_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65031,
        GIR_Done,
      // Label 1470: @30287
      GIM_Try, /*On fail goto*//*Label 1471*/ 30321, // Rule ID 65033 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_acq_rel>>  =>  (AMOSWAP_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65033,
        GIR_Done,
      // Label 1471: @30321
      GIM_Try, /*On fail goto*//*Label 1472*/ 30355, // Rule ID 65035 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_seq_cst>>  =>  (AMOSWAP_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65035,
        GIR_Done,
      // Label 1472: @30355
      GIM_Reject,
    // Label 1462: @30356
    GIM_Reject,
    // Label 1460: @30357
    GIM_Try, /*On fail goto*//*Label 1473*/ 30704,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 1474*/ 30397, // Rule ID 63950 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_monotonic>>  =>  (AMOSWAP_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63950,
        GIR_Done,
      // Label 1474: @30397
      GIM_Try, /*On fail goto*//*Label 1475*/ 30431, // Rule ID 63970 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_acquire>>  =>  (AMOSWAP_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63970,
        GIR_Done,
      // Label 1475: @30431
      GIM_Try, /*On fail goto*//*Label 1476*/ 30465, // Rule ID 63992 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_release>>  =>  (AMOSWAP_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63992,
        GIR_Done,
      // Label 1476: @30465
      GIM_Try, /*On fail goto*//*Label 1477*/ 30499, // Rule ID 64014 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_acq_rel>>  =>  (AMOSWAP_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64014,
        GIR_Done,
      // Label 1477: @30499
      GIM_Try, /*On fail goto*//*Label 1478*/ 30533, // Rule ID 64036 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_seq_cst>>  =>  (AMOSWAP_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64036,
        GIR_Done,
      // Label 1478: @30533
      GIM_Try, /*On fail goto*//*Label 1479*/ 30567, // Rule ID 65026 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_monotonic>>  =>  (AMOSWAP_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65026,
        GIR_Done,
      // Label 1479: @30567
      GIM_Try, /*On fail goto*//*Label 1480*/ 30601, // Rule ID 65028 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_acquire>>  =>  (AMOSWAP_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65028,
        GIR_Done,
      // Label 1480: @30601
      GIM_Try, /*On fail goto*//*Label 1481*/ 30635, // Rule ID 65030 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_release>>  =>  (AMOSWAP_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65030,
        GIR_Done,
      // Label 1481: @30635
      GIM_Try, /*On fail goto*//*Label 1482*/ 30669, // Rule ID 65032 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_acq_rel>>  =>  (AMOSWAP_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65032,
        GIR_Done,
      // Label 1482: @30669
      GIM_Try, /*On fail goto*//*Label 1483*/ 30703, // Rule ID 65034 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_seq_cst>>  =>  (AMOSWAP_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65034,
        GIR_Done,
      // Label 1483: @30703
      GIM_Reject,
    // Label 1473: @30704
    GIM_Reject,
    // Label 1461: @30705
    GIM_Reject,
    // Label 16: @30706
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1486*/ 31410,
    /*GILLT_s32*//*Label 1484*/ 30714,
    /*GILLT_s64*//*Label 1485*/ 31062,
    // Label 1484: @30714
    GIM_Try, /*On fail goto*//*Label 1487*/ 31061,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 1488*/ 30754, // Rule ID 64099 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_monotonic>>  =>  (AMOADD_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64099,
        GIR_Done,
      // Label 1488: @30754
      GIM_Try, /*On fail goto*//*Label 1489*/ 30788, // Rule ID 64121 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_acquire>>  =>  (AMOADD_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64121,
        GIR_Done,
      // Label 1489: @30788
      GIM_Try, /*On fail goto*//*Label 1490*/ 30822, // Rule ID 64143 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_release>>  =>  (AMOADD_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64143,
        GIR_Done,
      // Label 1490: @30822
      GIM_Try, /*On fail goto*//*Label 1491*/ 30856, // Rule ID 64163 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_acq_rel>>  =>  (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64163,
        GIR_Done,
      // Label 1491: @30856
      GIM_Try, /*On fail goto*//*Label 1492*/ 30890, // Rule ID 64183 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_seq_cst>>  =>  (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64183,
        GIR_Done,
      // Label 1492: @30890
      GIM_Try, /*On fail goto*//*Label 1493*/ 30924, // Rule ID 65037 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_monotonic>>  =>  (AMOADD_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65037,
        GIR_Done,
      // Label 1493: @30924
      GIM_Try, /*On fail goto*//*Label 1494*/ 30958, // Rule ID 65039 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_acquire>>  =>  (AMOADD_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65039,
        GIR_Done,
      // Label 1494: @30958
      GIM_Try, /*On fail goto*//*Label 1495*/ 30992, // Rule ID 65041 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_release>>  =>  (AMOADD_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65041,
        GIR_Done,
      // Label 1495: @30992
      GIM_Try, /*On fail goto*//*Label 1496*/ 31026, // Rule ID 65043 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_acq_rel>>  =>  (AMOADD_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65043,
        GIR_Done,
      // Label 1496: @31026
      GIM_Try, /*On fail goto*//*Label 1497*/ 31060, // Rule ID 65045 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_seq_cst>>  =>  (AMOADD_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65045,
        GIR_Done,
      // Label 1497: @31060
      GIM_Reject,
    // Label 1487: @31061
    GIM_Reject,
    // Label 1485: @31062
    GIM_Try, /*On fail goto*//*Label 1498*/ 31409,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 1499*/ 31102, // Rule ID 64098 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_monotonic>>  =>  (AMOADD_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64098,
        GIR_Done,
      // Label 1499: @31102
      GIM_Try, /*On fail goto*//*Label 1500*/ 31136, // Rule ID 64120 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_acquire>>  =>  (AMOADD_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64120,
        GIR_Done,
      // Label 1500: @31136
      GIM_Try, /*On fail goto*//*Label 1501*/ 31170, // Rule ID 64142 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_release>>  =>  (AMOADD_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64142,
        GIR_Done,
      // Label 1501: @31170
      GIM_Try, /*On fail goto*//*Label 1502*/ 31204, // Rule ID 64162 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_acq_rel>>  =>  (AMOADD_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64162,
        GIR_Done,
      // Label 1502: @31204
      GIM_Try, /*On fail goto*//*Label 1503*/ 31238, // Rule ID 64182 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_seq_cst>>  =>  (AMOADD_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64182,
        GIR_Done,
      // Label 1503: @31238
      GIM_Try, /*On fail goto*//*Label 1504*/ 31272, // Rule ID 65036 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_monotonic>>  =>  (AMOADD_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65036,
        GIR_Done,
      // Label 1504: @31272
      GIM_Try, /*On fail goto*//*Label 1505*/ 31306, // Rule ID 65038 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_acquire>>  =>  (AMOADD_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65038,
        GIR_Done,
      // Label 1505: @31306
      GIM_Try, /*On fail goto*//*Label 1506*/ 31340, // Rule ID 65040 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_release>>  =>  (AMOADD_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65040,
        GIR_Done,
      // Label 1506: @31340
      GIM_Try, /*On fail goto*//*Label 1507*/ 31374, // Rule ID 65042 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_acq_rel>>  =>  (AMOADD_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65042,
        GIR_Done,
      // Label 1507: @31374
      GIM_Try, /*On fail goto*//*Label 1508*/ 31408, // Rule ID 65044 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_seq_cst>>  =>  (AMOADD_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65044,
        GIR_Done,
      // Label 1508: @31408
      GIM_Reject,
    // Label 1498: @31409
    GIM_Reject,
    // Label 1486: @31410
    GIM_Reject,
    // Label 17: @31411
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1511*/ 32484,
    /*GILLT_s32*//*Label 1509*/ 31419,
    /*GILLT_s64*//*Label 1510*/ 31766,
    // Label 1509: @31419
    GIM_Try, /*On fail goto*//*Label 1512*/ 31765,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
      GIM_Try, /*On fail goto*//*Label 1513*/ 31496, // Rule ID 64848 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_monotonic>>  =>  (AMOADD_W:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
        GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64848,
        GIR_Done,
      // Label 1513: @31496
      GIM_Try, /*On fail goto*//*Label 1514*/ 31563, // Rule ID 64850 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_acquire>>  =>  (AMOADD_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
        GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64850,
        GIR_Done,
      // Label 1514: @31563
      GIM_Try, /*On fail goto*//*Label 1515*/ 31630, // Rule ID 64852 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_release>>  =>  (AMOADD_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
        GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_RL,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64852,
        GIR_Done,
      // Label 1515: @31630
      GIM_Try, /*On fail goto*//*Label 1516*/ 31697, // Rule ID 64854 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_acq_rel>>  =>  (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
        GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64854,
        GIR_Done,
      // Label 1516: @31697
      GIM_Try, /*On fail goto*//*Label 1517*/ 31764, // Rule ID 64874 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_seq_cst>>  =>  (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
        GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64874,
        GIR_Done,
      // Label 1517: @31764
      GIM_Reject,
    // Label 1512: @31765
    GIM_Reject,
    // Label 1510: @31766
    GIM_Try, /*On fail goto*//*Label 1518*/ 32483,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 1519*/ 31843, // Rule ID 64847 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_monotonic>>  =>  (AMOADD_W:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
        GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64847,
        GIR_Done,
      // Label 1519: @31843
      GIM_Try, /*On fail goto*//*Label 1520*/ 31914, // Rule ID 64849 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_acquire>>  =>  (AMOADD_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
        GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64849,
        GIR_Done,
      // Label 1520: @31914
      GIM_Try, /*On fail goto*//*Label 1521*/ 31985, // Rule ID 64851 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_release>>  =>  (AMOADD_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
        GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_RL,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64851,
        GIR_Done,
      // Label 1521: @31985
      GIM_Try, /*On fail goto*//*Label 1522*/ 32056, // Rule ID 64853 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_acq_rel>>  =>  (AMOADD_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
        GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64853,
        GIR_Done,
      // Label 1522: @32056
      GIM_Try, /*On fail goto*//*Label 1523*/ 32127, // Rule ID 64873 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_seq_cst>>  =>  (AMOADD_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
        GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64873,
        GIR_Done,
      // Label 1523: @32127
      GIM_Try, /*On fail goto*//*Label 1524*/ 32198, // Rule ID 65116 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_monotonic>>  =>  (AMOADD_D:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
        GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65116,
        GIR_Done,
      // Label 1524: @32198
      GIM_Try, /*On fail goto*//*Label 1525*/ 32269, // Rule ID 65117 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_acquire>>  =>  (AMOADD_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
        GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65117,
        GIR_Done,
      // Label 1525: @32269
      GIM_Try, /*On fail goto*//*Label 1526*/ 32340, // Rule ID 65118 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_release>>  =>  (AMOADD_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
        GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_RL,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65118,
        GIR_Done,
      // Label 1526: @32340
      GIM_Try, /*On fail goto*//*Label 1527*/ 32411, // Rule ID 65119 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_acq_rel>>  =>  (AMOADD_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
        GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65119,
        GIR_Done,
      // Label 1527: @32411
      GIM_Try, /*On fail goto*//*Label 1528*/ 32482, // Rule ID 65120 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_seq_cst>>  =>  (AMOADD_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
        GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65120,
        GIR_Done,
      // Label 1528: @32482
      GIM_Reject,
    // Label 1518: @32483
    GIM_Reject,
    // Label 1511: @32484
    GIM_Reject,
    // Label 18: @32485
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1531*/ 33189,
    /*GILLT_s32*//*Label 1529*/ 32493,
    /*GILLT_s64*//*Label 1530*/ 32841,
    // Label 1529: @32493
    GIM_Try, /*On fail goto*//*Label 1532*/ 32840,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 1533*/ 32533, // Rule ID 64223 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_monotonic>>  =>  (AMOAND_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64223,
        GIR_Done,
      // Label 1533: @32533
      GIM_Try, /*On fail goto*//*Label 1534*/ 32567, // Rule ID 64243 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_acquire>>  =>  (AMOAND_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64243,
        GIR_Done,
      // Label 1534: @32567
      GIM_Try, /*On fail goto*//*Label 1535*/ 32601, // Rule ID 64265 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_release>>  =>  (AMOAND_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64265,
        GIR_Done,
      // Label 1535: @32601
      GIM_Try, /*On fail goto*//*Label 1536*/ 32635, // Rule ID 64285 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_acq_rel>>  =>  (AMOAND_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64285,
        GIR_Done,
      // Label 1536: @32635
      GIM_Try, /*On fail goto*//*Label 1537*/ 32669, // Rule ID 64305 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_seq_cst>>  =>  (AMOAND_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64305,
        GIR_Done,
      // Label 1537: @32669
      GIM_Try, /*On fail goto*//*Label 1538*/ 32703, // Rule ID 65047 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_monotonic>>  =>  (AMOAND_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65047,
        GIR_Done,
      // Label 1538: @32703
      GIM_Try, /*On fail goto*//*Label 1539*/ 32737, // Rule ID 65049 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_acquire>>  =>  (AMOAND_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65049,
        GIR_Done,
      // Label 1539: @32737
      GIM_Try, /*On fail goto*//*Label 1540*/ 32771, // Rule ID 65051 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_release>>  =>  (AMOAND_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65051,
        GIR_Done,
      // Label 1540: @32771
      GIM_Try, /*On fail goto*//*Label 1541*/ 32805, // Rule ID 65053 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_acq_rel>>  =>  (AMOAND_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65053,
        GIR_Done,
      // Label 1541: @32805
      GIM_Try, /*On fail goto*//*Label 1542*/ 32839, // Rule ID 65055 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_seq_cst>>  =>  (AMOAND_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65055,
        GIR_Done,
      // Label 1542: @32839
      GIM_Reject,
    // Label 1532: @32840
    GIM_Reject,
    // Label 1530: @32841
    GIM_Try, /*On fail goto*//*Label 1543*/ 33188,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 1544*/ 32881, // Rule ID 64222 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_monotonic>>  =>  (AMOAND_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64222,
        GIR_Done,
      // Label 1544: @32881
      GIM_Try, /*On fail goto*//*Label 1545*/ 32915, // Rule ID 64242 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_acquire>>  =>  (AMOAND_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64242,
        GIR_Done,
      // Label 1545: @32915
      GIM_Try, /*On fail goto*//*Label 1546*/ 32949, // Rule ID 64264 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_release>>  =>  (AMOAND_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64264,
        GIR_Done,
      // Label 1546: @32949
      GIM_Try, /*On fail goto*//*Label 1547*/ 32983, // Rule ID 64284 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_acq_rel>>  =>  (AMOAND_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64284,
        GIR_Done,
      // Label 1547: @32983
      GIM_Try, /*On fail goto*//*Label 1548*/ 33017, // Rule ID 64304 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_seq_cst>>  =>  (AMOAND_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64304,
        GIR_Done,
      // Label 1548: @33017
      GIM_Try, /*On fail goto*//*Label 1549*/ 33051, // Rule ID 65046 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_monotonic>>  =>  (AMOAND_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65046,
        GIR_Done,
      // Label 1549: @33051
      GIM_Try, /*On fail goto*//*Label 1550*/ 33085, // Rule ID 65048 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_acquire>>  =>  (AMOAND_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65048,
        GIR_Done,
      // Label 1550: @33085
      GIM_Try, /*On fail goto*//*Label 1551*/ 33119, // Rule ID 65050 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_release>>  =>  (AMOAND_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65050,
        GIR_Done,
      // Label 1551: @33119
      GIM_Try, /*On fail goto*//*Label 1552*/ 33153, // Rule ID 65052 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_acq_rel>>  =>  (AMOAND_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65052,
        GIR_Done,
      // Label 1552: @33153
      GIM_Try, /*On fail goto*//*Label 1553*/ 33187, // Rule ID 65054 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_seq_cst>>  =>  (AMOAND_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65054,
        GIR_Done,
      // Label 1553: @33187
      GIM_Reject,
    // Label 1543: @33188
    GIM_Reject,
    // Label 1531: @33189
    GIM_Reject,
    // Label 19: @33190
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1556*/ 34113,
    /*GILLT_s32*//*Label 1554*/ 33198,
    /*GILLT_s64*//*Label 1555*/ 33495,
    // Label 1554: @33198
    GIM_Try, /*On fail goto*//*Label 1557*/ 33494,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
      GIM_Try, /*On fail goto*//*Label 1558*/ 33265, // Rule ID 64896 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_32>><<P:Predicate_atomic_load_nand_32_monotonic>>  =>  (PseudoAtomicLoadNand32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 2:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoAtomicLoadNand32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_AddImm, /*InsnID*/0, /*Imm*/2,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64896,
        GIR_Done,
      // Label 1558: @33265
      GIM_Try, /*On fail goto*//*Label 1559*/ 33322, // Rule ID 64916 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_32>><<P:Predicate_atomic_load_nand_32_acquire>>  =>  (PseudoAtomicLoadNand32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 4:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoAtomicLoadNand32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64916,
        GIR_Done,
      // Label 1559: @33322
      GIM_Try, /*On fail goto*//*Label 1560*/ 33379, // Rule ID 64938 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_32>><<P:Predicate_atomic_load_nand_32_release>>  =>  (PseudoAtomicLoadNand32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 5:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoAtomicLoadNand32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64938,
        GIR_Done,
      // Label 1560: @33379
      GIM_Try, /*On fail goto*//*Label 1561*/ 33436, // Rule ID 64958 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_32>><<P:Predicate_atomic_load_nand_32_acq_rel>>  =>  (PseudoAtomicLoadNand32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 6:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoAtomicLoadNand32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64958,
        GIR_Done,
      // Label 1561: @33436
      GIM_Try, /*On fail goto*//*Label 1562*/ 33493, // Rule ID 64980 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_32>><<P:Predicate_atomic_load_nand_32_seq_cst>>  =>  (PseudoAtomicLoadNand32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 7:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoAtomicLoadNand32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64980,
        GIR_Done,
      // Label 1562: @33493
      GIM_Reject,
    // Label 1557: @33494
    GIM_Reject,
    // Label 1555: @33495
    GIM_Try, /*On fail goto*//*Label 1563*/ 34112,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 1564*/ 33562, // Rule ID 64895 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_nand:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_32>><<P:Predicate_atomic_load_nand_32_monotonic>>  =>  (PseudoAtomicLoadNand32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, 2:{ *:[i64] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoAtomicLoadNand32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_AddImm, /*InsnID*/0, /*Imm*/2,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64895,
        GIR_Done,
      // Label 1564: @33562
      GIM_Try, /*On fail goto*//*Label 1565*/ 33623, // Rule ID 64915 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_nand:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_32>><<P:Predicate_atomic_load_nand_32_acquire>>  =>  (PseudoAtomicLoadNand32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, 4:{ *:[i64] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoAtomicLoadNand32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64915,
        GIR_Done,
      // Label 1565: @33623
      GIM_Try, /*On fail goto*//*Label 1566*/ 33684, // Rule ID 64937 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_nand:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_32>><<P:Predicate_atomic_load_nand_32_release>>  =>  (PseudoAtomicLoadNand32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, 5:{ *:[i64] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoAtomicLoadNand32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64937,
        GIR_Done,
      // Label 1566: @33684
      GIM_Try, /*On fail goto*//*Label 1567*/ 33745, // Rule ID 64957 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_nand:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_32>><<P:Predicate_atomic_load_nand_32_acq_rel>>  =>  (PseudoAtomicLoadNand32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, 6:{ *:[i64] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoAtomicLoadNand32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64957,
        GIR_Done,
      // Label 1567: @33745
      GIM_Try, /*On fail goto*//*Label 1568*/ 33806, // Rule ID 64979 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_nand:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_32>><<P:Predicate_atomic_load_nand_32_seq_cst>>  =>  (PseudoAtomicLoadNand32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, 7:{ *:[i64] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoAtomicLoadNand32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64979,
        GIR_Done,
      // Label 1568: @33806
      GIM_Try, /*On fail goto*//*Label 1569*/ 33867, // Rule ID 65121 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_nand:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_64>><<P:Predicate_atomic_load_nand_64_monotonic>>  =>  (PseudoAtomicLoadNand64:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, 2:{ *:[i64] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoAtomicLoadNand64,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_AddImm, /*InsnID*/0, /*Imm*/2,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65121,
        GIR_Done,
      // Label 1569: @33867
      GIM_Try, /*On fail goto*//*Label 1570*/ 33928, // Rule ID 65122 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_nand:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_64>><<P:Predicate_atomic_load_nand_64_acquire>>  =>  (PseudoAtomicLoadNand64:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, 4:{ *:[i64] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoAtomicLoadNand64,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65122,
        GIR_Done,
      // Label 1570: @33928
      GIM_Try, /*On fail goto*//*Label 1571*/ 33989, // Rule ID 65123 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_nand:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_64>><<P:Predicate_atomic_load_nand_64_release>>  =>  (PseudoAtomicLoadNand64:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, 5:{ *:[i64] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoAtomicLoadNand64,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65123,
        GIR_Done,
      // Label 1571: @33989
      GIM_Try, /*On fail goto*//*Label 1572*/ 34050, // Rule ID 65124 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_nand:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_64>><<P:Predicate_atomic_load_nand_64_acq_rel>>  =>  (PseudoAtomicLoadNand64:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, 6:{ *:[i64] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoAtomicLoadNand64,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65124,
        GIR_Done,
      // Label 1572: @34050
      GIM_Try, /*On fail goto*//*Label 1573*/ 34111, // Rule ID 65125 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_nand:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_64>><<P:Predicate_atomic_load_nand_64_seq_cst>>  =>  (PseudoAtomicLoadNand64:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, 7:{ *:[i64] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoAtomicLoadNand64,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // incr
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65125,
        GIR_Done,
      // Label 1573: @34111
      GIM_Reject,
    // Label 1563: @34112
    GIM_Reject,
    // Label 1556: @34113
    GIM_Reject,
    // Label 20: @34114
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1576*/ 34818,
    /*GILLT_s32*//*Label 1574*/ 34122,
    /*GILLT_s64*//*Label 1575*/ 34470,
    // Label 1574: @34122
    GIM_Try, /*On fail goto*//*Label 1577*/ 34469,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 1578*/ 34162, // Rule ID 64343 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_monotonic>>  =>  (AMOOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64343,
        GIR_Done,
      // Label 1578: @34162
      GIM_Try, /*On fail goto*//*Label 1579*/ 34196, // Rule ID 64365 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_acquire>>  =>  (AMOOR_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64365,
        GIR_Done,
      // Label 1579: @34196
      GIM_Try, /*On fail goto*//*Label 1580*/ 34230, // Rule ID 64385 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_release>>  =>  (AMOOR_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64385,
        GIR_Done,
      // Label 1580: @34230
      GIM_Try, /*On fail goto*//*Label 1581*/ 34264, // Rule ID 64405 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_acq_rel>>  =>  (AMOOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64405,
        GIR_Done,
      // Label 1581: @34264
      GIM_Try, /*On fail goto*//*Label 1582*/ 34298, // Rule ID 64427 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_seq_cst>>  =>  (AMOOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64427,
        GIR_Done,
      // Label 1582: @34298
      GIM_Try, /*On fail goto*//*Label 1583*/ 34332, // Rule ID 65057 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_monotonic>>  =>  (AMOOR_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65057,
        GIR_Done,
      // Label 1583: @34332
      GIM_Try, /*On fail goto*//*Label 1584*/ 34366, // Rule ID 65059 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_acquire>>  =>  (AMOOR_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65059,
        GIR_Done,
      // Label 1584: @34366
      GIM_Try, /*On fail goto*//*Label 1585*/ 34400, // Rule ID 65061 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_release>>  =>  (AMOOR_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65061,
        GIR_Done,
      // Label 1585: @34400
      GIM_Try, /*On fail goto*//*Label 1586*/ 34434, // Rule ID 65063 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_acq_rel>>  =>  (AMOOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65063,
        GIR_Done,
      // Label 1586: @34434
      GIM_Try, /*On fail goto*//*Label 1587*/ 34468, // Rule ID 65065 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_seq_cst>>  =>  (AMOOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65065,
        GIR_Done,
      // Label 1587: @34468
      GIM_Reject,
    // Label 1577: @34469
    GIM_Reject,
    // Label 1575: @34470
    GIM_Try, /*On fail goto*//*Label 1588*/ 34817,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 1589*/ 34510, // Rule ID 64342 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_monotonic>>  =>  (AMOOR_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64342,
        GIR_Done,
      // Label 1589: @34510
      GIM_Try, /*On fail goto*//*Label 1590*/ 34544, // Rule ID 64364 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_acquire>>  =>  (AMOOR_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64364,
        GIR_Done,
      // Label 1590: @34544
      GIM_Try, /*On fail goto*//*Label 1591*/ 34578, // Rule ID 64384 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_release>>  =>  (AMOOR_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64384,
        GIR_Done,
      // Label 1591: @34578
      GIM_Try, /*On fail goto*//*Label 1592*/ 34612, // Rule ID 64404 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_acq_rel>>  =>  (AMOOR_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64404,
        GIR_Done,
      // Label 1592: @34612
      GIM_Try, /*On fail goto*//*Label 1593*/ 34646, // Rule ID 64426 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_seq_cst>>  =>  (AMOOR_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64426,
        GIR_Done,
      // Label 1593: @34646
      GIM_Try, /*On fail goto*//*Label 1594*/ 34680, // Rule ID 65056 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_monotonic>>  =>  (AMOOR_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65056,
        GIR_Done,
      // Label 1594: @34680
      GIM_Try, /*On fail goto*//*Label 1595*/ 34714, // Rule ID 65058 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_acquire>>  =>  (AMOOR_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65058,
        GIR_Done,
      // Label 1595: @34714
      GIM_Try, /*On fail goto*//*Label 1596*/ 34748, // Rule ID 65060 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_release>>  =>  (AMOOR_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65060,
        GIR_Done,
      // Label 1596: @34748
      GIM_Try, /*On fail goto*//*Label 1597*/ 34782, // Rule ID 65062 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_acq_rel>>  =>  (AMOOR_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65062,
        GIR_Done,
      // Label 1597: @34782
      GIM_Try, /*On fail goto*//*Label 1598*/ 34816, // Rule ID 65064 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_seq_cst>>  =>  (AMOOR_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65064,
        GIR_Done,
      // Label 1598: @34816
      GIM_Reject,
    // Label 1588: @34817
    GIM_Reject,
    // Label 1576: @34818
    GIM_Reject,
    // Label 21: @34819
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1601*/ 35523,
    /*GILLT_s32*//*Label 1599*/ 34827,
    /*GILLT_s64*//*Label 1600*/ 35175,
    // Label 1599: @34827
    GIM_Try, /*On fail goto*//*Label 1602*/ 35174,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 1603*/ 34867, // Rule ID 64465 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_monotonic>>  =>  (AMOXOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64465,
        GIR_Done,
      // Label 1603: @34867
      GIM_Try, /*On fail goto*//*Label 1604*/ 34901, // Rule ID 64487 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_acquire>>  =>  (AMOXOR_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64487,
        GIR_Done,
      // Label 1604: @34901
      GIM_Try, /*On fail goto*//*Label 1605*/ 34935, // Rule ID 64509 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_release>>  =>  (AMOXOR_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64509,
        GIR_Done,
      // Label 1605: @34935
      GIM_Try, /*On fail goto*//*Label 1606*/ 34969, // Rule ID 64531 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_acq_rel>>  =>  (AMOXOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64531,
        GIR_Done,
      // Label 1606: @34969
      GIM_Try, /*On fail goto*//*Label 1607*/ 35003, // Rule ID 64553 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_seq_cst>>  =>  (AMOXOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64553,
        GIR_Done,
      // Label 1607: @35003
      GIM_Try, /*On fail goto*//*Label 1608*/ 35037, // Rule ID 65067 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_monotonic>>  =>  (AMOXOR_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65067,
        GIR_Done,
      // Label 1608: @35037
      GIM_Try, /*On fail goto*//*Label 1609*/ 35071, // Rule ID 65069 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_acquire>>  =>  (AMOXOR_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65069,
        GIR_Done,
      // Label 1609: @35071
      GIM_Try, /*On fail goto*//*Label 1610*/ 35105, // Rule ID 65071 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_release>>  =>  (AMOXOR_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65071,
        GIR_Done,
      // Label 1610: @35105
      GIM_Try, /*On fail goto*//*Label 1611*/ 35139, // Rule ID 65073 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_acq_rel>>  =>  (AMOXOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65073,
        GIR_Done,
      // Label 1611: @35139
      GIM_Try, /*On fail goto*//*Label 1612*/ 35173, // Rule ID 65075 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_seq_cst>>  =>  (AMOXOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65075,
        GIR_Done,
      // Label 1612: @35173
      GIM_Reject,
    // Label 1602: @35174
    GIM_Reject,
    // Label 1600: @35175
    GIM_Try, /*On fail goto*//*Label 1613*/ 35522,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 1614*/ 35215, // Rule ID 64464 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_monotonic>>  =>  (AMOXOR_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64464,
        GIR_Done,
      // Label 1614: @35215
      GIM_Try, /*On fail goto*//*Label 1615*/ 35249, // Rule ID 64486 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_acquire>>  =>  (AMOXOR_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64486,
        GIR_Done,
      // Label 1615: @35249
      GIM_Try, /*On fail goto*//*Label 1616*/ 35283, // Rule ID 64508 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_release>>  =>  (AMOXOR_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64508,
        GIR_Done,
      // Label 1616: @35283
      GIM_Try, /*On fail goto*//*Label 1617*/ 35317, // Rule ID 64530 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_acq_rel>>  =>  (AMOXOR_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64530,
        GIR_Done,
      // Label 1617: @35317
      GIM_Try, /*On fail goto*//*Label 1618*/ 35351, // Rule ID 64552 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_seq_cst>>  =>  (AMOXOR_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64552,
        GIR_Done,
      // Label 1618: @35351
      GIM_Try, /*On fail goto*//*Label 1619*/ 35385, // Rule ID 65066 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_monotonic>>  =>  (AMOXOR_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65066,
        GIR_Done,
      // Label 1619: @35385
      GIM_Try, /*On fail goto*//*Label 1620*/ 35419, // Rule ID 65068 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_acquire>>  =>  (AMOXOR_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65068,
        GIR_Done,
      // Label 1620: @35419
      GIM_Try, /*On fail goto*//*Label 1621*/ 35453, // Rule ID 65070 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_release>>  =>  (AMOXOR_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65070,
        GIR_Done,
      // Label 1621: @35453
      GIM_Try, /*On fail goto*//*Label 1622*/ 35487, // Rule ID 65072 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_acq_rel>>  =>  (AMOXOR_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65072,
        GIR_Done,
      // Label 1622: @35487
      GIM_Try, /*On fail goto*//*Label 1623*/ 35521, // Rule ID 65074 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_seq_cst>>  =>  (AMOXOR_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65074,
        GIR_Done,
      // Label 1623: @35521
      GIM_Reject,
    // Label 1613: @35522
    GIM_Reject,
    // Label 1601: @35523
    GIM_Reject,
    // Label 22: @35524
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1626*/ 36228,
    /*GILLT_s32*//*Label 1624*/ 35532,
    /*GILLT_s64*//*Label 1625*/ 35880,
    // Label 1624: @35532
    GIM_Try, /*On fail goto*//*Label 1627*/ 35879,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 1628*/ 35572, // Rule ID 64589 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_monotonic>>  =>  (AMOMAX_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64589,
        GIR_Done,
      // Label 1628: @35572
      GIM_Try, /*On fail goto*//*Label 1629*/ 35606, // Rule ID 64591 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_acquire>>  =>  (AMOMAX_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64591,
        GIR_Done,
      // Label 1629: @35606
      GIM_Try, /*On fail goto*//*Label 1630*/ 35640, // Rule ID 64593 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_release>>  =>  (AMOMAX_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64593,
        GIR_Done,
      // Label 1630: @35640
      GIM_Try, /*On fail goto*//*Label 1631*/ 35674, // Rule ID 64595 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_acq_rel>>  =>  (AMOMAX_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64595,
        GIR_Done,
      // Label 1631: @35674
      GIM_Try, /*On fail goto*//*Label 1632*/ 35708, // Rule ID 64597 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_seq_cst>>  =>  (AMOMAX_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64597,
        GIR_Done,
      // Label 1632: @35708
      GIM_Try, /*On fail goto*//*Label 1633*/ 35742, // Rule ID 65077 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_monotonic>>  =>  (AMOMAX_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65077,
        GIR_Done,
      // Label 1633: @35742
      GIM_Try, /*On fail goto*//*Label 1634*/ 35776, // Rule ID 65079 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_acquire>>  =>  (AMOMAX_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65079,
        GIR_Done,
      // Label 1634: @35776
      GIM_Try, /*On fail goto*//*Label 1635*/ 35810, // Rule ID 65081 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_release>>  =>  (AMOMAX_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65081,
        GIR_Done,
      // Label 1635: @35810
      GIM_Try, /*On fail goto*//*Label 1636*/ 35844, // Rule ID 65083 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_acq_rel>>  =>  (AMOMAX_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65083,
        GIR_Done,
      // Label 1636: @35844
      GIM_Try, /*On fail goto*//*Label 1637*/ 35878, // Rule ID 65085 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_seq_cst>>  =>  (AMOMAX_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65085,
        GIR_Done,
      // Label 1637: @35878
      GIM_Reject,
    // Label 1627: @35879
    GIM_Reject,
    // Label 1625: @35880
    GIM_Try, /*On fail goto*//*Label 1638*/ 36227,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 1639*/ 35920, // Rule ID 64588 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_monotonic>>  =>  (AMOMAX_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64588,
        GIR_Done,
      // Label 1639: @35920
      GIM_Try, /*On fail goto*//*Label 1640*/ 35954, // Rule ID 64590 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_acquire>>  =>  (AMOMAX_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64590,
        GIR_Done,
      // Label 1640: @35954
      GIM_Try, /*On fail goto*//*Label 1641*/ 35988, // Rule ID 64592 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_release>>  =>  (AMOMAX_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64592,
        GIR_Done,
      // Label 1641: @35988
      GIM_Try, /*On fail goto*//*Label 1642*/ 36022, // Rule ID 64594 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_acq_rel>>  =>  (AMOMAX_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64594,
        GIR_Done,
      // Label 1642: @36022
      GIM_Try, /*On fail goto*//*Label 1643*/ 36056, // Rule ID 64596 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_seq_cst>>  =>  (AMOMAX_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64596,
        GIR_Done,
      // Label 1643: @36056
      GIM_Try, /*On fail goto*//*Label 1644*/ 36090, // Rule ID 65076 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_monotonic>>  =>  (AMOMAX_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65076,
        GIR_Done,
      // Label 1644: @36090
      GIM_Try, /*On fail goto*//*Label 1645*/ 36124, // Rule ID 65078 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_acquire>>  =>  (AMOMAX_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65078,
        GIR_Done,
      // Label 1645: @36124
      GIM_Try, /*On fail goto*//*Label 1646*/ 36158, // Rule ID 65080 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_release>>  =>  (AMOMAX_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65080,
        GIR_Done,
      // Label 1646: @36158
      GIM_Try, /*On fail goto*//*Label 1647*/ 36192, // Rule ID 65082 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_acq_rel>>  =>  (AMOMAX_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65082,
        GIR_Done,
      // Label 1647: @36192
      GIM_Try, /*On fail goto*//*Label 1648*/ 36226, // Rule ID 65084 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_seq_cst>>  =>  (AMOMAX_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65084,
        GIR_Done,
      // Label 1648: @36226
      GIM_Reject,
    // Label 1638: @36227
    GIM_Reject,
    // Label 1626: @36228
    GIM_Reject,
    // Label 23: @36229
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1651*/ 36933,
    /*GILLT_s32*//*Label 1649*/ 36237,
    /*GILLT_s64*//*Label 1650*/ 36585,
    // Label 1649: @36237
    GIM_Try, /*On fail goto*//*Label 1652*/ 36584,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 1653*/ 36277, // Rule ID 64599 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_monotonic>>  =>  (AMOMIN_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64599,
        GIR_Done,
      // Label 1653: @36277
      GIM_Try, /*On fail goto*//*Label 1654*/ 36311, // Rule ID 64607 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_acquire>>  =>  (AMOMIN_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64607,
        GIR_Done,
      // Label 1654: @36311
      GIM_Try, /*On fail goto*//*Label 1655*/ 36345, // Rule ID 64635 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_release>>  =>  (AMOMIN_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64635,
        GIR_Done,
      // Label 1655: @36345
      GIM_Try, /*On fail goto*//*Label 1656*/ 36379, // Rule ID 64667 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_acq_rel>>  =>  (AMOMIN_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64667,
        GIR_Done,
      // Label 1656: @36379
      GIM_Try, /*On fail goto*//*Label 1657*/ 36413, // Rule ID 64697 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_seq_cst>>  =>  (AMOMIN_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64697,
        GIR_Done,
      // Label 1657: @36413
      GIM_Try, /*On fail goto*//*Label 1658*/ 36447, // Rule ID 65087 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_monotonic>>  =>  (AMOMIN_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65087,
        GIR_Done,
      // Label 1658: @36447
      GIM_Try, /*On fail goto*//*Label 1659*/ 36481, // Rule ID 65089 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_acquire>>  =>  (AMOMIN_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65089,
        GIR_Done,
      // Label 1659: @36481
      GIM_Try, /*On fail goto*//*Label 1660*/ 36515, // Rule ID 65091 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_release>>  =>  (AMOMIN_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65091,
        GIR_Done,
      // Label 1660: @36515
      GIM_Try, /*On fail goto*//*Label 1661*/ 36549, // Rule ID 65093 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_acq_rel>>  =>  (AMOMIN_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65093,
        GIR_Done,
      // Label 1661: @36549
      GIM_Try, /*On fail goto*//*Label 1662*/ 36583, // Rule ID 65095 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_seq_cst>>  =>  (AMOMIN_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65095,
        GIR_Done,
      // Label 1662: @36583
      GIM_Reject,
    // Label 1652: @36584
    GIM_Reject,
    // Label 1650: @36585
    GIM_Try, /*On fail goto*//*Label 1663*/ 36932,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 1664*/ 36625, // Rule ID 64598 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_monotonic>>  =>  (AMOMIN_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64598,
        GIR_Done,
      // Label 1664: @36625
      GIM_Try, /*On fail goto*//*Label 1665*/ 36659, // Rule ID 64606 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_acquire>>  =>  (AMOMIN_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64606,
        GIR_Done,
      // Label 1665: @36659
      GIM_Try, /*On fail goto*//*Label 1666*/ 36693, // Rule ID 64634 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_release>>  =>  (AMOMIN_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64634,
        GIR_Done,
      // Label 1666: @36693
      GIM_Try, /*On fail goto*//*Label 1667*/ 36727, // Rule ID 64666 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_acq_rel>>  =>  (AMOMIN_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64666,
        GIR_Done,
      // Label 1667: @36727
      GIM_Try, /*On fail goto*//*Label 1668*/ 36761, // Rule ID 64696 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_seq_cst>>  =>  (AMOMIN_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64696,
        GIR_Done,
      // Label 1668: @36761
      GIM_Try, /*On fail goto*//*Label 1669*/ 36795, // Rule ID 65086 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_monotonic>>  =>  (AMOMIN_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65086,
        GIR_Done,
      // Label 1669: @36795
      GIM_Try, /*On fail goto*//*Label 1670*/ 36829, // Rule ID 65088 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_acquire>>  =>  (AMOMIN_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65088,
        GIR_Done,
      // Label 1670: @36829
      GIM_Try, /*On fail goto*//*Label 1671*/ 36863, // Rule ID 65090 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_release>>  =>  (AMOMIN_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65090,
        GIR_Done,
      // Label 1671: @36863
      GIM_Try, /*On fail goto*//*Label 1672*/ 36897, // Rule ID 65092 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_acq_rel>>  =>  (AMOMIN_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65092,
        GIR_Done,
      // Label 1672: @36897
      GIM_Try, /*On fail goto*//*Label 1673*/ 36931, // Rule ID 65094 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_seq_cst>>  =>  (AMOMIN_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65094,
        GIR_Done,
      // Label 1673: @36931
      GIM_Reject,
    // Label 1663: @36932
    GIM_Reject,
    // Label 1651: @36933
    GIM_Reject,
    // Label 24: @36934
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1676*/ 37638,
    /*GILLT_s32*//*Label 1674*/ 36942,
    /*GILLT_s64*//*Label 1675*/ 37290,
    // Label 1674: @36942
    GIM_Try, /*On fail goto*//*Label 1677*/ 37289,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 1678*/ 36982, // Rule ID 64734 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_monotonic>>  =>  (AMOMAXU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64734,
        GIR_Done,
      // Label 1678: @36982
      GIM_Try, /*On fail goto*//*Label 1679*/ 37016, // Rule ID 64754 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_acquire>>  =>  (AMOMAXU_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64754,
        GIR_Done,
      // Label 1679: @37016
      GIM_Try, /*On fail goto*//*Label 1680*/ 37050, // Rule ID 64777 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_release>>  =>  (AMOMAXU_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64777,
        GIR_Done,
      // Label 1680: @37050
      GIM_Try, /*On fail goto*//*Label 1681*/ 37084, // Rule ID 64799 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_acq_rel>>  =>  (AMOMAXU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64799,
        GIR_Done,
      // Label 1681: @37084
      GIM_Try, /*On fail goto*//*Label 1682*/ 37118, // Rule ID 64813 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_seq_cst>>  =>  (AMOMAXU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64813,
        GIR_Done,
      // Label 1682: @37118
      GIM_Try, /*On fail goto*//*Label 1683*/ 37152, // Rule ID 65097 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_monotonic>>  =>  (AMOMAXU_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65097,
        GIR_Done,
      // Label 1683: @37152
      GIM_Try, /*On fail goto*//*Label 1684*/ 37186, // Rule ID 65099 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_acquire>>  =>  (AMOMAXU_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65099,
        GIR_Done,
      // Label 1684: @37186
      GIM_Try, /*On fail goto*//*Label 1685*/ 37220, // Rule ID 65101 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_release>>  =>  (AMOMAXU_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65101,
        GIR_Done,
      // Label 1685: @37220
      GIM_Try, /*On fail goto*//*Label 1686*/ 37254, // Rule ID 65103 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_acq_rel>>  =>  (AMOMAXU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65103,
        GIR_Done,
      // Label 1686: @37254
      GIM_Try, /*On fail goto*//*Label 1687*/ 37288, // Rule ID 65105 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_seq_cst>>  =>  (AMOMAXU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65105,
        GIR_Done,
      // Label 1687: @37288
      GIM_Reject,
    // Label 1677: @37289
    GIM_Reject,
    // Label 1675: @37290
    GIM_Try, /*On fail goto*//*Label 1688*/ 37637,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 1689*/ 37330, // Rule ID 64733 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_monotonic>>  =>  (AMOMAXU_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64733,
        GIR_Done,
      // Label 1689: @37330
      GIM_Try, /*On fail goto*//*Label 1690*/ 37364, // Rule ID 64753 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_acquire>>  =>  (AMOMAXU_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64753,
        GIR_Done,
      // Label 1690: @37364
      GIM_Try, /*On fail goto*//*Label 1691*/ 37398, // Rule ID 64776 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_release>>  =>  (AMOMAXU_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64776,
        GIR_Done,
      // Label 1691: @37398
      GIM_Try, /*On fail goto*//*Label 1692*/ 37432, // Rule ID 64798 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_acq_rel>>  =>  (AMOMAXU_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64798,
        GIR_Done,
      // Label 1692: @37432
      GIM_Try, /*On fail goto*//*Label 1693*/ 37466, // Rule ID 64812 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_seq_cst>>  =>  (AMOMAXU_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64812,
        GIR_Done,
      // Label 1693: @37466
      GIM_Try, /*On fail goto*//*Label 1694*/ 37500, // Rule ID 65096 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_monotonic>>  =>  (AMOMAXU_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65096,
        GIR_Done,
      // Label 1694: @37500
      GIM_Try, /*On fail goto*//*Label 1695*/ 37534, // Rule ID 65098 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_acquire>>  =>  (AMOMAXU_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65098,
        GIR_Done,
      // Label 1695: @37534
      GIM_Try, /*On fail goto*//*Label 1696*/ 37568, // Rule ID 65100 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_release>>  =>  (AMOMAXU_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65100,
        GIR_Done,
      // Label 1696: @37568
      GIM_Try, /*On fail goto*//*Label 1697*/ 37602, // Rule ID 65102 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_acq_rel>>  =>  (AMOMAXU_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65102,
        GIR_Done,
      // Label 1697: @37602
      GIM_Try, /*On fail goto*//*Label 1698*/ 37636, // Rule ID 65104 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_seq_cst>>  =>  (AMOMAXU_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65104,
        GIR_Done,
      // Label 1698: @37636
      GIM_Reject,
    // Label 1688: @37637
    GIM_Reject,
    // Label 1676: @37638
    GIM_Reject,
    // Label 25: @37639
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1701*/ 38343,
    /*GILLT_s32*//*Label 1699*/ 37647,
    /*GILLT_s64*//*Label 1700*/ 37995,
    // Label 1699: @37647
    GIM_Try, /*On fail goto*//*Label 1702*/ 37994,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 1703*/ 37687, // Rule ID 64835 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_monotonic>>  =>  (AMOMINU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64835,
        GIR_Done,
      // Label 1703: @37687
      GIM_Try, /*On fail goto*//*Label 1704*/ 37721, // Rule ID 64840 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_acquire>>  =>  (AMOMINU_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64840,
        GIR_Done,
      // Label 1704: @37721
      GIM_Try, /*On fail goto*//*Label 1705*/ 37755, // Rule ID 64842 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_release>>  =>  (AMOMINU_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64842,
        GIR_Done,
      // Label 1705: @37755
      GIM_Try, /*On fail goto*//*Label 1706*/ 37789, // Rule ID 64844 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_acq_rel>>  =>  (AMOMINU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64844,
        GIR_Done,
      // Label 1706: @37789
      GIM_Try, /*On fail goto*//*Label 1707*/ 37823, // Rule ID 64846 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_seq_cst>>  =>  (AMOMINU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64846,
        GIR_Done,
      // Label 1707: @37823
      GIM_Try, /*On fail goto*//*Label 1708*/ 37857, // Rule ID 65107 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_monotonic>>  =>  (AMOMINU_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65107,
        GIR_Done,
      // Label 1708: @37857
      GIM_Try, /*On fail goto*//*Label 1709*/ 37891, // Rule ID 65109 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_acquire>>  =>  (AMOMINU_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65109,
        GIR_Done,
      // Label 1709: @37891
      GIM_Try, /*On fail goto*//*Label 1710*/ 37925, // Rule ID 65111 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_release>>  =>  (AMOMINU_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65111,
        GIR_Done,
      // Label 1710: @37925
      GIM_Try, /*On fail goto*//*Label 1711*/ 37959, // Rule ID 65113 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_acq_rel>>  =>  (AMOMINU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65113,
        GIR_Done,
      // Label 1711: @37959
      GIM_Try, /*On fail goto*//*Label 1712*/ 37993, // Rule ID 65115 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_seq_cst>>  =>  (AMOMINU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65115,
        GIR_Done,
      // Label 1712: @37993
      GIM_Reject,
    // Label 1702: @37994
    GIM_Reject,
    // Label 1700: @37995
    GIM_Try, /*On fail goto*//*Label 1713*/ 38342,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 1714*/ 38035, // Rule ID 64834 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_monotonic>>  =>  (AMOMINU_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64834,
        GIR_Done,
      // Label 1714: @38035
      GIM_Try, /*On fail goto*//*Label 1715*/ 38069, // Rule ID 64839 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_acquire>>  =>  (AMOMINU_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64839,
        GIR_Done,
      // Label 1715: @38069
      GIM_Try, /*On fail goto*//*Label 1716*/ 38103, // Rule ID 64841 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_release>>  =>  (AMOMINU_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64841,
        GIR_Done,
      // Label 1716: @38103
      GIM_Try, /*On fail goto*//*Label 1717*/ 38137, // Rule ID 64843 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_acq_rel>>  =>  (AMOMINU_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64843,
        GIR_Done,
      // Label 1717: @38137
      GIM_Try, /*On fail goto*//*Label 1718*/ 38171, // Rule ID 64845 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_seq_cst>>  =>  (AMOMINU_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64845,
        GIR_Done,
      // Label 1718: @38171
      GIM_Try, /*On fail goto*//*Label 1719*/ 38205, // Rule ID 65106 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_monotonic>>  =>  (AMOMINU_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65106,
        GIR_Done,
      // Label 1719: @38205
      GIM_Try, /*On fail goto*//*Label 1720*/ 38239, // Rule ID 65108 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_acquire>>  =>  (AMOMINU_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_AQ,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65108,
        GIR_Done,
      // Label 1720: @38239
      GIM_Try, /*On fail goto*//*Label 1721*/ 38273, // Rule ID 65110 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_release>>  =>  (AMOMINU_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65110,
        GIR_Done,
      // Label 1721: @38273
      GIM_Try, /*On fail goto*//*Label 1722*/ 38307, // Rule ID 65112 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_acq_rel>>  =>  (AMOMINU_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65112,
        GIR_Done,
      // Label 1722: @38307
      GIM_Try, /*On fail goto*//*Label 1723*/ 38341, // Rule ID 65114 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rs1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_seq_cst>>  =>  (AMOMINU_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_AQ_RL,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65114,
        GIR_Done,
      // Label 1723: @38341
      GIM_Reject,
    // Label 1713: @38342
    GIM_Reject,
    // Label 1701: @38343
    GIM_Reject,
    // Label 26: @38344
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1726*/ 38526,
    /*GILLT_s32*//*Label 1724*/ 38352,
    /*GILLT_s64*//*Label 1725*/ 38439,
    // Label 1724: @38352
    GIM_Try, /*On fail goto*//*Label 1727*/ 38375, // Rule ID 62103 //
      GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 4,
      // MIs[0] Operand 1
      GIM_CheckIsImm, /*MI*/0, /*Op*/1,
      // (atomic_fence 4:{ *:[i32] }, (timm:{ *:[i32] }))  =>  (FENCE 2:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE,
      GIR_AddImm, /*InsnID*/0, /*Imm*/2,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 62103,
      GIR_Done,
    // Label 1727: @38375
    GIM_Try, /*On fail goto*//*Label 1728*/ 38398, // Rule ID 62131 //
      GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 5,
      // MIs[0] Operand 1
      GIM_CheckIsImm, /*MI*/0, /*Op*/1,
      // (atomic_fence 5:{ *:[i32] }, (timm:{ *:[i32] }))  =>  (FENCE 3:{ *:[i32] }, 1:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_AddImm, /*InsnID*/0, /*Imm*/1,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 62131,
      GIR_Done,
    // Label 1728: @38398
    GIM_Try, /*On fail goto*//*Label 1729*/ 38415, // Rule ID 62155 //
      GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 6,
      // MIs[0] Operand 1
      GIM_CheckIsImm, /*MI*/0, /*Op*/1,
      // (atomic_fence 6:{ *:[i32] }, (timm:{ *:[i32] }))  =>  (FENCE_TSO)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE_TSO,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 62155,
      GIR_Done,
    // Label 1729: @38415
    GIM_Try, /*On fail goto*//*Label 1730*/ 38438, // Rule ID 62177 //
      GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 7,
      // MIs[0] Operand 1
      GIM_CheckIsImm, /*MI*/0, /*Op*/1,
      // (atomic_fence 7:{ *:[i32] }, (timm:{ *:[i32] }))  =>  (FENCE 3:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 62177,
      GIR_Done,
    // Label 1730: @38438
    GIM_Reject,
    // Label 1725: @38439
    GIM_Try, /*On fail goto*//*Label 1731*/ 38462, // Rule ID 62102 //
      GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 4,
      // MIs[0] Operand 1
      GIM_CheckIsImm, /*MI*/0, /*Op*/1,
      // (atomic_fence 4:{ *:[i64] }, (timm:{ *:[i64] }))  =>  (FENCE 2:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE,
      GIR_AddImm, /*InsnID*/0, /*Imm*/2,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 62102,
      GIR_Done,
    // Label 1731: @38462
    GIM_Try, /*On fail goto*//*Label 1732*/ 38485, // Rule ID 62130 //
      GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 5,
      // MIs[0] Operand 1
      GIM_CheckIsImm, /*MI*/0, /*Op*/1,
      // (atomic_fence 5:{ *:[i64] }, (timm:{ *:[i64] }))  =>  (FENCE 3:{ *:[i64] }, 1:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_AddImm, /*InsnID*/0, /*Imm*/1,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 62130,
      GIR_Done,
    // Label 1732: @38485
    GIM_Try, /*On fail goto*//*Label 1733*/ 38502, // Rule ID 62154 //
      GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 6,
      // MIs[0] Operand 1
      GIM_CheckIsImm, /*MI*/0, /*Op*/1,
      // (atomic_fence 6:{ *:[i64] }, (timm:{ *:[i64] }))  =>  (FENCE_TSO)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE_TSO,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 62154,
      GIR_Done,
    // Label 1733: @38502
    GIM_Try, /*On fail goto*//*Label 1734*/ 38525, // Rule ID 62176 //
      GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 7,
      // MIs[0] Operand 1
      GIM_CheckIsImm, /*MI*/0, /*Op*/1,
      // (atomic_fence 7:{ *:[i64] }, (timm:{ *:[i64] }))  =>  (FENCE 3:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 62176,
      GIR_Done,
    // Label 1734: @38525
    GIM_Reject,
    // Label 1726: @38526
    GIM_Reject,
    // Label 27: @38527
    GIM_Try, /*On fail goto*//*Label 1735*/ 39213,
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
      GIM_Try, /*On fail goto*//*Label 1736*/ 38572, // Rule ID 65631 //
        GIM_CheckFeatures, GIFBS_HasStdExtZknd_IsRV64,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_aes64im,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i64] } 7772:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1)  =>  (AES64IM:{ *:[i64] } GPR:{ *:[i64] }:$rs1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AES64IM,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65631,
        GIR_Done,
      // Label 1736: @38572
      GIM_Try, /*On fail goto*//*Label 1737*/ 38612, // Rule ID 65638 //
        GIM_CheckFeatures, GIFBS_HasStdExtZknh,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_sha256sig0,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i64] } 7807:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1)  =>  (SHA256SIG0:{ *:[i64] } GPR:{ *:[i64] }:$rs1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SHA256SIG0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65638,
        GIR_Done,
      // Label 1737: @38612
      GIM_Try, /*On fail goto*//*Label 1738*/ 38652, // Rule ID 65639 //
        GIM_CheckFeatures, GIFBS_HasStdExtZknh,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_sha256sig0,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i32] } 7807:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1)  =>  (SHA256SIG0:{ *:[i32] } GPR:{ *:[i32] }:$rs1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SHA256SIG0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65639,
        GIR_Done,
      // Label 1738: @38652
      GIM_Try, /*On fail goto*//*Label 1739*/ 38692, // Rule ID 65640 //
        GIM_CheckFeatures, GIFBS_HasStdExtZknh,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_sha256sig1,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i64] } 7808:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1)  =>  (SHA256SIG1:{ *:[i64] } GPR:{ *:[i64] }:$rs1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SHA256SIG1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65640,
        GIR_Done,
      // Label 1739: @38692
      GIM_Try, /*On fail goto*//*Label 1740*/ 38732, // Rule ID 65641 //
        GIM_CheckFeatures, GIFBS_HasStdExtZknh,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_sha256sig1,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i32] } 7808:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1)  =>  (SHA256SIG1:{ *:[i32] } GPR:{ *:[i32] }:$rs1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SHA256SIG1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65641,
        GIR_Done,
      // Label 1740: @38732
      GIM_Try, /*On fail goto*//*Label 1741*/ 38772, // Rule ID 65642 //
        GIM_CheckFeatures, GIFBS_HasStdExtZknh,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_sha256sum0,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i64] } 7809:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1)  =>  (SHA256SUM0:{ *:[i64] } GPR:{ *:[i64] }:$rs1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SHA256SUM0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65642,
        GIR_Done,
      // Label 1741: @38772
      GIM_Try, /*On fail goto*//*Label 1742*/ 38812, // Rule ID 65643 //
        GIM_CheckFeatures, GIFBS_HasStdExtZknh,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_sha256sum0,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i32] } 7809:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1)  =>  (SHA256SUM0:{ *:[i32] } GPR:{ *:[i32] }:$rs1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SHA256SUM0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65643,
        GIR_Done,
      // Label 1742: @38812
      GIM_Try, /*On fail goto*//*Label 1743*/ 38852, // Rule ID 65644 //
        GIM_CheckFeatures, GIFBS_HasStdExtZknh,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_sha256sum1,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i64] } 7810:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1)  =>  (SHA256SUM1:{ *:[i64] } GPR:{ *:[i64] }:$rs1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SHA256SUM1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65644,
        GIR_Done,
      // Label 1743: @38852
      GIM_Try, /*On fail goto*//*Label 1744*/ 38892, // Rule ID 65645 //
        GIM_CheckFeatures, GIFBS_HasStdExtZknh,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_sha256sum1,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i32] } 7810:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1)  =>  (SHA256SUM1:{ *:[i32] } GPR:{ *:[i32] }:$rs1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SHA256SUM1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65645,
        GIR_Done,
      // Label 1744: @38892
      GIM_Try, /*On fail goto*//*Label 1745*/ 38932, // Rule ID 65652 //
        GIM_CheckFeatures, GIFBS_HasStdExtZknh_IsRV64,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_sha512sig0,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i64] } 7811:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1)  =>  (SHA512SIG0:{ *:[i64] } GPR:{ *:[i64] }:$rs1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SHA512SIG0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65652,
        GIR_Done,
      // Label 1745: @38932
      GIM_Try, /*On fail goto*//*Label 1746*/ 38972, // Rule ID 65653 //
        GIM_CheckFeatures, GIFBS_HasStdExtZknh_IsRV64,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_sha512sig1,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i64] } 7814:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1)  =>  (SHA512SIG1:{ *:[i64] } GPR:{ *:[i64] }:$rs1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SHA512SIG1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65653,
        GIR_Done,
      // Label 1746: @38972
      GIM_Try, /*On fail goto*//*Label 1747*/ 39012, // Rule ID 65654 //
        GIM_CheckFeatures, GIFBS_HasStdExtZknh_IsRV64,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_sha512sum0,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i64] } 7817:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1)  =>  (SHA512SUM0:{ *:[i64] } GPR:{ *:[i64] }:$rs1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SHA512SUM0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65654,
        GIR_Done,
      // Label 1747: @39012
      GIM_Try, /*On fail goto*//*Label 1748*/ 39052, // Rule ID 65655 //
        GIM_CheckFeatures, GIFBS_HasStdExtZknh_IsRV64,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_sha512sum1,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i64] } 7819:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1)  =>  (SHA512SUM1:{ *:[i64] } GPR:{ *:[i64] }:$rs1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SHA512SUM1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65655,
        GIR_Done,
      // Label 1748: @39052
      GIM_Try, /*On fail goto*//*Label 1749*/ 39092, // Rule ID 65660 //
        GIM_CheckFeatures, GIFBS_HasStdExtZksh,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_sm3p0,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i64] } 7821:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1)  =>  (SM3P0:{ *:[i64] } GPR:{ *:[i64] }:$rs1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SM3P0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65660,
        GIR_Done,
      // Label 1749: @39092
      GIM_Try, /*On fail goto*//*Label 1750*/ 39132, // Rule ID 65661 //
        GIM_CheckFeatures, GIFBS_HasStdExtZksh,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_sm3p0,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i32] } 7821:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1)  =>  (SM3P0:{ *:[i32] } GPR:{ *:[i32] }:$rs1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SM3P0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65661,
        GIR_Done,
      // Label 1750: @39132
      GIM_Try, /*On fail goto*//*Label 1751*/ 39172, // Rule ID 65662 //
        GIM_CheckFeatures, GIFBS_HasStdExtZksh,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_sm3p1,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i64] } 7822:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1)  =>  (SM3P1:{ *:[i64] } GPR:{ *:[i64] }:$rs1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SM3P1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65662,
        GIR_Done,
      // Label 1751: @39172
      GIM_Try, /*On fail goto*//*Label 1752*/ 39212, // Rule ID 65663 //
        GIM_CheckFeatures, GIFBS_HasStdExtZksh,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_sm3p1,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i32] } 7822:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1)  =>  (SM3P1:{ *:[i32] } GPR:{ *:[i32] }:$rs1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SM3P1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65663,
        GIR_Done,
      // Label 1752: @39212
      GIM_Reject,
    // Label 1735: @39213
    GIM_Try, /*On fail goto*//*Label 1753*/ 40355,
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
      GIM_Try, /*On fail goto*//*Label 1754*/ 39270, // Rule ID 65617 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbcOrZbkc,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_clmul,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i64] } 7776:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (CLMUL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::CLMUL,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65617,
        GIR_Done,
      // Label 1754: @39270
      GIM_Try, /*On fail goto*//*Label 1755*/ 39322, // Rule ID 65618 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbcOrZbkc,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_clmul,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i32] } 7776:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (CLMUL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::CLMUL,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65618,
        GIR_Done,
      // Label 1755: @39322
      GIM_Try, /*On fail goto*//*Label 1756*/ 39374, // Rule ID 65619 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbcOrZbkc,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_clmulh,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i64] } 7777:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (CLMULH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::CLMULH,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65619,
        GIR_Done,
      // Label 1756: @39374
      GIM_Try, /*On fail goto*//*Label 1757*/ 39426, // Rule ID 65620 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbcOrZbkc,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_clmulh,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i32] } 7777:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (CLMULH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::CLMULH,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65620,
        GIR_Done,
      // Label 1757: @39426
      GIM_Try, /*On fail goto*//*Label 1758*/ 39478, // Rule ID 65621 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbc,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_clmulr,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i64] } 7778:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (CLMULR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::CLMULR,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65621,
        GIR_Done,
      // Label 1758: @39478
      GIM_Try, /*On fail goto*//*Label 1759*/ 39530, // Rule ID 65622 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbc,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_clmulr,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i32] } 7778:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (CLMULR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::CLMULR,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65622,
        GIR_Done,
      // Label 1759: @39530
      GIM_Try, /*On fail goto*//*Label 1760*/ 39582, // Rule ID 65623 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbkx,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_xperm4,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i64] } 8326:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (XPERM4:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XPERM4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65623,
        GIR_Done,
      // Label 1760: @39582
      GIM_Try, /*On fail goto*//*Label 1761*/ 39634, // Rule ID 65624 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbkx,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_xperm4,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i32] } 8326:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (XPERM4:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XPERM4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65624,
        GIR_Done,
      // Label 1761: @39634
      GIM_Try, /*On fail goto*//*Label 1762*/ 39686, // Rule ID 65625 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbkx,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_xperm8,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i64] } 8327:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (XPERM8:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XPERM8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65625,
        GIR_Done,
      // Label 1762: @39686
      GIM_Try, /*On fail goto*//*Label 1763*/ 39738, // Rule ID 65626 //
        GIM_CheckFeatures, GIFBS_HasStdExtZbkx,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_xperm8,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i32] } 8327:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (XPERM8:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XPERM8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65626,
        GIR_Done,
      // Label 1763: @39738
      GIM_Try, /*On fail goto*//*Label 1764*/ 39790, // Rule ID 65629 //
        GIM_CheckFeatures, GIFBS_HasStdExtZknd_IsRV64,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_aes64ds,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i64] } 7768:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (AES64DS:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AES64DS,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65629,
        GIR_Done,
      // Label 1764: @39790
      GIM_Try, /*On fail goto*//*Label 1765*/ 39842, // Rule ID 65630 //
        GIM_CheckFeatures, GIFBS_HasStdExtZknd_IsRV64,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_aes64dsm,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i64] } 7769:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (AES64DSM:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AES64DSM,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65630,
        GIR_Done,
      // Label 1765: @39842
      GIM_Try, /*On fail goto*//*Label 1766*/ 39894, // Rule ID 65632 //
        GIM_CheckFeatures, GIFBS_HasStdExtZkndOrZkne_IsRV64,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_aes64ks2,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i64] } 7774:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (AES64KS2:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AES64KS2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65632,
        GIR_Done,
      // Label 1766: @39894
      GIM_Try, /*On fail goto*//*Label 1767*/ 39946, // Rule ID 65636 //
        GIM_CheckFeatures, GIFBS_HasStdExtZkne_IsRV64,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_aes64es,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i64] } 7770:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (AES64ES:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AES64ES,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65636,
        GIR_Done,
      // Label 1767: @39946
      GIM_Try, /*On fail goto*//*Label 1768*/ 39998, // Rule ID 65637 //
        GIM_CheckFeatures, GIFBS_HasStdExtZkne_IsRV64,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_aes64esm,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i64] } 7771:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (AES64ESM:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AES64ESM,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65637,
        GIR_Done,
      // Label 1768: @39998
      GIM_Try, /*On fail goto*//*Label 1769*/ 40050, // Rule ID 65646 //
        GIM_CheckFeatures, GIFBS_HasStdExtZknh_IsRV32,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_sha512sig0l,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i32] } 7813:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (SHA512SIG0L:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SHA512SIG0L,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65646,
        GIR_Done,
      // Label 1769: @40050
      GIM_Try, /*On fail goto*//*Label 1770*/ 40102, // Rule ID 65647 //
        GIM_CheckFeatures, GIFBS_HasStdExtZknh_IsRV32,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_sha512sig0h,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i32] } 7812:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (SHA512SIG0H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SHA512SIG0H,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65647,
        GIR_Done,
      // Label 1770: @40102
      GIM_Try, /*On fail goto*//*Label 1771*/ 40154, // Rule ID 65648 //
        GIM_CheckFeatures, GIFBS_HasStdExtZknh_IsRV32,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_sha512sig1l,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i32] } 7816:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (SHA512SIG1L:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SHA512SIG1L,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65648,
        GIR_Done,
      // Label 1771: @40154
      GIM_Try, /*On fail goto*//*Label 1772*/ 40206, // Rule ID 65649 //
        GIM_CheckFeatures, GIFBS_HasStdExtZknh_IsRV32,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_sha512sig1h,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i32] } 7815:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (SHA512SIG1H:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SHA512SIG1H,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65649,
        GIR_Done,
      // Label 1772: @40206
      GIM_Try, /*On fail goto*//*Label 1773*/ 40258, // Rule ID 65650 //
        GIM_CheckFeatures, GIFBS_HasStdExtZknh_IsRV32,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_sha512sum0r,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i32] } 7818:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (SHA512SUM0R:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SHA512SUM0R,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65650,
        GIR_Done,
      // Label 1773: @40258
      GIM_Try, /*On fail goto*//*Label 1774*/ 40310, // Rule ID 65651 //
        GIM_CheckFeatures, GIFBS_HasStdExtZknh_IsRV32,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_sha512sum1r,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (intrinsic_wo_chain:{ *:[i32] } 7820:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (SHA512SUM1R:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SHA512SUM1R,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65651,
        GIR_Done,
      // Label 1774: @40310
      GIM_Try, /*On fail goto*//*Label 1775*/ 40354, // Rule ID 65633 //
        GIM_CheckFeatures, GIFBS_HasStdExtZkndOrZkne_IsRV64,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_aes64ks1i,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] rnum
        // No operand predicates
        // (intrinsic_wo_chain:{ *:[i64] } 7773:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1, i32:{ *:[i32] }:$rnum)  =>  (AES64KS1I:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (timm:{ *:[i32] })<<P:Predicate_rnum>>:$rnum)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AES64KS1I,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rnum
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65633,
        GIR_Done,
      // Label 1775: @40354
      GIM_Reject,
    // Label 1753: @40355
    GIM_Try, /*On fail goto*//*Label 1776*/ 40809,
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
      GIM_Try, /*On fail goto*//*Label 1777*/ 40416, // Rule ID 65627 //
        GIM_CheckFeatures, GIFBS_HasStdExtZknd_IsRV32,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_aes32dsi,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] imm
        // No operand predicates
        // (intrinsic_wo_chain:{ *:[i32] } 7764:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, i8:{ *:[i8] }:$imm)  =>  (AES32DSI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i8] })<<P:Predicate_byteselect>>:$imm)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AES32DSI,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // imm
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65627,
        GIR_Done,
      // Label 1777: @40416
      GIM_Try, /*On fail goto*//*Label 1778*/ 40472, // Rule ID 65628 //
        GIM_CheckFeatures, GIFBS_HasStdExtZknd_IsRV32,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_aes32dsmi,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] imm
        // No operand predicates
        // (intrinsic_wo_chain:{ *:[i32] } 7765:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, i8:{ *:[i8] }:$imm)  =>  (AES32DSMI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i8] })<<P:Predicate_byteselect>>:$imm)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AES32DSMI,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // imm
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65628,
        GIR_Done,
      // Label 1778: @40472
      GIM_Try, /*On fail goto*//*Label 1779*/ 40528, // Rule ID 65634 //
        GIM_CheckFeatures, GIFBS_HasStdExtZkne_IsRV32,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_aes32esi,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] imm
        // No operand predicates
        // (intrinsic_wo_chain:{ *:[i32] } 7766:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, i8:{ *:[i8] }:$imm)  =>  (AES32ESI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i8] })<<P:Predicate_byteselect>>:$imm)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AES32ESI,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // imm
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65634,
        GIR_Done,
      // Label 1779: @40528
      GIM_Try, /*On fail goto*//*Label 1780*/ 40584, // Rule ID 65635 //
        GIM_CheckFeatures, GIFBS_HasStdExtZkne_IsRV32,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_aes32esmi,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] imm
        // No operand predicates
        // (intrinsic_wo_chain:{ *:[i32] } 7767:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, i8:{ *:[i8] }:$imm)  =>  (AES32ESMI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i8] })<<P:Predicate_byteselect>>:$imm)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AES32ESMI,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // imm
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65635,
        GIR_Done,
      // Label 1780: @40584
      GIM_Try, /*On fail goto*//*Label 1781*/ 40640, // Rule ID 65656 //
        GIM_CheckFeatures, GIFBS_HasStdExtZksed,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_sm4ks,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] imm
        // No operand predicates
        // (intrinsic_wo_chain:{ *:[i64] } 7824:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, i8:{ *:[i8] }:$imm)  =>  (SM4KS:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, (timm:{ *:[i8] })<<P:Predicate_byteselect>>:$imm)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SM4KS,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // imm
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65656,
        GIR_Done,
      // Label 1781: @40640
      GIM_Try, /*On fail goto*//*Label 1782*/ 40696, // Rule ID 65657 //
        GIM_CheckFeatures, GIFBS_HasStdExtZksed,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_sm4ks,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] imm
        // No operand predicates
        // (intrinsic_wo_chain:{ *:[i32] } 7824:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, i8:{ *:[i8] }:$imm)  =>  (SM4KS:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i8] })<<P:Predicate_byteselect>>:$imm)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SM4KS,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // imm
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65657,
        GIR_Done,
      // Label 1782: @40696
      GIM_Try, /*On fail goto*//*Label 1783*/ 40752, // Rule ID 65658 //
        GIM_CheckFeatures, GIFBS_HasStdExtZksed,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_sm4ed,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] imm
        // No operand predicates
        // (intrinsic_wo_chain:{ *:[i64] } 7823:{ *:[iPTR] }, GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, i8:{ *:[i8] }:$imm)  =>  (SM4ED:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, (timm:{ *:[i8] })<<P:Predicate_byteselect>>:$imm)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SM4ED,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // imm
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65658,
        GIR_Done,
      // Label 1783: @40752
      GIM_Try, /*On fail goto*//*Label 1784*/ 40808, // Rule ID 65659 //
        GIM_CheckFeatures, GIFBS_HasStdExtZksed,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_sm4ed,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] imm
        // No operand predicates
        // (intrinsic_wo_chain:{ *:[i32] } 7823:{ *:[iPTR] }, GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, i8:{ *:[i8] }:$imm)  =>  (SM4ED:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, (timm:{ *:[i8] })<<P:Predicate_byteselect>>:$imm)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SM4ED,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // imm
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65659,
        GIR_Done,
      // Label 1784: @40808
      GIM_Reject,
    // Label 1776: @40809
    GIM_Reject,
    // Label 28: @40810
    GIM_Try, /*On fail goto*//*Label 1785*/ 40928,
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::hwasan_check_memaccess_shortgranules,
      GIM_Try, /*On fail goto*//*Label 1786*/ 40873, // Rule ID 25 //
        GIM_CheckFeatures, GIFBS_IsRV64,
        // MIs[0] Operand 1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRNoX0X2RegClassID,
        // MIs[0] ptr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRJALRRegClassID,
        // MIs[0] accessinfo
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        // (intrinsic_void 155:{ *:[iPTR] }, X5:{ *:[i64] }, GPRJALR:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo)  =>  (HWASAN_CHECK_MEMACCESS_SHORTGRANULES GPRJALR:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo)
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
        GIR_AddRegister, /*InsnID*/1, RISCV::X5, /*AddRegisterRegFlags*/RegState::Define,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // X5
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::HWASAN_CHECK_MEMACCESS_SHORTGRANULES,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // accessinfo
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 25,
        GIR_Done,
      // Label 1786: @40873
      GIM_Try, /*On fail goto*//*Label 1787*/ 40927, // Rule ID 26 //
        GIM_CheckFeatures, GIFBS_IsRV64,
        // MIs[0] Operand 1
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRNoX0X2RegClassID,
        // MIs[0] ptr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRJALRRegClassID,
        // MIs[0] accessinfo
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        // (intrinsic_void 155:{ *:[iPTR] }, X5:{ *:[i32] }, GPRJALR:{ *:[i32] }:$ptr, (timm:{ *:[i32] }):$accessinfo)  =>  (HWASAN_CHECK_MEMACCESS_SHORTGRANULES GPRJALR:{ *:[i32] }:$ptr, (timm:{ *:[i32] }):$accessinfo)
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
        GIR_AddRegister, /*InsnID*/1, RISCV::X5, /*AddRegisterRegFlags*/RegState::Define,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // X5
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::HWASAN_CHECK_MEMACCESS_SHORTGRANULES,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // accessinfo
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 26,
        GIR_Done,
      // Label 1787: @40927
      GIM_Reject,
    // Label 1785: @40928
    GIM_Try, /*On fail goto*//*Label 1788*/ 41946,
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
      GIM_Try, /*On fail goto*//*Label 1789*/ 41015, // Rule ID 64999 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_masked_atomicrmw_xchg_i32,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] ordering
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // (intrinsic_w_chain:{ *:[i32] } 7793:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering)  =>  (PseudoMaskedAtomicSwap32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoMaskedAtomicSwap32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // incr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // mask
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // ordering
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64999,
        GIR_Done,
      // Label 1789: @41015
      GIM_Try, /*On fail goto*//*Label 1790*/ 41097, // Rule ID 65008 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_masked_atomicrmw_add_i32,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] ordering
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // (intrinsic_w_chain:{ *:[i32] } 7779:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering)  =>  (PseudoMaskedAtomicLoadAdd32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoMaskedAtomicLoadAdd32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // incr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // mask
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // ordering
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65008,
        GIR_Done,
      // Label 1790: @41097
      GIM_Try, /*On fail goto*//*Label 1791*/ 41179, // Rule ID 65009 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_masked_atomicrmw_sub_i32,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] ordering
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // (intrinsic_w_chain:{ *:[i32] } 7787:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering)  =>  (PseudoMaskedAtomicLoadSub32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoMaskedAtomicLoadSub32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // incr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // mask
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // ordering
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65009,
        GIR_Done,
      // Label 1791: @41179
      GIM_Try, /*On fail goto*//*Label 1792*/ 41261, // Rule ID 65010 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_masked_atomicrmw_nand_i32,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] ordering
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // (intrinsic_w_chain:{ *:[i32] } 7785:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering)  =>  (PseudoMaskedAtomicLoadNand32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoMaskedAtomicLoadNand32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // incr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // mask
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // ordering
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65010,
        GIR_Done,
      // Label 1792: @41261
      GIM_Try, /*On fail goto*//*Label 1793*/ 41350, // Rule ID 65013 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_masked_atomicrmw_umax_i32,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] ordering
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // (intrinsic_w_chain:{ *:[i32] } 7789:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering)  =>  (PseudoMaskedAtomicLoadUMax32:{ *:[i32] }:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering)
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoMaskedAtomicLoadUMax32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // incr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // mask
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // ordering
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65013,
        GIR_Done,
      // Label 1793: @41350
      GIM_Try, /*On fail goto*//*Label 1794*/ 41439, // Rule ID 65014 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_masked_atomicrmw_umin_i32,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] ordering
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // (intrinsic_w_chain:{ *:[i32] } 7791:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering)  =>  (PseudoMaskedAtomicLoadUMin32:{ *:[i32] }:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering)
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoMaskedAtomicLoadUMin32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // incr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // mask
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // ordering
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65014,
        GIR_Done,
      // Label 1794: @41439
      GIM_Try, /*On fail goto*//*Label 1795*/ 41521, // Rule ID 65126 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_masked_atomicrmw_xchg_i64,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] ordering
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // (intrinsic_w_chain:{ *:[i64] } 7794:{ *:[iPTR] }, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, (timm:{ *:[i64] }):$ordering)  =>  (PseudoMaskedAtomicSwap32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, (timm:{ *:[i64] }):$ordering)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoMaskedAtomicSwap32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // incr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // mask
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // ordering
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65126,
        GIR_Done,
      // Label 1795: @41521
      GIM_Try, /*On fail goto*//*Label 1796*/ 41603, // Rule ID 65127 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_masked_atomicrmw_add_i64,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] ordering
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // (intrinsic_w_chain:{ *:[i64] } 7780:{ *:[iPTR] }, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, (timm:{ *:[i64] }):$ordering)  =>  (PseudoMaskedAtomicLoadAdd32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, (timm:{ *:[i64] }):$ordering)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoMaskedAtomicLoadAdd32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // incr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // mask
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // ordering
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65127,
        GIR_Done,
      // Label 1796: @41603
      GIM_Try, /*On fail goto*//*Label 1797*/ 41685, // Rule ID 65128 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_masked_atomicrmw_sub_i64,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] ordering
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // (intrinsic_w_chain:{ *:[i64] } 7788:{ *:[iPTR] }, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, (timm:{ *:[i64] }):$ordering)  =>  (PseudoMaskedAtomicLoadSub32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, (timm:{ *:[i64] }):$ordering)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoMaskedAtomicLoadSub32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // incr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // mask
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // ordering
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65128,
        GIR_Done,
      // Label 1797: @41685
      GIM_Try, /*On fail goto*//*Label 1798*/ 41767, // Rule ID 65129 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_masked_atomicrmw_nand_i64,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] ordering
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // (intrinsic_w_chain:{ *:[i64] } 7786:{ *:[iPTR] }, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, (timm:{ *:[i64] }):$ordering)  =>  (PseudoMaskedAtomicLoadNand32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, (timm:{ *:[i64] }):$ordering)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoMaskedAtomicLoadNand32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // incr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // mask
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // ordering
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65129,
        GIR_Done,
      // Label 1798: @41767
      GIM_Try, /*On fail goto*//*Label 1799*/ 41856, // Rule ID 65132 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_masked_atomicrmw_umax_i64,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] ordering
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // (intrinsic_w_chain:{ *:[i64] } 7790:{ *:[iPTR] }, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, (timm:{ *:[i64] }):$ordering)  =>  (PseudoMaskedAtomicLoadUMax32:{ *:[i64] }:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, (timm:{ *:[i64] }):$ordering)
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoMaskedAtomicLoadUMax32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // incr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // mask
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // ordering
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65132,
        GIR_Done,
      // Label 1799: @41856
      GIM_Try, /*On fail goto*//*Label 1800*/ 41945, // Rule ID 65133 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_masked_atomicrmw_umin_i64,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] ordering
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // (intrinsic_w_chain:{ *:[i64] } 7792:{ *:[iPTR] }, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, (timm:{ *:[i64] }):$ordering)  =>  (PseudoMaskedAtomicLoadUMin32:{ *:[i64] }:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, (timm:{ *:[i64] }):$ordering)
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoMaskedAtomicLoadUMin32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // incr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // mask
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // ordering
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65133,
        GIR_Done,
      // Label 1800: @41945
      GIM_Reject,
    // Label 1788: @41946
    GIM_Try, /*On fail goto*//*Label 1801*/ 42544,
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/7,
      GIM_Try, /*On fail goto*//*Label 1802*/ 42052, // Rule ID 65011 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_masked_atomicrmw_max_i32,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] ordering
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // (intrinsic_w_chain:{ *:[i32] } 7781:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, GPR:{ *:[i32] }:$shiftamt, (timm:{ *:[i32] }):$ordering)  =>  (PseudoMaskedAtomicLoadMax32:{ *:[i32] }:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, GPR:{ *:[i32] }:$shiftamt, (timm:{ *:[i32] }):$ordering)
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoMaskedAtomicLoadMax32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // incr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // mask
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // shiftamt
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // ordering
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65011,
        GIR_Done,
      // Label 1802: @42052
      GIM_Try, /*On fail goto*//*Label 1803*/ 42153, // Rule ID 65012 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_masked_atomicrmw_min_i32,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] ordering
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // (intrinsic_w_chain:{ *:[i32] } 7783:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, GPR:{ *:[i32] }:$shiftamt, (timm:{ *:[i32] }):$ordering)  =>  (PseudoMaskedAtomicLoadMin32:{ *:[i32] }:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, GPR:{ *:[i32] }:$shiftamt, (timm:{ *:[i32] }):$ordering)
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoMaskedAtomicLoadMin32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // incr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // mask
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // shiftamt
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // ordering
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65012,
        GIR_Done,
      // Label 1803: @42153
      GIM_Try, /*On fail goto*//*Label 1804*/ 42247, // Rule ID 65025 //
        GIM_CheckFeatures, GIFBS_HasStdExtA,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_masked_cmpxchg_i32,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] ordering
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // (intrinsic_w_chain:{ *:[i32] } 7795:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmpval, GPR:{ *:[i32] }:$newval, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering)  =>  (PseudoMaskedCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmpval, GPR:{ *:[i32] }:$newval, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoMaskedCmpXchg32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // cmpval
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // newval
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // mask
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // ordering
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65025,
        GIR_Done,
      // Label 1804: @42247
      GIM_Try, /*On fail goto*//*Label 1805*/ 42348, // Rule ID 65130 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_masked_atomicrmw_max_i64,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] ordering
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // (intrinsic_w_chain:{ *:[i64] } 7782:{ *:[iPTR] }, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, GPR:{ *:[i64] }:$shiftamt, (timm:{ *:[i64] }):$ordering)  =>  (PseudoMaskedAtomicLoadMax32:{ *:[i64] }:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, GPR:{ *:[i64] }:$shiftamt, (timm:{ *:[i64] }):$ordering)
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoMaskedAtomicLoadMax32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // incr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // mask
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // shiftamt
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // ordering
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65130,
        GIR_Done,
      // Label 1805: @42348
      GIM_Try, /*On fail goto*//*Label 1806*/ 42449, // Rule ID 65131 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_masked_atomicrmw_min_i64,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] ordering
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // (intrinsic_w_chain:{ *:[i64] } 7784:{ *:[iPTR] }, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, GPR:{ *:[i64] }:$shiftamt, (timm:{ *:[i64] }):$ordering)  =>  (PseudoMaskedAtomicLoadMin32:{ *:[i64] }:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, GPR:{ *:[i64] }:$shiftamt, (timm:{ *:[i64] }):$ordering)
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoMaskedAtomicLoadMin32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // incr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // mask
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // shiftamt
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // ordering
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65131,
        GIR_Done,
      // Label 1806: @42449
      GIM_Try, /*On fail goto*//*Label 1807*/ 42543, // Rule ID 65144 //
        GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::riscv_masked_cmpxchg_i64,
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] addr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/RISCV::GPRRegClassID,
        // MIs[0] ordering
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // (intrinsic_w_chain:{ *:[i64] } 7796:{ *:[iPTR] }, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmpval, GPR:{ *:[i64] }:$newval, GPR:{ *:[i64] }:$mask, (timm:{ *:[i64] }):$ordering)  =>  (PseudoMaskedCmpXchg32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmpval, GPR:{ *:[i64] }:$newval, GPR:{ *:[i64] }:$mask, (timm:{ *:[i64] }):$ordering)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoMaskedCmpXchg32,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // res
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // cmpval
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // newval
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // mask
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // ordering
        GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65144,
        GIR_Done,
      // Label 1807: @42543
      GIM_Reject,
    // Label 1801: @42544
    GIM_Reject,
    // Label 29: @42545
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 30, /*)*//*default:*//*Label 1823*/ 44665,
    /*GILLT_nxv1s16*//*Label 1808*/ 42576,
    /*GILLT_nxv1s32*//*Label 1809*/ 42644,
    /*GILLT_nxv1s64*//*Label 1810*/ 42797, 0, 0,
    /*GILLT_nxv2s16*//*Label 1811*/ 43026,
    /*GILLT_nxv2s32*//*Label 1812*/ 43094,
    /*GILLT_nxv2s64*//*Label 1813*/ 43247, 0, 0,
    /*GILLT_nxv4s16*//*Label 1814*/ 43476,
    /*GILLT_nxv4s32*//*Label 1815*/ 43544,
    /*GILLT_nxv4s64*//*Label 1816*/ 43697, 0, 0,
    /*GILLT_nxv8s16*//*Label 1817*/ 43926,
    /*GILLT_nxv8s32*//*Label 1818*/ 43994,
    /*GILLT_nxv8s64*//*Label 1819*/ 44147, 0, 0,
    /*GILLT_nxv16s16*//*Label 1820*/ 44376,
    /*GILLT_nxv16s32*//*Label 1821*/ 44444, 0, 0,
    /*GILLT_nxv32s16*//*Label 1822*/ 44597,
    // Label 1808: @42576
    GIM_Try, /*On fail goto*//*Label 1824*/ 42643,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1825*/ 42616, // Rule ID 56223 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (anyext:{ *:[nxv1i16] } VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVZEXT_VF2_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56223,
        GIR_Done,
      // Label 1825: @42616
      GIM_Try, /*On fail goto*//*Label 1826*/ 42642, // Rule ID 56224 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (anyext:{ *:[nxv1i16] } VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVZEXT_VF2_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56224,
        GIR_Done,
      // Label 1826: @42642
      GIM_Reject,
    // Label 1824: @42643
    GIM_Reject,
    // Label 1809: @42644
    GIM_Try, /*On fail goto*//*Label 1827*/ 42682, // Rule ID 56247 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv1i32] } VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVZEXT_VF2_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56247,
      GIR_Done,
    // Label 1827: @42682
    GIM_Try, /*On fail goto*//*Label 1828*/ 42720, // Rule ID 56248 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv1i32] } VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVZEXT_VF2_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56248,
      GIR_Done,
    // Label 1828: @42720
    GIM_Try, /*On fail goto*//*Label 1829*/ 42758, // Rule ID 56313 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv1i32] } VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVZEXT_VF4_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56313,
      GIR_Done,
    // Label 1829: @42758
    GIM_Try, /*On fail goto*//*Label 1830*/ 42796, // Rule ID 56314 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv1i32] } VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVZEXT_VF4_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56314,
      GIR_Done,
    // Label 1830: @42796
    GIM_Reject,
    // Label 1810: @42797
    GIM_Try, /*On fail goto*//*Label 1831*/ 42835, // Rule ID 56267 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv1i64] } VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVZEXT_VF2_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56267,
      GIR_Done,
    // Label 1831: @42835
    GIM_Try, /*On fail goto*//*Label 1832*/ 42873, // Rule ID 56268 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv1i64] } VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVZEXT_VF2_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56268,
      GIR_Done,
    // Label 1832: @42873
    GIM_Try, /*On fail goto*//*Label 1833*/ 42911, // Rule ID 56333 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv1i64] } VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVZEXT_VF4_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56333,
      GIR_Done,
    // Label 1833: @42911
    GIM_Try, /*On fail goto*//*Label 1834*/ 42949, // Rule ID 56334 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv1i64] } VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVZEXT_VF4_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56334,
      GIR_Done,
    // Label 1834: @42949
    GIM_Try, /*On fail goto*//*Label 1835*/ 42987, // Rule ID 56367 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv1i64] } VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVZEXT_VF8_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF8_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56367,
      GIR_Done,
    // Label 1835: @42987
    GIM_Try, /*On fail goto*//*Label 1836*/ 43025, // Rule ID 56368 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv1i64] } VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVZEXT_VF8_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF8_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56368,
      GIR_Done,
    // Label 1836: @43025
    GIM_Reject,
    // Label 1811: @43026
    GIM_Try, /*On fail goto*//*Label 1837*/ 43093,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1838*/ 43066, // Rule ID 56227 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (anyext:{ *:[nxv2i16] } VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVZEXT_VF2_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56227,
        GIR_Done,
      // Label 1838: @43066
      GIM_Try, /*On fail goto*//*Label 1839*/ 43092, // Rule ID 56228 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (anyext:{ *:[nxv2i16] } VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVZEXT_VF2_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56228,
        GIR_Done,
      // Label 1839: @43092
      GIM_Reject,
    // Label 1837: @43093
    GIM_Reject,
    // Label 1812: @43094
    GIM_Try, /*On fail goto*//*Label 1840*/ 43132, // Rule ID 56251 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv2i32] } VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVZEXT_VF2_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56251,
      GIR_Done,
    // Label 1840: @43132
    GIM_Try, /*On fail goto*//*Label 1841*/ 43170, // Rule ID 56252 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv2i32] } VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVZEXT_VF2_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56252,
      GIR_Done,
    // Label 1841: @43170
    GIM_Try, /*On fail goto*//*Label 1842*/ 43208, // Rule ID 56317 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv2i32] } VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVZEXT_VF4_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56317,
      GIR_Done,
    // Label 1842: @43208
    GIM_Try, /*On fail goto*//*Label 1843*/ 43246, // Rule ID 56318 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv2i32] } VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVZEXT_VF4_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56318,
      GIR_Done,
    // Label 1843: @43246
    GIM_Reject,
    // Label 1813: @43247
    GIM_Try, /*On fail goto*//*Label 1844*/ 43285, // Rule ID 56271 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv2i64] } VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVZEXT_VF2_M2:{ *:[nxv2i64] } VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56271,
      GIR_Done,
    // Label 1844: @43285
    GIM_Try, /*On fail goto*//*Label 1845*/ 43323, // Rule ID 56272 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv2i64] } VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVZEXT_VF2_M2:{ *:[nxv2i64] } VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56272,
      GIR_Done,
    // Label 1845: @43323
    GIM_Try, /*On fail goto*//*Label 1846*/ 43361, // Rule ID 56337 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv2i64] } VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVZEXT_VF4_M2:{ *:[nxv2i64] } VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56337,
      GIR_Done,
    // Label 1846: @43361
    GIM_Try, /*On fail goto*//*Label 1847*/ 43399, // Rule ID 56338 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv2i64] } VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVZEXT_VF4_M2:{ *:[nxv2i64] } VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56338,
      GIR_Done,
    // Label 1847: @43399
    GIM_Try, /*On fail goto*//*Label 1848*/ 43437, // Rule ID 56371 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv2i64] } VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVZEXT_VF8_M2:{ *:[nxv2i64] } VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF8_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56371,
      GIR_Done,
    // Label 1848: @43437
    GIM_Try, /*On fail goto*//*Label 1849*/ 43475, // Rule ID 56372 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv2i64] } VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVZEXT_VF8_M2:{ *:[nxv2i64] } VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF8_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56372,
      GIR_Done,
    // Label 1849: @43475
    GIM_Reject,
    // Label 1814: @43476
    GIM_Try, /*On fail goto*//*Label 1850*/ 43543,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1851*/ 43516, // Rule ID 56231 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (anyext:{ *:[nxv4i16] } VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVZEXT_VF2_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56231,
        GIR_Done,
      // Label 1851: @43516
      GIM_Try, /*On fail goto*//*Label 1852*/ 43542, // Rule ID 56232 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (anyext:{ *:[nxv4i16] } VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVZEXT_VF2_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56232,
        GIR_Done,
      // Label 1852: @43542
      GIM_Reject,
    // Label 1850: @43543
    GIM_Reject,
    // Label 1815: @43544
    GIM_Try, /*On fail goto*//*Label 1853*/ 43582, // Rule ID 56255 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv4i32] } VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVZEXT_VF2_M2:{ *:[nxv4i32] } VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56255,
      GIR_Done,
    // Label 1853: @43582
    GIM_Try, /*On fail goto*//*Label 1854*/ 43620, // Rule ID 56256 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv4i32] } VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVZEXT_VF2_M2:{ *:[nxv4i32] } VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56256,
      GIR_Done,
    // Label 1854: @43620
    GIM_Try, /*On fail goto*//*Label 1855*/ 43658, // Rule ID 56321 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv4i32] } VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVZEXT_VF4_M2:{ *:[nxv4i32] } VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56321,
      GIR_Done,
    // Label 1855: @43658
    GIM_Try, /*On fail goto*//*Label 1856*/ 43696, // Rule ID 56322 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv4i32] } VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVZEXT_VF4_M2:{ *:[nxv4i32] } VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56322,
      GIR_Done,
    // Label 1856: @43696
    GIM_Reject,
    // Label 1816: @43697
    GIM_Try, /*On fail goto*//*Label 1857*/ 43735, // Rule ID 56275 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (anyext:{ *:[nxv4i64] } VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVZEXT_VF2_M4:{ *:[nxv4i64] } VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56275,
      GIR_Done,
    // Label 1857: @43735
    GIM_Try, /*On fail goto*//*Label 1858*/ 43773, // Rule ID 56276 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (anyext:{ *:[nxv4i64] } VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVZEXT_VF2_M4:{ *:[nxv4i64] } VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56276,
      GIR_Done,
    // Label 1858: @43773
    GIM_Try, /*On fail goto*//*Label 1859*/ 43811, // Rule ID 56341 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv4i64] } VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVZEXT_VF4_M4:{ *:[nxv4i64] } VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56341,
      GIR_Done,
    // Label 1859: @43811
    GIM_Try, /*On fail goto*//*Label 1860*/ 43849, // Rule ID 56342 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv4i64] } VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVZEXT_VF4_M4:{ *:[nxv4i64] } VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56342,
      GIR_Done,
    // Label 1860: @43849
    GIM_Try, /*On fail goto*//*Label 1861*/ 43887, // Rule ID 56375 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv4i64] } VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVZEXT_VF8_M4:{ *:[nxv4i64] } VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF8_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56375,
      GIR_Done,
    // Label 1861: @43887
    GIM_Try, /*On fail goto*//*Label 1862*/ 43925, // Rule ID 56376 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv4i64] } VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVZEXT_VF8_M4:{ *:[nxv4i64] } VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF8_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56376,
      GIR_Done,
    // Label 1862: @43925
    GIM_Reject,
    // Label 1817: @43926
    GIM_Try, /*On fail goto*//*Label 1863*/ 43993,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1864*/ 43966, // Rule ID 56235 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (anyext:{ *:[nxv8i16] } VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVZEXT_VF2_M2:{ *:[nxv8i16] } VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56235,
        GIR_Done,
      // Label 1864: @43966
      GIM_Try, /*On fail goto*//*Label 1865*/ 43992, // Rule ID 56236 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (anyext:{ *:[nxv8i16] } VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVZEXT_VF2_M2:{ *:[nxv8i16] } VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56236,
        GIR_Done,
      // Label 1865: @43992
      GIM_Reject,
    // Label 1863: @43993
    GIM_Reject,
    // Label 1818: @43994
    GIM_Try, /*On fail goto*//*Label 1866*/ 44032, // Rule ID 56259 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (anyext:{ *:[nxv8i32] } VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVZEXT_VF2_M4:{ *:[nxv8i32] } VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56259,
      GIR_Done,
    // Label 1866: @44032
    GIM_Try, /*On fail goto*//*Label 1867*/ 44070, // Rule ID 56260 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (anyext:{ *:[nxv8i32] } VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVZEXT_VF2_M4:{ *:[nxv8i32] } VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56260,
      GIR_Done,
    // Label 1867: @44070
    GIM_Try, /*On fail goto*//*Label 1868*/ 44108, // Rule ID 56325 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv8i32] } VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVZEXT_VF4_M4:{ *:[nxv8i32] } VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56325,
      GIR_Done,
    // Label 1868: @44108
    GIM_Try, /*On fail goto*//*Label 1869*/ 44146, // Rule ID 56326 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv8i32] } VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVZEXT_VF4_M4:{ *:[nxv8i32] } VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56326,
      GIR_Done,
    // Label 1869: @44146
    GIM_Reject,
    // Label 1819: @44147
    GIM_Try, /*On fail goto*//*Label 1870*/ 44185, // Rule ID 56279 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (anyext:{ *:[nxv8i64] } VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVZEXT_VF2_M8:{ *:[nxv8i64] } VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56279,
      GIR_Done,
    // Label 1870: @44185
    GIM_Try, /*On fail goto*//*Label 1871*/ 44223, // Rule ID 56280 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (anyext:{ *:[nxv8i64] } VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVZEXT_VF2_M8:{ *:[nxv8i64] } VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56280,
      GIR_Done,
    // Label 1871: @44223
    GIM_Try, /*On fail goto*//*Label 1872*/ 44261, // Rule ID 56345 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (anyext:{ *:[nxv8i64] } VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVZEXT_VF4_M8:{ *:[nxv8i64] } VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56345,
      GIR_Done,
    // Label 1872: @44261
    GIM_Try, /*On fail goto*//*Label 1873*/ 44299, // Rule ID 56346 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (anyext:{ *:[nxv8i64] } VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVZEXT_VF4_M8:{ *:[nxv8i64] } VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56346,
      GIR_Done,
    // Label 1873: @44299
    GIM_Try, /*On fail goto*//*Label 1874*/ 44337, // Rule ID 56379 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv8i64] } VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVZEXT_VF8_M8:{ *:[nxv8i64] } VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF8_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56379,
      GIR_Done,
    // Label 1874: @44337
    GIM_Try, /*On fail goto*//*Label 1875*/ 44375, // Rule ID 56380 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (anyext:{ *:[nxv8i64] } VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVZEXT_VF8_M8:{ *:[nxv8i64] } VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF8_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56380,
      GIR_Done,
    // Label 1875: @44375
    GIM_Reject,
    // Label 1820: @44376
    GIM_Try, /*On fail goto*//*Label 1876*/ 44443,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 1877*/ 44416, // Rule ID 56239 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (anyext:{ *:[nxv16i16] } VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVZEXT_VF2_M4:{ *:[nxv16i16] } VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56239,
        GIR_Done,
      // Label 1877: @44416
      GIM_Try, /*On fail goto*//*Label 1878*/ 44442, // Rule ID 56240 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (anyext:{ *:[nxv16i16] } VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVZEXT_VF2_M4:{ *:[nxv16i16] } VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56240,
        GIR_Done,
      // Label 1878: @44442
      GIM_Reject,
    // Label 1876: @44443
    GIM_Reject,
    // Label 1821: @44444
    GIM_Try, /*On fail goto*//*Label 1879*/ 44482, // Rule ID 56263 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (anyext:{ *:[nxv16i32] } VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVZEXT_VF2_M8:{ *:[nxv16i32] } VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56263,
      GIR_Done,
    // Label 1879: @44482
    GIM_Try, /*On fail goto*//*Label 1880*/ 44520, // Rule ID 56264 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (anyext:{ *:[nxv16i32] } VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVZEXT_VF2_M8:{ *:[nxv16i32] } VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56264,
      GIR_Done,
    // Label 1880: @44520
    GIM_Try, /*On fail goto*//*Label 1881*/ 44558, // Rule ID 56329 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (anyext:{ *:[nxv16i32] } VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVZEXT_VF4_M8:{ *:[nxv16i32] } VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56329,
      GIR_Done,
    // Label 1881: @44558
    GIM_Try, /*On fail goto*//*Label 1882*/ 44596, // Rule ID 56330 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (anyext:{ *:[nxv16i32] } VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVZEXT_VF4_M8:{ *:[nxv16i32] } VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56330,
      GIR_Done,
    // Label 1882: @44596
    GIM_Reject,
    // Label 1822: @44597
    GIM_Try, /*On fail goto*//*Label 1883*/ 44664,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 1884*/ 44637, // Rule ID 56243 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (anyext:{ *:[nxv32i16] } VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVZEXT_VF2_M8:{ *:[nxv32i16] } VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56243,
        GIR_Done,
      // Label 1884: @44637
      GIM_Try, /*On fail goto*//*Label 1885*/ 44663, // Rule ID 56244 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (anyext:{ *:[nxv32i16] } VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVZEXT_VF2_M8:{ *:[nxv32i16] } VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56244,
        GIR_Done,
      // Label 1885: @44663
      GIM_Reject,
    // Label 1883: @44664
    GIM_Reject,
    // Label 1823: @44665
    GIM_Reject,
    // Label 30: @44666
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 30, /*)*//*default:*//*Label 1901*/ 46786,
    /*GILLT_nxv1s16*//*Label 1886*/ 44697,
    /*GILLT_nxv1s32*//*Label 1887*/ 44765,
    /*GILLT_nxv1s64*//*Label 1888*/ 44918, 0, 0,
    /*GILLT_nxv2s16*//*Label 1889*/ 45147,
    /*GILLT_nxv2s32*//*Label 1890*/ 45215,
    /*GILLT_nxv2s64*//*Label 1891*/ 45368, 0, 0,
    /*GILLT_nxv4s16*//*Label 1892*/ 45597,
    /*GILLT_nxv4s32*//*Label 1893*/ 45665,
    /*GILLT_nxv4s64*//*Label 1894*/ 45818, 0, 0,
    /*GILLT_nxv8s16*//*Label 1895*/ 46047,
    /*GILLT_nxv8s32*//*Label 1896*/ 46115,
    /*GILLT_nxv8s64*//*Label 1897*/ 46268, 0, 0,
    /*GILLT_nxv16s16*//*Label 1898*/ 46497,
    /*GILLT_nxv16s32*//*Label 1899*/ 46565, 0, 0,
    /*GILLT_nxv32s16*//*Label 1900*/ 46718,
    // Label 1886: @44697
    GIM_Try, /*On fail goto*//*Label 1902*/ 44764,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1903*/ 44737, // Rule ID 56281 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sext:{ *:[nxv1i16] } VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVSEXT_VF2_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56281,
        GIR_Done,
      // Label 1903: @44737
      GIM_Try, /*On fail goto*//*Label 1904*/ 44763, // Rule ID 56282 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sext:{ *:[nxv1i16] } VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVSEXT_VF2_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56282,
        GIR_Done,
      // Label 1904: @44763
      GIM_Reject,
    // Label 1902: @44764
    GIM_Reject,
    // Label 1887: @44765
    GIM_Try, /*On fail goto*//*Label 1905*/ 44803, // Rule ID 56293 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv1i32] } VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVSEXT_VF2_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56293,
      GIR_Done,
    // Label 1905: @44803
    GIM_Try, /*On fail goto*//*Label 1906*/ 44841, // Rule ID 56294 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv1i32] } VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVSEXT_VF2_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56294,
      GIR_Done,
    // Label 1906: @44841
    GIM_Try, /*On fail goto*//*Label 1907*/ 44879, // Rule ID 56347 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv1i32] } VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVSEXT_VF4_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF4_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56347,
      GIR_Done,
    // Label 1907: @44879
    GIM_Try, /*On fail goto*//*Label 1908*/ 44917, // Rule ID 56348 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv1i32] } VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVSEXT_VF4_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF4_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56348,
      GIR_Done,
    // Label 1908: @44917
    GIM_Reject,
    // Label 1888: @44918
    GIM_Try, /*On fail goto*//*Label 1909*/ 44956, // Rule ID 56303 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv1i64] } VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVSEXT_VF2_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56303,
      GIR_Done,
    // Label 1909: @44956
    GIM_Try, /*On fail goto*//*Label 1910*/ 44994, // Rule ID 56304 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv1i64] } VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVSEXT_VF2_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56304,
      GIR_Done,
    // Label 1910: @44994
    GIM_Try, /*On fail goto*//*Label 1911*/ 45032, // Rule ID 56357 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv1i64] } VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVSEXT_VF4_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF4_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56357,
      GIR_Done,
    // Label 1911: @45032
    GIM_Try, /*On fail goto*//*Label 1912*/ 45070, // Rule ID 56358 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv1i64] } VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVSEXT_VF4_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF4_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56358,
      GIR_Done,
    // Label 1912: @45070
    GIM_Try, /*On fail goto*//*Label 1913*/ 45108, // Rule ID 56381 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv1i64] } VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVSEXT_VF8_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF8_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56381,
      GIR_Done,
    // Label 1913: @45108
    GIM_Try, /*On fail goto*//*Label 1914*/ 45146, // Rule ID 56382 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv1i64] } VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVSEXT_VF8_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF8_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56382,
      GIR_Done,
    // Label 1914: @45146
    GIM_Reject,
    // Label 1889: @45147
    GIM_Try, /*On fail goto*//*Label 1915*/ 45214,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1916*/ 45187, // Rule ID 56283 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sext:{ *:[nxv2i16] } VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVSEXT_VF2_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56283,
        GIR_Done,
      // Label 1916: @45187
      GIM_Try, /*On fail goto*//*Label 1917*/ 45213, // Rule ID 56284 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sext:{ *:[nxv2i16] } VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVSEXT_VF2_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56284,
        GIR_Done,
      // Label 1917: @45213
      GIM_Reject,
    // Label 1915: @45214
    GIM_Reject,
    // Label 1890: @45215
    GIM_Try, /*On fail goto*//*Label 1918*/ 45253, // Rule ID 56295 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv2i32] } VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVSEXT_VF2_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56295,
      GIR_Done,
    // Label 1918: @45253
    GIM_Try, /*On fail goto*//*Label 1919*/ 45291, // Rule ID 56296 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv2i32] } VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVSEXT_VF2_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56296,
      GIR_Done,
    // Label 1919: @45291
    GIM_Try, /*On fail goto*//*Label 1920*/ 45329, // Rule ID 56349 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv2i32] } VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVSEXT_VF4_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF4_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56349,
      GIR_Done,
    // Label 1920: @45329
    GIM_Try, /*On fail goto*//*Label 1921*/ 45367, // Rule ID 56350 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv2i32] } VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVSEXT_VF4_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF4_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56350,
      GIR_Done,
    // Label 1921: @45367
    GIM_Reject,
    // Label 1891: @45368
    GIM_Try, /*On fail goto*//*Label 1922*/ 45406, // Rule ID 56305 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv2i64] } VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVSEXT_VF2_M2:{ *:[nxv2i64] } VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56305,
      GIR_Done,
    // Label 1922: @45406
    GIM_Try, /*On fail goto*//*Label 1923*/ 45444, // Rule ID 56306 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv2i64] } VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVSEXT_VF2_M2:{ *:[nxv2i64] } VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56306,
      GIR_Done,
    // Label 1923: @45444
    GIM_Try, /*On fail goto*//*Label 1924*/ 45482, // Rule ID 56359 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv2i64] } VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVSEXT_VF4_M2:{ *:[nxv2i64] } VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF4_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56359,
      GIR_Done,
    // Label 1924: @45482
    GIM_Try, /*On fail goto*//*Label 1925*/ 45520, // Rule ID 56360 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv2i64] } VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVSEXT_VF4_M2:{ *:[nxv2i64] } VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF4_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56360,
      GIR_Done,
    // Label 1925: @45520
    GIM_Try, /*On fail goto*//*Label 1926*/ 45558, // Rule ID 56383 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv2i64] } VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVSEXT_VF8_M2:{ *:[nxv2i64] } VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF8_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56383,
      GIR_Done,
    // Label 1926: @45558
    GIM_Try, /*On fail goto*//*Label 1927*/ 45596, // Rule ID 56384 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv2i64] } VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVSEXT_VF8_M2:{ *:[nxv2i64] } VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF8_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56384,
      GIR_Done,
    // Label 1927: @45596
    GIM_Reject,
    // Label 1892: @45597
    GIM_Try, /*On fail goto*//*Label 1928*/ 45664,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1929*/ 45637, // Rule ID 56285 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sext:{ *:[nxv4i16] } VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVSEXT_VF2_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56285,
        GIR_Done,
      // Label 1929: @45637
      GIM_Try, /*On fail goto*//*Label 1930*/ 45663, // Rule ID 56286 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sext:{ *:[nxv4i16] } VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVSEXT_VF2_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56286,
        GIR_Done,
      // Label 1930: @45663
      GIM_Reject,
    // Label 1928: @45664
    GIM_Reject,
    // Label 1893: @45665
    GIM_Try, /*On fail goto*//*Label 1931*/ 45703, // Rule ID 56297 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv4i32] } VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVSEXT_VF2_M2:{ *:[nxv4i32] } VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56297,
      GIR_Done,
    // Label 1931: @45703
    GIM_Try, /*On fail goto*//*Label 1932*/ 45741, // Rule ID 56298 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv4i32] } VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVSEXT_VF2_M2:{ *:[nxv4i32] } VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56298,
      GIR_Done,
    // Label 1932: @45741
    GIM_Try, /*On fail goto*//*Label 1933*/ 45779, // Rule ID 56351 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv4i32] } VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVSEXT_VF4_M2:{ *:[nxv4i32] } VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF4_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56351,
      GIR_Done,
    // Label 1933: @45779
    GIM_Try, /*On fail goto*//*Label 1934*/ 45817, // Rule ID 56352 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv4i32] } VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVSEXT_VF4_M2:{ *:[nxv4i32] } VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF4_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56352,
      GIR_Done,
    // Label 1934: @45817
    GIM_Reject,
    // Label 1894: @45818
    GIM_Try, /*On fail goto*//*Label 1935*/ 45856, // Rule ID 56307 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (sext:{ *:[nxv4i64] } VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVSEXT_VF2_M4:{ *:[nxv4i64] } VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56307,
      GIR_Done,
    // Label 1935: @45856
    GIM_Try, /*On fail goto*//*Label 1936*/ 45894, // Rule ID 56308 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (sext:{ *:[nxv4i64] } VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVSEXT_VF2_M4:{ *:[nxv4i64] } VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56308,
      GIR_Done,
    // Label 1936: @45894
    GIM_Try, /*On fail goto*//*Label 1937*/ 45932, // Rule ID 56361 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv4i64] } VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVSEXT_VF4_M4:{ *:[nxv4i64] } VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF4_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56361,
      GIR_Done,
    // Label 1937: @45932
    GIM_Try, /*On fail goto*//*Label 1938*/ 45970, // Rule ID 56362 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv4i64] } VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVSEXT_VF4_M4:{ *:[nxv4i64] } VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF4_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56362,
      GIR_Done,
    // Label 1938: @45970
    GIM_Try, /*On fail goto*//*Label 1939*/ 46008, // Rule ID 56385 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv4i64] } VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVSEXT_VF8_M4:{ *:[nxv4i64] } VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF8_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56385,
      GIR_Done,
    // Label 1939: @46008
    GIM_Try, /*On fail goto*//*Label 1940*/ 46046, // Rule ID 56386 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv4i64] } VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVSEXT_VF8_M4:{ *:[nxv4i64] } VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF8_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56386,
      GIR_Done,
    // Label 1940: @46046
    GIM_Reject,
    // Label 1895: @46047
    GIM_Try, /*On fail goto*//*Label 1941*/ 46114,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1942*/ 46087, // Rule ID 56287 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sext:{ *:[nxv8i16] } VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVSEXT_VF2_M2:{ *:[nxv8i16] } VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56287,
        GIR_Done,
      // Label 1942: @46087
      GIM_Try, /*On fail goto*//*Label 1943*/ 46113, // Rule ID 56288 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sext:{ *:[nxv8i16] } VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVSEXT_VF2_M2:{ *:[nxv8i16] } VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56288,
        GIR_Done,
      // Label 1943: @46113
      GIM_Reject,
    // Label 1941: @46114
    GIM_Reject,
    // Label 1896: @46115
    GIM_Try, /*On fail goto*//*Label 1944*/ 46153, // Rule ID 56299 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (sext:{ *:[nxv8i32] } VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVSEXT_VF2_M4:{ *:[nxv8i32] } VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56299,
      GIR_Done,
    // Label 1944: @46153
    GIM_Try, /*On fail goto*//*Label 1945*/ 46191, // Rule ID 56300 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (sext:{ *:[nxv8i32] } VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVSEXT_VF2_M4:{ *:[nxv8i32] } VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56300,
      GIR_Done,
    // Label 1945: @46191
    GIM_Try, /*On fail goto*//*Label 1946*/ 46229, // Rule ID 56353 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv8i32] } VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVSEXT_VF4_M4:{ *:[nxv8i32] } VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF4_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56353,
      GIR_Done,
    // Label 1946: @46229
    GIM_Try, /*On fail goto*//*Label 1947*/ 46267, // Rule ID 56354 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv8i32] } VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVSEXT_VF4_M4:{ *:[nxv8i32] } VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF4_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56354,
      GIR_Done,
    // Label 1947: @46267
    GIM_Reject,
    // Label 1897: @46268
    GIM_Try, /*On fail goto*//*Label 1948*/ 46306, // Rule ID 56309 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (sext:{ *:[nxv8i64] } VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVSEXT_VF2_M8:{ *:[nxv8i64] } VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56309,
      GIR_Done,
    // Label 1948: @46306
    GIM_Try, /*On fail goto*//*Label 1949*/ 46344, // Rule ID 56310 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (sext:{ *:[nxv8i64] } VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVSEXT_VF2_M8:{ *:[nxv8i64] } VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56310,
      GIR_Done,
    // Label 1949: @46344
    GIM_Try, /*On fail goto*//*Label 1950*/ 46382, // Rule ID 56363 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (sext:{ *:[nxv8i64] } VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVSEXT_VF4_M8:{ *:[nxv8i64] } VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF4_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56363,
      GIR_Done,
    // Label 1950: @46382
    GIM_Try, /*On fail goto*//*Label 1951*/ 46420, // Rule ID 56364 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (sext:{ *:[nxv8i64] } VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVSEXT_VF4_M8:{ *:[nxv8i64] } VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF4_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56364,
      GIR_Done,
    // Label 1951: @46420
    GIM_Try, /*On fail goto*//*Label 1952*/ 46458, // Rule ID 56387 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv8i64] } VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVSEXT_VF8_M8:{ *:[nxv8i64] } VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF8_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56387,
      GIR_Done,
    // Label 1952: @46458
    GIM_Try, /*On fail goto*//*Label 1953*/ 46496, // Rule ID 56388 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sext:{ *:[nxv8i64] } VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVSEXT_VF8_M8:{ *:[nxv8i64] } VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF8_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56388,
      GIR_Done,
    // Label 1953: @46496
    GIM_Reject,
    // Label 1898: @46497
    GIM_Try, /*On fail goto*//*Label 1954*/ 46564,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 1955*/ 46537, // Rule ID 56289 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sext:{ *:[nxv16i16] } VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVSEXT_VF2_M4:{ *:[nxv16i16] } VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56289,
        GIR_Done,
      // Label 1955: @46537
      GIM_Try, /*On fail goto*//*Label 1956*/ 46563, // Rule ID 56290 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sext:{ *:[nxv16i16] } VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVSEXT_VF2_M4:{ *:[nxv16i16] } VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56290,
        GIR_Done,
      // Label 1956: @46563
      GIM_Reject,
    // Label 1954: @46564
    GIM_Reject,
    // Label 1899: @46565
    GIM_Try, /*On fail goto*//*Label 1957*/ 46603, // Rule ID 56301 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (sext:{ *:[nxv16i32] } VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVSEXT_VF2_M8:{ *:[nxv16i32] } VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56301,
      GIR_Done,
    // Label 1957: @46603
    GIM_Try, /*On fail goto*//*Label 1958*/ 46641, // Rule ID 56302 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (sext:{ *:[nxv16i32] } VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVSEXT_VF2_M8:{ *:[nxv16i32] } VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56302,
      GIR_Done,
    // Label 1958: @46641
    GIM_Try, /*On fail goto*//*Label 1959*/ 46679, // Rule ID 56355 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (sext:{ *:[nxv16i32] } VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVSEXT_VF4_M8:{ *:[nxv16i32] } VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF4_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56355,
      GIR_Done,
    // Label 1959: @46679
    GIM_Try, /*On fail goto*//*Label 1960*/ 46717, // Rule ID 56356 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (sext:{ *:[nxv16i32] } VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVSEXT_VF4_M8:{ *:[nxv16i32] } VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF4_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56356,
      GIR_Done,
    // Label 1960: @46717
    GIM_Reject,
    // Label 1900: @46718
    GIM_Try, /*On fail goto*//*Label 1961*/ 46785,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 1962*/ 46758, // Rule ID 56291 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sext:{ *:[nxv32i16] } VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVSEXT_VF2_M8:{ *:[nxv32i16] } VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56291,
        GIR_Done,
      // Label 1962: @46758
      GIM_Try, /*On fail goto*//*Label 1963*/ 46784, // Rule ID 56292 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sext:{ *:[nxv32i16] } VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVSEXT_VF2_M8:{ *:[nxv32i16] } VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSEXT_VF2_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56292,
        GIR_Done,
      // Label 1963: @46784
      GIM_Reject,
    // Label 1961: @46785
    GIM_Reject,
    // Label 1901: @46786
    GIM_Reject,
    // Label 31: @46787
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 30, /*)*//*default:*//*Label 1979*/ 48907,
    /*GILLT_nxv1s16*//*Label 1964*/ 46818,
    /*GILLT_nxv1s32*//*Label 1965*/ 46886,
    /*GILLT_nxv1s64*//*Label 1966*/ 47039, 0, 0,
    /*GILLT_nxv2s16*//*Label 1967*/ 47268,
    /*GILLT_nxv2s32*//*Label 1968*/ 47336,
    /*GILLT_nxv2s64*//*Label 1969*/ 47489, 0, 0,
    /*GILLT_nxv4s16*//*Label 1970*/ 47718,
    /*GILLT_nxv4s32*//*Label 1971*/ 47786,
    /*GILLT_nxv4s64*//*Label 1972*/ 47939, 0, 0,
    /*GILLT_nxv8s16*//*Label 1973*/ 48168,
    /*GILLT_nxv8s32*//*Label 1974*/ 48236,
    /*GILLT_nxv8s64*//*Label 1975*/ 48389, 0, 0,
    /*GILLT_nxv16s16*//*Label 1976*/ 48618,
    /*GILLT_nxv16s32*//*Label 1977*/ 48686, 0, 0,
    /*GILLT_nxv32s16*//*Label 1978*/ 48839,
    // Label 1964: @46818
    GIM_Try, /*On fail goto*//*Label 1980*/ 46885,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1981*/ 46858, // Rule ID 54967 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (zext:{ *:[nxv1i16] } VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVZEXT_VF2_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 54967,
        GIR_Done,
      // Label 1981: @46858
      GIM_Try, /*On fail goto*//*Label 1982*/ 46884, // Rule ID 54968 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (zext:{ *:[nxv1i16] } VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVZEXT_VF2_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 54968,
        GIR_Done,
      // Label 1982: @46884
      GIM_Reject,
    // Label 1980: @46885
    GIM_Reject,
    // Label 1965: @46886
    GIM_Try, /*On fail goto*//*Label 1983*/ 46924, // Rule ID 56245 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv1i32] } VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVZEXT_VF2_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56245,
      GIR_Done,
    // Label 1983: @46924
    GIM_Try, /*On fail goto*//*Label 1984*/ 46962, // Rule ID 56246 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv1i32] } VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVZEXT_VF2_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56246,
      GIR_Done,
    // Label 1984: @46962
    GIM_Try, /*On fail goto*//*Label 1985*/ 47000, // Rule ID 56311 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv1i32] } VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVZEXT_VF4_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56311,
      GIR_Done,
    // Label 1985: @47000
    GIM_Try, /*On fail goto*//*Label 1986*/ 47038, // Rule ID 56312 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv1i32] } VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVZEXT_VF4_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56312,
      GIR_Done,
    // Label 1986: @47038
    GIM_Reject,
    // Label 1966: @47039
    GIM_Try, /*On fail goto*//*Label 1987*/ 47077, // Rule ID 56265 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv1i64] } VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVZEXT_VF2_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56265,
      GIR_Done,
    // Label 1987: @47077
    GIM_Try, /*On fail goto*//*Label 1988*/ 47115, // Rule ID 56266 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv1i64] } VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVZEXT_VF2_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56266,
      GIR_Done,
    // Label 1988: @47115
    GIM_Try, /*On fail goto*//*Label 1989*/ 47153, // Rule ID 56331 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv1i64] } VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVZEXT_VF4_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56331,
      GIR_Done,
    // Label 1989: @47153
    GIM_Try, /*On fail goto*//*Label 1990*/ 47191, // Rule ID 56332 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv1i64] } VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVZEXT_VF4_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56332,
      GIR_Done,
    // Label 1990: @47191
    GIM_Try, /*On fail goto*//*Label 1991*/ 47229, // Rule ID 56365 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv1i64] } VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVZEXT_VF8_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF8_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56365,
      GIR_Done,
    // Label 1991: @47229
    GIM_Try, /*On fail goto*//*Label 1992*/ 47267, // Rule ID 56366 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv1i64] } VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVZEXT_VF8_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF8_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56366,
      GIR_Done,
    // Label 1992: @47267
    GIM_Reject,
    // Label 1967: @47268
    GIM_Try, /*On fail goto*//*Label 1993*/ 47335,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 1994*/ 47308, // Rule ID 56225 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (zext:{ *:[nxv2i16] } VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVZEXT_VF2_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56225,
        GIR_Done,
      // Label 1994: @47308
      GIM_Try, /*On fail goto*//*Label 1995*/ 47334, // Rule ID 56226 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (zext:{ *:[nxv2i16] } VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVZEXT_VF2_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56226,
        GIR_Done,
      // Label 1995: @47334
      GIM_Reject,
    // Label 1993: @47335
    GIM_Reject,
    // Label 1968: @47336
    GIM_Try, /*On fail goto*//*Label 1996*/ 47374, // Rule ID 56249 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv2i32] } VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVZEXT_VF2_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56249,
      GIR_Done,
    // Label 1996: @47374
    GIM_Try, /*On fail goto*//*Label 1997*/ 47412, // Rule ID 56250 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv2i32] } VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVZEXT_VF2_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56250,
      GIR_Done,
    // Label 1997: @47412
    GIM_Try, /*On fail goto*//*Label 1998*/ 47450, // Rule ID 56315 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv2i32] } VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVZEXT_VF4_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56315,
      GIR_Done,
    // Label 1998: @47450
    GIM_Try, /*On fail goto*//*Label 1999*/ 47488, // Rule ID 56316 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv2i32] } VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVZEXT_VF4_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56316,
      GIR_Done,
    // Label 1999: @47488
    GIM_Reject,
    // Label 1969: @47489
    GIM_Try, /*On fail goto*//*Label 2000*/ 47527, // Rule ID 56269 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv2i64] } VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVZEXT_VF2_M2:{ *:[nxv2i64] } VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56269,
      GIR_Done,
    // Label 2000: @47527
    GIM_Try, /*On fail goto*//*Label 2001*/ 47565, // Rule ID 56270 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv2i64] } VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVZEXT_VF2_M2:{ *:[nxv2i64] } VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56270,
      GIR_Done,
    // Label 2001: @47565
    GIM_Try, /*On fail goto*//*Label 2002*/ 47603, // Rule ID 56335 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv2i64] } VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVZEXT_VF4_M2:{ *:[nxv2i64] } VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56335,
      GIR_Done,
    // Label 2002: @47603
    GIM_Try, /*On fail goto*//*Label 2003*/ 47641, // Rule ID 56336 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv2i64] } VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVZEXT_VF4_M2:{ *:[nxv2i64] } VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56336,
      GIR_Done,
    // Label 2003: @47641
    GIM_Try, /*On fail goto*//*Label 2004*/ 47679, // Rule ID 56369 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv2i64] } VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVZEXT_VF8_M2:{ *:[nxv2i64] } VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF8_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56369,
      GIR_Done,
    // Label 2004: @47679
    GIM_Try, /*On fail goto*//*Label 2005*/ 47717, // Rule ID 56370 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv2i64] } VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVZEXT_VF8_M2:{ *:[nxv2i64] } VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF8_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56370,
      GIR_Done,
    // Label 2005: @47717
    GIM_Reject,
    // Label 1970: @47718
    GIM_Try, /*On fail goto*//*Label 2006*/ 47785,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2007*/ 47758, // Rule ID 56229 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (zext:{ *:[nxv4i16] } VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVZEXT_VF2_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56229,
        GIR_Done,
      // Label 2007: @47758
      GIM_Try, /*On fail goto*//*Label 2008*/ 47784, // Rule ID 56230 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (zext:{ *:[nxv4i16] } VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVZEXT_VF2_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56230,
        GIR_Done,
      // Label 2008: @47784
      GIM_Reject,
    // Label 2006: @47785
    GIM_Reject,
    // Label 1971: @47786
    GIM_Try, /*On fail goto*//*Label 2009*/ 47824, // Rule ID 56253 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv4i32] } VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVZEXT_VF2_M2:{ *:[nxv4i32] } VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56253,
      GIR_Done,
    // Label 2009: @47824
    GIM_Try, /*On fail goto*//*Label 2010*/ 47862, // Rule ID 56254 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv4i32] } VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVZEXT_VF2_M2:{ *:[nxv4i32] } VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56254,
      GIR_Done,
    // Label 2010: @47862
    GIM_Try, /*On fail goto*//*Label 2011*/ 47900, // Rule ID 56319 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv4i32] } VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVZEXT_VF4_M2:{ *:[nxv4i32] } VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56319,
      GIR_Done,
    // Label 2011: @47900
    GIM_Try, /*On fail goto*//*Label 2012*/ 47938, // Rule ID 56320 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv4i32] } VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVZEXT_VF4_M2:{ *:[nxv4i32] } VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56320,
      GIR_Done,
    // Label 2012: @47938
    GIM_Reject,
    // Label 1972: @47939
    GIM_Try, /*On fail goto*//*Label 2013*/ 47977, // Rule ID 56273 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (zext:{ *:[nxv4i64] } VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVZEXT_VF2_M4:{ *:[nxv4i64] } VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56273,
      GIR_Done,
    // Label 2013: @47977
    GIM_Try, /*On fail goto*//*Label 2014*/ 48015, // Rule ID 56274 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (zext:{ *:[nxv4i64] } VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVZEXT_VF2_M4:{ *:[nxv4i64] } VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56274,
      GIR_Done,
    // Label 2014: @48015
    GIM_Try, /*On fail goto*//*Label 2015*/ 48053, // Rule ID 56339 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv4i64] } VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVZEXT_VF4_M4:{ *:[nxv4i64] } VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56339,
      GIR_Done,
    // Label 2015: @48053
    GIM_Try, /*On fail goto*//*Label 2016*/ 48091, // Rule ID 56340 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv4i64] } VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVZEXT_VF4_M4:{ *:[nxv4i64] } VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56340,
      GIR_Done,
    // Label 2016: @48091
    GIM_Try, /*On fail goto*//*Label 2017*/ 48129, // Rule ID 56373 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv4i64] } VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVZEXT_VF8_M4:{ *:[nxv4i64] } VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF8_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56373,
      GIR_Done,
    // Label 2017: @48129
    GIM_Try, /*On fail goto*//*Label 2018*/ 48167, // Rule ID 56374 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv4i64] } VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVZEXT_VF8_M4:{ *:[nxv4i64] } VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF8_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56374,
      GIR_Done,
    // Label 2018: @48167
    GIM_Reject,
    // Label 1973: @48168
    GIM_Try, /*On fail goto*//*Label 2019*/ 48235,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2020*/ 48208, // Rule ID 56233 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (zext:{ *:[nxv8i16] } VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVZEXT_VF2_M2:{ *:[nxv8i16] } VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56233,
        GIR_Done,
      // Label 2020: @48208
      GIM_Try, /*On fail goto*//*Label 2021*/ 48234, // Rule ID 56234 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (zext:{ *:[nxv8i16] } VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVZEXT_VF2_M2:{ *:[nxv8i16] } VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56234,
        GIR_Done,
      // Label 2021: @48234
      GIM_Reject,
    // Label 2019: @48235
    GIM_Reject,
    // Label 1974: @48236
    GIM_Try, /*On fail goto*//*Label 2022*/ 48274, // Rule ID 56257 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (zext:{ *:[nxv8i32] } VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVZEXT_VF2_M4:{ *:[nxv8i32] } VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56257,
      GIR_Done,
    // Label 2022: @48274
    GIM_Try, /*On fail goto*//*Label 2023*/ 48312, // Rule ID 56258 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (zext:{ *:[nxv8i32] } VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVZEXT_VF2_M4:{ *:[nxv8i32] } VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56258,
      GIR_Done,
    // Label 2023: @48312
    GIM_Try, /*On fail goto*//*Label 2024*/ 48350, // Rule ID 56323 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv8i32] } VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVZEXT_VF4_M4:{ *:[nxv8i32] } VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56323,
      GIR_Done,
    // Label 2024: @48350
    GIM_Try, /*On fail goto*//*Label 2025*/ 48388, // Rule ID 56324 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv8i32] } VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVZEXT_VF4_M4:{ *:[nxv8i32] } VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56324,
      GIR_Done,
    // Label 2025: @48388
    GIM_Reject,
    // Label 1975: @48389
    GIM_Try, /*On fail goto*//*Label 2026*/ 48427, // Rule ID 56277 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (zext:{ *:[nxv8i64] } VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVZEXT_VF2_M8:{ *:[nxv8i64] } VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56277,
      GIR_Done,
    // Label 2026: @48427
    GIM_Try, /*On fail goto*//*Label 2027*/ 48465, // Rule ID 56278 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (zext:{ *:[nxv8i64] } VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVZEXT_VF2_M8:{ *:[nxv8i64] } VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56278,
      GIR_Done,
    // Label 2027: @48465
    GIM_Try, /*On fail goto*//*Label 2028*/ 48503, // Rule ID 56343 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (zext:{ *:[nxv8i64] } VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVZEXT_VF4_M8:{ *:[nxv8i64] } VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56343,
      GIR_Done,
    // Label 2028: @48503
    GIM_Try, /*On fail goto*//*Label 2029*/ 48541, // Rule ID 56344 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (zext:{ *:[nxv8i64] } VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVZEXT_VF4_M8:{ *:[nxv8i64] } VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56344,
      GIR_Done,
    // Label 2029: @48541
    GIM_Try, /*On fail goto*//*Label 2030*/ 48579, // Rule ID 56377 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv8i64] } VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVZEXT_VF8_M8:{ *:[nxv8i64] } VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF8_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56377,
      GIR_Done,
    // Label 2030: @48579
    GIM_Try, /*On fail goto*//*Label 2031*/ 48617, // Rule ID 56378 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (zext:{ *:[nxv8i64] } VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVZEXT_VF8_M8:{ *:[nxv8i64] } VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF8_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56378,
      GIR_Done,
    // Label 2031: @48617
    GIM_Reject,
    // Label 1976: @48618
    GIM_Try, /*On fail goto*//*Label 2032*/ 48685,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 2033*/ 48658, // Rule ID 56237 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (zext:{ *:[nxv16i16] } VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVZEXT_VF2_M4:{ *:[nxv16i16] } VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56237,
        GIR_Done,
      // Label 2033: @48658
      GIM_Try, /*On fail goto*//*Label 2034*/ 48684, // Rule ID 56238 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (zext:{ *:[nxv16i16] } VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVZEXT_VF2_M4:{ *:[nxv16i16] } VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56238,
        GIR_Done,
      // Label 2034: @48684
      GIM_Reject,
    // Label 2032: @48685
    GIM_Reject,
    // Label 1977: @48686
    GIM_Try, /*On fail goto*//*Label 2035*/ 48724, // Rule ID 56261 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (zext:{ *:[nxv16i32] } VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVZEXT_VF2_M8:{ *:[nxv16i32] } VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56261,
      GIR_Done,
    // Label 2035: @48724
    GIM_Try, /*On fail goto*//*Label 2036*/ 48762, // Rule ID 56262 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (zext:{ *:[nxv16i32] } VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVZEXT_VF2_M8:{ *:[nxv16i32] } VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56262,
      GIR_Done,
    // Label 2036: @48762
    GIM_Try, /*On fail goto*//*Label 2037*/ 48800, // Rule ID 56327 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (zext:{ *:[nxv16i32] } VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVZEXT_VF4_M8:{ *:[nxv16i32] } VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56327,
      GIR_Done,
    // Label 2037: @48800
    GIM_Try, /*On fail goto*//*Label 2038*/ 48838, // Rule ID 56328 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (zext:{ *:[nxv16i32] } VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVZEXT_VF4_M8:{ *:[nxv16i32] } VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF4_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 56328,
      GIR_Done,
    // Label 2038: @48838
    GIM_Reject,
    // Label 1978: @48839
    GIM_Try, /*On fail goto*//*Label 2039*/ 48906,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 2040*/ 48879, // Rule ID 56241 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (zext:{ *:[nxv32i16] } VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVZEXT_VF2_M8:{ *:[nxv32i16] } VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56241,
        GIR_Done,
      // Label 2040: @48879
      GIM_Try, /*On fail goto*//*Label 2041*/ 48905, // Rule ID 56242 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (zext:{ *:[nxv32i16] } VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVZEXT_VF2_M8:{ *:[nxv32i16] } VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVZEXT_VF2_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56242,
        GIR_Done,
      // Label 2041: @48905
      GIM_Reject,
    // Label 2039: @48906
    GIM_Reject,
    // Label 1979: @48907
    GIM_Reject,
    // Label 32: @48908
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 32, /*)*//*default:*//*Label 2066*/ 50956,
    /*GILLT_s32*//*Label 2042*/ 48945,
    /*GILLT_s64*//*Label 2043*/ 48995, 0,
    /*GILLT_nxv1s8*//*Label 2044*/ 49108,
    /*GILLT_nxv1s16*//*Label 2045*/ 49192,
    /*GILLT_nxv1s32*//*Label 2046*/ 49276,
    /*GILLT_nxv1s64*//*Label 2047*/ 49360, 0,
    /*GILLT_nxv2s8*//*Label 2048*/ 49444,
    /*GILLT_nxv2s16*//*Label 2049*/ 49528,
    /*GILLT_nxv2s32*//*Label 2050*/ 49612,
    /*GILLT_nxv2s64*//*Label 2051*/ 49696, 0,
    /*GILLT_nxv4s8*//*Label 2052*/ 49780,
    /*GILLT_nxv4s16*//*Label 2053*/ 49864,
    /*GILLT_nxv4s32*//*Label 2054*/ 49948,
    /*GILLT_nxv4s64*//*Label 2055*/ 50032, 0,
    /*GILLT_nxv8s8*//*Label 2056*/ 50116,
    /*GILLT_nxv8s16*//*Label 2057*/ 50200,
    /*GILLT_nxv8s32*//*Label 2058*/ 50284,
    /*GILLT_nxv8s64*//*Label 2059*/ 50368, 0,
    /*GILLT_nxv16s8*//*Label 2060*/ 50452,
    /*GILLT_nxv16s16*//*Label 2061*/ 50536,
    /*GILLT_nxv16s32*//*Label 2062*/ 50620, 0,
    /*GILLT_nxv32s8*//*Label 2063*/ 50704,
    /*GILLT_nxv32s16*//*Label 2064*/ 50788, 0,
    /*GILLT_nxv64s8*//*Label 2065*/ 50872,
    // Label 2042: @48945
    GIM_Try, /*On fail goto*//*Label 2067*/ 48994, // Rule ID 60002 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
      GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen,
      // MIs[1] Operand 1
      // No operand predicates
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      // (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$imm)  =>  (SLLI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$imm)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLLI,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 60002,
      GIR_Done,
    // Label 2067: @48994
    GIM_Reject,
    // Label 2043: @48995
    GIM_Try, /*On fail goto*//*Label 2068*/ 49107,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2069*/ 49069, // Rule ID 65589 //
        GIM_CheckFeatures, GIFBS_HasStdExtZba_IsRV64,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294967295,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_uimm5,
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (shl:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$shamt)  =>  (SLLI_UW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$shamt)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLLI_UW,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shamt
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65589,
        GIR_Done,
      // Label 2069: @49069
      GIM_Try, /*On fail goto*//*Label 2070*/ 49106, // Rule ID 60001 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen,
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$imm)  =>  (SLLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$imm)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLLI,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60001,
        GIR_Done,
      // Label 2070: @49106
      GIM_Reject,
    // Label 2068: @49107
    GIM_Reject,
    // Label 2044: @49108
    GIM_Try, /*On fail goto*//*Label 2071*/ 49191,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2072*/ 49160, // Rule ID 56785 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVSLL_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56785,
        GIR_Done,
      // Label 2072: @49160
      GIM_Try, /*On fail goto*//*Label 2073*/ 49190, // Rule ID 56786 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVSLL_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56786,
        GIR_Done,
      // Label 2073: @49190
      GIM_Reject,
    // Label 2071: @49191
    GIM_Reject,
    // Label 2045: @49192
    GIM_Try, /*On fail goto*//*Label 2074*/ 49275,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2075*/ 49244, // Rule ID 56797 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVSLL_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56797,
        GIR_Done,
      // Label 2075: @49244
      GIM_Try, /*On fail goto*//*Label 2076*/ 49274, // Rule ID 56798 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVSLL_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56798,
        GIR_Done,
      // Label 2076: @49274
      GIM_Reject,
    // Label 2074: @49275
    GIM_Reject,
    // Label 2046: @49276
    GIM_Try, /*On fail goto*//*Label 2077*/ 49359,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2078*/ 49328, // Rule ID 56805 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVSLL_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56805,
        GIR_Done,
      // Label 2078: @49328
      GIM_Try, /*On fail goto*//*Label 2079*/ 49358, // Rule ID 56806 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVSLL_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56806,
        GIR_Done,
      // Label 2079: @49358
      GIM_Reject,
    // Label 2077: @49359
    GIM_Reject,
    // Label 2047: @49360
    GIM_Try, /*On fail goto*//*Label 2080*/ 49443,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2081*/ 49412, // Rule ID 56821 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVSLL_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56821,
        GIR_Done,
      // Label 2081: @49412
      GIM_Try, /*On fail goto*//*Label 2082*/ 49442, // Rule ID 56822 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVSLL_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56822,
        GIR_Done,
      // Label 2082: @49442
      GIM_Reject,
    // Label 2080: @49443
    GIM_Reject,
    // Label 2048: @49444
    GIM_Try, /*On fail goto*//*Label 2083*/ 49527,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2084*/ 49496, // Rule ID 56789 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVSLL_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56789,
        GIR_Done,
      // Label 2084: @49496
      GIM_Try, /*On fail goto*//*Label 2085*/ 49526, // Rule ID 56790 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVSLL_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56790,
        GIR_Done,
      // Label 2085: @49526
      GIM_Reject,
    // Label 2083: @49527
    GIM_Reject,
    // Label 2049: @49528
    GIM_Try, /*On fail goto*//*Label 2086*/ 49611,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2087*/ 49580, // Rule ID 56801 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVSLL_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56801,
        GIR_Done,
      // Label 2087: @49580
      GIM_Try, /*On fail goto*//*Label 2088*/ 49610, // Rule ID 56802 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVSLL_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56802,
        GIR_Done,
      // Label 2088: @49610
      GIM_Reject,
    // Label 2086: @49611
    GIM_Reject,
    // Label 2050: @49612
    GIM_Try, /*On fail goto*//*Label 2089*/ 49695,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2090*/ 49664, // Rule ID 56817 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVSLL_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56817,
        GIR_Done,
      // Label 2090: @49664
      GIM_Try, /*On fail goto*//*Label 2091*/ 49694, // Rule ID 56818 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVSLL_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56818,
        GIR_Done,
      // Label 2091: @49694
      GIM_Reject,
    // Label 2089: @49695
    GIM_Reject,
    // Label 2051: @49696
    GIM_Try, /*On fail goto*//*Label 2092*/ 49779,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 2093*/ 49748, // Rule ID 56861 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVSLL_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56861,
        GIR_Done,
      // Label 2093: @49748
      GIM_Try, /*On fail goto*//*Label 2094*/ 49778, // Rule ID 56862 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVSLL_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56862,
        GIR_Done,
      // Label 2094: @49778
      GIM_Reject,
    // Label 2092: @49779
    GIM_Reject,
    // Label 2052: @49780
    GIM_Try, /*On fail goto*//*Label 2095*/ 49863,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2096*/ 49832, // Rule ID 56793 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVSLL_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56793,
        GIR_Done,
      // Label 2096: @49832
      GIM_Try, /*On fail goto*//*Label 2097*/ 49862, // Rule ID 56794 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVSLL_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56794,
        GIR_Done,
      // Label 2097: @49862
      GIM_Reject,
    // Label 2095: @49863
    GIM_Reject,
    // Label 2053: @49864
    GIM_Try, /*On fail goto*//*Label 2098*/ 49947,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2099*/ 49916, // Rule ID 56813 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVSLL_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56813,
        GIR_Done,
      // Label 2099: @49916
      GIM_Try, /*On fail goto*//*Label 2100*/ 49946, // Rule ID 56814 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVSLL_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56814,
        GIR_Done,
      // Label 2100: @49946
      GIM_Reject,
    // Label 2098: @49947
    GIM_Reject,
    // Label 2054: @49948
    GIM_Try, /*On fail goto*//*Label 2101*/ 50031,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 2102*/ 50000, // Rule ID 56849 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVSLL_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56849,
        GIR_Done,
      // Label 2102: @50000
      GIM_Try, /*On fail goto*//*Label 2103*/ 50030, // Rule ID 56850 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVSLL_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56850,
        GIR_Done,
      // Label 2103: @50030
      GIM_Reject,
    // Label 2101: @50031
    GIM_Reject,
    // Label 2055: @50032
    GIM_Try, /*On fail goto*//*Label 2104*/ 50115,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 2105*/ 50084, // Rule ID 56865 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVSLL_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56865,
        GIR_Done,
      // Label 2105: @50084
      GIM_Try, /*On fail goto*//*Label 2106*/ 50114, // Rule ID 56866 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVSLL_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56866,
        GIR_Done,
      // Label 2106: @50114
      GIM_Reject,
    // Label 2104: @50115
    GIM_Reject,
    // Label 2056: @50116
    GIM_Try, /*On fail goto*//*Label 2107*/ 50199,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2108*/ 50168, // Rule ID 56809 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVSLL_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56809,
        GIR_Done,
      // Label 2108: @50168
      GIM_Try, /*On fail goto*//*Label 2109*/ 50198, // Rule ID 56810 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVSLL_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56810,
        GIR_Done,
      // Label 2109: @50198
      GIM_Reject,
    // Label 2107: @50199
    GIM_Reject,
    // Label 2057: @50200
    GIM_Try, /*On fail goto*//*Label 2110*/ 50283,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 2111*/ 50252, // Rule ID 56837 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVSLL_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56837,
        GIR_Done,
      // Label 2111: @50252
      GIM_Try, /*On fail goto*//*Label 2112*/ 50282, // Rule ID 56838 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVSLL_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56838,
        GIR_Done,
      // Label 2112: @50282
      GIM_Reject,
    // Label 2110: @50283
    GIM_Reject,
    // Label 2058: @50284
    GIM_Try, /*On fail goto*//*Label 2113*/ 50367,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 2114*/ 50336, // Rule ID 56853 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVSLL_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56853,
        GIR_Done,
      // Label 2114: @50336
      GIM_Try, /*On fail goto*//*Label 2115*/ 50366, // Rule ID 56854 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVSLL_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56854,
        GIR_Done,
      // Label 2115: @50366
      GIM_Reject,
    // Label 2113: @50367
    GIM_Reject,
    // Label 2059: @50368
    GIM_Try, /*On fail goto*//*Label 2116*/ 50451,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 2117*/ 50420, // Rule ID 56869 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVSLL_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56869,
        GIR_Done,
      // Label 2117: @50420
      GIM_Try, /*On fail goto*//*Label 2118*/ 50450, // Rule ID 56870 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVSLL_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56870,
        GIR_Done,
      // Label 2118: @50450
      GIM_Reject,
    // Label 2116: @50451
    GIM_Reject,
    // Label 2060: @50452
    GIM_Try, /*On fail goto*//*Label 2119*/ 50535,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 2120*/ 50504, // Rule ID 56825 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVSLL_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56825,
        GIR_Done,
      // Label 2120: @50504
      GIM_Try, /*On fail goto*//*Label 2121*/ 50534, // Rule ID 56826 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVSLL_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56826,
        GIR_Done,
      // Label 2121: @50534
      GIM_Reject,
    // Label 2119: @50535
    GIM_Reject,
    // Label 2061: @50536
    GIM_Try, /*On fail goto*//*Label 2122*/ 50619,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 2123*/ 50588, // Rule ID 56841 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVSLL_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56841,
        GIR_Done,
      // Label 2123: @50588
      GIM_Try, /*On fail goto*//*Label 2124*/ 50618, // Rule ID 56842 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVSLL_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56842,
        GIR_Done,
      // Label 2124: @50618
      GIM_Reject,
    // Label 2122: @50619
    GIM_Reject,
    // Label 2062: @50620
    GIM_Try, /*On fail goto*//*Label 2125*/ 50703,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 2126*/ 50672, // Rule ID 56857 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVSLL_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56857,
        GIR_Done,
      // Label 2126: @50672
      GIM_Try, /*On fail goto*//*Label 2127*/ 50702, // Rule ID 56858 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVSLL_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56858,
        GIR_Done,
      // Label 2127: @50702
      GIM_Reject,
    // Label 2125: @50703
    GIM_Reject,
    // Label 2063: @50704
    GIM_Try, /*On fail goto*//*Label 2128*/ 50787,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 2129*/ 50756, // Rule ID 56829 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVSLL_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56829,
        GIR_Done,
      // Label 2129: @50756
      GIM_Try, /*On fail goto*//*Label 2130*/ 50786, // Rule ID 56830 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVSLL_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56830,
        GIR_Done,
      // Label 2130: @50786
      GIM_Reject,
    // Label 2128: @50787
    GIM_Reject,
    // Label 2064: @50788
    GIM_Try, /*On fail goto*//*Label 2131*/ 50871,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 2132*/ 50840, // Rule ID 56845 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVSLL_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56845,
        GIR_Done,
      // Label 2132: @50840
      GIM_Try, /*On fail goto*//*Label 2133*/ 50870, // Rule ID 56846 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVSLL_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56846,
        GIR_Done,
      // Label 2133: @50870
      GIM_Reject,
    // Label 2131: @50871
    GIM_Reject,
    // Label 2065: @50872
    GIM_Try, /*On fail goto*//*Label 2134*/ 50955,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv64s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 2135*/ 50924, // Rule ID 56833 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVSLL_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56833,
        GIR_Done,
      // Label 2135: @50924
      GIM_Try, /*On fail goto*//*Label 2136*/ 50954, // Rule ID 56834 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (shl:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVSLL_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSLL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56834,
        GIR_Done,
      // Label 2136: @50954
      GIM_Reject,
    // Label 2134: @50955
    GIM_Reject,
    // Label 2066: @50956
    GIM_Reject,
    // Label 33: @50957
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 32, /*)*//*default:*//*Label 2161*/ 53005,
    /*GILLT_s32*//*Label 2137*/ 50994,
    /*GILLT_s64*//*Label 2138*/ 51044, 0,
    /*GILLT_nxv1s8*//*Label 2139*/ 51157,
    /*GILLT_nxv1s16*//*Label 2140*/ 51241,
    /*GILLT_nxv1s32*//*Label 2141*/ 51325,
    /*GILLT_nxv1s64*//*Label 2142*/ 51409, 0,
    /*GILLT_nxv2s8*//*Label 2143*/ 51493,
    /*GILLT_nxv2s16*//*Label 2144*/ 51577,
    /*GILLT_nxv2s32*//*Label 2145*/ 51661,
    /*GILLT_nxv2s64*//*Label 2146*/ 51745, 0,
    /*GILLT_nxv4s8*//*Label 2147*/ 51829,
    /*GILLT_nxv4s16*//*Label 2148*/ 51913,
    /*GILLT_nxv4s32*//*Label 2149*/ 51997,
    /*GILLT_nxv4s64*//*Label 2150*/ 52081, 0,
    /*GILLT_nxv8s8*//*Label 2151*/ 52165,
    /*GILLT_nxv8s16*//*Label 2152*/ 52249,
    /*GILLT_nxv8s32*//*Label 2153*/ 52333,
    /*GILLT_nxv8s64*//*Label 2154*/ 52417, 0,
    /*GILLT_nxv16s8*//*Label 2155*/ 52501,
    /*GILLT_nxv16s16*//*Label 2156*/ 52585,
    /*GILLT_nxv16s32*//*Label 2157*/ 52669, 0,
    /*GILLT_nxv32s8*//*Label 2158*/ 52753,
    /*GILLT_nxv32s16*//*Label 2159*/ 52837, 0,
    /*GILLT_nxv64s8*//*Label 2160*/ 52921,
    // Label 2137: @50994
    GIM_Try, /*On fail goto*//*Label 2162*/ 51043, // Rule ID 60024 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
      GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen,
      // MIs[1] Operand 1
      // No operand predicates
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      // (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$imm)  =>  (SRLI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$imm)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRLI,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 60024,
      GIR_Done,
    // Label 2162: @51043
    GIM_Reject,
    // Label 2138: @51044
    GIM_Try, /*On fail goto*//*Label 2163*/ 51156,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2164*/ 51118, // Rule ID 62299 //
        GIM_CheckFeatures, GIFBS_IsRV64,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 4294967295,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
        GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_uimm5,
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (srl:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$shamt)  =>  (SRLIW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$shamt)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRLIW,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shamt
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62299,
        GIR_Done,
      // Label 2164: @51118
      GIM_Try, /*On fail goto*//*Label 2165*/ 51155, // Rule ID 60023 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen,
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (srl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$imm)  =>  (SRLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$imm)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRLI,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60023,
        GIR_Done,
      // Label 2165: @51155
      GIM_Reject,
    // Label 2163: @51156
    GIM_Reject,
    // Label 2139: @51157
    GIM_Try, /*On fail goto*//*Label 2166*/ 51240,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2167*/ 51209, // Rule ID 56917 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVSRL_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56917,
        GIR_Done,
      // Label 2167: @51209
      GIM_Try, /*On fail goto*//*Label 2168*/ 51239, // Rule ID 56918 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVSRL_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56918,
        GIR_Done,
      // Label 2168: @51239
      GIM_Reject,
    // Label 2166: @51240
    GIM_Reject,
    // Label 2140: @51241
    GIM_Try, /*On fail goto*//*Label 2169*/ 51324,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2170*/ 51293, // Rule ID 56929 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVSRL_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56929,
        GIR_Done,
      // Label 2170: @51293
      GIM_Try, /*On fail goto*//*Label 2171*/ 51323, // Rule ID 56930 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVSRL_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56930,
        GIR_Done,
      // Label 2171: @51323
      GIM_Reject,
    // Label 2169: @51324
    GIM_Reject,
    // Label 2141: @51325
    GIM_Try, /*On fail goto*//*Label 2172*/ 51408,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2173*/ 51377, // Rule ID 56937 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVSRL_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56937,
        GIR_Done,
      // Label 2173: @51377
      GIM_Try, /*On fail goto*//*Label 2174*/ 51407, // Rule ID 56938 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVSRL_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56938,
        GIR_Done,
      // Label 2174: @51407
      GIM_Reject,
    // Label 2172: @51408
    GIM_Reject,
    // Label 2142: @51409
    GIM_Try, /*On fail goto*//*Label 2175*/ 51492,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2176*/ 51461, // Rule ID 56953 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVSRL_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56953,
        GIR_Done,
      // Label 2176: @51461
      GIM_Try, /*On fail goto*//*Label 2177*/ 51491, // Rule ID 56954 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVSRL_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56954,
        GIR_Done,
      // Label 2177: @51491
      GIM_Reject,
    // Label 2175: @51492
    GIM_Reject,
    // Label 2143: @51493
    GIM_Try, /*On fail goto*//*Label 2178*/ 51576,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2179*/ 51545, // Rule ID 56921 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVSRL_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56921,
        GIR_Done,
      // Label 2179: @51545
      GIM_Try, /*On fail goto*//*Label 2180*/ 51575, // Rule ID 56922 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVSRL_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56922,
        GIR_Done,
      // Label 2180: @51575
      GIM_Reject,
    // Label 2178: @51576
    GIM_Reject,
    // Label 2144: @51577
    GIM_Try, /*On fail goto*//*Label 2181*/ 51660,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2182*/ 51629, // Rule ID 56933 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVSRL_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56933,
        GIR_Done,
      // Label 2182: @51629
      GIM_Try, /*On fail goto*//*Label 2183*/ 51659, // Rule ID 56934 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVSRL_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56934,
        GIR_Done,
      // Label 2183: @51659
      GIM_Reject,
    // Label 2181: @51660
    GIM_Reject,
    // Label 2145: @51661
    GIM_Try, /*On fail goto*//*Label 2184*/ 51744,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2185*/ 51713, // Rule ID 56949 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVSRL_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56949,
        GIR_Done,
      // Label 2185: @51713
      GIM_Try, /*On fail goto*//*Label 2186*/ 51743, // Rule ID 56950 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVSRL_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56950,
        GIR_Done,
      // Label 2186: @51743
      GIM_Reject,
    // Label 2184: @51744
    GIM_Reject,
    // Label 2146: @51745
    GIM_Try, /*On fail goto*//*Label 2187*/ 51828,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 2188*/ 51797, // Rule ID 56993 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVSRL_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56993,
        GIR_Done,
      // Label 2188: @51797
      GIM_Try, /*On fail goto*//*Label 2189*/ 51827, // Rule ID 56994 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVSRL_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56994,
        GIR_Done,
      // Label 2189: @51827
      GIM_Reject,
    // Label 2187: @51828
    GIM_Reject,
    // Label 2147: @51829
    GIM_Try, /*On fail goto*//*Label 2190*/ 51912,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2191*/ 51881, // Rule ID 56925 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVSRL_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56925,
        GIR_Done,
      // Label 2191: @51881
      GIM_Try, /*On fail goto*//*Label 2192*/ 51911, // Rule ID 56926 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVSRL_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56926,
        GIR_Done,
      // Label 2192: @51911
      GIM_Reject,
    // Label 2190: @51912
    GIM_Reject,
    // Label 2148: @51913
    GIM_Try, /*On fail goto*//*Label 2193*/ 51996,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2194*/ 51965, // Rule ID 56945 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVSRL_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56945,
        GIR_Done,
      // Label 2194: @51965
      GIM_Try, /*On fail goto*//*Label 2195*/ 51995, // Rule ID 56946 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVSRL_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56946,
        GIR_Done,
      // Label 2195: @51995
      GIM_Reject,
    // Label 2193: @51996
    GIM_Reject,
    // Label 2149: @51997
    GIM_Try, /*On fail goto*//*Label 2196*/ 52080,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 2197*/ 52049, // Rule ID 56981 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVSRL_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56981,
        GIR_Done,
      // Label 2197: @52049
      GIM_Try, /*On fail goto*//*Label 2198*/ 52079, // Rule ID 56982 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVSRL_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56982,
        GIR_Done,
      // Label 2198: @52079
      GIM_Reject,
    // Label 2196: @52080
    GIM_Reject,
    // Label 2150: @52081
    GIM_Try, /*On fail goto*//*Label 2199*/ 52164,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 2200*/ 52133, // Rule ID 56997 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVSRL_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56997,
        GIR_Done,
      // Label 2200: @52133
      GIM_Try, /*On fail goto*//*Label 2201*/ 52163, // Rule ID 56998 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVSRL_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56998,
        GIR_Done,
      // Label 2201: @52163
      GIM_Reject,
    // Label 2199: @52164
    GIM_Reject,
    // Label 2151: @52165
    GIM_Try, /*On fail goto*//*Label 2202*/ 52248,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2203*/ 52217, // Rule ID 56941 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVSRL_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56941,
        GIR_Done,
      // Label 2203: @52217
      GIM_Try, /*On fail goto*//*Label 2204*/ 52247, // Rule ID 56942 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVSRL_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56942,
        GIR_Done,
      // Label 2204: @52247
      GIM_Reject,
    // Label 2202: @52248
    GIM_Reject,
    // Label 2152: @52249
    GIM_Try, /*On fail goto*//*Label 2205*/ 52332,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 2206*/ 52301, // Rule ID 56969 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVSRL_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56969,
        GIR_Done,
      // Label 2206: @52301
      GIM_Try, /*On fail goto*//*Label 2207*/ 52331, // Rule ID 56970 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVSRL_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56970,
        GIR_Done,
      // Label 2207: @52331
      GIM_Reject,
    // Label 2205: @52332
    GIM_Reject,
    // Label 2153: @52333
    GIM_Try, /*On fail goto*//*Label 2208*/ 52416,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 2209*/ 52385, // Rule ID 56985 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVSRL_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56985,
        GIR_Done,
      // Label 2209: @52385
      GIM_Try, /*On fail goto*//*Label 2210*/ 52415, // Rule ID 56986 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVSRL_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56986,
        GIR_Done,
      // Label 2210: @52415
      GIM_Reject,
    // Label 2208: @52416
    GIM_Reject,
    // Label 2154: @52417
    GIM_Try, /*On fail goto*//*Label 2211*/ 52500,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 2212*/ 52469, // Rule ID 57001 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVSRL_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57001,
        GIR_Done,
      // Label 2212: @52469
      GIM_Try, /*On fail goto*//*Label 2213*/ 52499, // Rule ID 57002 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVSRL_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57002,
        GIR_Done,
      // Label 2213: @52499
      GIM_Reject,
    // Label 2211: @52500
    GIM_Reject,
    // Label 2155: @52501
    GIM_Try, /*On fail goto*//*Label 2214*/ 52584,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 2215*/ 52553, // Rule ID 56957 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVSRL_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56957,
        GIR_Done,
      // Label 2215: @52553
      GIM_Try, /*On fail goto*//*Label 2216*/ 52583, // Rule ID 56958 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVSRL_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56958,
        GIR_Done,
      // Label 2216: @52583
      GIM_Reject,
    // Label 2214: @52584
    GIM_Reject,
    // Label 2156: @52585
    GIM_Try, /*On fail goto*//*Label 2217*/ 52668,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 2218*/ 52637, // Rule ID 56973 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVSRL_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56973,
        GIR_Done,
      // Label 2218: @52637
      GIM_Try, /*On fail goto*//*Label 2219*/ 52667, // Rule ID 56974 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVSRL_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56974,
        GIR_Done,
      // Label 2219: @52667
      GIM_Reject,
    // Label 2217: @52668
    GIM_Reject,
    // Label 2157: @52669
    GIM_Try, /*On fail goto*//*Label 2220*/ 52752,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 2221*/ 52721, // Rule ID 56989 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVSRL_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56989,
        GIR_Done,
      // Label 2221: @52721
      GIM_Try, /*On fail goto*//*Label 2222*/ 52751, // Rule ID 56990 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVSRL_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56990,
        GIR_Done,
      // Label 2222: @52751
      GIM_Reject,
    // Label 2220: @52752
    GIM_Reject,
    // Label 2158: @52753
    GIM_Try, /*On fail goto*//*Label 2223*/ 52836,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 2224*/ 52805, // Rule ID 56961 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVSRL_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56961,
        GIR_Done,
      // Label 2224: @52805
      GIM_Try, /*On fail goto*//*Label 2225*/ 52835, // Rule ID 56962 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVSRL_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56962,
        GIR_Done,
      // Label 2225: @52835
      GIM_Reject,
    // Label 2223: @52836
    GIM_Reject,
    // Label 2159: @52837
    GIM_Try, /*On fail goto*//*Label 2226*/ 52920,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 2227*/ 52889, // Rule ID 56977 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVSRL_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56977,
        GIR_Done,
      // Label 2227: @52889
      GIM_Try, /*On fail goto*//*Label 2228*/ 52919, // Rule ID 56978 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVSRL_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56978,
        GIR_Done,
      // Label 2228: @52919
      GIM_Reject,
    // Label 2226: @52920
    GIM_Reject,
    // Label 2160: @52921
    GIM_Try, /*On fail goto*//*Label 2229*/ 53004,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv64s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 2230*/ 52973, // Rule ID 56965 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVSRL_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56965,
        GIR_Done,
      // Label 2230: @52973
      GIM_Try, /*On fail goto*//*Label 2231*/ 53003, // Rule ID 56966 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (srl:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVSRL_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56966,
        GIR_Done,
      // Label 2231: @53003
      GIM_Reject,
    // Label 2229: @53004
    GIM_Reject,
    // Label 2161: @53005
    GIM_Reject,
    // Label 34: @53006
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 32, /*)*//*default:*//*Label 2256*/ 54991,
    /*GILLT_s32*//*Label 2232*/ 53043,
    /*GILLT_s64*//*Label 2233*/ 53093, 0,
    /*GILLT_nxv1s8*//*Label 2234*/ 53143,
    /*GILLT_nxv1s16*//*Label 2235*/ 53227,
    /*GILLT_nxv1s32*//*Label 2236*/ 53311,
    /*GILLT_nxv1s64*//*Label 2237*/ 53395, 0,
    /*GILLT_nxv2s8*//*Label 2238*/ 53479,
    /*GILLT_nxv2s16*//*Label 2239*/ 53563,
    /*GILLT_nxv2s32*//*Label 2240*/ 53647,
    /*GILLT_nxv2s64*//*Label 2241*/ 53731, 0,
    /*GILLT_nxv4s8*//*Label 2242*/ 53815,
    /*GILLT_nxv4s16*//*Label 2243*/ 53899,
    /*GILLT_nxv4s32*//*Label 2244*/ 53983,
    /*GILLT_nxv4s64*//*Label 2245*/ 54067, 0,
    /*GILLT_nxv8s8*//*Label 2246*/ 54151,
    /*GILLT_nxv8s16*//*Label 2247*/ 54235,
    /*GILLT_nxv8s32*//*Label 2248*/ 54319,
    /*GILLT_nxv8s64*//*Label 2249*/ 54403, 0,
    /*GILLT_nxv16s8*//*Label 2250*/ 54487,
    /*GILLT_nxv16s16*//*Label 2251*/ 54571,
    /*GILLT_nxv16s32*//*Label 2252*/ 54655, 0,
    /*GILLT_nxv32s8*//*Label 2253*/ 54739,
    /*GILLT_nxv32s16*//*Label 2254*/ 54823, 0,
    /*GILLT_nxv64s8*//*Label 2255*/ 54907,
    // Label 2232: @53043
    GIM_Try, /*On fail goto*//*Label 2257*/ 53092, // Rule ID 60046 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
      GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen,
      // MIs[1] Operand 1
      // No operand predicates
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      // (sra:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$imm)  =>  (SRAI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$imm)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRAI,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 60046,
      GIR_Done,
    // Label 2257: @53092
    GIM_Reject,
    // Label 2233: @53093
    GIM_Try, /*On fail goto*//*Label 2258*/ 53142, // Rule ID 60045 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
      GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen,
      // MIs[1] Operand 1
      // No operand predicates
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      // (sra:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$imm)  =>  (SRAI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$imm)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRAI,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 60045,
      GIR_Done,
    // Label 2258: @53142
    GIM_Reject,
    // Label 2234: @53143
    GIM_Try, /*On fail goto*//*Label 2259*/ 53226,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2260*/ 53195, // Rule ID 57049 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVSRA_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57049,
        GIR_Done,
      // Label 2260: @53195
      GIM_Try, /*On fail goto*//*Label 2261*/ 53225, // Rule ID 57050 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVSRA_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57050,
        GIR_Done,
      // Label 2261: @53225
      GIM_Reject,
    // Label 2259: @53226
    GIM_Reject,
    // Label 2235: @53227
    GIM_Try, /*On fail goto*//*Label 2262*/ 53310,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2263*/ 53279, // Rule ID 57061 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVSRA_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57061,
        GIR_Done,
      // Label 2263: @53279
      GIM_Try, /*On fail goto*//*Label 2264*/ 53309, // Rule ID 57062 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVSRA_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57062,
        GIR_Done,
      // Label 2264: @53309
      GIM_Reject,
    // Label 2262: @53310
    GIM_Reject,
    // Label 2236: @53311
    GIM_Try, /*On fail goto*//*Label 2265*/ 53394,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2266*/ 53363, // Rule ID 57069 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVSRA_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57069,
        GIR_Done,
      // Label 2266: @53363
      GIM_Try, /*On fail goto*//*Label 2267*/ 53393, // Rule ID 57070 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVSRA_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57070,
        GIR_Done,
      // Label 2267: @53393
      GIM_Reject,
    // Label 2265: @53394
    GIM_Reject,
    // Label 2237: @53395
    GIM_Try, /*On fail goto*//*Label 2268*/ 53478,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2269*/ 53447, // Rule ID 57085 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVSRA_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57085,
        GIR_Done,
      // Label 2269: @53447
      GIM_Try, /*On fail goto*//*Label 2270*/ 53477, // Rule ID 57086 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVSRA_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57086,
        GIR_Done,
      // Label 2270: @53477
      GIM_Reject,
    // Label 2268: @53478
    GIM_Reject,
    // Label 2238: @53479
    GIM_Try, /*On fail goto*//*Label 2271*/ 53562,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2272*/ 53531, // Rule ID 57053 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVSRA_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57053,
        GIR_Done,
      // Label 2272: @53531
      GIM_Try, /*On fail goto*//*Label 2273*/ 53561, // Rule ID 57054 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVSRA_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57054,
        GIR_Done,
      // Label 2273: @53561
      GIM_Reject,
    // Label 2271: @53562
    GIM_Reject,
    // Label 2239: @53563
    GIM_Try, /*On fail goto*//*Label 2274*/ 53646,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2275*/ 53615, // Rule ID 57065 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVSRA_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57065,
        GIR_Done,
      // Label 2275: @53615
      GIM_Try, /*On fail goto*//*Label 2276*/ 53645, // Rule ID 57066 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVSRA_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57066,
        GIR_Done,
      // Label 2276: @53645
      GIM_Reject,
    // Label 2274: @53646
    GIM_Reject,
    // Label 2240: @53647
    GIM_Try, /*On fail goto*//*Label 2277*/ 53730,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2278*/ 53699, // Rule ID 57081 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVSRA_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57081,
        GIR_Done,
      // Label 2278: @53699
      GIM_Try, /*On fail goto*//*Label 2279*/ 53729, // Rule ID 57082 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVSRA_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57082,
        GIR_Done,
      // Label 2279: @53729
      GIM_Reject,
    // Label 2277: @53730
    GIM_Reject,
    // Label 2241: @53731
    GIM_Try, /*On fail goto*//*Label 2280*/ 53814,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 2281*/ 53783, // Rule ID 57125 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVSRA_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57125,
        GIR_Done,
      // Label 2281: @53783
      GIM_Try, /*On fail goto*//*Label 2282*/ 53813, // Rule ID 57126 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVSRA_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57126,
        GIR_Done,
      // Label 2282: @53813
      GIM_Reject,
    // Label 2280: @53814
    GIM_Reject,
    // Label 2242: @53815
    GIM_Try, /*On fail goto*//*Label 2283*/ 53898,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2284*/ 53867, // Rule ID 57057 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVSRA_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57057,
        GIR_Done,
      // Label 2284: @53867
      GIM_Try, /*On fail goto*//*Label 2285*/ 53897, // Rule ID 57058 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVSRA_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57058,
        GIR_Done,
      // Label 2285: @53897
      GIM_Reject,
    // Label 2283: @53898
    GIM_Reject,
    // Label 2243: @53899
    GIM_Try, /*On fail goto*//*Label 2286*/ 53982,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2287*/ 53951, // Rule ID 57077 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVSRA_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57077,
        GIR_Done,
      // Label 2287: @53951
      GIM_Try, /*On fail goto*//*Label 2288*/ 53981, // Rule ID 57078 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVSRA_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57078,
        GIR_Done,
      // Label 2288: @53981
      GIM_Reject,
    // Label 2286: @53982
    GIM_Reject,
    // Label 2244: @53983
    GIM_Try, /*On fail goto*//*Label 2289*/ 54066,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 2290*/ 54035, // Rule ID 57113 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVSRA_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57113,
        GIR_Done,
      // Label 2290: @54035
      GIM_Try, /*On fail goto*//*Label 2291*/ 54065, // Rule ID 57114 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVSRA_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57114,
        GIR_Done,
      // Label 2291: @54065
      GIM_Reject,
    // Label 2289: @54066
    GIM_Reject,
    // Label 2245: @54067
    GIM_Try, /*On fail goto*//*Label 2292*/ 54150,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 2293*/ 54119, // Rule ID 57129 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVSRA_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57129,
        GIR_Done,
      // Label 2293: @54119
      GIM_Try, /*On fail goto*//*Label 2294*/ 54149, // Rule ID 57130 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVSRA_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57130,
        GIR_Done,
      // Label 2294: @54149
      GIM_Reject,
    // Label 2292: @54150
    GIM_Reject,
    // Label 2246: @54151
    GIM_Try, /*On fail goto*//*Label 2295*/ 54234,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2296*/ 54203, // Rule ID 57073 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVSRA_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57073,
        GIR_Done,
      // Label 2296: @54203
      GIM_Try, /*On fail goto*//*Label 2297*/ 54233, // Rule ID 57074 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVSRA_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57074,
        GIR_Done,
      // Label 2297: @54233
      GIM_Reject,
    // Label 2295: @54234
    GIM_Reject,
    // Label 2247: @54235
    GIM_Try, /*On fail goto*//*Label 2298*/ 54318,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 2299*/ 54287, // Rule ID 57101 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVSRA_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57101,
        GIR_Done,
      // Label 2299: @54287
      GIM_Try, /*On fail goto*//*Label 2300*/ 54317, // Rule ID 57102 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVSRA_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57102,
        GIR_Done,
      // Label 2300: @54317
      GIM_Reject,
    // Label 2298: @54318
    GIM_Reject,
    // Label 2248: @54319
    GIM_Try, /*On fail goto*//*Label 2301*/ 54402,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 2302*/ 54371, // Rule ID 57117 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVSRA_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57117,
        GIR_Done,
      // Label 2302: @54371
      GIM_Try, /*On fail goto*//*Label 2303*/ 54401, // Rule ID 57118 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVSRA_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57118,
        GIR_Done,
      // Label 2303: @54401
      GIM_Reject,
    // Label 2301: @54402
    GIM_Reject,
    // Label 2249: @54403
    GIM_Try, /*On fail goto*//*Label 2304*/ 54486,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 2305*/ 54455, // Rule ID 57133 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVSRA_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57133,
        GIR_Done,
      // Label 2305: @54455
      GIM_Try, /*On fail goto*//*Label 2306*/ 54485, // Rule ID 57134 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVSRA_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57134,
        GIR_Done,
      // Label 2306: @54485
      GIM_Reject,
    // Label 2304: @54486
    GIM_Reject,
    // Label 2250: @54487
    GIM_Try, /*On fail goto*//*Label 2307*/ 54570,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 2308*/ 54539, // Rule ID 57089 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVSRA_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57089,
        GIR_Done,
      // Label 2308: @54539
      GIM_Try, /*On fail goto*//*Label 2309*/ 54569, // Rule ID 57090 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVSRA_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57090,
        GIR_Done,
      // Label 2309: @54569
      GIM_Reject,
    // Label 2307: @54570
    GIM_Reject,
    // Label 2251: @54571
    GIM_Try, /*On fail goto*//*Label 2310*/ 54654,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 2311*/ 54623, // Rule ID 57105 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVSRA_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57105,
        GIR_Done,
      // Label 2311: @54623
      GIM_Try, /*On fail goto*//*Label 2312*/ 54653, // Rule ID 57106 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVSRA_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57106,
        GIR_Done,
      // Label 2312: @54653
      GIM_Reject,
    // Label 2310: @54654
    GIM_Reject,
    // Label 2252: @54655
    GIM_Try, /*On fail goto*//*Label 2313*/ 54738,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 2314*/ 54707, // Rule ID 57121 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVSRA_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57121,
        GIR_Done,
      // Label 2314: @54707
      GIM_Try, /*On fail goto*//*Label 2315*/ 54737, // Rule ID 57122 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVSRA_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57122,
        GIR_Done,
      // Label 2315: @54737
      GIM_Reject,
    // Label 2313: @54738
    GIM_Reject,
    // Label 2253: @54739
    GIM_Try, /*On fail goto*//*Label 2316*/ 54822,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 2317*/ 54791, // Rule ID 57093 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVSRA_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57093,
        GIR_Done,
      // Label 2317: @54791
      GIM_Try, /*On fail goto*//*Label 2318*/ 54821, // Rule ID 57094 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVSRA_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57094,
        GIR_Done,
      // Label 2318: @54821
      GIM_Reject,
    // Label 2316: @54822
    GIM_Reject,
    // Label 2254: @54823
    GIM_Try, /*On fail goto*//*Label 2319*/ 54906,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 2320*/ 54875, // Rule ID 57109 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVSRA_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57109,
        GIR_Done,
      // Label 2320: @54875
      GIM_Try, /*On fail goto*//*Label 2321*/ 54905, // Rule ID 57110 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVSRA_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57110,
        GIR_Done,
      // Label 2321: @54905
      GIM_Reject,
    // Label 2319: @54906
    GIM_Reject,
    // Label 2255: @54907
    GIM_Try, /*On fail goto*//*Label 2322*/ 54990,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv64s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 2323*/ 54959, // Rule ID 57097 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVSRA_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57097,
        GIR_Done,
      // Label 2323: @54959
      GIM_Try, /*On fail goto*//*Label 2324*/ 54989, // Rule ID 57098 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (sra:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVSRA_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSRA_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57098,
        GIR_Done,
      // Label 2324: @54989
      GIM_Reject,
    // Label 2322: @54990
    GIM_Reject,
    // Label 2256: @54991
    GIM_Reject,
    // Label 35: @54992
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 2327*/ 55104,
    /*GILLT_s32*//*Label 2325*/ 55000,
    /*GILLT_s64*//*Label 2326*/ 55052,
    // Label 2325: @55000
    GIM_Try, /*On fail goto*//*Label 2328*/ 55051, // Rule ID 65444 //
      GIM_CheckFeatures, GIFBS_HasStdExtZbbOrZbkb,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
      GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen,
      // MIs[1] Operand 1
      // No operand predicates
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      // (rotr:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$imm)  =>  (RORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$imm)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::RORI,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65444,
      GIR_Done,
    // Label 2328: @55051
    GIM_Reject,
    // Label 2326: @55052
    GIM_Try, /*On fail goto*//*Label 2329*/ 55103, // Rule ID 65443 //
      GIM_CheckFeatures, GIFBS_HasStdExtZbbOrZbkb,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
      GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen,
      // MIs[1] Operand 1
      // No operand predicates
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      // (rotr:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$imm)  =>  (RORI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$imm)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::RORI,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65443,
      GIR_Done,
    // Label 2329: @55103
    GIM_Reject,
    // Label 2327: @55104
    GIM_Reject,
    // Label 36: @55105
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 31, /*)*//*default:*//*Label 2339*/ 79639,
    /*GILLT_s32*//*Label 2330*/ 55141,
    /*GILLT_s64*//*Label 2331*/ 55619,
    /*GILLT_nxv1s1*//*Label 2332*/ 56097, 0, 0, 0, 0,
    /*GILLT_nxv2s1*//*Label 2333*/ 60418, 0, 0, 0, 0,
    /*GILLT_nxv4s1*//*Label 2334*/ 64739, 0, 0, 0, 0,
    /*GILLT_nxv8s1*//*Label 2335*/ 69060, 0, 0, 0, 0,
    /*GILLT_nxv16s1*//*Label 2336*/ 73381, 0, 0, 0,
    /*GILLT_nxv32s1*//*Label 2337*/ 76622, 0, 0,
    /*GILLT_nxv64s1*//*Label 2338*/ 78783,
    // Label 2330: @55141
    GIM_Try, /*On fail goto*//*Label 2340*/ 55618,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2341*/ 55188, // Rule ID 60617 //
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
        // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }, SETEQ:{ *:[Other] })  =>  (SLTIU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60617,
        GIR_Done,
      // Label 2341: @55188
      GIM_Try, /*On fail goto*//*Label 2342*/ 55240, // Rule ID 60681 //
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, -2048,
        // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, -2048:{ *:[i32] }, SETEQ:{ *:[Other] })  =>  (SLTIU:{ *:[i32] } (XORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, -2048:{ *:[i32] }), 1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XORI,
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_AddImm, /*InsnID*/1, /*Imm*/-2048,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60681,
        GIR_Done,
      // Label 2342: @55240
      GIM_Try, /*On fail goto*//*Label 2343*/ 55274, // Rule ID 60703 //
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
        // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }, SETNE:{ *:[Other] })  =>  (SLTU:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$rs1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60703,
        GIR_Done,
      // Label 2343: @55274
      GIM_Try, /*On fail goto*//*Label 2344*/ 55327, // Rule ID 60765 //
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, -2048,
        // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, -2048:{ *:[i32] }, SETNE:{ *:[Other] })  =>  (SLTU:{ *:[i32] } X0:{ *:[i32] }, (XORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, -2048:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XORI,
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_AddImm, /*InsnID*/1, /*Imm*/-2048,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0,
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60765,
        GIR_Done,
      // Label 2344: @55327
      GIM_Try, /*On fail goto*//*Label 2345*/ 55360, // Rule ID 60787 //
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, -1,
        // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] }, SETNE:{ *:[Other] })  =>  (SLTIU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, -1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60787,
        GIR_Done,
      // Label 2345: @55360
      GIM_Try, /*On fail goto*//*Label 2346*/ 55401, // Rule ID 60551 //
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm, SETLT:{ *:[Other] })  =>  (SLTI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTI,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60551,
        GIR_Done,
      // Label 2346: @55401
      GIM_Try, /*On fail goto*//*Label 2347*/ 55442, // Rule ID 60595 //
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm, SETULT:{ *:[Other] })  =>  (SLTIU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60595,
        GIR_Done,
      // Label 2347: @55442
      GIM_Try, /*On fail goto*//*Label 2348*/ 55476, // Rule ID 60531 //
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETLT:{ *:[Other] })  =>  (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLT,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60531,
        GIR_Done,
      // Label 2348: @55476
      GIM_Try, /*On fail goto*//*Label 2349*/ 55510, // Rule ID 60573 //
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETULT:{ *:[Other] })  =>  (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60573,
        GIR_Done,
      // Label 2349: @55510
      GIM_Try, /*On fail goto*//*Label 2350*/ 55563, // Rule ID 60637 //
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETEQ:{ *:[Other] })  =>  (SLTIU:{ *:[i32] } (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), 1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XOR,
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60637,
        GIR_Done,
      // Label 2350: @55563
      GIM_Try, /*On fail goto*//*Label 2351*/ 55617, // Rule ID 60725 //
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETNE:{ *:[Other] })  =>  (SLTU:{ *:[i32] } X0:{ *:[i32] }, (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XOR,
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0,
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60725,
        GIR_Done,
      // Label 2351: @55617
      GIM_Reject,
    // Label 2340: @55618
    GIM_Reject,
    // Label 2331: @55619
    GIM_Try, /*On fail goto*//*Label 2352*/ 56096,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2353*/ 55666, // Rule ID 60616 //
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
        // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }, SETEQ:{ *:[Other] })  =>  (SLTIU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60616,
        GIR_Done,
      // Label 2353: @55666
      GIM_Try, /*On fail goto*//*Label 2354*/ 55718, // Rule ID 60680 //
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, -2048,
        // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, -2048:{ *:[i64] }, SETEQ:{ *:[Other] })  =>  (SLTIU:{ *:[i64] } (XORI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, -2048:{ *:[i64] }), 1:{ *:[i64] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XORI,
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_AddImm, /*InsnID*/1, /*Imm*/-2048,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60680,
        GIR_Done,
      // Label 2354: @55718
      GIM_Try, /*On fail goto*//*Label 2355*/ 55752, // Rule ID 60702 //
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
        // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }, SETNE:{ *:[Other] })  =>  (SLTU:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$rs1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60702,
        GIR_Done,
      // Label 2355: @55752
      GIM_Try, /*On fail goto*//*Label 2356*/ 55805, // Rule ID 60764 //
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, -2048,
        // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, -2048:{ *:[i64] }, SETNE:{ *:[Other] })  =>  (SLTU:{ *:[i64] } X0:{ *:[i64] }, (XORI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, -2048:{ *:[i64] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XORI,
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_AddImm, /*InsnID*/1, /*Imm*/-2048,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0,
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60764,
        GIR_Done,
      // Label 2356: @55805
      GIM_Try, /*On fail goto*//*Label 2357*/ 55838, // Rule ID 60786 //
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckConstantInt, /*MI*/0, /*Op*/3, -1,
        // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] }, SETNE:{ *:[Other] })  =>  (SLTIU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, -1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60786,
        GIR_Done,
      // Label 2357: @55838
      GIM_Try, /*On fail goto*//*Label 2358*/ 55879, // Rule ID 60550 //
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm, SETLT:{ *:[Other] })  =>  (SLTI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTI,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60550,
        GIR_Done,
      // Label 2358: @55879
      GIM_Try, /*On fail goto*//*Label 2359*/ 55920, // Rule ID 60594 //
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm, SETULT:{ *:[Other] })  =>  (SLTIU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60594,
        GIR_Done,
      // Label 2359: @55920
      GIM_Try, /*On fail goto*//*Label 2360*/ 55954, // Rule ID 60530 //
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETLT:{ *:[Other] })  =>  (SLT:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLT,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60530,
        GIR_Done,
      // Label 2360: @55954
      GIM_Try, /*On fail goto*//*Label 2361*/ 55988, // Rule ID 60572 //
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETULT:{ *:[Other] })  =>  (SLTU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60572,
        GIR_Done,
      // Label 2361: @55988
      GIM_Try, /*On fail goto*//*Label 2362*/ 56041, // Rule ID 60636 //
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETEQ:{ *:[Other] })  =>  (SLTIU:{ *:[i64] } (XOR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2), 1:{ *:[i64] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XOR,
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60636,
        GIR_Done,
      // Label 2362: @56041
      GIM_Try, /*On fail goto*//*Label 2363*/ 56095, // Rule ID 60724 //
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETNE:{ *:[Other] })  =>  (SLTU:{ *:[i64] } X0:{ *:[i64] }, (XOR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XOR,
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0,
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 60724,
        GIR_Done,
      // Label 2363: @56095
      GIM_Reject,
    // Label 2352: @56096
    GIM_Reject,
    // Label 2332: @56097
    GIM_Try, /*On fail goto*//*Label 2364*/ 56151, // Rule ID 54949 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_MF8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 54949,
      GIR_Done,
    // Label 2364: @56151
    GIM_Try, /*On fail goto*//*Label 2365*/ 56205, // Rule ID 54950 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_MF8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 54950,
      GIR_Done,
    // Label 2365: @56205
    GIM_Try, /*On fail goto*//*Label 2366*/ 56259, // Rule ID 54951 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs2, VR:{ *:[nxv1i8] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_MF8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 54951,
      GIR_Done,
    // Label 2366: @56259
    GIM_Try, /*On fail goto*//*Label 2367*/ 56313, // Rule ID 54952 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs2, VR:{ *:[nxv1i8] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_MF8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 54952,
      GIR_Done,
    // Label 2367: @56313
    GIM_Try, /*On fail goto*//*Label 2368*/ 56367, // Rule ID 57229 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57229,
      GIR_Done,
    // Label 2368: @56367
    GIM_Try, /*On fail goto*//*Label 2369*/ 56421, // Rule ID 57230 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57230,
      GIR_Done,
    // Label 2369: @56421
    GIM_Try, /*On fail goto*//*Label 2370*/ 56475, // Rule ID 57233 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57233,
      GIR_Done,
    // Label 2370: @56475
    GIM_Try, /*On fail goto*//*Label 2371*/ 56529, // Rule ID 57234 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57234,
      GIR_Done,
    // Label 2371: @56529
    GIM_Try, /*On fail goto*//*Label 2372*/ 56583, // Rule ID 57241 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57241,
      GIR_Done,
    // Label 2372: @56583
    GIM_Try, /*On fail goto*//*Label 2373*/ 56637, // Rule ID 57242 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57242,
      GIR_Done,
    // Label 2373: @56637
    GIM_Try, /*On fail goto*//*Label 2374*/ 56691, // Rule ID 57267 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_MF8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57267,
      GIR_Done,
    // Label 2374: @56691
    GIM_Try, /*On fail goto*//*Label 2375*/ 56745, // Rule ID 57268 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_MF8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57268,
      GIR_Done,
    // Label 2375: @56745
    GIM_Try, /*On fail goto*//*Label 2376*/ 56799, // Rule ID 57273 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57273,
      GIR_Done,
    // Label 2376: @56799
    GIM_Try, /*On fail goto*//*Label 2377*/ 56853, // Rule ID 57274 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57274,
      GIR_Done,
    // Label 2377: @56853
    GIM_Try, /*On fail goto*//*Label 2378*/ 56907, // Rule ID 57277 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57277,
      GIR_Done,
    // Label 2378: @56907
    GIM_Try, /*On fail goto*//*Label 2379*/ 56961, // Rule ID 57278 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57278,
      GIR_Done,
    // Label 2379: @56961
    GIM_Try, /*On fail goto*//*Label 2380*/ 57015, // Rule ID 57285 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57285,
      GIR_Done,
    // Label 2380: @57015
    GIM_Try, /*On fail goto*//*Label 2381*/ 57069, // Rule ID 57286 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57286,
      GIR_Done,
    // Label 2381: @57069
    GIM_Try, /*On fail goto*//*Label 2382*/ 57123, // Rule ID 57311 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_MF8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57311,
      GIR_Done,
    // Label 2382: @57123
    GIM_Try, /*On fail goto*//*Label 2383*/ 57177, // Rule ID 57312 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_MF8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57312,
      GIR_Done,
    // Label 2383: @57177
    GIM_Try, /*On fail goto*//*Label 2384*/ 57231, // Rule ID 57317 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57317,
      GIR_Done,
    // Label 2384: @57231
    GIM_Try, /*On fail goto*//*Label 2385*/ 57285, // Rule ID 57318 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57318,
      GIR_Done,
    // Label 2385: @57285
    GIM_Try, /*On fail goto*//*Label 2386*/ 57339, // Rule ID 57321 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57321,
      GIR_Done,
    // Label 2386: @57339
    GIM_Try, /*On fail goto*//*Label 2387*/ 57393, // Rule ID 57322 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57322,
      GIR_Done,
    // Label 2387: @57393
    GIM_Try, /*On fail goto*//*Label 2388*/ 57447, // Rule ID 57329 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57329,
      GIR_Done,
    // Label 2388: @57447
    GIM_Try, /*On fail goto*//*Label 2389*/ 57501, // Rule ID 57330 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57330,
      GIR_Done,
    // Label 2389: @57501
    GIM_Try, /*On fail goto*//*Label 2390*/ 57555, // Rule ID 57359 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs2, VR:{ *:[nxv1i16] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57359,
      GIR_Done,
    // Label 2390: @57555
    GIM_Try, /*On fail goto*//*Label 2391*/ 57609, // Rule ID 57360 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs2, VR:{ *:[nxv1i16] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57360,
      GIR_Done,
    // Label 2391: @57609
    GIM_Try, /*On fail goto*//*Label 2392*/ 57663, // Rule ID 57363 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs2, VR:{ *:[nxv1i32] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57363,
      GIR_Done,
    // Label 2392: @57663
    GIM_Try, /*On fail goto*//*Label 2393*/ 57717, // Rule ID 57364 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs2, VR:{ *:[nxv1i32] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57364,
      GIR_Done,
    // Label 2393: @57717
    GIM_Try, /*On fail goto*//*Label 2394*/ 57771, // Rule ID 57371 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs2, VR:{ *:[nxv1i64] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57371,
      GIR_Done,
    // Label 2394: @57771
    GIM_Try, /*On fail goto*//*Label 2395*/ 57825, // Rule ID 57372 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs2, VR:{ *:[nxv1i64] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57372,
      GIR_Done,
    // Label 2395: @57825
    GIM_Try, /*On fail goto*//*Label 2396*/ 57879, // Rule ID 57397 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_MF8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57397,
      GIR_Done,
    // Label 2396: @57879
    GIM_Try, /*On fail goto*//*Label 2397*/ 57933, // Rule ID 57398 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_MF8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57398,
      GIR_Done,
    // Label 2397: @57933
    GIM_Try, /*On fail goto*//*Label 2398*/ 57987, // Rule ID 57403 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57403,
      GIR_Done,
    // Label 2398: @57987
    GIM_Try, /*On fail goto*//*Label 2399*/ 58041, // Rule ID 57404 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57404,
      GIR_Done,
    // Label 2399: @58041
    GIM_Try, /*On fail goto*//*Label 2400*/ 58095, // Rule ID 57407 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57407,
      GIR_Done,
    // Label 2400: @58095
    GIM_Try, /*On fail goto*//*Label 2401*/ 58149, // Rule ID 57408 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57408,
      GIR_Done,
    // Label 2401: @58149
    GIM_Try, /*On fail goto*//*Label 2402*/ 58203, // Rule ID 57415 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57415,
      GIR_Done,
    // Label 2402: @58203
    GIM_Try, /*On fail goto*//*Label 2403*/ 58257, // Rule ID 57416 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57416,
      GIR_Done,
    // Label 2403: @58257
    GIM_Try, /*On fail goto*//*Label 2404*/ 58311, // Rule ID 57441 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs2, VR:{ *:[nxv1i8] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_MF8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57441,
      GIR_Done,
    // Label 2404: @58311
    GIM_Try, /*On fail goto*//*Label 2405*/ 58365, // Rule ID 57442 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs2, VR:{ *:[nxv1i8] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_MF8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57442,
      GIR_Done,
    // Label 2405: @58365
    GIM_Try, /*On fail goto*//*Label 2406*/ 58419, // Rule ID 57447 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs2, VR:{ *:[nxv1i16] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57447,
      GIR_Done,
    // Label 2406: @58419
    GIM_Try, /*On fail goto*//*Label 2407*/ 58473, // Rule ID 57448 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs2, VR:{ *:[nxv1i16] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57448,
      GIR_Done,
    // Label 2407: @58473
    GIM_Try, /*On fail goto*//*Label 2408*/ 58527, // Rule ID 57451 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs2, VR:{ *:[nxv1i32] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57451,
      GIR_Done,
    // Label 2408: @58527
    GIM_Try, /*On fail goto*//*Label 2409*/ 58581, // Rule ID 57452 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs2, VR:{ *:[nxv1i32] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57452,
      GIR_Done,
    // Label 2409: @58581
    GIM_Try, /*On fail goto*//*Label 2410*/ 58635, // Rule ID 57459 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs2, VR:{ *:[nxv1i64] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57459,
      GIR_Done,
    // Label 2410: @58635
    GIM_Try, /*On fail goto*//*Label 2411*/ 58689, // Rule ID 57460 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs2, VR:{ *:[nxv1i64] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57460,
      GIR_Done,
    // Label 2411: @58689
    GIM_Try, /*On fail goto*//*Label 2412*/ 58743, // Rule ID 57485 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_MF8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57485,
      GIR_Done,
    // Label 2412: @58743
    GIM_Try, /*On fail goto*//*Label 2413*/ 58797, // Rule ID 57486 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_MF8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57486,
      GIR_Done,
    // Label 2413: @58797
    GIM_Try, /*On fail goto*//*Label 2414*/ 58851, // Rule ID 57491 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57491,
      GIR_Done,
    // Label 2414: @58851
    GIM_Try, /*On fail goto*//*Label 2415*/ 58905, // Rule ID 57492 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57492,
      GIR_Done,
    // Label 2415: @58905
    GIM_Try, /*On fail goto*//*Label 2416*/ 58959, // Rule ID 57495 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57495,
      GIR_Done,
    // Label 2416: @58959
    GIM_Try, /*On fail goto*//*Label 2417*/ 59013, // Rule ID 57496 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57496,
      GIR_Done,
    // Label 2417: @59013
    GIM_Try, /*On fail goto*//*Label 2418*/ 59067, // Rule ID 57503 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57503,
      GIR_Done,
    // Label 2418: @59067
    GIM_Try, /*On fail goto*//*Label 2419*/ 59121, // Rule ID 57504 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57504,
      GIR_Done,
    // Label 2419: @59121
    GIM_Try, /*On fail goto*//*Label 2420*/ 59175, // Rule ID 57529 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs2, VR:{ *:[nxv1i8] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_MF8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57529,
      GIR_Done,
    // Label 2420: @59175
    GIM_Try, /*On fail goto*//*Label 2421*/ 59229, // Rule ID 57530 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs2, VR:{ *:[nxv1i8] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_MF8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57530,
      GIR_Done,
    // Label 2421: @59229
    GIM_Try, /*On fail goto*//*Label 2422*/ 59283, // Rule ID 57535 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs2, VR:{ *:[nxv1i16] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57535,
      GIR_Done,
    // Label 2422: @59283
    GIM_Try, /*On fail goto*//*Label 2423*/ 59337, // Rule ID 57536 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs2, VR:{ *:[nxv1i16] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57536,
      GIR_Done,
    // Label 2423: @59337
    GIM_Try, /*On fail goto*//*Label 2424*/ 59391, // Rule ID 57539 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs2, VR:{ *:[nxv1i32] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57539,
      GIR_Done,
    // Label 2424: @59391
    GIM_Try, /*On fail goto*//*Label 2425*/ 59445, // Rule ID 57540 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs2, VR:{ *:[nxv1i32] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57540,
      GIR_Done,
    // Label 2425: @59445
    GIM_Try, /*On fail goto*//*Label 2426*/ 59499, // Rule ID 57547 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs2, VR:{ *:[nxv1i64] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57547,
      GIR_Done,
    // Label 2426: @59499
    GIM_Try, /*On fail goto*//*Label 2427*/ 59553, // Rule ID 57548 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs2, VR:{ *:[nxv1i64] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57548,
      GIR_Done,
    // Label 2427: @59553
    GIM_Try, /*On fail goto*//*Label 2428*/ 59607, // Rule ID 57573 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_MF8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57573,
      GIR_Done,
    // Label 2428: @59607
    GIM_Try, /*On fail goto*//*Label 2429*/ 59661, // Rule ID 57574 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_MF8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57574,
      GIR_Done,
    // Label 2429: @59661
    GIM_Try, /*On fail goto*//*Label 2430*/ 59715, // Rule ID 57579 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57579,
      GIR_Done,
    // Label 2430: @59715
    GIM_Try, /*On fail goto*//*Label 2431*/ 59769, // Rule ID 57580 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57580,
      GIR_Done,
    // Label 2431: @59769
    GIM_Try, /*On fail goto*//*Label 2432*/ 59823, // Rule ID 57583 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57583,
      GIR_Done,
    // Label 2432: @59823
    GIM_Try, /*On fail goto*//*Label 2433*/ 59877, // Rule ID 57584 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57584,
      GIR_Done,
    // Label 2433: @59877
    GIM_Try, /*On fail goto*//*Label 2434*/ 59931, // Rule ID 57591 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57591,
      GIR_Done,
    // Label 2434: @59931
    GIM_Try, /*On fail goto*//*Label 2435*/ 59985, // Rule ID 57592 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57592,
      GIR_Done,
    // Label 2435: @59985
    GIM_Try, /*On fail goto*//*Label 2436*/ 60039, // Rule ID 57617 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs2, VR:{ *:[nxv1i8] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_MF8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57617,
      GIR_Done,
    // Label 2436: @60039
    GIM_Try, /*On fail goto*//*Label 2437*/ 60093, // Rule ID 57618 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs2, VR:{ *:[nxv1i8] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_MF8:{ *:[nxv1i1] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_MF8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57618,
      GIR_Done,
    // Label 2437: @60093
    GIM_Try, /*On fail goto*//*Label 2438*/ 60147, // Rule ID 57623 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs2, VR:{ *:[nxv1i16] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57623,
      GIR_Done,
    // Label 2438: @60147
    GIM_Try, /*On fail goto*//*Label 2439*/ 60201, // Rule ID 57624 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs2, VR:{ *:[nxv1i16] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57624,
      GIR_Done,
    // Label 2439: @60201
    GIM_Try, /*On fail goto*//*Label 2440*/ 60255, // Rule ID 57627 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs2, VR:{ *:[nxv1i32] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57627,
      GIR_Done,
    // Label 2440: @60255
    GIM_Try, /*On fail goto*//*Label 2441*/ 60309, // Rule ID 57628 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs2, VR:{ *:[nxv1i32] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57628,
      GIR_Done,
    // Label 2441: @60309
    GIM_Try, /*On fail goto*//*Label 2442*/ 60363, // Rule ID 57635 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs2, VR:{ *:[nxv1i64] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57635,
      GIR_Done,
    // Label 2442: @60363
    GIM_Try, /*On fail goto*//*Label 2443*/ 60417, // Rule ID 57636 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs2, VR:{ *:[nxv1i64] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57636,
      GIR_Done,
    // Label 2443: @60417
    GIM_Reject,
    // Label 2333: @60418
    GIM_Try, /*On fail goto*//*Label 2444*/ 60472, // Rule ID 57225 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57225,
      GIR_Done,
    // Label 2444: @60472
    GIM_Try, /*On fail goto*//*Label 2445*/ 60526, // Rule ID 57226 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57226,
      GIR_Done,
    // Label 2445: @60526
    GIM_Try, /*On fail goto*//*Label 2446*/ 60580, // Rule ID 57231 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57231,
      GIR_Done,
    // Label 2446: @60580
    GIM_Try, /*On fail goto*//*Label 2447*/ 60634, // Rule ID 57232 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57232,
      GIR_Done,
    // Label 2447: @60634
    GIM_Try, /*On fail goto*//*Label 2448*/ 60688, // Rule ID 57239 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57239,
      GIR_Done,
    // Label 2448: @60688
    GIM_Try, /*On fail goto*//*Label 2449*/ 60742, // Rule ID 57240 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57240,
      GIR_Done,
    // Label 2449: @60742
    GIM_Try, /*On fail goto*//*Label 2450*/ 60796, // Rule ID 57261 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57261,
      GIR_Done,
    // Label 2450: @60796
    GIM_Try, /*On fail goto*//*Label 2451*/ 60850, // Rule ID 57262 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57262,
      GIR_Done,
    // Label 2451: @60850
    GIM_Try, /*On fail goto*//*Label 2452*/ 60904, // Rule ID 57269 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57269,
      GIR_Done,
    // Label 2452: @60904
    GIM_Try, /*On fail goto*//*Label 2453*/ 60958, // Rule ID 57270 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57270,
      GIR_Done,
    // Label 2453: @60958
    GIM_Try, /*On fail goto*//*Label 2454*/ 61012, // Rule ID 57275 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57275,
      GIR_Done,
    // Label 2454: @61012
    GIM_Try, /*On fail goto*//*Label 2455*/ 61066, // Rule ID 57276 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57276,
      GIR_Done,
    // Label 2455: @61066
    GIM_Try, /*On fail goto*//*Label 2456*/ 61120, // Rule ID 57283 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57283,
      GIR_Done,
    // Label 2456: @61120
    GIM_Try, /*On fail goto*//*Label 2457*/ 61174, // Rule ID 57284 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57284,
      GIR_Done,
    // Label 2457: @61174
    GIM_Try, /*On fail goto*//*Label 2458*/ 61228, // Rule ID 57305 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57305,
      GIR_Done,
    // Label 2458: @61228
    GIM_Try, /*On fail goto*//*Label 2459*/ 61282, // Rule ID 57306 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57306,
      GIR_Done,
    // Label 2459: @61282
    GIM_Try, /*On fail goto*//*Label 2460*/ 61336, // Rule ID 57313 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57313,
      GIR_Done,
    // Label 2460: @61336
    GIM_Try, /*On fail goto*//*Label 2461*/ 61390, // Rule ID 57314 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57314,
      GIR_Done,
    // Label 2461: @61390
    GIM_Try, /*On fail goto*//*Label 2462*/ 61444, // Rule ID 57319 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57319,
      GIR_Done,
    // Label 2462: @61444
    GIM_Try, /*On fail goto*//*Label 2463*/ 61498, // Rule ID 57320 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57320,
      GIR_Done,
    // Label 2463: @61498
    GIM_Try, /*On fail goto*//*Label 2464*/ 61552, // Rule ID 57327 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57327,
      GIR_Done,
    // Label 2464: @61552
    GIM_Try, /*On fail goto*//*Label 2465*/ 61606, // Rule ID 57328 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57328,
      GIR_Done,
    // Label 2465: @61606
    GIM_Try, /*On fail goto*//*Label 2466*/ 61660, // Rule ID 57349 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57349,
      GIR_Done,
    // Label 2466: @61660
    GIM_Try, /*On fail goto*//*Label 2467*/ 61714, // Rule ID 57350 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57350,
      GIR_Done,
    // Label 2467: @61714
    GIM_Try, /*On fail goto*//*Label 2468*/ 61768, // Rule ID 57355 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs2, VR:{ *:[nxv2i8] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57355,
      GIR_Done,
    // Label 2468: @61768
    GIM_Try, /*On fail goto*//*Label 2469*/ 61822, // Rule ID 57356 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs2, VR:{ *:[nxv2i8] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57356,
      GIR_Done,
    // Label 2469: @61822
    GIM_Try, /*On fail goto*//*Label 2470*/ 61876, // Rule ID 57361 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs2, VR:{ *:[nxv2i16] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57361,
      GIR_Done,
    // Label 2470: @61876
    GIM_Try, /*On fail goto*//*Label 2471*/ 61930, // Rule ID 57362 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs2, VR:{ *:[nxv2i16] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57362,
      GIR_Done,
    // Label 2471: @61930
    GIM_Try, /*On fail goto*//*Label 2472*/ 61984, // Rule ID 57369 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs2, VR:{ *:[nxv2i32] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57369,
      GIR_Done,
    // Label 2472: @61984
    GIM_Try, /*On fail goto*//*Label 2473*/ 62038, // Rule ID 57370 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs2, VR:{ *:[nxv2i32] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57370,
      GIR_Done,
    // Label 2473: @62038
    GIM_Try, /*On fail goto*//*Label 2474*/ 62092, // Rule ID 57391 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs2, VRM2:{ *:[nxv2i64] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57391,
      GIR_Done,
    // Label 2474: @62092
    GIM_Try, /*On fail goto*//*Label 2475*/ 62146, // Rule ID 57392 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs2, VRM2:{ *:[nxv2i64] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57392,
      GIR_Done,
    // Label 2475: @62146
    GIM_Try, /*On fail goto*//*Label 2476*/ 62200, // Rule ID 57399 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57399,
      GIR_Done,
    // Label 2476: @62200
    GIM_Try, /*On fail goto*//*Label 2477*/ 62254, // Rule ID 57400 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57400,
      GIR_Done,
    // Label 2477: @62254
    GIM_Try, /*On fail goto*//*Label 2478*/ 62308, // Rule ID 57405 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57405,
      GIR_Done,
    // Label 2478: @62308
    GIM_Try, /*On fail goto*//*Label 2479*/ 62362, // Rule ID 57406 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57406,
      GIR_Done,
    // Label 2479: @62362
    GIM_Try, /*On fail goto*//*Label 2480*/ 62416, // Rule ID 57413 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57413,
      GIR_Done,
    // Label 2480: @62416
    GIM_Try, /*On fail goto*//*Label 2481*/ 62470, // Rule ID 57414 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57414,
      GIR_Done,
    // Label 2481: @62470
    GIM_Try, /*On fail goto*//*Label 2482*/ 62524, // Rule ID 57435 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57435,
      GIR_Done,
    // Label 2482: @62524
    GIM_Try, /*On fail goto*//*Label 2483*/ 62578, // Rule ID 57436 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57436,
      GIR_Done,
    // Label 2483: @62578
    GIM_Try, /*On fail goto*//*Label 2484*/ 62632, // Rule ID 57443 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs2, VR:{ *:[nxv2i8] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57443,
      GIR_Done,
    // Label 2484: @62632
    GIM_Try, /*On fail goto*//*Label 2485*/ 62686, // Rule ID 57444 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs2, VR:{ *:[nxv2i8] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57444,
      GIR_Done,
    // Label 2485: @62686
    GIM_Try, /*On fail goto*//*Label 2486*/ 62740, // Rule ID 57449 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs2, VR:{ *:[nxv2i16] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57449,
      GIR_Done,
    // Label 2486: @62740
    GIM_Try, /*On fail goto*//*Label 2487*/ 62794, // Rule ID 57450 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs2, VR:{ *:[nxv2i16] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57450,
      GIR_Done,
    // Label 2487: @62794
    GIM_Try, /*On fail goto*//*Label 2488*/ 62848, // Rule ID 57457 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs2, VR:{ *:[nxv2i32] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57457,
      GIR_Done,
    // Label 2488: @62848
    GIM_Try, /*On fail goto*//*Label 2489*/ 62902, // Rule ID 57458 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs2, VR:{ *:[nxv2i32] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57458,
      GIR_Done,
    // Label 2489: @62902
    GIM_Try, /*On fail goto*//*Label 2490*/ 62956, // Rule ID 57479 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs2, VRM2:{ *:[nxv2i64] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57479,
      GIR_Done,
    // Label 2490: @62956
    GIM_Try, /*On fail goto*//*Label 2491*/ 63010, // Rule ID 57480 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs2, VRM2:{ *:[nxv2i64] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57480,
      GIR_Done,
    // Label 2491: @63010
    GIM_Try, /*On fail goto*//*Label 2492*/ 63064, // Rule ID 57487 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57487,
      GIR_Done,
    // Label 2492: @63064
    GIM_Try, /*On fail goto*//*Label 2493*/ 63118, // Rule ID 57488 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57488,
      GIR_Done,
    // Label 2493: @63118
    GIM_Try, /*On fail goto*//*Label 2494*/ 63172, // Rule ID 57493 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57493,
      GIR_Done,
    // Label 2494: @63172
    GIM_Try, /*On fail goto*//*Label 2495*/ 63226, // Rule ID 57494 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57494,
      GIR_Done,
    // Label 2495: @63226
    GIM_Try, /*On fail goto*//*Label 2496*/ 63280, // Rule ID 57501 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57501,
      GIR_Done,
    // Label 2496: @63280
    GIM_Try, /*On fail goto*//*Label 2497*/ 63334, // Rule ID 57502 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57502,
      GIR_Done,
    // Label 2497: @63334
    GIM_Try, /*On fail goto*//*Label 2498*/ 63388, // Rule ID 57523 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57523,
      GIR_Done,
    // Label 2498: @63388
    GIM_Try, /*On fail goto*//*Label 2499*/ 63442, // Rule ID 57524 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57524,
      GIR_Done,
    // Label 2499: @63442
    GIM_Try, /*On fail goto*//*Label 2500*/ 63496, // Rule ID 57531 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs2, VR:{ *:[nxv2i8] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57531,
      GIR_Done,
    // Label 2500: @63496
    GIM_Try, /*On fail goto*//*Label 2501*/ 63550, // Rule ID 57532 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs2, VR:{ *:[nxv2i8] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57532,
      GIR_Done,
    // Label 2501: @63550
    GIM_Try, /*On fail goto*//*Label 2502*/ 63604, // Rule ID 57537 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs2, VR:{ *:[nxv2i16] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57537,
      GIR_Done,
    // Label 2502: @63604
    GIM_Try, /*On fail goto*//*Label 2503*/ 63658, // Rule ID 57538 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs2, VR:{ *:[nxv2i16] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57538,
      GIR_Done,
    // Label 2503: @63658
    GIM_Try, /*On fail goto*//*Label 2504*/ 63712, // Rule ID 57545 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs2, VR:{ *:[nxv2i32] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57545,
      GIR_Done,
    // Label 2504: @63712
    GIM_Try, /*On fail goto*//*Label 2505*/ 63766, // Rule ID 57546 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs2, VR:{ *:[nxv2i32] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57546,
      GIR_Done,
    // Label 2505: @63766
    GIM_Try, /*On fail goto*//*Label 2506*/ 63820, // Rule ID 57567 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs2, VRM2:{ *:[nxv2i64] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57567,
      GIR_Done,
    // Label 2506: @63820
    GIM_Try, /*On fail goto*//*Label 2507*/ 63874, // Rule ID 57568 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs2, VRM2:{ *:[nxv2i64] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57568,
      GIR_Done,
    // Label 2507: @63874
    GIM_Try, /*On fail goto*//*Label 2508*/ 63928, // Rule ID 57575 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57575,
      GIR_Done,
    // Label 2508: @63928
    GIM_Try, /*On fail goto*//*Label 2509*/ 63982, // Rule ID 57576 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57576,
      GIR_Done,
    // Label 2509: @63982
    GIM_Try, /*On fail goto*//*Label 2510*/ 64036, // Rule ID 57581 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57581,
      GIR_Done,
    // Label 2510: @64036
    GIM_Try, /*On fail goto*//*Label 2511*/ 64090, // Rule ID 57582 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57582,
      GIR_Done,
    // Label 2511: @64090
    GIM_Try, /*On fail goto*//*Label 2512*/ 64144, // Rule ID 57589 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57589,
      GIR_Done,
    // Label 2512: @64144
    GIM_Try, /*On fail goto*//*Label 2513*/ 64198, // Rule ID 57590 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57590,
      GIR_Done,
    // Label 2513: @64198
    GIM_Try, /*On fail goto*//*Label 2514*/ 64252, // Rule ID 57611 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57611,
      GIR_Done,
    // Label 2514: @64252
    GIM_Try, /*On fail goto*//*Label 2515*/ 64306, // Rule ID 57612 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57612,
      GIR_Done,
    // Label 2515: @64306
    GIM_Try, /*On fail goto*//*Label 2516*/ 64360, // Rule ID 57619 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs2, VR:{ *:[nxv2i8] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57619,
      GIR_Done,
    // Label 2516: @64360
    GIM_Try, /*On fail goto*//*Label 2517*/ 64414, // Rule ID 57620 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs2, VR:{ *:[nxv2i8] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_MF4:{ *:[nxv2i1] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57620,
      GIR_Done,
    // Label 2517: @64414
    GIM_Try, /*On fail goto*//*Label 2518*/ 64468, // Rule ID 57625 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs2, VR:{ *:[nxv2i16] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57625,
      GIR_Done,
    // Label 2518: @64468
    GIM_Try, /*On fail goto*//*Label 2519*/ 64522, // Rule ID 57626 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs2, VR:{ *:[nxv2i16] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57626,
      GIR_Done,
    // Label 2519: @64522
    GIM_Try, /*On fail goto*//*Label 2520*/ 64576, // Rule ID 57633 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs2, VR:{ *:[nxv2i32] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57633,
      GIR_Done,
    // Label 2520: @64576
    GIM_Try, /*On fail goto*//*Label 2521*/ 64630, // Rule ID 57634 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs2, VR:{ *:[nxv2i32] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57634,
      GIR_Done,
    // Label 2521: @64630
    GIM_Try, /*On fail goto*//*Label 2522*/ 64684, // Rule ID 57655 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs2, VRM2:{ *:[nxv2i64] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57655,
      GIR_Done,
    // Label 2522: @64684
    GIM_Try, /*On fail goto*//*Label 2523*/ 64738, // Rule ID 57656 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs2, VRM2:{ *:[nxv2i64] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57656,
      GIR_Done,
    // Label 2523: @64738
    GIM_Reject,
    // Label 2334: @64739
    GIM_Try, /*On fail goto*//*Label 2524*/ 64793, // Rule ID 57227 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57227,
      GIR_Done,
    // Label 2524: @64793
    GIM_Try, /*On fail goto*//*Label 2525*/ 64847, // Rule ID 57228 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57228,
      GIR_Done,
    // Label 2525: @64847
    GIM_Try, /*On fail goto*//*Label 2526*/ 64901, // Rule ID 57237 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57237,
      GIR_Done,
    // Label 2526: @64901
    GIM_Try, /*On fail goto*//*Label 2527*/ 64955, // Rule ID 57238 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57238,
      GIR_Done,
    // Label 2527: @64955
    GIM_Try, /*On fail goto*//*Label 2528*/ 65009, // Rule ID 57255 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57255,
      GIR_Done,
    // Label 2528: @65009
    GIM_Try, /*On fail goto*//*Label 2529*/ 65063, // Rule ID 57256 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57256,
      GIR_Done,
    // Label 2529: @65063
    GIM_Try, /*On fail goto*//*Label 2530*/ 65117, // Rule ID 57263 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57263,
      GIR_Done,
    // Label 2530: @65117
    GIM_Try, /*On fail goto*//*Label 2531*/ 65171, // Rule ID 57264 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57264,
      GIR_Done,
    // Label 2531: @65171
    GIM_Try, /*On fail goto*//*Label 2532*/ 65225, // Rule ID 57271 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57271,
      GIR_Done,
    // Label 2532: @65225
    GIM_Try, /*On fail goto*//*Label 2533*/ 65279, // Rule ID 57272 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57272,
      GIR_Done,
    // Label 2533: @65279
    GIM_Try, /*On fail goto*//*Label 2534*/ 65333, // Rule ID 57281 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57281,
      GIR_Done,
    // Label 2534: @65333
    GIM_Try, /*On fail goto*//*Label 2535*/ 65387, // Rule ID 57282 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57282,
      GIR_Done,
    // Label 2535: @65387
    GIM_Try, /*On fail goto*//*Label 2536*/ 65441, // Rule ID 57299 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57299,
      GIR_Done,
    // Label 2536: @65441
    GIM_Try, /*On fail goto*//*Label 2537*/ 65495, // Rule ID 57300 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57300,
      GIR_Done,
    // Label 2537: @65495
    GIM_Try, /*On fail goto*//*Label 2538*/ 65549, // Rule ID 57307 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57307,
      GIR_Done,
    // Label 2538: @65549
    GIM_Try, /*On fail goto*//*Label 2539*/ 65603, // Rule ID 57308 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57308,
      GIR_Done,
    // Label 2539: @65603
    GIM_Try, /*On fail goto*//*Label 2540*/ 65657, // Rule ID 57315 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57315,
      GIR_Done,
    // Label 2540: @65657
    GIM_Try, /*On fail goto*//*Label 2541*/ 65711, // Rule ID 57316 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57316,
      GIR_Done,
    // Label 2541: @65711
    GIM_Try, /*On fail goto*//*Label 2542*/ 65765, // Rule ID 57325 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57325,
      GIR_Done,
    // Label 2542: @65765
    GIM_Try, /*On fail goto*//*Label 2543*/ 65819, // Rule ID 57326 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57326,
      GIR_Done,
    // Label 2543: @65819
    GIM_Try, /*On fail goto*//*Label 2544*/ 65873, // Rule ID 57343 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57343,
      GIR_Done,
    // Label 2544: @65873
    GIM_Try, /*On fail goto*//*Label 2545*/ 65927, // Rule ID 57344 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57344,
      GIR_Done,
    // Label 2545: @65927
    GIM_Try, /*On fail goto*//*Label 2546*/ 65981, // Rule ID 57351 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57351,
      GIR_Done,
    // Label 2546: @65981
    GIM_Try, /*On fail goto*//*Label 2547*/ 66035, // Rule ID 57352 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57352,
      GIR_Done,
    // Label 2547: @66035
    GIM_Try, /*On fail goto*//*Label 2548*/ 66089, // Rule ID 57357 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs2, VR:{ *:[nxv4i8] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57357,
      GIR_Done,
    // Label 2548: @66089
    GIM_Try, /*On fail goto*//*Label 2549*/ 66143, // Rule ID 57358 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs2, VR:{ *:[nxv4i8] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57358,
      GIR_Done,
    // Label 2549: @66143
    GIM_Try, /*On fail goto*//*Label 2550*/ 66197, // Rule ID 57367 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs2, VR:{ *:[nxv4i16] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57367,
      GIR_Done,
    // Label 2550: @66197
    GIM_Try, /*On fail goto*//*Label 2551*/ 66251, // Rule ID 57368 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs2, VR:{ *:[nxv4i16] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57368,
      GIR_Done,
    // Label 2551: @66251
    GIM_Try, /*On fail goto*//*Label 2552*/ 66305, // Rule ID 57385 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs2, VRM2:{ *:[nxv4i32] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57385,
      GIR_Done,
    // Label 2552: @66305
    GIM_Try, /*On fail goto*//*Label 2553*/ 66359, // Rule ID 57386 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs2, VRM2:{ *:[nxv4i32] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57386,
      GIR_Done,
    // Label 2553: @66359
    GIM_Try, /*On fail goto*//*Label 2554*/ 66413, // Rule ID 57393 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs2, VRM4:{ *:[nxv4i64] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57393,
      GIR_Done,
    // Label 2554: @66413
    GIM_Try, /*On fail goto*//*Label 2555*/ 66467, // Rule ID 57394 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs2, VRM4:{ *:[nxv4i64] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57394,
      GIR_Done,
    // Label 2555: @66467
    GIM_Try, /*On fail goto*//*Label 2556*/ 66521, // Rule ID 57401 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57401,
      GIR_Done,
    // Label 2556: @66521
    GIM_Try, /*On fail goto*//*Label 2557*/ 66575, // Rule ID 57402 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57402,
      GIR_Done,
    // Label 2557: @66575
    GIM_Try, /*On fail goto*//*Label 2558*/ 66629, // Rule ID 57411 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57411,
      GIR_Done,
    // Label 2558: @66629
    GIM_Try, /*On fail goto*//*Label 2559*/ 66683, // Rule ID 57412 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57412,
      GIR_Done,
    // Label 2559: @66683
    GIM_Try, /*On fail goto*//*Label 2560*/ 66737, // Rule ID 57429 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57429,
      GIR_Done,
    // Label 2560: @66737
    GIM_Try, /*On fail goto*//*Label 2561*/ 66791, // Rule ID 57430 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57430,
      GIR_Done,
    // Label 2561: @66791
    GIM_Try, /*On fail goto*//*Label 2562*/ 66845, // Rule ID 57437 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57437,
      GIR_Done,
    // Label 2562: @66845
    GIM_Try, /*On fail goto*//*Label 2563*/ 66899, // Rule ID 57438 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57438,
      GIR_Done,
    // Label 2563: @66899
    GIM_Try, /*On fail goto*//*Label 2564*/ 66953, // Rule ID 57445 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs2, VR:{ *:[nxv4i8] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57445,
      GIR_Done,
    // Label 2564: @66953
    GIM_Try, /*On fail goto*//*Label 2565*/ 67007, // Rule ID 57446 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs2, VR:{ *:[nxv4i8] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57446,
      GIR_Done,
    // Label 2565: @67007
    GIM_Try, /*On fail goto*//*Label 2566*/ 67061, // Rule ID 57455 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs2, VR:{ *:[nxv4i16] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57455,
      GIR_Done,
    // Label 2566: @67061
    GIM_Try, /*On fail goto*//*Label 2567*/ 67115, // Rule ID 57456 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs2, VR:{ *:[nxv4i16] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57456,
      GIR_Done,
    // Label 2567: @67115
    GIM_Try, /*On fail goto*//*Label 2568*/ 67169, // Rule ID 57473 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs2, VRM2:{ *:[nxv4i32] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57473,
      GIR_Done,
    // Label 2568: @67169
    GIM_Try, /*On fail goto*//*Label 2569*/ 67223, // Rule ID 57474 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs2, VRM2:{ *:[nxv4i32] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57474,
      GIR_Done,
    // Label 2569: @67223
    GIM_Try, /*On fail goto*//*Label 2570*/ 67277, // Rule ID 57481 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs2, VRM4:{ *:[nxv4i64] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57481,
      GIR_Done,
    // Label 2570: @67277
    GIM_Try, /*On fail goto*//*Label 2571*/ 67331, // Rule ID 57482 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs2, VRM4:{ *:[nxv4i64] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57482,
      GIR_Done,
    // Label 2571: @67331
    GIM_Try, /*On fail goto*//*Label 2572*/ 67385, // Rule ID 57489 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57489,
      GIR_Done,
    // Label 2572: @67385
    GIM_Try, /*On fail goto*//*Label 2573*/ 67439, // Rule ID 57490 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57490,
      GIR_Done,
    // Label 2573: @67439
    GIM_Try, /*On fail goto*//*Label 2574*/ 67493, // Rule ID 57499 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57499,
      GIR_Done,
    // Label 2574: @67493
    GIM_Try, /*On fail goto*//*Label 2575*/ 67547, // Rule ID 57500 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57500,
      GIR_Done,
    // Label 2575: @67547
    GIM_Try, /*On fail goto*//*Label 2576*/ 67601, // Rule ID 57517 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57517,
      GIR_Done,
    // Label 2576: @67601
    GIM_Try, /*On fail goto*//*Label 2577*/ 67655, // Rule ID 57518 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57518,
      GIR_Done,
    // Label 2577: @67655
    GIM_Try, /*On fail goto*//*Label 2578*/ 67709, // Rule ID 57525 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57525,
      GIR_Done,
    // Label 2578: @67709
    GIM_Try, /*On fail goto*//*Label 2579*/ 67763, // Rule ID 57526 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57526,
      GIR_Done,
    // Label 2579: @67763
    GIM_Try, /*On fail goto*//*Label 2580*/ 67817, // Rule ID 57533 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs2, VR:{ *:[nxv4i8] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57533,
      GIR_Done,
    // Label 2580: @67817
    GIM_Try, /*On fail goto*//*Label 2581*/ 67871, // Rule ID 57534 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs2, VR:{ *:[nxv4i8] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57534,
      GIR_Done,
    // Label 2581: @67871
    GIM_Try, /*On fail goto*//*Label 2582*/ 67925, // Rule ID 57543 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs2, VR:{ *:[nxv4i16] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57543,
      GIR_Done,
    // Label 2582: @67925
    GIM_Try, /*On fail goto*//*Label 2583*/ 67979, // Rule ID 57544 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs2, VR:{ *:[nxv4i16] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57544,
      GIR_Done,
    // Label 2583: @67979
    GIM_Try, /*On fail goto*//*Label 2584*/ 68033, // Rule ID 57561 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs2, VRM2:{ *:[nxv4i32] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57561,
      GIR_Done,
    // Label 2584: @68033
    GIM_Try, /*On fail goto*//*Label 2585*/ 68087, // Rule ID 57562 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs2, VRM2:{ *:[nxv4i32] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57562,
      GIR_Done,
    // Label 2585: @68087
    GIM_Try, /*On fail goto*//*Label 2586*/ 68141, // Rule ID 57569 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs2, VRM4:{ *:[nxv4i64] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57569,
      GIR_Done,
    // Label 2586: @68141
    GIM_Try, /*On fail goto*//*Label 2587*/ 68195, // Rule ID 57570 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs2, VRM4:{ *:[nxv4i64] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57570,
      GIR_Done,
    // Label 2587: @68195
    GIM_Try, /*On fail goto*//*Label 2588*/ 68249, // Rule ID 57577 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57577,
      GIR_Done,
    // Label 2588: @68249
    GIM_Try, /*On fail goto*//*Label 2589*/ 68303, // Rule ID 57578 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57578,
      GIR_Done,
    // Label 2589: @68303
    GIM_Try, /*On fail goto*//*Label 2590*/ 68357, // Rule ID 57587 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57587,
      GIR_Done,
    // Label 2590: @68357
    GIM_Try, /*On fail goto*//*Label 2591*/ 68411, // Rule ID 57588 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57588,
      GIR_Done,
    // Label 2591: @68411
    GIM_Try, /*On fail goto*//*Label 2592*/ 68465, // Rule ID 57605 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57605,
      GIR_Done,
    // Label 2592: @68465
    GIM_Try, /*On fail goto*//*Label 2593*/ 68519, // Rule ID 57606 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57606,
      GIR_Done,
    // Label 2593: @68519
    GIM_Try, /*On fail goto*//*Label 2594*/ 68573, // Rule ID 57613 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57613,
      GIR_Done,
    // Label 2594: @68573
    GIM_Try, /*On fail goto*//*Label 2595*/ 68627, // Rule ID 57614 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57614,
      GIR_Done,
    // Label 2595: @68627
    GIM_Try, /*On fail goto*//*Label 2596*/ 68681, // Rule ID 57621 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs2, VR:{ *:[nxv4i8] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57621,
      GIR_Done,
    // Label 2596: @68681
    GIM_Try, /*On fail goto*//*Label 2597*/ 68735, // Rule ID 57622 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs2, VR:{ *:[nxv4i8] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_MF2:{ *:[nxv4i1] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57622,
      GIR_Done,
    // Label 2597: @68735
    GIM_Try, /*On fail goto*//*Label 2598*/ 68789, // Rule ID 57631 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs2, VR:{ *:[nxv4i16] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57631,
      GIR_Done,
    // Label 2598: @68789
    GIM_Try, /*On fail goto*//*Label 2599*/ 68843, // Rule ID 57632 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs2, VR:{ *:[nxv4i16] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57632,
      GIR_Done,
    // Label 2599: @68843
    GIM_Try, /*On fail goto*//*Label 2600*/ 68897, // Rule ID 57649 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs2, VRM2:{ *:[nxv4i32] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57649,
      GIR_Done,
    // Label 2600: @68897
    GIM_Try, /*On fail goto*//*Label 2601*/ 68951, // Rule ID 57650 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs2, VRM2:{ *:[nxv4i32] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57650,
      GIR_Done,
    // Label 2601: @68951
    GIM_Try, /*On fail goto*//*Label 2602*/ 69005, // Rule ID 57657 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs2, VRM4:{ *:[nxv4i64] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57657,
      GIR_Done,
    // Label 2602: @69005
    GIM_Try, /*On fail goto*//*Label 2603*/ 69059, // Rule ID 57658 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs2, VRM4:{ *:[nxv4i64] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57658,
      GIR_Done,
    // Label 2603: @69059
    GIM_Reject,
    // Label 2335: @69060
    GIM_Try, /*On fail goto*//*Label 2604*/ 69114, // Rule ID 57235 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57235,
      GIR_Done,
    // Label 2604: @69114
    GIM_Try, /*On fail goto*//*Label 2605*/ 69168, // Rule ID 57236 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57236,
      GIR_Done,
    // Label 2605: @69168
    GIM_Try, /*On fail goto*//*Label 2606*/ 69222, // Rule ID 57249 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57249,
      GIR_Done,
    // Label 2606: @69222
    GIM_Try, /*On fail goto*//*Label 2607*/ 69276, // Rule ID 57250 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57250,
      GIR_Done,
    // Label 2607: @69276
    GIM_Try, /*On fail goto*//*Label 2608*/ 69330, // Rule ID 57257 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57257,
      GIR_Done,
    // Label 2608: @69330
    GIM_Try, /*On fail goto*//*Label 2609*/ 69384, // Rule ID 57258 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57258,
      GIR_Done,
    // Label 2609: @69384
    GIM_Try, /*On fail goto*//*Label 2610*/ 69438, // Rule ID 57265 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57265,
      GIR_Done,
    // Label 2610: @69438
    GIM_Try, /*On fail goto*//*Label 2611*/ 69492, // Rule ID 57266 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57266,
      GIR_Done,
    // Label 2611: @69492
    GIM_Try, /*On fail goto*//*Label 2612*/ 69546, // Rule ID 57279 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57279,
      GIR_Done,
    // Label 2612: @69546
    GIM_Try, /*On fail goto*//*Label 2613*/ 69600, // Rule ID 57280 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57280,
      GIR_Done,
    // Label 2613: @69600
    GIM_Try, /*On fail goto*//*Label 2614*/ 69654, // Rule ID 57293 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57293,
      GIR_Done,
    // Label 2614: @69654
    GIM_Try, /*On fail goto*//*Label 2615*/ 69708, // Rule ID 57294 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57294,
      GIR_Done,
    // Label 2615: @69708
    GIM_Try, /*On fail goto*//*Label 2616*/ 69762, // Rule ID 57301 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57301,
      GIR_Done,
    // Label 2616: @69762
    GIM_Try, /*On fail goto*//*Label 2617*/ 69816, // Rule ID 57302 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57302,
      GIR_Done,
    // Label 2617: @69816
    GIM_Try, /*On fail goto*//*Label 2618*/ 69870, // Rule ID 57309 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57309,
      GIR_Done,
    // Label 2618: @69870
    GIM_Try, /*On fail goto*//*Label 2619*/ 69924, // Rule ID 57310 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57310,
      GIR_Done,
    // Label 2619: @69924
    GIM_Try, /*On fail goto*//*Label 2620*/ 69978, // Rule ID 57323 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57323,
      GIR_Done,
    // Label 2620: @69978
    GIM_Try, /*On fail goto*//*Label 2621*/ 70032, // Rule ID 57324 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57324,
      GIR_Done,
    // Label 2621: @70032
    GIM_Try, /*On fail goto*//*Label 2622*/ 70086, // Rule ID 57337 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57337,
      GIR_Done,
    // Label 2622: @70086
    GIM_Try, /*On fail goto*//*Label 2623*/ 70140, // Rule ID 57338 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57338,
      GIR_Done,
    // Label 2623: @70140
    GIM_Try, /*On fail goto*//*Label 2624*/ 70194, // Rule ID 57345 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57345,
      GIR_Done,
    // Label 2624: @70194
    GIM_Try, /*On fail goto*//*Label 2625*/ 70248, // Rule ID 57346 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57346,
      GIR_Done,
    // Label 2625: @70248
    GIM_Try, /*On fail goto*//*Label 2626*/ 70302, // Rule ID 57353 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57353,
      GIR_Done,
    // Label 2626: @70302
    GIM_Try, /*On fail goto*//*Label 2627*/ 70356, // Rule ID 57354 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57354,
      GIR_Done,
    // Label 2627: @70356
    GIM_Try, /*On fail goto*//*Label 2628*/ 70410, // Rule ID 57365 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs2, VR:{ *:[nxv8i8] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57365,
      GIR_Done,
    // Label 2628: @70410
    GIM_Try, /*On fail goto*//*Label 2629*/ 70464, // Rule ID 57366 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs2, VR:{ *:[nxv8i8] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57366,
      GIR_Done,
    // Label 2629: @70464
    GIM_Try, /*On fail goto*//*Label 2630*/ 70518, // Rule ID 57379 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs2, VRM2:{ *:[nxv8i16] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57379,
      GIR_Done,
    // Label 2630: @70518
    GIM_Try, /*On fail goto*//*Label 2631*/ 70572, // Rule ID 57380 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs2, VRM2:{ *:[nxv8i16] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57380,
      GIR_Done,
    // Label 2631: @70572
    GIM_Try, /*On fail goto*//*Label 2632*/ 70626, // Rule ID 57387 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs2, VRM4:{ *:[nxv8i32] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57387,
      GIR_Done,
    // Label 2632: @70626
    GIM_Try, /*On fail goto*//*Label 2633*/ 70680, // Rule ID 57388 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs2, VRM4:{ *:[nxv8i32] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57388,
      GIR_Done,
    // Label 2633: @70680
    GIM_Try, /*On fail goto*//*Label 2634*/ 70734, // Rule ID 57395 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs2, VRM8:{ *:[nxv8i64] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57395,
      GIR_Done,
    // Label 2634: @70734
    GIM_Try, /*On fail goto*//*Label 2635*/ 70788, // Rule ID 57396 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs2, VRM8:{ *:[nxv8i64] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57396,
      GIR_Done,
    // Label 2635: @70788
    GIM_Try, /*On fail goto*//*Label 2636*/ 70842, // Rule ID 57409 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57409,
      GIR_Done,
    // Label 2636: @70842
    GIM_Try, /*On fail goto*//*Label 2637*/ 70896, // Rule ID 57410 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57410,
      GIR_Done,
    // Label 2637: @70896
    GIM_Try, /*On fail goto*//*Label 2638*/ 70950, // Rule ID 57423 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57423,
      GIR_Done,
    // Label 2638: @70950
    GIM_Try, /*On fail goto*//*Label 2639*/ 71004, // Rule ID 57424 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57424,
      GIR_Done,
    // Label 2639: @71004
    GIM_Try, /*On fail goto*//*Label 2640*/ 71058, // Rule ID 57431 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57431,
      GIR_Done,
    // Label 2640: @71058
    GIM_Try, /*On fail goto*//*Label 2641*/ 71112, // Rule ID 57432 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57432,
      GIR_Done,
    // Label 2641: @71112
    GIM_Try, /*On fail goto*//*Label 2642*/ 71166, // Rule ID 57439 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57439,
      GIR_Done,
    // Label 2642: @71166
    GIM_Try, /*On fail goto*//*Label 2643*/ 71220, // Rule ID 57440 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57440,
      GIR_Done,
    // Label 2643: @71220
    GIM_Try, /*On fail goto*//*Label 2644*/ 71274, // Rule ID 57453 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs2, VR:{ *:[nxv8i8] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57453,
      GIR_Done,
    // Label 2644: @71274
    GIM_Try, /*On fail goto*//*Label 2645*/ 71328, // Rule ID 57454 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs2, VR:{ *:[nxv8i8] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57454,
      GIR_Done,
    // Label 2645: @71328
    GIM_Try, /*On fail goto*//*Label 2646*/ 71382, // Rule ID 57467 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs2, VRM2:{ *:[nxv8i16] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57467,
      GIR_Done,
    // Label 2646: @71382
    GIM_Try, /*On fail goto*//*Label 2647*/ 71436, // Rule ID 57468 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs2, VRM2:{ *:[nxv8i16] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57468,
      GIR_Done,
    // Label 2647: @71436
    GIM_Try, /*On fail goto*//*Label 2648*/ 71490, // Rule ID 57475 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs2, VRM4:{ *:[nxv8i32] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57475,
      GIR_Done,
    // Label 2648: @71490
    GIM_Try, /*On fail goto*//*Label 2649*/ 71544, // Rule ID 57476 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs2, VRM4:{ *:[nxv8i32] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57476,
      GIR_Done,
    // Label 2649: @71544
    GIM_Try, /*On fail goto*//*Label 2650*/ 71598, // Rule ID 57483 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs2, VRM8:{ *:[nxv8i64] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57483,
      GIR_Done,
    // Label 2650: @71598
    GIM_Try, /*On fail goto*//*Label 2651*/ 71652, // Rule ID 57484 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs2, VRM8:{ *:[nxv8i64] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57484,
      GIR_Done,
    // Label 2651: @71652
    GIM_Try, /*On fail goto*//*Label 2652*/ 71706, // Rule ID 57497 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57497,
      GIR_Done,
    // Label 2652: @71706
    GIM_Try, /*On fail goto*//*Label 2653*/ 71760, // Rule ID 57498 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57498,
      GIR_Done,
    // Label 2653: @71760
    GIM_Try, /*On fail goto*//*Label 2654*/ 71814, // Rule ID 57511 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57511,
      GIR_Done,
    // Label 2654: @71814
    GIM_Try, /*On fail goto*//*Label 2655*/ 71868, // Rule ID 57512 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57512,
      GIR_Done,
    // Label 2655: @71868
    GIM_Try, /*On fail goto*//*Label 2656*/ 71922, // Rule ID 57519 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57519,
      GIR_Done,
    // Label 2656: @71922
    GIM_Try, /*On fail goto*//*Label 2657*/ 71976, // Rule ID 57520 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57520,
      GIR_Done,
    // Label 2657: @71976
    GIM_Try, /*On fail goto*//*Label 2658*/ 72030, // Rule ID 57527 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57527,
      GIR_Done,
    // Label 2658: @72030
    GIM_Try, /*On fail goto*//*Label 2659*/ 72084, // Rule ID 57528 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57528,
      GIR_Done,
    // Label 2659: @72084
    GIM_Try, /*On fail goto*//*Label 2660*/ 72138, // Rule ID 57541 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs2, VR:{ *:[nxv8i8] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57541,
      GIR_Done,
    // Label 2660: @72138
    GIM_Try, /*On fail goto*//*Label 2661*/ 72192, // Rule ID 57542 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs2, VR:{ *:[nxv8i8] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57542,
      GIR_Done,
    // Label 2661: @72192
    GIM_Try, /*On fail goto*//*Label 2662*/ 72246, // Rule ID 57555 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs2, VRM2:{ *:[nxv8i16] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57555,
      GIR_Done,
    // Label 2662: @72246
    GIM_Try, /*On fail goto*//*Label 2663*/ 72300, // Rule ID 57556 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs2, VRM2:{ *:[nxv8i16] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57556,
      GIR_Done,
    // Label 2663: @72300
    GIM_Try, /*On fail goto*//*Label 2664*/ 72354, // Rule ID 57563 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs2, VRM4:{ *:[nxv8i32] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57563,
      GIR_Done,
    // Label 2664: @72354
    GIM_Try, /*On fail goto*//*Label 2665*/ 72408, // Rule ID 57564 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs2, VRM4:{ *:[nxv8i32] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57564,
      GIR_Done,
    // Label 2665: @72408
    GIM_Try, /*On fail goto*//*Label 2666*/ 72462, // Rule ID 57571 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs2, VRM8:{ *:[nxv8i64] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57571,
      GIR_Done,
    // Label 2666: @72462
    GIM_Try, /*On fail goto*//*Label 2667*/ 72516, // Rule ID 57572 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs2, VRM8:{ *:[nxv8i64] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57572,
      GIR_Done,
    // Label 2667: @72516
    GIM_Try, /*On fail goto*//*Label 2668*/ 72570, // Rule ID 57585 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57585,
      GIR_Done,
    // Label 2668: @72570
    GIM_Try, /*On fail goto*//*Label 2669*/ 72624, // Rule ID 57586 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57586,
      GIR_Done,
    // Label 2669: @72624
    GIM_Try, /*On fail goto*//*Label 2670*/ 72678, // Rule ID 57599 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57599,
      GIR_Done,
    // Label 2670: @72678
    GIM_Try, /*On fail goto*//*Label 2671*/ 72732, // Rule ID 57600 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57600,
      GIR_Done,
    // Label 2671: @72732
    GIM_Try, /*On fail goto*//*Label 2672*/ 72786, // Rule ID 57607 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57607,
      GIR_Done,
    // Label 2672: @72786
    GIM_Try, /*On fail goto*//*Label 2673*/ 72840, // Rule ID 57608 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57608,
      GIR_Done,
    // Label 2673: @72840
    GIM_Try, /*On fail goto*//*Label 2674*/ 72894, // Rule ID 57615 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57615,
      GIR_Done,
    // Label 2674: @72894
    GIM_Try, /*On fail goto*//*Label 2675*/ 72948, // Rule ID 57616 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57616,
      GIR_Done,
    // Label 2675: @72948
    GIM_Try, /*On fail goto*//*Label 2676*/ 73002, // Rule ID 57629 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs2, VR:{ *:[nxv8i8] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57629,
      GIR_Done,
    // Label 2676: @73002
    GIM_Try, /*On fail goto*//*Label 2677*/ 73056, // Rule ID 57630 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs2, VR:{ *:[nxv8i8] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M1:{ *:[nxv8i1] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57630,
      GIR_Done,
    // Label 2677: @73056
    GIM_Try, /*On fail goto*//*Label 2678*/ 73110, // Rule ID 57643 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs2, VRM2:{ *:[nxv8i16] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57643,
      GIR_Done,
    // Label 2678: @73110
    GIM_Try, /*On fail goto*//*Label 2679*/ 73164, // Rule ID 57644 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs2, VRM2:{ *:[nxv8i16] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57644,
      GIR_Done,
    // Label 2679: @73164
    GIM_Try, /*On fail goto*//*Label 2680*/ 73218, // Rule ID 57651 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs2, VRM4:{ *:[nxv8i32] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57651,
      GIR_Done,
    // Label 2680: @73218
    GIM_Try, /*On fail goto*//*Label 2681*/ 73272, // Rule ID 57652 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs2, VRM4:{ *:[nxv8i32] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57652,
      GIR_Done,
    // Label 2681: @73272
    GIM_Try, /*On fail goto*//*Label 2682*/ 73326, // Rule ID 57659 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs2, VRM8:{ *:[nxv8i64] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57659,
      GIR_Done,
    // Label 2682: @73326
    GIM_Try, /*On fail goto*//*Label 2683*/ 73380, // Rule ID 57660 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs2, VRM8:{ *:[nxv8i64] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57660,
      GIR_Done,
    // Label 2683: @73380
    GIM_Reject,
    // Label 2336: @73381
    GIM_Try, /*On fail goto*//*Label 2684*/ 73435, // Rule ID 57243 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57243,
      GIR_Done,
    // Label 2684: @73435
    GIM_Try, /*On fail goto*//*Label 2685*/ 73489, // Rule ID 57244 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57244,
      GIR_Done,
    // Label 2685: @73489
    GIM_Try, /*On fail goto*//*Label 2686*/ 73543, // Rule ID 57251 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57251,
      GIR_Done,
    // Label 2686: @73543
    GIM_Try, /*On fail goto*//*Label 2687*/ 73597, // Rule ID 57252 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57252,
      GIR_Done,
    // Label 2687: @73597
    GIM_Try, /*On fail goto*//*Label 2688*/ 73651, // Rule ID 57259 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57259,
      GIR_Done,
    // Label 2688: @73651
    GIM_Try, /*On fail goto*//*Label 2689*/ 73705, // Rule ID 57260 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57260,
      GIR_Done,
    // Label 2689: @73705
    GIM_Try, /*On fail goto*//*Label 2690*/ 73759, // Rule ID 57287 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57287,
      GIR_Done,
    // Label 2690: @73759
    GIM_Try, /*On fail goto*//*Label 2691*/ 73813, // Rule ID 57288 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57288,
      GIR_Done,
    // Label 2691: @73813
    GIM_Try, /*On fail goto*//*Label 2692*/ 73867, // Rule ID 57295 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57295,
      GIR_Done,
    // Label 2692: @73867
    GIM_Try, /*On fail goto*//*Label 2693*/ 73921, // Rule ID 57296 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57296,
      GIR_Done,
    // Label 2693: @73921
    GIM_Try, /*On fail goto*//*Label 2694*/ 73975, // Rule ID 57303 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57303,
      GIR_Done,
    // Label 2694: @73975
    GIM_Try, /*On fail goto*//*Label 2695*/ 74029, // Rule ID 57304 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57304,
      GIR_Done,
    // Label 2695: @74029
    GIM_Try, /*On fail goto*//*Label 2696*/ 74083, // Rule ID 57331 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57331,
      GIR_Done,
    // Label 2696: @74083
    GIM_Try, /*On fail goto*//*Label 2697*/ 74137, // Rule ID 57332 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57332,
      GIR_Done,
    // Label 2697: @74137
    GIM_Try, /*On fail goto*//*Label 2698*/ 74191, // Rule ID 57339 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57339,
      GIR_Done,
    // Label 2698: @74191
    GIM_Try, /*On fail goto*//*Label 2699*/ 74245, // Rule ID 57340 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57340,
      GIR_Done,
    // Label 2699: @74245
    GIM_Try, /*On fail goto*//*Label 2700*/ 74299, // Rule ID 57347 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57347,
      GIR_Done,
    // Label 2700: @74299
    GIM_Try, /*On fail goto*//*Label 2701*/ 74353, // Rule ID 57348 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57348,
      GIR_Done,
    // Label 2701: @74353
    GIM_Try, /*On fail goto*//*Label 2702*/ 74407, // Rule ID 57373 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs2, VRM2:{ *:[nxv16i8] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57373,
      GIR_Done,
    // Label 2702: @74407
    GIM_Try, /*On fail goto*//*Label 2703*/ 74461, // Rule ID 57374 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs2, VRM2:{ *:[nxv16i8] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57374,
      GIR_Done,
    // Label 2703: @74461
    GIM_Try, /*On fail goto*//*Label 2704*/ 74515, // Rule ID 57381 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs2, VRM4:{ *:[nxv16i16] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57381,
      GIR_Done,
    // Label 2704: @74515
    GIM_Try, /*On fail goto*//*Label 2705*/ 74569, // Rule ID 57382 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs2, VRM4:{ *:[nxv16i16] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57382,
      GIR_Done,
    // Label 2705: @74569
    GIM_Try, /*On fail goto*//*Label 2706*/ 74623, // Rule ID 57389 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs2, VRM8:{ *:[nxv16i32] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57389,
      GIR_Done,
    // Label 2706: @74623
    GIM_Try, /*On fail goto*//*Label 2707*/ 74677, // Rule ID 57390 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs2, VRM8:{ *:[nxv16i32] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57390,
      GIR_Done,
    // Label 2707: @74677
    GIM_Try, /*On fail goto*//*Label 2708*/ 74731, // Rule ID 57417 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57417,
      GIR_Done,
    // Label 2708: @74731
    GIM_Try, /*On fail goto*//*Label 2709*/ 74785, // Rule ID 57418 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57418,
      GIR_Done,
    // Label 2709: @74785
    GIM_Try, /*On fail goto*//*Label 2710*/ 74839, // Rule ID 57425 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57425,
      GIR_Done,
    // Label 2710: @74839
    GIM_Try, /*On fail goto*//*Label 2711*/ 74893, // Rule ID 57426 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57426,
      GIR_Done,
    // Label 2711: @74893
    GIM_Try, /*On fail goto*//*Label 2712*/ 74947, // Rule ID 57433 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57433,
      GIR_Done,
    // Label 2712: @74947
    GIM_Try, /*On fail goto*//*Label 2713*/ 75001, // Rule ID 57434 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57434,
      GIR_Done,
    // Label 2713: @75001
    GIM_Try, /*On fail goto*//*Label 2714*/ 75055, // Rule ID 57461 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs2, VRM2:{ *:[nxv16i8] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57461,
      GIR_Done,
    // Label 2714: @75055
    GIM_Try, /*On fail goto*//*Label 2715*/ 75109, // Rule ID 57462 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs2, VRM2:{ *:[nxv16i8] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57462,
      GIR_Done,
    // Label 2715: @75109
    GIM_Try, /*On fail goto*//*Label 2716*/ 75163, // Rule ID 57469 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs2, VRM4:{ *:[nxv16i16] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57469,
      GIR_Done,
    // Label 2716: @75163
    GIM_Try, /*On fail goto*//*Label 2717*/ 75217, // Rule ID 57470 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs2, VRM4:{ *:[nxv16i16] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57470,
      GIR_Done,
    // Label 2717: @75217
    GIM_Try, /*On fail goto*//*Label 2718*/ 75271, // Rule ID 57477 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs2, VRM8:{ *:[nxv16i32] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57477,
      GIR_Done,
    // Label 2718: @75271
    GIM_Try, /*On fail goto*//*Label 2719*/ 75325, // Rule ID 57478 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs2, VRM8:{ *:[nxv16i32] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57478,
      GIR_Done,
    // Label 2719: @75325
    GIM_Try, /*On fail goto*//*Label 2720*/ 75379, // Rule ID 57505 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57505,
      GIR_Done,
    // Label 2720: @75379
    GIM_Try, /*On fail goto*//*Label 2721*/ 75433, // Rule ID 57506 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57506,
      GIR_Done,
    // Label 2721: @75433
    GIM_Try, /*On fail goto*//*Label 2722*/ 75487, // Rule ID 57513 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57513,
      GIR_Done,
    // Label 2722: @75487
    GIM_Try, /*On fail goto*//*Label 2723*/ 75541, // Rule ID 57514 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57514,
      GIR_Done,
    // Label 2723: @75541
    GIM_Try, /*On fail goto*//*Label 2724*/ 75595, // Rule ID 57521 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57521,
      GIR_Done,
    // Label 2724: @75595
    GIM_Try, /*On fail goto*//*Label 2725*/ 75649, // Rule ID 57522 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57522,
      GIR_Done,
    // Label 2725: @75649
    GIM_Try, /*On fail goto*//*Label 2726*/ 75703, // Rule ID 57549 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs2, VRM2:{ *:[nxv16i8] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57549,
      GIR_Done,
    // Label 2726: @75703
    GIM_Try, /*On fail goto*//*Label 2727*/ 75757, // Rule ID 57550 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs2, VRM2:{ *:[nxv16i8] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57550,
      GIR_Done,
    // Label 2727: @75757
    GIM_Try, /*On fail goto*//*Label 2728*/ 75811, // Rule ID 57557 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs2, VRM4:{ *:[nxv16i16] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57557,
      GIR_Done,
    // Label 2728: @75811
    GIM_Try, /*On fail goto*//*Label 2729*/ 75865, // Rule ID 57558 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs2, VRM4:{ *:[nxv16i16] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57558,
      GIR_Done,
    // Label 2729: @75865
    GIM_Try, /*On fail goto*//*Label 2730*/ 75919, // Rule ID 57565 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs2, VRM8:{ *:[nxv16i32] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57565,
      GIR_Done,
    // Label 2730: @75919
    GIM_Try, /*On fail goto*//*Label 2731*/ 75973, // Rule ID 57566 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs2, VRM8:{ *:[nxv16i32] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57566,
      GIR_Done,
    // Label 2731: @75973
    GIM_Try, /*On fail goto*//*Label 2732*/ 76027, // Rule ID 57593 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57593,
      GIR_Done,
    // Label 2732: @76027
    GIM_Try, /*On fail goto*//*Label 2733*/ 76081, // Rule ID 57594 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57594,
      GIR_Done,
    // Label 2733: @76081
    GIM_Try, /*On fail goto*//*Label 2734*/ 76135, // Rule ID 57601 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57601,
      GIR_Done,
    // Label 2734: @76135
    GIM_Try, /*On fail goto*//*Label 2735*/ 76189, // Rule ID 57602 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57602,
      GIR_Done,
    // Label 2735: @76189
    GIM_Try, /*On fail goto*//*Label 2736*/ 76243, // Rule ID 57609 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57609,
      GIR_Done,
    // Label 2736: @76243
    GIM_Try, /*On fail goto*//*Label 2737*/ 76297, // Rule ID 57610 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57610,
      GIR_Done,
    // Label 2737: @76297
    GIM_Try, /*On fail goto*//*Label 2738*/ 76351, // Rule ID 57637 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs2, VRM2:{ *:[nxv16i8] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57637,
      GIR_Done,
    // Label 2738: @76351
    GIM_Try, /*On fail goto*//*Label 2739*/ 76405, // Rule ID 57638 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs2, VRM2:{ *:[nxv16i8] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M2:{ *:[nxv16i1] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57638,
      GIR_Done,
    // Label 2739: @76405
    GIM_Try, /*On fail goto*//*Label 2740*/ 76459, // Rule ID 57645 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs2, VRM4:{ *:[nxv16i16] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57645,
      GIR_Done,
    // Label 2740: @76459
    GIM_Try, /*On fail goto*//*Label 2741*/ 76513, // Rule ID 57646 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs2, VRM4:{ *:[nxv16i16] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57646,
      GIR_Done,
    // Label 2741: @76513
    GIM_Try, /*On fail goto*//*Label 2742*/ 76567, // Rule ID 57653 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs2, VRM8:{ *:[nxv16i32] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57653,
      GIR_Done,
    // Label 2742: @76567
    GIM_Try, /*On fail goto*//*Label 2743*/ 76621, // Rule ID 57654 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs2, VRM8:{ *:[nxv16i32] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57654,
      GIR_Done,
    // Label 2743: @76621
    GIM_Reject,
    // Label 2337: @76622
    GIM_Try, /*On fail goto*//*Label 2744*/ 76676, // Rule ID 57245 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57245,
      GIR_Done,
    // Label 2744: @76676
    GIM_Try, /*On fail goto*//*Label 2745*/ 76730, // Rule ID 57246 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57246,
      GIR_Done,
    // Label 2745: @76730
    GIM_Try, /*On fail goto*//*Label 2746*/ 76784, // Rule ID 57253 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57253,
      GIR_Done,
    // Label 2746: @76784
    GIM_Try, /*On fail goto*//*Label 2747*/ 76838, // Rule ID 57254 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57254,
      GIR_Done,
    // Label 2747: @76838
    GIM_Try, /*On fail goto*//*Label 2748*/ 76892, // Rule ID 57289 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57289,
      GIR_Done,
    // Label 2748: @76892
    GIM_Try, /*On fail goto*//*Label 2749*/ 76946, // Rule ID 57290 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57290,
      GIR_Done,
    // Label 2749: @76946
    GIM_Try, /*On fail goto*//*Label 2750*/ 77000, // Rule ID 57297 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57297,
      GIR_Done,
    // Label 2750: @77000
    GIM_Try, /*On fail goto*//*Label 2751*/ 77054, // Rule ID 57298 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57298,
      GIR_Done,
    // Label 2751: @77054
    GIM_Try, /*On fail goto*//*Label 2752*/ 77108, // Rule ID 57333 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57333,
      GIR_Done,
    // Label 2752: @77108
    GIM_Try, /*On fail goto*//*Label 2753*/ 77162, // Rule ID 57334 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57334,
      GIR_Done,
    // Label 2753: @77162
    GIM_Try, /*On fail goto*//*Label 2754*/ 77216, // Rule ID 57341 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57341,
      GIR_Done,
    // Label 2754: @77216
    GIM_Try, /*On fail goto*//*Label 2755*/ 77270, // Rule ID 57342 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57342,
      GIR_Done,
    // Label 2755: @77270
    GIM_Try, /*On fail goto*//*Label 2756*/ 77324, // Rule ID 57375 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs2, VRM4:{ *:[nxv32i8] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57375,
      GIR_Done,
    // Label 2756: @77324
    GIM_Try, /*On fail goto*//*Label 2757*/ 77378, // Rule ID 57376 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs2, VRM4:{ *:[nxv32i8] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57376,
      GIR_Done,
    // Label 2757: @77378
    GIM_Try, /*On fail goto*//*Label 2758*/ 77432, // Rule ID 57383 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs2, VRM8:{ *:[nxv32i16] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57383,
      GIR_Done,
    // Label 2758: @77432
    GIM_Try, /*On fail goto*//*Label 2759*/ 77486, // Rule ID 57384 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs2, VRM8:{ *:[nxv32i16] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57384,
      GIR_Done,
    // Label 2759: @77486
    GIM_Try, /*On fail goto*//*Label 2760*/ 77540, // Rule ID 57419 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57419,
      GIR_Done,
    // Label 2760: @77540
    GIM_Try, /*On fail goto*//*Label 2761*/ 77594, // Rule ID 57420 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57420,
      GIR_Done,
    // Label 2761: @77594
    GIM_Try, /*On fail goto*//*Label 2762*/ 77648, // Rule ID 57427 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57427,
      GIR_Done,
    // Label 2762: @77648
    GIM_Try, /*On fail goto*//*Label 2763*/ 77702, // Rule ID 57428 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57428,
      GIR_Done,
    // Label 2763: @77702
    GIM_Try, /*On fail goto*//*Label 2764*/ 77756, // Rule ID 57463 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs2, VRM4:{ *:[nxv32i8] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57463,
      GIR_Done,
    // Label 2764: @77756
    GIM_Try, /*On fail goto*//*Label 2765*/ 77810, // Rule ID 57464 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs2, VRM4:{ *:[nxv32i8] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57464,
      GIR_Done,
    // Label 2765: @77810
    GIM_Try, /*On fail goto*//*Label 2766*/ 77864, // Rule ID 57471 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs2, VRM8:{ *:[nxv32i16] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57471,
      GIR_Done,
    // Label 2766: @77864
    GIM_Try, /*On fail goto*//*Label 2767*/ 77918, // Rule ID 57472 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs2, VRM8:{ *:[nxv32i16] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57472,
      GIR_Done,
    // Label 2767: @77918
    GIM_Try, /*On fail goto*//*Label 2768*/ 77972, // Rule ID 57507 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57507,
      GIR_Done,
    // Label 2768: @77972
    GIM_Try, /*On fail goto*//*Label 2769*/ 78026, // Rule ID 57508 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57508,
      GIR_Done,
    // Label 2769: @78026
    GIM_Try, /*On fail goto*//*Label 2770*/ 78080, // Rule ID 57515 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57515,
      GIR_Done,
    // Label 2770: @78080
    GIM_Try, /*On fail goto*//*Label 2771*/ 78134, // Rule ID 57516 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57516,
      GIR_Done,
    // Label 2771: @78134
    GIM_Try, /*On fail goto*//*Label 2772*/ 78188, // Rule ID 57551 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs2, VRM4:{ *:[nxv32i8] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57551,
      GIR_Done,
    // Label 2772: @78188
    GIM_Try, /*On fail goto*//*Label 2773*/ 78242, // Rule ID 57552 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs2, VRM4:{ *:[nxv32i8] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57552,
      GIR_Done,
    // Label 2773: @78242
    GIM_Try, /*On fail goto*//*Label 2774*/ 78296, // Rule ID 57559 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs2, VRM8:{ *:[nxv32i16] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57559,
      GIR_Done,
    // Label 2774: @78296
    GIM_Try, /*On fail goto*//*Label 2775*/ 78350, // Rule ID 57560 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs2, VRM8:{ *:[nxv32i16] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57560,
      GIR_Done,
    // Label 2775: @78350
    GIM_Try, /*On fail goto*//*Label 2776*/ 78404, // Rule ID 57595 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57595,
      GIR_Done,
    // Label 2776: @78404
    GIM_Try, /*On fail goto*//*Label 2777*/ 78458, // Rule ID 57596 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57596,
      GIR_Done,
    // Label 2777: @78458
    GIM_Try, /*On fail goto*//*Label 2778*/ 78512, // Rule ID 57603 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57603,
      GIR_Done,
    // Label 2778: @78512
    GIM_Try, /*On fail goto*//*Label 2779*/ 78566, // Rule ID 57604 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57604,
      GIR_Done,
    // Label 2779: @78566
    GIM_Try, /*On fail goto*//*Label 2780*/ 78620, // Rule ID 57639 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs2, VRM4:{ *:[nxv32i8] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57639,
      GIR_Done,
    // Label 2780: @78620
    GIM_Try, /*On fail goto*//*Label 2781*/ 78674, // Rule ID 57640 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs2, VRM4:{ *:[nxv32i8] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M4:{ *:[nxv32i1] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57640,
      GIR_Done,
    // Label 2781: @78674
    GIM_Try, /*On fail goto*//*Label 2782*/ 78728, // Rule ID 57647 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs2, VRM8:{ *:[nxv32i16] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57647,
      GIR_Done,
    // Label 2782: @78728
    GIM_Try, /*On fail goto*//*Label 2783*/ 78782, // Rule ID 57648 //
      GIM_CheckFeatures, GIFBS_HasVInstructions,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs2, VRM8:{ *:[nxv32i16] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 57648,
      GIR_Done,
    // Label 2783: @78782
    GIM_Reject,
    // Label 2338: @78783
    GIM_Try, /*On fail goto*//*Label 2784*/ 79638,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s8,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv64s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2785*/ 78839, // Rule ID 57247 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57247,
        GIR_Done,
      // Label 2785: @78839
      GIM_Try, /*On fail goto*//*Label 2786*/ 78881, // Rule ID 57248 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, SETEQ:{ *:[Other] })  =>  (PseudoVMSEQ_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSEQ_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57248,
        GIR_Done,
      // Label 2786: @78881
      GIM_Try, /*On fail goto*//*Label 2787*/ 78923, // Rule ID 57291 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57291,
        GIR_Done,
      // Label 2787: @78923
      GIM_Try, /*On fail goto*//*Label 2788*/ 78965, // Rule ID 57292 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, SETNE:{ *:[Other] })  =>  (PseudoVMSNE_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSNE_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57292,
        GIR_Done,
      // Label 2788: @78965
      GIM_Try, /*On fail goto*//*Label 2789*/ 79007, // Rule ID 57335 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57335,
        GIR_Done,
      // Label 2789: @79007
      GIM_Try, /*On fail goto*//*Label 2790*/ 79049, // Rule ID 57336 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, SETLT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57336,
        GIR_Done,
      // Label 2790: @79049
      GIM_Try, /*On fail goto*//*Label 2791*/ 79091, // Rule ID 57377 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs2, VRM8:{ *:[nxv64i8] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57377,
        GIR_Done,
      // Label 2791: @79091
      GIM_Try, /*On fail goto*//*Label 2792*/ 79133, // Rule ID 57378 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs2, VRM8:{ *:[nxv64i8] }:$rs1, SETGT:{ *:[Other] })  =>  (PseudoVMSLT_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLT_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57378,
        GIR_Done,
      // Label 2792: @79133
      GIM_Try, /*On fail goto*//*Label 2793*/ 79175, // Rule ID 57421 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57421,
        GIR_Done,
      // Label 2793: @79175
      GIM_Try, /*On fail goto*//*Label 2794*/ 79217, // Rule ID 57422 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, SETULT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57422,
        GIR_Done,
      // Label 2794: @79217
      GIM_Try, /*On fail goto*//*Label 2795*/ 79259, // Rule ID 57465 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs2, VRM8:{ *:[nxv64i8] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57465,
        GIR_Done,
      // Label 2795: @79259
      GIM_Try, /*On fail goto*//*Label 2796*/ 79301, // Rule ID 57466 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs2, VRM8:{ *:[nxv64i8] }:$rs1, SETUGT:{ *:[Other] })  =>  (PseudoVMSLTU_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLTU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57466,
        GIR_Done,
      // Label 2796: @79301
      GIM_Try, /*On fail goto*//*Label 2797*/ 79343, // Rule ID 57509 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57509,
        GIR_Done,
      // Label 2797: @79343
      GIM_Try, /*On fail goto*//*Label 2798*/ 79385, // Rule ID 57510 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, SETLE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57510,
        GIR_Done,
      // Label 2798: @79385
      GIM_Try, /*On fail goto*//*Label 2799*/ 79427, // Rule ID 57553 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs2, VRM8:{ *:[nxv64i8] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57553,
        GIR_Done,
      // Label 2799: @79427
      GIM_Try, /*On fail goto*//*Label 2800*/ 79469, // Rule ID 57554 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs2, VRM8:{ *:[nxv64i8] }:$rs1, SETGE:{ *:[Other] })  =>  (PseudoVMSLE_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLE_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57554,
        GIR_Done,
      // Label 2800: @79469
      GIM_Try, /*On fail goto*//*Label 2801*/ 79511, // Rule ID 57597 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57597,
        GIR_Done,
      // Label 2801: @79511
      GIM_Try, /*On fail goto*//*Label 2802*/ 79553, // Rule ID 57598 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, SETULE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57598,
        GIR_Done,
      // Label 2802: @79553
      GIM_Try, /*On fail goto*//*Label 2803*/ 79595, // Rule ID 57641 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs2, VRM8:{ *:[nxv64i8] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57641,
        GIR_Done,
      // Label 2803: @79595
      GIM_Try, /*On fail goto*//*Label 2804*/ 79637, // Rule ID 57642 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs2, VRM8:{ *:[nxv64i8] }:$rs1, SETUGE:{ *:[Other] })  =>  (PseudoVMSLEU_VV_M8:{ *:[nxv64i1] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMSLEU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57642,
        GIR_Done,
      // Label 2804: @79637
      GIM_Reject,
    // Label 2784: @79638
    GIM_Reject,
    // Label 2339: @79639
    GIM_Reject,
    // Label 37: @79640
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/3, 28, /*)*//*default:*//*Label 2811*/ 86076,
    /*GILLT_nxv1s1*//*Label 2805*/ 79671, 0, 0, 0, 0,
    /*GILLT_nxv2s1*//*Label 2806*/ 80968, 0, 0, 0, 0,
    /*GILLT_nxv4s1*//*Label 2807*/ 82265, 0, 0, 0, 0,
    /*GILLT_nxv8s1*//*Label 2808*/ 83562, 0, 0, 0, 0,
    /*GILLT_nxv16s1*//*Label 2809*/ 84859, 0, 0, 0,
    /*GILLT_nxv32s1*//*Label 2810*/ 85724,
    // Label 2805: @79671
    GIM_Try, /*On fail goto*//*Label 2812*/ 79725, // Rule ID 63384 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63384,
      GIR_Done,
    // Label 2812: @79725
    GIM_Try, /*On fail goto*//*Label 2813*/ 79779, // Rule ID 63385 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63385,
      GIR_Done,
    // Label 2813: @79779
    GIM_Try, /*On fail goto*//*Label 2814*/ 79833, // Rule ID 63398 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63398,
      GIR_Done,
    // Label 2814: @79833
    GIM_Try, /*On fail goto*//*Label 2815*/ 79887, // Rule ID 63399 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63399,
      GIR_Done,
    // Label 2815: @79887
    GIM_Try, /*On fail goto*//*Label 2816*/ 79941, // Rule ID 63418 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63418,
      GIR_Done,
    // Label 2816: @79941
    GIM_Try, /*On fail goto*//*Label 2817*/ 79995, // Rule ID 63419 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63419,
      GIR_Done,
    // Label 2817: @79995
    GIM_Try, /*On fail goto*//*Label 2818*/ 80049, // Rule ID 63574 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63574,
      GIR_Done,
    // Label 2818: @80049
    GIM_Try, /*On fail goto*//*Label 2819*/ 80103, // Rule ID 63575 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63575,
      GIR_Done,
    // Label 2819: @80103
    GIM_Try, /*On fail goto*//*Label 2820*/ 80157, // Rule ID 63587 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63587,
      GIR_Done,
    // Label 2820: @80157
    GIM_Try, /*On fail goto*//*Label 2821*/ 80211, // Rule ID 63588 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63588,
      GIR_Done,
    // Label 2821: @80211
    GIM_Try, /*On fail goto*//*Label 2822*/ 80265, // Rule ID 63606 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63606,
      GIR_Done,
    // Label 2822: @80265
    GIM_Try, /*On fail goto*//*Label 2823*/ 80319, // Rule ID 63607 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63607,
      GIR_Done,
    // Label 2823: @80319
    GIM_Try, /*On fail goto*//*Label 2824*/ 80373, // Rule ID 63764 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63764,
      GIR_Done,
    // Label 2824: @80373
    GIM_Try, /*On fail goto*//*Label 2825*/ 80427, // Rule ID 63765 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63765,
      GIR_Done,
    // Label 2825: @80427
    GIM_Try, /*On fail goto*//*Label 2826*/ 80481, // Rule ID 63776 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63776,
      GIR_Done,
    // Label 2826: @80481
    GIM_Try, /*On fail goto*//*Label 2827*/ 80535, // Rule ID 63777 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63777,
      GIR_Done,
    // Label 2827: @80535
    GIM_Try, /*On fail goto*//*Label 2828*/ 80589, // Rule ID 63794 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63794,
      GIR_Done,
    // Label 2828: @80589
    GIM_Try, /*On fail goto*//*Label 2829*/ 80643, // Rule ID 63795 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63795,
      GIR_Done,
    // Label 2829: @80643
    GIM_Try, /*On fail goto*//*Label 2830*/ 80697, // Rule ID 63952 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63952,
      GIR_Done,
    // Label 2830: @80697
    GIM_Try, /*On fail goto*//*Label 2831*/ 80751, // Rule ID 63953 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_MF4:{ *:[nxv1i1] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63953,
      GIR_Done,
    // Label 2831: @80751
    GIM_Try, /*On fail goto*//*Label 2832*/ 80805, // Rule ID 63964 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63964,
      GIR_Done,
    // Label 2832: @80805
    GIM_Try, /*On fail goto*//*Label 2833*/ 80859, // Rule ID 63965 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_MF2:{ *:[nxv1i1] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63965,
      GIR_Done,
    // Label 2833: @80859
    GIM_Try, /*On fail goto*//*Label 2834*/ 80913, // Rule ID 63984 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63984,
      GIR_Done,
    // Label 2834: @80913
    GIM_Try, /*On fail goto*//*Label 2835*/ 80967, // Rule ID 63985 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_M1:{ *:[nxv1i1] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63985,
      GIR_Done,
    // Label 2835: @80967
    GIM_Reject,
    // Label 2806: @80968
    GIM_Try, /*On fail goto*//*Label 2836*/ 81022, // Rule ID 63390 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63390,
      GIR_Done,
    // Label 2836: @81022
    GIM_Try, /*On fail goto*//*Label 2837*/ 81076, // Rule ID 63391 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63391,
      GIR_Done,
    // Label 2837: @81076
    GIM_Try, /*On fail goto*//*Label 2838*/ 81130, // Rule ID 63410 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63410,
      GIR_Done,
    // Label 2838: @81130
    GIM_Try, /*On fail goto*//*Label 2839*/ 81184, // Rule ID 63411 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63411,
      GIR_Done,
    // Label 2839: @81184
    GIM_Try, /*On fail goto*//*Label 2840*/ 81238, // Rule ID 63461 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63461,
      GIR_Done,
    // Label 2840: @81238
    GIM_Try, /*On fail goto*//*Label 2841*/ 81292, // Rule ID 63462 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63462,
      GIR_Done,
    // Label 2841: @81292
    GIM_Try, /*On fail goto*//*Label 2842*/ 81346, // Rule ID 63581 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63581,
      GIR_Done,
    // Label 2842: @81346
    GIM_Try, /*On fail goto*//*Label 2843*/ 81400, // Rule ID 63582 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63582,
      GIR_Done,
    // Label 2843: @81400
    GIM_Try, /*On fail goto*//*Label 2844*/ 81454, // Rule ID 63599 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63599,
      GIR_Done,
    // Label 2844: @81454
    GIM_Try, /*On fail goto*//*Label 2845*/ 81508, // Rule ID 63600 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63600,
      GIR_Done,
    // Label 2845: @81508
    GIM_Try, /*On fail goto*//*Label 2846*/ 81562, // Rule ID 63650 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63650,
      GIR_Done,
    // Label 2846: @81562
    GIM_Try, /*On fail goto*//*Label 2847*/ 81616, // Rule ID 63651 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63651,
      GIR_Done,
    // Label 2847: @81616
    GIM_Try, /*On fail goto*//*Label 2848*/ 81670, // Rule ID 63770 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63770,
      GIR_Done,
    // Label 2848: @81670
    GIM_Try, /*On fail goto*//*Label 2849*/ 81724, // Rule ID 63771 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63771,
      GIR_Done,
    // Label 2849: @81724
    GIM_Try, /*On fail goto*//*Label 2850*/ 81778, // Rule ID 63788 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63788,
      GIR_Done,
    // Label 2850: @81778
    GIM_Try, /*On fail goto*//*Label 2851*/ 81832, // Rule ID 63789 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63789,
      GIR_Done,
    // Label 2851: @81832
    GIM_Try, /*On fail goto*//*Label 2852*/ 81886, // Rule ID 63838 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63838,
      GIR_Done,
    // Label 2852: @81886
    GIM_Try, /*On fail goto*//*Label 2853*/ 81940, // Rule ID 63839 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63839,
      GIR_Done,
    // Label 2853: @81940
    GIM_Try, /*On fail goto*//*Label 2854*/ 81994, // Rule ID 63958 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63958,
      GIR_Done,
    // Label 2854: @81994
    GIM_Try, /*On fail goto*//*Label 2855*/ 82048, // Rule ID 63959 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_MF2:{ *:[nxv2i1] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63959,
      GIR_Done,
    // Label 2855: @82048
    GIM_Try, /*On fail goto*//*Label 2856*/ 82102, // Rule ID 63978 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63978,
      GIR_Done,
    // Label 2856: @82102
    GIM_Try, /*On fail goto*//*Label 2857*/ 82156, // Rule ID 63979 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_M1:{ *:[nxv2i1] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63979,
      GIR_Done,
    // Label 2857: @82156
    GIM_Try, /*On fail goto*//*Label 2858*/ 82210, // Rule ID 64030 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64030,
      GIR_Done,
    // Label 2858: @82210
    GIM_Try, /*On fail goto*//*Label 2859*/ 82264, // Rule ID 64031 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_M2:{ *:[nxv2i1] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64031,
      GIR_Done,
    // Label 2859: @82264
    GIM_Reject,
    // Label 2807: @82265
    GIM_Try, /*On fail goto*//*Label 2860*/ 82319, // Rule ID 63404 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63404,
      GIR_Done,
    // Label 2860: @82319
    GIM_Try, /*On fail goto*//*Label 2861*/ 82373, // Rule ID 63405 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63405,
      GIR_Done,
    // Label 2861: @82373
    GIM_Try, /*On fail goto*//*Label 2862*/ 82427, // Rule ID 63443 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63443,
      GIR_Done,
    // Label 2862: @82427
    GIM_Try, /*On fail goto*//*Label 2863*/ 82481, // Rule ID 63444 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63444,
      GIR_Done,
    // Label 2863: @82481
    GIM_Try, /*On fail goto*//*Label 2864*/ 82535, // Rule ID 63467 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63467,
      GIR_Done,
    // Label 2864: @82535
    GIM_Try, /*On fail goto*//*Label 2865*/ 82589, // Rule ID 63468 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63468,
      GIR_Done,
    // Label 2865: @82589
    GIM_Try, /*On fail goto*//*Label 2866*/ 82643, // Rule ID 63593 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63593,
      GIR_Done,
    // Label 2866: @82643
    GIM_Try, /*On fail goto*//*Label 2867*/ 82697, // Rule ID 63594 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63594,
      GIR_Done,
    // Label 2867: @82697
    GIM_Try, /*On fail goto*//*Label 2868*/ 82751, // Rule ID 63632 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63632,
      GIR_Done,
    // Label 2868: @82751
    GIM_Try, /*On fail goto*//*Label 2869*/ 82805, // Rule ID 63633 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63633,
      GIR_Done,
    // Label 2869: @82805
    GIM_Try, /*On fail goto*//*Label 2870*/ 82859, // Rule ID 63656 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63656,
      GIR_Done,
    // Label 2870: @82859
    GIM_Try, /*On fail goto*//*Label 2871*/ 82913, // Rule ID 63657 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63657,
      GIR_Done,
    // Label 2871: @82913
    GIM_Try, /*On fail goto*//*Label 2872*/ 82967, // Rule ID 63782 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63782,
      GIR_Done,
    // Label 2872: @82967
    GIM_Try, /*On fail goto*//*Label 2873*/ 83021, // Rule ID 63783 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63783,
      GIR_Done,
    // Label 2873: @83021
    GIM_Try, /*On fail goto*//*Label 2874*/ 83075, // Rule ID 63820 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63820,
      GIR_Done,
    // Label 2874: @83075
    GIM_Try, /*On fail goto*//*Label 2875*/ 83129, // Rule ID 63821 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63821,
      GIR_Done,
    // Label 2875: @83129
    GIM_Try, /*On fail goto*//*Label 2876*/ 83183, // Rule ID 63844 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63844,
      GIR_Done,
    // Label 2876: @83183
    GIM_Try, /*On fail goto*//*Label 2877*/ 83237, // Rule ID 63845 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63845,
      GIR_Done,
    // Label 2877: @83237
    GIM_Try, /*On fail goto*//*Label 2878*/ 83291, // Rule ID 63972 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63972,
      GIR_Done,
    // Label 2878: @83291
    GIM_Try, /*On fail goto*//*Label 2879*/ 83345, // Rule ID 63973 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
      // (setcc:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_M1:{ *:[nxv4i1] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63973,
      GIR_Done,
    // Label 2879: @83345
    GIM_Try, /*On fail goto*//*Label 2880*/ 83399, // Rule ID 64010 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64010,
      GIR_Done,
    // Label 2880: @83399
    GIM_Try, /*On fail goto*//*Label 2881*/ 83453, // Rule ID 64011 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_M2:{ *:[nxv4i1] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64011,
      GIR_Done,
    // Label 2881: @83453
    GIM_Try, /*On fail goto*//*Label 2882*/ 83507, // Rule ID 64038 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64038,
      GIR_Done,
    // Label 2882: @83507
    GIM_Try, /*On fail goto*//*Label 2883*/ 83561, // Rule ID 64039 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_M4:{ *:[nxv4i1] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64039,
      GIR_Done,
    // Label 2883: @83561
    GIM_Reject,
    // Label 2808: @83562
    GIM_Try, /*On fail goto*//*Label 2884*/ 83616, // Rule ID 63424 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63424,
      GIR_Done,
    // Label 2884: @83616
    GIM_Try, /*On fail goto*//*Label 2885*/ 83670, // Rule ID 63425 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63425,
      GIR_Done,
    // Label 2885: @83670
    GIM_Try, /*On fail goto*//*Label 2886*/ 83724, // Rule ID 63449 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63449,
      GIR_Done,
    // Label 2886: @83724
    GIM_Try, /*On fail goto*//*Label 2887*/ 83778, // Rule ID 63450 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63450,
      GIR_Done,
    // Label 2887: @83778
    GIM_Try, /*On fail goto*//*Label 2888*/ 83832, // Rule ID 63473 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63473,
      GIR_Done,
    // Label 2888: @83832
    GIM_Try, /*On fail goto*//*Label 2889*/ 83886, // Rule ID 63474 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63474,
      GIR_Done,
    // Label 2889: @83886
    GIM_Try, /*On fail goto*//*Label 2890*/ 83940, // Rule ID 63612 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63612,
      GIR_Done,
    // Label 2890: @83940
    GIM_Try, /*On fail goto*//*Label 2891*/ 83994, // Rule ID 63613 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63613,
      GIR_Done,
    // Label 2891: @83994
    GIM_Try, /*On fail goto*//*Label 2892*/ 84048, // Rule ID 63638 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63638,
      GIR_Done,
    // Label 2892: @84048
    GIM_Try, /*On fail goto*//*Label 2893*/ 84102, // Rule ID 63639 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63639,
      GIR_Done,
    // Label 2893: @84102
    GIM_Try, /*On fail goto*//*Label 2894*/ 84156, // Rule ID 63662 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63662,
      GIR_Done,
    // Label 2894: @84156
    GIM_Try, /*On fail goto*//*Label 2895*/ 84210, // Rule ID 63663 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63663,
      GIR_Done,
    // Label 2895: @84210
    GIM_Try, /*On fail goto*//*Label 2896*/ 84264, // Rule ID 63800 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63800,
      GIR_Done,
    // Label 2896: @84264
    GIM_Try, /*On fail goto*//*Label 2897*/ 84318, // Rule ID 63801 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63801,
      GIR_Done,
    // Label 2897: @84318
    GIM_Try, /*On fail goto*//*Label 2898*/ 84372, // Rule ID 63826 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63826,
      GIR_Done,
    // Label 2898: @84372
    GIM_Try, /*On fail goto*//*Label 2899*/ 84426, // Rule ID 63827 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63827,
      GIR_Done,
    // Label 2899: @84426
    GIM_Try, /*On fail goto*//*Label 2900*/ 84480, // Rule ID 63852 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63852,
      GIR_Done,
    // Label 2900: @84480
    GIM_Try, /*On fail goto*//*Label 2901*/ 84534, // Rule ID 63853 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63853,
      GIR_Done,
    // Label 2901: @84534
    GIM_Try, /*On fail goto*//*Label 2902*/ 84588, // Rule ID 63990 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63990,
      GIR_Done,
    // Label 2902: @84588
    GIM_Try, /*On fail goto*//*Label 2903*/ 84642, // Rule ID 63991 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_M2:{ *:[nxv8i1] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63991,
      GIR_Done,
    // Label 2903: @84642
    GIM_Try, /*On fail goto*//*Label 2904*/ 84696, // Rule ID 64018 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64018,
      GIR_Done,
    // Label 2904: @84696
    GIM_Try, /*On fail goto*//*Label 2905*/ 84750, // Rule ID 64019 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_M4:{ *:[nxv8i1] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64019,
      GIR_Done,
    // Label 2905: @84750
    GIM_Try, /*On fail goto*//*Label 2906*/ 84804, // Rule ID 64044 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64044,
      GIR_Done,
    // Label 2906: @84804
    GIM_Try, /*On fail goto*//*Label 2907*/ 84858, // Rule ID 64045 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_M8:{ *:[nxv8i1] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64045,
      GIR_Done,
    // Label 2907: @84858
    GIM_Reject,
    // Label 2809: @84859
    GIM_Try, /*On fail goto*//*Label 2908*/ 84913, // Rule ID 63430 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63430,
      GIR_Done,
    // Label 2908: @84913
    GIM_Try, /*On fail goto*//*Label 2909*/ 84967, // Rule ID 63431 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63431,
      GIR_Done,
    // Label 2909: @84967
    GIM_Try, /*On fail goto*//*Label 2910*/ 85021, // Rule ID 63455 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63455,
      GIR_Done,
    // Label 2910: @85021
    GIM_Try, /*On fail goto*//*Label 2911*/ 85075, // Rule ID 63456 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63456,
      GIR_Done,
    // Label 2911: @85075
    GIM_Try, /*On fail goto*//*Label 2912*/ 85129, // Rule ID 63618 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63618,
      GIR_Done,
    // Label 2912: @85129
    GIM_Try, /*On fail goto*//*Label 2913*/ 85183, // Rule ID 63619 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63619,
      GIR_Done,
    // Label 2913: @85183
    GIM_Try, /*On fail goto*//*Label 2914*/ 85237, // Rule ID 63644 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63644,
      GIR_Done,
    // Label 2914: @85237
    GIM_Try, /*On fail goto*//*Label 2915*/ 85291, // Rule ID 63645 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63645,
      GIR_Done,
    // Label 2915: @85291
    GIM_Try, /*On fail goto*//*Label 2916*/ 85345, // Rule ID 63808 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63808,
      GIR_Done,
    // Label 2916: @85345
    GIM_Try, /*On fail goto*//*Label 2917*/ 85399, // Rule ID 63809 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63809,
      GIR_Done,
    // Label 2917: @85399
    GIM_Try, /*On fail goto*//*Label 2918*/ 85453, // Rule ID 63832 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63832,
      GIR_Done,
    // Label 2918: @85453
    GIM_Try, /*On fail goto*//*Label 2919*/ 85507, // Rule ID 63833 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63833,
      GIR_Done,
    // Label 2919: @85507
    GIM_Try, /*On fail goto*//*Label 2920*/ 85561, // Rule ID 63998 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63998,
      GIR_Done,
    // Label 2920: @85561
    GIM_Try, /*On fail goto*//*Label 2921*/ 85615, // Rule ID 63999 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_M4:{ *:[nxv16i1] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63999,
      GIR_Done,
    // Label 2921: @85615
    GIM_Try, /*On fail goto*//*Label 2922*/ 85669, // Rule ID 64024 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64024,
      GIR_Done,
    // Label 2922: @85669
    GIM_Try, /*On fail goto*//*Label 2923*/ 85723, // Rule ID 64025 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      // MIs[0] Operand 1
      GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
      // (setcc:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_M8:{ *:[nxv16i1] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64025,
      GIR_Done,
    // Label 2923: @85723
    GIM_Reject,
    // Label 2810: @85724
    GIM_Try, /*On fail goto*//*Label 2924*/ 86075,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2925*/ 85780, // Rule ID 63436 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63436,
        GIR_Done,
      // Label 2925: @85780
      GIM_Try, /*On fail goto*//*Label 2926*/ 85822, // Rule ID 63437 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, SETOEQ:{ *:[Other] })  =>  (PseudoVMFEQ_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFEQ_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63437,
        GIR_Done,
      // Label 2926: @85822
      GIM_Try, /*On fail goto*//*Label 2927*/ 85864, // Rule ID 63626 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63626,
        GIR_Done,
      // Label 2927: @85864
      GIM_Try, /*On fail goto*//*Label 2928*/ 85906, // Rule ID 63627 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNE,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, SETUNE:{ *:[Other] })  =>  (PseudoVMFNE_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFNE_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63627,
        GIR_Done,
      // Label 2928: @85906
      GIM_Try, /*On fail goto*//*Label 2929*/ 85948, // Rule ID 63814 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63814,
        GIR_Done,
      // Label 2929: @85948
      GIM_Try, /*On fail goto*//*Label 2930*/ 85990, // Rule ID 63815 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLT,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, SETOLT:{ *:[Other] })  =>  (PseudoVMFLT_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLT_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63815,
        GIR_Done,
      // Label 2930: @85990
      GIM_Try, /*On fail goto*//*Label 2931*/ 86032, // Rule ID 64004 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64004,
        GIR_Done,
      // Label 2931: @86032
      GIM_Try, /*On fail goto*//*Label 2932*/ 86074, // Rule ID 64005 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // MIs[0] Operand 1
        GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OLE,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (setcc:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, SETOLE:{ *:[Other] })  =>  (PseudoVMFLE_VV_M8:{ *:[nxv32i1] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMFLE_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64005,
        GIR_Done,
      // Label 2932: @86074
      GIM_Reject,
    // Label 2924: @86075
    GIM_Reject,
    // Label 2811: @86076
    GIM_Reject,
    // Label 38: @86077
    GIM_Try, /*On fail goto*//*Label 2933*/ 87690,
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2934*/ 86360,
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        GIM_Try, /*On fail goto*//*Label 2935*/ 86162, // Rule ID 64810 //
          GIM_CheckFeatures, GIFBS_HasVendorXVentanaCondOps_IsRV64,
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
          GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
          // MIs[1] Operand 1
          GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          // (select:{ *:[i64] } (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rc, 0:{ *:[i64] }, SETNE:{ *:[Other] }), 0:{ *:[i64] }, GPR:{ *:[i64] }:$rs1)  =>  (VT_MASKCN:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rc)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::VT_MASKCN,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rc
          GIR_EraseFromParent, /*InsnID*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          // GIR_Coverage, 64810,
          GIR_Done,
        // Label 2935: @86162
        GIM_Try, /*On fail goto*//*Label 2936*/ 86215, // Rule ID 64811 //
          GIM_CheckFeatures, GIFBS_HasVendorXVentanaCondOps_IsRV64,
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
          GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
          // MIs[1] Operand 1
          GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          // (select:{ *:[i64] } (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rc, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), 0:{ *:[i64] }, GPR:{ *:[i64] }:$rs1)  =>  (VT_MASKC:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rc)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::VT_MASKC,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rc
          GIR_EraseFromParent, /*InsnID*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          // GIR_Coverage, 64811,
          GIR_Done,
        // Label 2936: @86215
        GIM_Try, /*On fail goto*//*Label 2937*/ 86287, // Rule ID 64820 //
          GIM_CheckFeatures, GIFBS_HasVendorXVentanaCondOps_IsRV64,
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
          GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
          // MIs[1] Operand 1
          GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckConstantInt, /*MI*/1, /*Op*/3, -2048,
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          // (select:{ *:[i64] } (setcc:{ *:[i64] } GPR:{ *:[i64] }:$x, -2048:{ *:[i64] }, SETNE:{ *:[Other] }), 0:{ *:[i64] }, GPR:{ *:[i64] }:$rs1)  =>  (VT_MASKCN:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (XORI:{ *:[i64] } GPR:{ *:[i64] }:$x, -2048:{ *:[i64] }))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XORI,
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
          GIR_AddImm, /*InsnID*/1, /*Imm*/-2048,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::VT_MASKCN,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          // GIR_Coverage, 64820,
          GIR_Done,
        // Label 2937: @86287
        GIM_Try, /*On fail goto*//*Label 2938*/ 86359, // Rule ID 64821 //
          GIM_CheckFeatures, GIFBS_HasVendorXVentanaCondOps_IsRV64,
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
          GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
          // MIs[1] Operand 1
          GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckConstantInt, /*MI*/1, /*Op*/3, -2048,
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          // (select:{ *:[i64] } (setcc:{ *:[i64] } GPR:{ *:[i64] }:$x, -2048:{ *:[i64] }, SETEQ:{ *:[Other] }), 0:{ *:[i64] }, GPR:{ *:[i64] }:$rs1)  =>  (VT_MASKC:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (XORI:{ *:[i64] } GPR:{ *:[i64] }:$x, -2048:{ *:[i64] }))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XORI,
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
          GIR_AddImm, /*InsnID*/1, /*Imm*/-2048,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::VT_MASKC,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          // GIR_Coverage, 64821,
          GIR_Done,
        // Label 2938: @86359
        GIM_Reject,
      // Label 2934: @86360
      GIM_Try, /*On fail goto*//*Label 2939*/ 87097,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_Try, /*On fail goto*//*Label 2940*/ 86423, // Rule ID 64808 //
          GIM_CheckFeatures, GIFBS_HasVendorXVentanaCondOps_IsRV64,
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
          GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
          // MIs[1] Operand 1
          GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
          GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          // (select:{ *:[i64] } (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rc, 0:{ *:[i64] }, SETNE:{ *:[Other] }), GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })  =>  (VT_MASKC:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rc)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::VT_MASKC,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rc
          GIR_EraseFromParent, /*InsnID*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          // GIR_Coverage, 64808,
          GIR_Done,
        // Label 2940: @86423
        GIM_Try, /*On fail goto*//*Label 2941*/ 86480, // Rule ID 64809 //
          GIM_CheckFeatures, GIFBS_HasVendorXVentanaCondOps_IsRV64,
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
          GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
          // MIs[1] Operand 1
          GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
          GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          // (select:{ *:[i64] } (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rc, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })  =>  (VT_MASKCN:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rc)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::VT_MASKCN,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rc
          GIR_EraseFromParent, /*InsnID*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          // GIR_Coverage, 64809,
          GIR_Done,
        // Label 2941: @86480
        GIM_Try, /*On fail goto*//*Label 2942*/ 86556, // Rule ID 64818 //
          GIM_CheckFeatures, GIFBS_HasVendorXVentanaCondOps_IsRV64,
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
          GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
          // MIs[1] Operand 1
          GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckConstantInt, /*MI*/1, /*Op*/3, -2048,
          GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          // (select:{ *:[i64] } (setcc:{ *:[i64] } GPR:{ *:[i64] }:$x, -2048:{ *:[i64] }, SETNE:{ *:[Other] }), GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })  =>  (VT_MASKC:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (XORI:{ *:[i64] } GPR:{ *:[i64] }:$x, -2048:{ *:[i64] }))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XORI,
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
          GIR_AddImm, /*InsnID*/1, /*Imm*/-2048,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::VT_MASKC,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          // GIR_Coverage, 64818,
          GIR_Done,
        // Label 2942: @86556
        GIM_Try, /*On fail goto*//*Label 2943*/ 86632, // Rule ID 64819 //
          GIM_CheckFeatures, GIFBS_HasVendorXVentanaCondOps_IsRV64,
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
          GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
          // MIs[1] Operand 1
          GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckConstantInt, /*MI*/1, /*Op*/3, -2048,
          GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          // (select:{ *:[i64] } (setcc:{ *:[i64] } GPR:{ *:[i64] }:$x, -2048:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })  =>  (VT_MASKCN:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (XORI:{ *:[i64] } GPR:{ *:[i64] }:$x, -2048:{ *:[i64] }))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XORI,
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
          GIR_AddImm, /*InsnID*/1, /*Imm*/-2048,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::VT_MASKCN,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          // GIR_Coverage, 64819,
          GIR_Done,
        // Label 2943: @86632
        GIM_Try, /*On fail goto*//*Label 2944*/ 86729, // Rule ID 64829 //
          GIM_CheckFeatures, GIFBS_HasVendorXVentanaCondOps_IsRV64,
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
          GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
          // MIs[1] Operand 1
          GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          // (select:{ *:[i64] } (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rc, 0:{ *:[i64] }, SETNE:{ *:[Other] }), GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (OR:{ *:[i64] } (VT_MASKC:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rc), (VT_MASKCN:{ *:[i64] } GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rc))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
          GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
          GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::VT_MASKCN,
          GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rs2
          GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // rc
          GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::VT_MASKC,
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // rc
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::OR,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          // GIR_Coverage, 64829,
          GIR_Done,
        // Label 2944: @86729
        GIM_Try, /*On fail goto*//*Label 2945*/ 86826, // Rule ID 64830 //
          GIM_CheckFeatures, GIFBS_HasVendorXVentanaCondOps_IsRV64,
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
          GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
          // MIs[1] Operand 1
          GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckConstantInt, /*MI*/1, /*Op*/3, 0,
          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          // (select:{ *:[i64] } (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rc, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1)  =>  (OR:{ *:[i64] } (VT_MASKC:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rc), (VT_MASKCN:{ *:[i64] } GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rc))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
          GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
          GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::VT_MASKCN,
          GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // rs2
          GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // rc
          GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::VT_MASKC,
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs1
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // rc
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::OR,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          // GIR_Coverage, 64830,
          GIR_Done,
        // Label 2945: @86826
        GIM_Try, /*On fail goto*//*Label 2946*/ 86961, // Rule ID 64833 //
          GIM_CheckFeatures, GIFBS_HasVendorXVentanaCondOps_IsRV64,
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
          GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
          // MIs[1] Operand 1
          GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckConstantInt, /*MI*/1, /*Op*/3, -2048,
          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          // (select:{ *:[i64] } (setcc:{ *:[i64] } GPR:{ *:[i64] }:$x, -2048:{ *:[i64] }, SETNE:{ *:[Other] }), GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (OR:{ *:[i64] } (VT_MASKC:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (XORI:{ *:[i64] } GPR:{ *:[i64] }:$x, -2048:{ *:[i64] })), (VT_MASKCN:{ *:[i64] } GPR:{ *:[i64] }:$rs2, (XORI:{ *:[i64] } GPR:{ *:[i64] }:$x, -2048:{ *:[i64] })))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
          GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
          GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
          GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
          GIR_BuildMI, /*InsnID*/4, /*Opcode*/RISCV::XORI,
          GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // x
          GIR_AddImm, /*InsnID*/4, /*Imm*/-2048,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
          GIR_BuildMI, /*InsnID*/3, /*Opcode*/RISCV::VT_MASKCN,
          GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // rs2
          GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
          GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::XORI,
          GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // x
          GIR_AddImm, /*InsnID*/2, /*Imm*/-2048,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::VT_MASKC,
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::OR,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          // GIR_Coverage, 64833,
          GIR_Done,
        // Label 2946: @86961
        GIM_Try, /*On fail goto*//*Label 2947*/ 87096, // Rule ID 64836 //
          GIM_CheckFeatures, GIFBS_HasVendorXVentanaCondOps_IsRV64,
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
          GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
          // MIs[1] Operand 1
          GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckConstantInt, /*MI*/1, /*Op*/3, -2048,
          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          // (select:{ *:[i64] } (setcc:{ *:[i64] } GPR:{ *:[i64] }:$x, -2048:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1)  =>  (OR:{ *:[i64] } (VT_MASKC:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (XORI:{ *:[i64] } GPR:{ *:[i64] }:$x, -2048:{ *:[i64] })), (VT_MASKCN:{ *:[i64] } GPR:{ *:[i64] }:$rs2, (XORI:{ *:[i64] } GPR:{ *:[i64] }:$x, -2048:{ *:[i64] })))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
          GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
          GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
          GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
          GIR_BuildMI, /*InsnID*/4, /*Opcode*/RISCV::XORI,
          GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // x
          GIR_AddImm, /*InsnID*/4, /*Imm*/-2048,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
          GIR_BuildMI, /*InsnID*/3, /*Opcode*/RISCV::VT_MASKCN,
          GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // rs2
          GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
          GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::XORI,
          GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // x
          GIR_AddImm, /*InsnID*/2, /*Imm*/-2048,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::VT_MASKC,
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs1
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::OR,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          // GIR_Coverage, 64836,
          GIR_Done,
        // Label 2947: @87096
        GIM_Reject,
      // Label 2939: @87097
      GIM_Try, /*On fail goto*//*Label 2948*/ 87254,
        GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 0,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
        GIM_Try, /*On fail goto*//*Label 2949*/ 87180, // Rule ID 64824 //
          GIM_CheckFeatures, GIFBS_HasVendorXVentanaCondOps_IsRV64,
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
          GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
          // MIs[1] Operand 1
          GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          // (select:{ *:[i64] } (setcc:{ *:[i64] } GPR:{ *:[i64] }:$x, GPR:{ *:[i64] }:$y, SETNE:{ *:[Other] }), 0:{ *:[i64] }, GPR:{ *:[i64] }:$rs1)  =>  (VT_MASKCN:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (XOR:{ *:[i64] } GPR:{ *:[i64] }:$x, GPR:{ *:[i64] }:$y))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XOR,
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // y
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::VT_MASKCN,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          // GIR_Coverage, 64824,
          GIR_Done,
        // Label 2949: @87180
        GIM_Try, /*On fail goto*//*Label 2950*/ 87253, // Rule ID 64825 //
          GIM_CheckFeatures, GIFBS_HasVendorXVentanaCondOps_IsRV64,
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
          GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
          // MIs[1] Operand 1
          GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          // (select:{ *:[i64] } (setcc:{ *:[i64] } GPR:{ *:[i64] }:$x, GPR:{ *:[i64] }:$y, SETEQ:{ *:[Other] }), 0:{ *:[i64] }, GPR:{ *:[i64] }:$rs1)  =>  (VT_MASKC:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (XOR:{ *:[i64] } GPR:{ *:[i64] }:$x, GPR:{ *:[i64] }:$y))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XOR,
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // y
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::VT_MASKC,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs1
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          // GIR_Coverage, 64825,
          GIR_Done,
        // Label 2950: @87253
        GIM_Reject,
      // Label 2948: @87254
      GIM_Try, /*On fail goto*//*Label 2951*/ 87689,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
        GIM_Try, /*On fail goto*//*Label 2952*/ 87337, // Rule ID 64822 //
          GIM_CheckFeatures, GIFBS_HasVendorXVentanaCondOps_IsRV64,
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
          GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
          // MIs[1] Operand 1
          GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          // (select:{ *:[i64] } (setcc:{ *:[i64] } GPR:{ *:[i64] }:$x, GPR:{ *:[i64] }:$y, SETNE:{ *:[Other] }), GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })  =>  (VT_MASKC:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (XOR:{ *:[i64] } GPR:{ *:[i64] }:$x, GPR:{ *:[i64] }:$y))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XOR,
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // y
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::VT_MASKC,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          // GIR_Coverage, 64822,
          GIR_Done,
        // Label 2952: @87337
        GIM_Try, /*On fail goto*//*Label 2953*/ 87414, // Rule ID 64823 //
          GIM_CheckFeatures, GIFBS_HasVendorXVentanaCondOps_IsRV64,
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
          GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
          // MIs[1] Operand 1
          GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          // (select:{ *:[i64] } (setcc:{ *:[i64] } GPR:{ *:[i64] }:$x, GPR:{ *:[i64] }:$y, SETEQ:{ *:[Other] }), GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })  =>  (VT_MASKCN:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (XOR:{ *:[i64] } GPR:{ *:[i64] }:$x, GPR:{ *:[i64] }:$y))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XOR,
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // y
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::VT_MASKCN,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          // GIR_Coverage, 64823,
          GIR_Done,
        // Label 2953: @87414
        GIM_Try, /*On fail goto*//*Label 2954*/ 87551, // Rule ID 64837 //
          GIM_CheckFeatures, GIFBS_HasVendorXVentanaCondOps_IsRV64,
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
          GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
          // MIs[1] Operand 1
          GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          // (select:{ *:[i64] } (setcc:{ *:[i64] } GPR:{ *:[i64] }:$x, GPR:{ *:[i64] }:$y, SETNE:{ *:[Other] }), GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (OR:{ *:[i64] } (VT_MASKC:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (XOR:{ *:[i64] } GPR:{ *:[i64] }:$x, GPR:{ *:[i64] }:$y)), (VT_MASKCN:{ *:[i64] } GPR:{ *:[i64] }:$rs2, (XOR:{ *:[i64] } GPR:{ *:[i64] }:$x, GPR:{ *:[i64] }:$y)))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
          GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
          GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
          GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
          GIR_BuildMI, /*InsnID*/4, /*Opcode*/RISCV::XOR,
          GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // x
          GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/3, // y
          GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
          GIR_BuildMI, /*InsnID*/3, /*Opcode*/RISCV::VT_MASKCN,
          GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // rs2
          GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
          GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::XOR,
          GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // x
          GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // y
          GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::VT_MASKC,
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::OR,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          // GIR_Coverage, 64837,
          GIR_Done,
        // Label 2954: @87551
        GIM_Try, /*On fail goto*//*Label 2955*/ 87688, // Rule ID 64838 //
          GIM_CheckFeatures, GIFBS_HasVendorXVentanaCondOps_IsRV64,
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ICMP,
          GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
          GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
          // MIs[1] Operand 1
          GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          // (select:{ *:[i64] } (setcc:{ *:[i64] } GPR:{ *:[i64] }:$x, GPR:{ *:[i64] }:$y, SETEQ:{ *:[Other] }), GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1)  =>  (OR:{ *:[i64] } (VT_MASKC:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (XOR:{ *:[i64] } GPR:{ *:[i64] }:$x, GPR:{ *:[i64] }:$y)), (VT_MASKCN:{ *:[i64] } GPR:{ *:[i64] }:$rs2, (XOR:{ *:[i64] } GPR:{ *:[i64] }:$x, GPR:{ *:[i64] }:$y)))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
          GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
          GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
          GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
          GIR_BuildMI, /*InsnID*/4, /*Opcode*/RISCV::XOR,
          GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // x
          GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/3, // y
          GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
          GIR_BuildMI, /*InsnID*/3, /*Opcode*/RISCV::VT_MASKCN,
          GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // rs2
          GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
          GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::XOR,
          GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // x
          GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/3, // y
          GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::VT_MASKC,
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs1
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::OR,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
          GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          // GIR_Coverage, 64838,
          GIR_Done,
        // Label 2955: @87688
        GIM_Reject,
      // Label 2951: @87689
      GIM_Reject,
    // Label 2933: @87690
    GIM_Reject,
    // Label 39: @87691
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 32, /*)*//*default:*//*Label 2980*/ 89640,
    /*GILLT_s32*//*Label 2956*/ 87728,
    /*GILLT_s64*//*Label 2957*/ 87760, 0,
    /*GILLT_nxv1s8*//*Label 2958*/ 87792,
    /*GILLT_nxv1s16*//*Label 2959*/ 87876,
    /*GILLT_nxv1s32*//*Label 2960*/ 87960,
    /*GILLT_nxv1s64*//*Label 2961*/ 88044, 0,
    /*GILLT_nxv2s8*//*Label 2962*/ 88128,
    /*GILLT_nxv2s16*//*Label 2963*/ 88212,
    /*GILLT_nxv2s32*//*Label 2964*/ 88296,
    /*GILLT_nxv2s64*//*Label 2965*/ 88380, 0,
    /*GILLT_nxv4s8*//*Label 2966*/ 88464,
    /*GILLT_nxv4s16*//*Label 2967*/ 88548,
    /*GILLT_nxv4s32*//*Label 2968*/ 88632,
    /*GILLT_nxv4s64*//*Label 2969*/ 88716, 0,
    /*GILLT_nxv8s8*//*Label 2970*/ 88800,
    /*GILLT_nxv8s16*//*Label 2971*/ 88884,
    /*GILLT_nxv8s32*//*Label 2972*/ 88968,
    /*GILLT_nxv8s64*//*Label 2973*/ 89052, 0,
    /*GILLT_nxv16s8*//*Label 2974*/ 89136,
    /*GILLT_nxv16s16*//*Label 2975*/ 89220,
    /*GILLT_nxv16s32*//*Label 2976*/ 89304, 0,
    /*GILLT_nxv32s8*//*Label 2977*/ 89388,
    /*GILLT_nxv32s16*//*Label 2978*/ 89472, 0,
    /*GILLT_nxv64s8*//*Label 2979*/ 89556,
    // Label 2956: @87728
    GIM_Try, /*On fail goto*//*Label 2981*/ 87759, // Rule ID 63309 //
      GIM_CheckFeatures, GIFBS_HasStdExtMOrZmmul,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
      // (mulhu:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (MULHU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MULHU,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63309,
      GIR_Done,
    // Label 2981: @87759
    GIM_Reject,
    // Label 2957: @87760
    GIM_Try, /*On fail goto*//*Label 2982*/ 87791, // Rule ID 63308 //
      GIM_CheckFeatures, GIFBS_HasStdExtMOrZmmul,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
      // (mulhu:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (MULHU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MULHU,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63308,
      GIR_Done,
    // Label 2982: @87791
    GIM_Reject,
    // Label 2958: @87792
    GIM_Try, /*On fail goto*//*Label 2983*/ 87875,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2984*/ 87844, // Rule ID 59677 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVMULHU_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59677,
        GIR_Done,
      // Label 2984: @87844
      GIM_Try, /*On fail goto*//*Label 2985*/ 87874, // Rule ID 59678 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVMULHU_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59678,
        GIR_Done,
      // Label 2985: @87874
      GIM_Reject,
    // Label 2983: @87875
    GIM_Reject,
    // Label 2959: @87876
    GIM_Try, /*On fail goto*//*Label 2986*/ 87959,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2987*/ 87928, // Rule ID 59689 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVMULHU_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59689,
        GIR_Done,
      // Label 2987: @87928
      GIM_Try, /*On fail goto*//*Label 2988*/ 87958, // Rule ID 59690 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVMULHU_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59690,
        GIR_Done,
      // Label 2988: @87958
      GIM_Reject,
    // Label 2986: @87959
    GIM_Reject,
    // Label 2960: @87960
    GIM_Try, /*On fail goto*//*Label 2989*/ 88043,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2990*/ 88012, // Rule ID 59697 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVMULHU_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59697,
        GIR_Done,
      // Label 2990: @88012
      GIM_Try, /*On fail goto*//*Label 2991*/ 88042, // Rule ID 59698 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVMULHU_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59698,
        GIR_Done,
      // Label 2991: @88042
      GIM_Reject,
    // Label 2989: @88043
    GIM_Reject,
    // Label 2961: @88044
    GIM_Try, /*On fail goto*//*Label 2992*/ 88127,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2993*/ 88096, // Rule ID 59713 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVMULHU_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59713,
        GIR_Done,
      // Label 2993: @88096
      GIM_Try, /*On fail goto*//*Label 2994*/ 88126, // Rule ID 59714 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVMULHU_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59714,
        GIR_Done,
      // Label 2994: @88126
      GIM_Reject,
    // Label 2992: @88127
    GIM_Reject,
    // Label 2962: @88128
    GIM_Try, /*On fail goto*//*Label 2995*/ 88211,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2996*/ 88180, // Rule ID 59681 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVMULHU_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59681,
        GIR_Done,
      // Label 2996: @88180
      GIM_Try, /*On fail goto*//*Label 2997*/ 88210, // Rule ID 59682 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVMULHU_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59682,
        GIR_Done,
      // Label 2997: @88210
      GIM_Reject,
    // Label 2995: @88211
    GIM_Reject,
    // Label 2963: @88212
    GIM_Try, /*On fail goto*//*Label 2998*/ 88295,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 2999*/ 88264, // Rule ID 59693 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVMULHU_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59693,
        GIR_Done,
      // Label 2999: @88264
      GIM_Try, /*On fail goto*//*Label 3000*/ 88294, // Rule ID 59694 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVMULHU_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59694,
        GIR_Done,
      // Label 3000: @88294
      GIM_Reject,
    // Label 2998: @88295
    GIM_Reject,
    // Label 2964: @88296
    GIM_Try, /*On fail goto*//*Label 3001*/ 88379,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3002*/ 88348, // Rule ID 59709 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVMULHU_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59709,
        GIR_Done,
      // Label 3002: @88348
      GIM_Try, /*On fail goto*//*Label 3003*/ 88378, // Rule ID 59710 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVMULHU_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59710,
        GIR_Done,
      // Label 3003: @88378
      GIM_Reject,
    // Label 3001: @88379
    GIM_Reject,
    // Label 2965: @88380
    GIM_Try, /*On fail goto*//*Label 3004*/ 88463,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3005*/ 88432, // Rule ID 59753 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVMULHU_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59753,
        GIR_Done,
      // Label 3005: @88432
      GIM_Try, /*On fail goto*//*Label 3006*/ 88462, // Rule ID 59754 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVMULHU_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59754,
        GIR_Done,
      // Label 3006: @88462
      GIM_Reject,
    // Label 3004: @88463
    GIM_Reject,
    // Label 2966: @88464
    GIM_Try, /*On fail goto*//*Label 3007*/ 88547,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3008*/ 88516, // Rule ID 59685 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVMULHU_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59685,
        GIR_Done,
      // Label 3008: @88516
      GIM_Try, /*On fail goto*//*Label 3009*/ 88546, // Rule ID 59686 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVMULHU_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59686,
        GIR_Done,
      // Label 3009: @88546
      GIM_Reject,
    // Label 3007: @88547
    GIM_Reject,
    // Label 2967: @88548
    GIM_Try, /*On fail goto*//*Label 3010*/ 88631,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3011*/ 88600, // Rule ID 59705 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVMULHU_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59705,
        GIR_Done,
      // Label 3011: @88600
      GIM_Try, /*On fail goto*//*Label 3012*/ 88630, // Rule ID 59706 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVMULHU_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59706,
        GIR_Done,
      // Label 3012: @88630
      GIM_Reject,
    // Label 3010: @88631
    GIM_Reject,
    // Label 2968: @88632
    GIM_Try, /*On fail goto*//*Label 3013*/ 88715,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3014*/ 88684, // Rule ID 59741 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVMULHU_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59741,
        GIR_Done,
      // Label 3014: @88684
      GIM_Try, /*On fail goto*//*Label 3015*/ 88714, // Rule ID 59742 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVMULHU_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59742,
        GIR_Done,
      // Label 3015: @88714
      GIM_Reject,
    // Label 3013: @88715
    GIM_Reject,
    // Label 2969: @88716
    GIM_Try, /*On fail goto*//*Label 3016*/ 88799,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3017*/ 88768, // Rule ID 59757 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVMULHU_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59757,
        GIR_Done,
      // Label 3017: @88768
      GIM_Try, /*On fail goto*//*Label 3018*/ 88798, // Rule ID 59758 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVMULHU_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59758,
        GIR_Done,
      // Label 3018: @88798
      GIM_Reject,
    // Label 3016: @88799
    GIM_Reject,
    // Label 2970: @88800
    GIM_Try, /*On fail goto*//*Label 3019*/ 88883,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3020*/ 88852, // Rule ID 59701 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVMULHU_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59701,
        GIR_Done,
      // Label 3020: @88852
      GIM_Try, /*On fail goto*//*Label 3021*/ 88882, // Rule ID 59702 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVMULHU_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59702,
        GIR_Done,
      // Label 3021: @88882
      GIM_Reject,
    // Label 3019: @88883
    GIM_Reject,
    // Label 2971: @88884
    GIM_Try, /*On fail goto*//*Label 3022*/ 88967,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3023*/ 88936, // Rule ID 59729 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVMULHU_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59729,
        GIR_Done,
      // Label 3023: @88936
      GIM_Try, /*On fail goto*//*Label 3024*/ 88966, // Rule ID 59730 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVMULHU_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59730,
        GIR_Done,
      // Label 3024: @88966
      GIM_Reject,
    // Label 3022: @88967
    GIM_Reject,
    // Label 2972: @88968
    GIM_Try, /*On fail goto*//*Label 3025*/ 89051,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3026*/ 89020, // Rule ID 59745 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVMULHU_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59745,
        GIR_Done,
      // Label 3026: @89020
      GIM_Try, /*On fail goto*//*Label 3027*/ 89050, // Rule ID 59746 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVMULHU_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59746,
        GIR_Done,
      // Label 3027: @89050
      GIM_Reject,
    // Label 3025: @89051
    GIM_Reject,
    // Label 2973: @89052
    GIM_Try, /*On fail goto*//*Label 3028*/ 89135,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3029*/ 89104, // Rule ID 59761 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVMULHU_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59761,
        GIR_Done,
      // Label 3029: @89104
      GIM_Try, /*On fail goto*//*Label 3030*/ 89134, // Rule ID 59762 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVMULHU_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59762,
        GIR_Done,
      // Label 3030: @89134
      GIM_Reject,
    // Label 3028: @89135
    GIM_Reject,
    // Label 2974: @89136
    GIM_Try, /*On fail goto*//*Label 3031*/ 89219,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3032*/ 89188, // Rule ID 59717 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVMULHU_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59717,
        GIR_Done,
      // Label 3032: @89188
      GIM_Try, /*On fail goto*//*Label 3033*/ 89218, // Rule ID 59718 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVMULHU_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59718,
        GIR_Done,
      // Label 3033: @89218
      GIM_Reject,
    // Label 3031: @89219
    GIM_Reject,
    // Label 2975: @89220
    GIM_Try, /*On fail goto*//*Label 3034*/ 89303,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3035*/ 89272, // Rule ID 59733 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVMULHU_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59733,
        GIR_Done,
      // Label 3035: @89272
      GIM_Try, /*On fail goto*//*Label 3036*/ 89302, // Rule ID 59734 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVMULHU_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59734,
        GIR_Done,
      // Label 3036: @89302
      GIM_Reject,
    // Label 3034: @89303
    GIM_Reject,
    // Label 2976: @89304
    GIM_Try, /*On fail goto*//*Label 3037*/ 89387,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3038*/ 89356, // Rule ID 59749 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVMULHU_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59749,
        GIR_Done,
      // Label 3038: @89356
      GIM_Try, /*On fail goto*//*Label 3039*/ 89386, // Rule ID 59750 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVMULHU_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59750,
        GIR_Done,
      // Label 3039: @89386
      GIM_Reject,
    // Label 3037: @89387
    GIM_Reject,
    // Label 2977: @89388
    GIM_Try, /*On fail goto*//*Label 3040*/ 89471,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3041*/ 89440, // Rule ID 59721 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVMULHU_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59721,
        GIR_Done,
      // Label 3041: @89440
      GIM_Try, /*On fail goto*//*Label 3042*/ 89470, // Rule ID 59722 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVMULHU_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59722,
        GIR_Done,
      // Label 3042: @89470
      GIM_Reject,
    // Label 3040: @89471
    GIM_Reject,
    // Label 2978: @89472
    GIM_Try, /*On fail goto*//*Label 3043*/ 89555,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3044*/ 89524, // Rule ID 59737 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVMULHU_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59737,
        GIR_Done,
      // Label 3044: @89524
      GIM_Try, /*On fail goto*//*Label 3045*/ 89554, // Rule ID 59738 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVMULHU_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59738,
        GIR_Done,
      // Label 3045: @89554
      GIM_Reject,
    // Label 3043: @89555
    GIM_Reject,
    // Label 2979: @89556
    GIM_Try, /*On fail goto*//*Label 3046*/ 89639,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv64s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3047*/ 89608, // Rule ID 59725 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVMULHU_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59725,
        GIR_Done,
      // Label 3047: @89608
      GIM_Try, /*On fail goto*//*Label 3048*/ 89638, // Rule ID 59726 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhu:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVMULHU_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULHU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59726,
        GIR_Done,
      // Label 3048: @89638
      GIM_Reject,
    // Label 3046: @89639
    GIM_Reject,
    // Label 2980: @89640
    GIM_Reject,
    // Label 40: @89641
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 32, /*)*//*default:*//*Label 3073*/ 91590,
    /*GILLT_s32*//*Label 3049*/ 89678,
    /*GILLT_s64*//*Label 3050*/ 89710, 0,
    /*GILLT_nxv1s8*//*Label 3051*/ 89742,
    /*GILLT_nxv1s16*//*Label 3052*/ 89826,
    /*GILLT_nxv1s32*//*Label 3053*/ 89910,
    /*GILLT_nxv1s64*//*Label 3054*/ 89994, 0,
    /*GILLT_nxv2s8*//*Label 3055*/ 90078,
    /*GILLT_nxv2s16*//*Label 3056*/ 90162,
    /*GILLT_nxv2s32*//*Label 3057*/ 90246,
    /*GILLT_nxv2s64*//*Label 3058*/ 90330, 0,
    /*GILLT_nxv4s8*//*Label 3059*/ 90414,
    /*GILLT_nxv4s16*//*Label 3060*/ 90498,
    /*GILLT_nxv4s32*//*Label 3061*/ 90582,
    /*GILLT_nxv4s64*//*Label 3062*/ 90666, 0,
    /*GILLT_nxv8s8*//*Label 3063*/ 90750,
    /*GILLT_nxv8s16*//*Label 3064*/ 90834,
    /*GILLT_nxv8s32*//*Label 3065*/ 90918,
    /*GILLT_nxv8s64*//*Label 3066*/ 91002, 0,
    /*GILLT_nxv16s8*//*Label 3067*/ 91086,
    /*GILLT_nxv16s16*//*Label 3068*/ 91170,
    /*GILLT_nxv16s32*//*Label 3069*/ 91254, 0,
    /*GILLT_nxv32s8*//*Label 3070*/ 91338,
    /*GILLT_nxv32s16*//*Label 3071*/ 91422, 0,
    /*GILLT_nxv64s8*//*Label 3072*/ 91506,
    // Label 3049: @89678
    GIM_Try, /*On fail goto*//*Label 3074*/ 89709, // Rule ID 63289 //
      GIM_CheckFeatures, GIFBS_HasStdExtMOrZmmul,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
      // (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (MULH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MULH,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63289,
      GIR_Done,
    // Label 3074: @89709
    GIM_Reject,
    // Label 3050: @89710
    GIM_Try, /*On fail goto*//*Label 3075*/ 89741, // Rule ID 63288 //
      GIM_CheckFeatures, GIFBS_HasStdExtMOrZmmul,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
      // (mulhs:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (MULH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MULH,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 63288,
      GIR_Done,
    // Label 3075: @89741
    GIM_Reject,
    // Label 3051: @89742
    GIM_Try, /*On fail goto*//*Label 3076*/ 89825,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3077*/ 89794, // Rule ID 59589 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVMULH_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59589,
        GIR_Done,
      // Label 3077: @89794
      GIM_Try, /*On fail goto*//*Label 3078*/ 89824, // Rule ID 59590 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVMULH_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59590,
        GIR_Done,
      // Label 3078: @89824
      GIM_Reject,
    // Label 3076: @89825
    GIM_Reject,
    // Label 3052: @89826
    GIM_Try, /*On fail goto*//*Label 3079*/ 89909,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3080*/ 89878, // Rule ID 59601 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVMULH_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59601,
        GIR_Done,
      // Label 3080: @89878
      GIM_Try, /*On fail goto*//*Label 3081*/ 89908, // Rule ID 59602 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVMULH_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59602,
        GIR_Done,
      // Label 3081: @89908
      GIM_Reject,
    // Label 3079: @89909
    GIM_Reject,
    // Label 3053: @89910
    GIM_Try, /*On fail goto*//*Label 3082*/ 89993,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3083*/ 89962, // Rule ID 59609 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVMULH_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59609,
        GIR_Done,
      // Label 3083: @89962
      GIM_Try, /*On fail goto*//*Label 3084*/ 89992, // Rule ID 59610 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVMULH_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59610,
        GIR_Done,
      // Label 3084: @89992
      GIM_Reject,
    // Label 3082: @89993
    GIM_Reject,
    // Label 3054: @89994
    GIM_Try, /*On fail goto*//*Label 3085*/ 90077,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3086*/ 90046, // Rule ID 59625 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVMULH_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59625,
        GIR_Done,
      // Label 3086: @90046
      GIM_Try, /*On fail goto*//*Label 3087*/ 90076, // Rule ID 59626 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVMULH_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59626,
        GIR_Done,
      // Label 3087: @90076
      GIM_Reject,
    // Label 3085: @90077
    GIM_Reject,
    // Label 3055: @90078
    GIM_Try, /*On fail goto*//*Label 3088*/ 90161,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3089*/ 90130, // Rule ID 59593 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVMULH_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59593,
        GIR_Done,
      // Label 3089: @90130
      GIM_Try, /*On fail goto*//*Label 3090*/ 90160, // Rule ID 59594 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVMULH_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59594,
        GIR_Done,
      // Label 3090: @90160
      GIM_Reject,
    // Label 3088: @90161
    GIM_Reject,
    // Label 3056: @90162
    GIM_Try, /*On fail goto*//*Label 3091*/ 90245,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3092*/ 90214, // Rule ID 59605 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVMULH_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59605,
        GIR_Done,
      // Label 3092: @90214
      GIM_Try, /*On fail goto*//*Label 3093*/ 90244, // Rule ID 59606 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVMULH_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59606,
        GIR_Done,
      // Label 3093: @90244
      GIM_Reject,
    // Label 3091: @90245
    GIM_Reject,
    // Label 3057: @90246
    GIM_Try, /*On fail goto*//*Label 3094*/ 90329,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3095*/ 90298, // Rule ID 59621 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVMULH_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59621,
        GIR_Done,
      // Label 3095: @90298
      GIM_Try, /*On fail goto*//*Label 3096*/ 90328, // Rule ID 59622 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVMULH_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59622,
        GIR_Done,
      // Label 3096: @90328
      GIM_Reject,
    // Label 3094: @90329
    GIM_Reject,
    // Label 3058: @90330
    GIM_Try, /*On fail goto*//*Label 3097*/ 90413,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3098*/ 90382, // Rule ID 59665 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVMULH_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59665,
        GIR_Done,
      // Label 3098: @90382
      GIM_Try, /*On fail goto*//*Label 3099*/ 90412, // Rule ID 59666 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVMULH_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59666,
        GIR_Done,
      // Label 3099: @90412
      GIM_Reject,
    // Label 3097: @90413
    GIM_Reject,
    // Label 3059: @90414
    GIM_Try, /*On fail goto*//*Label 3100*/ 90497,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3101*/ 90466, // Rule ID 59597 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVMULH_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59597,
        GIR_Done,
      // Label 3101: @90466
      GIM_Try, /*On fail goto*//*Label 3102*/ 90496, // Rule ID 59598 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVMULH_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59598,
        GIR_Done,
      // Label 3102: @90496
      GIM_Reject,
    // Label 3100: @90497
    GIM_Reject,
    // Label 3060: @90498
    GIM_Try, /*On fail goto*//*Label 3103*/ 90581,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3104*/ 90550, // Rule ID 59617 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVMULH_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59617,
        GIR_Done,
      // Label 3104: @90550
      GIM_Try, /*On fail goto*//*Label 3105*/ 90580, // Rule ID 59618 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVMULH_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59618,
        GIR_Done,
      // Label 3105: @90580
      GIM_Reject,
    // Label 3103: @90581
    GIM_Reject,
    // Label 3061: @90582
    GIM_Try, /*On fail goto*//*Label 3106*/ 90665,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3107*/ 90634, // Rule ID 59653 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVMULH_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59653,
        GIR_Done,
      // Label 3107: @90634
      GIM_Try, /*On fail goto*//*Label 3108*/ 90664, // Rule ID 59654 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVMULH_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59654,
        GIR_Done,
      // Label 3108: @90664
      GIM_Reject,
    // Label 3106: @90665
    GIM_Reject,
    // Label 3062: @90666
    GIM_Try, /*On fail goto*//*Label 3109*/ 90749,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3110*/ 90718, // Rule ID 59669 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVMULH_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59669,
        GIR_Done,
      // Label 3110: @90718
      GIM_Try, /*On fail goto*//*Label 3111*/ 90748, // Rule ID 59670 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVMULH_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59670,
        GIR_Done,
      // Label 3111: @90748
      GIM_Reject,
    // Label 3109: @90749
    GIM_Reject,
    // Label 3063: @90750
    GIM_Try, /*On fail goto*//*Label 3112*/ 90833,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3113*/ 90802, // Rule ID 59613 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVMULH_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59613,
        GIR_Done,
      // Label 3113: @90802
      GIM_Try, /*On fail goto*//*Label 3114*/ 90832, // Rule ID 59614 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVMULH_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59614,
        GIR_Done,
      // Label 3114: @90832
      GIM_Reject,
    // Label 3112: @90833
    GIM_Reject,
    // Label 3064: @90834
    GIM_Try, /*On fail goto*//*Label 3115*/ 90917,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3116*/ 90886, // Rule ID 59641 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVMULH_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59641,
        GIR_Done,
      // Label 3116: @90886
      GIM_Try, /*On fail goto*//*Label 3117*/ 90916, // Rule ID 59642 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVMULH_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59642,
        GIR_Done,
      // Label 3117: @90916
      GIM_Reject,
    // Label 3115: @90917
    GIM_Reject,
    // Label 3065: @90918
    GIM_Try, /*On fail goto*//*Label 3118*/ 91001,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3119*/ 90970, // Rule ID 59657 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVMULH_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59657,
        GIR_Done,
      // Label 3119: @90970
      GIM_Try, /*On fail goto*//*Label 3120*/ 91000, // Rule ID 59658 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVMULH_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59658,
        GIR_Done,
      // Label 3120: @91000
      GIM_Reject,
    // Label 3118: @91001
    GIM_Reject,
    // Label 3066: @91002
    GIM_Try, /*On fail goto*//*Label 3121*/ 91085,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3122*/ 91054, // Rule ID 59673 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVMULH_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59673,
        GIR_Done,
      // Label 3122: @91054
      GIM_Try, /*On fail goto*//*Label 3123*/ 91084, // Rule ID 59674 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVMULH_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59674,
        GIR_Done,
      // Label 3123: @91084
      GIM_Reject,
    // Label 3121: @91085
    GIM_Reject,
    // Label 3067: @91086
    GIM_Try, /*On fail goto*//*Label 3124*/ 91169,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3125*/ 91138, // Rule ID 59629 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVMULH_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59629,
        GIR_Done,
      // Label 3125: @91138
      GIM_Try, /*On fail goto*//*Label 3126*/ 91168, // Rule ID 59630 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVMULH_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59630,
        GIR_Done,
      // Label 3126: @91168
      GIM_Reject,
    // Label 3124: @91169
    GIM_Reject,
    // Label 3068: @91170
    GIM_Try, /*On fail goto*//*Label 3127*/ 91253,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3128*/ 91222, // Rule ID 59645 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVMULH_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59645,
        GIR_Done,
      // Label 3128: @91222
      GIM_Try, /*On fail goto*//*Label 3129*/ 91252, // Rule ID 59646 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVMULH_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59646,
        GIR_Done,
      // Label 3129: @91252
      GIM_Reject,
    // Label 3127: @91253
    GIM_Reject,
    // Label 3069: @91254
    GIM_Try, /*On fail goto*//*Label 3130*/ 91337,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3131*/ 91306, // Rule ID 59661 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVMULH_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59661,
        GIR_Done,
      // Label 3131: @91306
      GIM_Try, /*On fail goto*//*Label 3132*/ 91336, // Rule ID 59662 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVMULH_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59662,
        GIR_Done,
      // Label 3132: @91336
      GIM_Reject,
    // Label 3130: @91337
    GIM_Reject,
    // Label 3070: @91338
    GIM_Try, /*On fail goto*//*Label 3133*/ 91421,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3134*/ 91390, // Rule ID 59633 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVMULH_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59633,
        GIR_Done,
      // Label 3134: @91390
      GIM_Try, /*On fail goto*//*Label 3135*/ 91420, // Rule ID 59634 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVMULH_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59634,
        GIR_Done,
      // Label 3135: @91420
      GIM_Reject,
    // Label 3133: @91421
    GIM_Reject,
    // Label 3071: @91422
    GIM_Try, /*On fail goto*//*Label 3136*/ 91505,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3137*/ 91474, // Rule ID 59649 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVMULH_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59649,
        GIR_Done,
      // Label 3137: @91474
      GIM_Try, /*On fail goto*//*Label 3138*/ 91504, // Rule ID 59650 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVMULH_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59650,
        GIR_Done,
      // Label 3138: @91504
      GIM_Reject,
    // Label 3136: @91505
    GIM_Reject,
    // Label 3072: @91506
    GIM_Try, /*On fail goto*//*Label 3139*/ 91589,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv64s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3140*/ 91558, // Rule ID 59637 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVMULH_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59637,
        GIR_Done,
      // Label 3140: @91558
      GIM_Try, /*On fail goto*//*Label 3141*/ 91588, // Rule ID 59638 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (mulhs:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVMULH_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMULH_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59638,
        GIR_Done,
      // Label 3141: @91588
      GIM_Reject,
    // Label 3139: @91589
    GIM_Reject,
    // Label 3073: @91590
    GIM_Reject,
    // Label 41: @91591
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 32, /*)*//*default:*//*Label 3164*/ 93473,
    /*GILLT_nxv1s8*//*Label 3142*/ 91625,
    /*GILLT_nxv1s16*//*Label 3143*/ 91709,
    /*GILLT_nxv1s32*//*Label 3144*/ 91793,
    /*GILLT_nxv1s64*//*Label 3145*/ 91877, 0,
    /*GILLT_nxv2s8*//*Label 3146*/ 91961,
    /*GILLT_nxv2s16*//*Label 3147*/ 92045,
    /*GILLT_nxv2s32*//*Label 3148*/ 92129,
    /*GILLT_nxv2s64*//*Label 3149*/ 92213, 0,
    /*GILLT_nxv4s8*//*Label 3150*/ 92297,
    /*GILLT_nxv4s16*//*Label 3151*/ 92381,
    /*GILLT_nxv4s32*//*Label 3152*/ 92465,
    /*GILLT_nxv4s64*//*Label 3153*/ 92549, 0,
    /*GILLT_nxv8s8*//*Label 3154*/ 92633,
    /*GILLT_nxv8s16*//*Label 3155*/ 92717,
    /*GILLT_nxv8s32*//*Label 3156*/ 92801,
    /*GILLT_nxv8s64*//*Label 3157*/ 92885, 0,
    /*GILLT_nxv16s8*//*Label 3158*/ 92969,
    /*GILLT_nxv16s16*//*Label 3159*/ 93053,
    /*GILLT_nxv16s32*//*Label 3160*/ 93137, 0,
    /*GILLT_nxv32s8*//*Label 3161*/ 93221,
    /*GILLT_nxv32s16*//*Label 3162*/ 93305, 0,
    /*GILLT_nxv64s8*//*Label 3163*/ 93389,
    // Label 3142: @91625
    GIM_Try, /*On fail goto*//*Label 3165*/ 91708,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3166*/ 91677, // Rule ID 61236 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVSADDU_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61236,
        GIR_Done,
      // Label 3166: @91677
      GIM_Try, /*On fail goto*//*Label 3167*/ 91707, // Rule ID 61237 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVSADDU_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61237,
        GIR_Done,
      // Label 3167: @91707
      GIM_Reject,
    // Label 3165: @91708
    GIM_Reject,
    // Label 3143: @91709
    GIM_Try, /*On fail goto*//*Label 3168*/ 91792,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3169*/ 91761, // Rule ID 61250 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVSADDU_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61250,
        GIR_Done,
      // Label 3169: @91761
      GIM_Try, /*On fail goto*//*Label 3170*/ 91791, // Rule ID 61251 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVSADDU_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61251,
        GIR_Done,
      // Label 3170: @91791
      GIM_Reject,
    // Label 3168: @91792
    GIM_Reject,
    // Label 3144: @91793
    GIM_Try, /*On fail goto*//*Label 3171*/ 91876,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3172*/ 91845, // Rule ID 61258 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVSADDU_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61258,
        GIR_Done,
      // Label 3172: @91845
      GIM_Try, /*On fail goto*//*Label 3173*/ 91875, // Rule ID 61259 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVSADDU_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61259,
        GIR_Done,
      // Label 3173: @91875
      GIM_Reject,
    // Label 3171: @91876
    GIM_Reject,
    // Label 3145: @91877
    GIM_Try, /*On fail goto*//*Label 3174*/ 91960,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3175*/ 91929, // Rule ID 61276 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVSADDU_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61276,
        GIR_Done,
      // Label 3175: @91929
      GIM_Try, /*On fail goto*//*Label 3176*/ 91959, // Rule ID 61277 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVSADDU_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61277,
        GIR_Done,
      // Label 3176: @91959
      GIM_Reject,
    // Label 3174: @91960
    GIM_Reject,
    // Label 3146: @91961
    GIM_Try, /*On fail goto*//*Label 3177*/ 92044,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3178*/ 92013, // Rule ID 61240 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVSADDU_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61240,
        GIR_Done,
      // Label 3178: @92013
      GIM_Try, /*On fail goto*//*Label 3179*/ 92043, // Rule ID 61241 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVSADDU_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61241,
        GIR_Done,
      // Label 3179: @92043
      GIM_Reject,
    // Label 3177: @92044
    GIM_Reject,
    // Label 3147: @92045
    GIM_Try, /*On fail goto*//*Label 3180*/ 92128,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3181*/ 92097, // Rule ID 61254 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVSADDU_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61254,
        GIR_Done,
      // Label 3181: @92097
      GIM_Try, /*On fail goto*//*Label 3182*/ 92127, // Rule ID 61255 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVSADDU_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61255,
        GIR_Done,
      // Label 3182: @92127
      GIM_Reject,
    // Label 3180: @92128
    GIM_Reject,
    // Label 3148: @92129
    GIM_Try, /*On fail goto*//*Label 3183*/ 92212,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3184*/ 92181, // Rule ID 61272 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVSADDU_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61272,
        GIR_Done,
      // Label 3184: @92181
      GIM_Try, /*On fail goto*//*Label 3185*/ 92211, // Rule ID 61273 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVSADDU_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61273,
        GIR_Done,
      // Label 3185: @92211
      GIM_Reject,
    // Label 3183: @92212
    GIM_Reject,
    // Label 3149: @92213
    GIM_Try, /*On fail goto*//*Label 3186*/ 92296,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3187*/ 92265, // Rule ID 61320 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVSADDU_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61320,
        GIR_Done,
      // Label 3187: @92265
      GIM_Try, /*On fail goto*//*Label 3188*/ 92295, // Rule ID 61321 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVSADDU_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61321,
        GIR_Done,
      // Label 3188: @92295
      GIM_Reject,
    // Label 3186: @92296
    GIM_Reject,
    // Label 3150: @92297
    GIM_Try, /*On fail goto*//*Label 3189*/ 92380,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3190*/ 92349, // Rule ID 61246 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVSADDU_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61246,
        GIR_Done,
      // Label 3190: @92349
      GIM_Try, /*On fail goto*//*Label 3191*/ 92379, // Rule ID 61247 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVSADDU_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61247,
        GIR_Done,
      // Label 3191: @92379
      GIM_Reject,
    // Label 3189: @92380
    GIM_Reject,
    // Label 3151: @92381
    GIM_Try, /*On fail goto*//*Label 3192*/ 92464,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3193*/ 92433, // Rule ID 61268 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVSADDU_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61268,
        GIR_Done,
      // Label 3193: @92433
      GIM_Try, /*On fail goto*//*Label 3194*/ 92463, // Rule ID 61269 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVSADDU_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61269,
        GIR_Done,
      // Label 3194: @92463
      GIM_Reject,
    // Label 3192: @92464
    GIM_Reject,
    // Label 3152: @92465
    GIM_Try, /*On fail goto*//*Label 3195*/ 92548,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3196*/ 92517, // Rule ID 61306 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVSADDU_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61306,
        GIR_Done,
      // Label 3196: @92517
      GIM_Try, /*On fail goto*//*Label 3197*/ 92547, // Rule ID 61307 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVSADDU_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61307,
        GIR_Done,
      // Label 3197: @92547
      GIM_Reject,
    // Label 3195: @92548
    GIM_Reject,
    // Label 3153: @92549
    GIM_Try, /*On fail goto*//*Label 3198*/ 92632,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3199*/ 92601, // Rule ID 61324 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVSADDU_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61324,
        GIR_Done,
      // Label 3199: @92601
      GIM_Try, /*On fail goto*//*Label 3200*/ 92631, // Rule ID 61325 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVSADDU_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61325,
        GIR_Done,
      // Label 3200: @92631
      GIM_Reject,
    // Label 3198: @92632
    GIM_Reject,
    // Label 3154: @92633
    GIM_Try, /*On fail goto*//*Label 3201*/ 92716,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3202*/ 92685, // Rule ID 61262 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVSADDU_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61262,
        GIR_Done,
      // Label 3202: @92685
      GIM_Try, /*On fail goto*//*Label 3203*/ 92715, // Rule ID 61263 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVSADDU_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61263,
        GIR_Done,
      // Label 3203: @92715
      GIM_Reject,
    // Label 3201: @92716
    GIM_Reject,
    // Label 3155: @92717
    GIM_Try, /*On fail goto*//*Label 3204*/ 92800,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3205*/ 92769, // Rule ID 61294 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVSADDU_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61294,
        GIR_Done,
      // Label 3205: @92769
      GIM_Try, /*On fail goto*//*Label 3206*/ 92799, // Rule ID 61295 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVSADDU_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61295,
        GIR_Done,
      // Label 3206: @92799
      GIM_Reject,
    // Label 3204: @92800
    GIM_Reject,
    // Label 3156: @92801
    GIM_Try, /*On fail goto*//*Label 3207*/ 92884,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3208*/ 92853, // Rule ID 61312 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVSADDU_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61312,
        GIR_Done,
      // Label 3208: @92853
      GIM_Try, /*On fail goto*//*Label 3209*/ 92883, // Rule ID 61313 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVSADDU_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61313,
        GIR_Done,
      // Label 3209: @92883
      GIM_Reject,
    // Label 3207: @92884
    GIM_Reject,
    // Label 3157: @92885
    GIM_Try, /*On fail goto*//*Label 3210*/ 92968,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3211*/ 92937, // Rule ID 61328 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVSADDU_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61328,
        GIR_Done,
      // Label 3211: @92937
      GIM_Try, /*On fail goto*//*Label 3212*/ 92967, // Rule ID 61329 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVSADDU_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61329,
        GIR_Done,
      // Label 3212: @92967
      GIM_Reject,
    // Label 3210: @92968
    GIM_Reject,
    // Label 3158: @92969
    GIM_Try, /*On fail goto*//*Label 3213*/ 93052,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3214*/ 93021, // Rule ID 61280 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVSADDU_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61280,
        GIR_Done,
      // Label 3214: @93021
      GIM_Try, /*On fail goto*//*Label 3215*/ 93051, // Rule ID 61281 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVSADDU_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61281,
        GIR_Done,
      // Label 3215: @93051
      GIM_Reject,
    // Label 3213: @93052
    GIM_Reject,
    // Label 3159: @93053
    GIM_Try, /*On fail goto*//*Label 3216*/ 93136,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3217*/ 93105, // Rule ID 61298 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVSADDU_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61298,
        GIR_Done,
      // Label 3217: @93105
      GIM_Try, /*On fail goto*//*Label 3218*/ 93135, // Rule ID 61299 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVSADDU_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61299,
        GIR_Done,
      // Label 3218: @93135
      GIM_Reject,
    // Label 3216: @93136
    GIM_Reject,
    // Label 3160: @93137
    GIM_Try, /*On fail goto*//*Label 3219*/ 93220,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3220*/ 93189, // Rule ID 61316 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVSADDU_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61316,
        GIR_Done,
      // Label 3220: @93189
      GIM_Try, /*On fail goto*//*Label 3221*/ 93219, // Rule ID 61317 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVSADDU_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61317,
        GIR_Done,
      // Label 3221: @93219
      GIM_Reject,
    // Label 3219: @93220
    GIM_Reject,
    // Label 3161: @93221
    GIM_Try, /*On fail goto*//*Label 3222*/ 93304,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3223*/ 93273, // Rule ID 61284 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVSADDU_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61284,
        GIR_Done,
      // Label 3223: @93273
      GIM_Try, /*On fail goto*//*Label 3224*/ 93303, // Rule ID 61285 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVSADDU_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61285,
        GIR_Done,
      // Label 3224: @93303
      GIM_Reject,
    // Label 3222: @93304
    GIM_Reject,
    // Label 3162: @93305
    GIM_Try, /*On fail goto*//*Label 3225*/ 93388,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3226*/ 93357, // Rule ID 61302 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVSADDU_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61302,
        GIR_Done,
      // Label 3226: @93357
      GIM_Try, /*On fail goto*//*Label 3227*/ 93387, // Rule ID 61303 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVSADDU_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61303,
        GIR_Done,
      // Label 3227: @93387
      GIM_Reject,
    // Label 3225: @93388
    GIM_Reject,
    // Label 3163: @93389
    GIM_Try, /*On fail goto*//*Label 3228*/ 93472,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv64s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3229*/ 93441, // Rule ID 61290 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVSADDU_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61290,
        GIR_Done,
      // Label 3229: @93441
      GIM_Try, /*On fail goto*//*Label 3230*/ 93471, // Rule ID 61291 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (uaddsat:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVSADDU_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADDU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61291,
        GIR_Done,
      // Label 3230: @93471
      GIM_Reject,
    // Label 3228: @93472
    GIM_Reject,
    // Label 3164: @93473
    GIM_Reject,
    // Label 42: @93474
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 32, /*)*//*default:*//*Label 3253*/ 95356,
    /*GILLT_nxv1s8*//*Label 3231*/ 93508,
    /*GILLT_nxv1s16*//*Label 3232*/ 93592,
    /*GILLT_nxv1s32*//*Label 3233*/ 93676,
    /*GILLT_nxv1s64*//*Label 3234*/ 93760, 0,
    /*GILLT_nxv2s8*//*Label 3235*/ 93844,
    /*GILLT_nxv2s16*//*Label 3236*/ 93928,
    /*GILLT_nxv2s32*//*Label 3237*/ 94012,
    /*GILLT_nxv2s64*//*Label 3238*/ 94096, 0,
    /*GILLT_nxv4s8*//*Label 3239*/ 94180,
    /*GILLT_nxv4s16*//*Label 3240*/ 94264,
    /*GILLT_nxv4s32*//*Label 3241*/ 94348,
    /*GILLT_nxv4s64*//*Label 3242*/ 94432, 0,
    /*GILLT_nxv8s8*//*Label 3243*/ 94516,
    /*GILLT_nxv8s16*//*Label 3244*/ 94600,
    /*GILLT_nxv8s32*//*Label 3245*/ 94684,
    /*GILLT_nxv8s64*//*Label 3246*/ 94768, 0,
    /*GILLT_nxv16s8*//*Label 3247*/ 94852,
    /*GILLT_nxv16s16*//*Label 3248*/ 94936,
    /*GILLT_nxv16s32*//*Label 3249*/ 95020, 0,
    /*GILLT_nxv32s8*//*Label 3250*/ 95104,
    /*GILLT_nxv32s16*//*Label 3251*/ 95188, 0,
    /*GILLT_nxv64s8*//*Label 3252*/ 95272,
    // Label 3231: @93508
    GIM_Try, /*On fail goto*//*Label 3254*/ 93591,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3255*/ 93560, // Rule ID 61094 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVSADD_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61094,
        GIR_Done,
      // Label 3255: @93560
      GIM_Try, /*On fail goto*//*Label 3256*/ 93590, // Rule ID 61095 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVSADD_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61095,
        GIR_Done,
      // Label 3256: @93590
      GIM_Reject,
    // Label 3254: @93591
    GIM_Reject,
    // Label 3232: @93592
    GIM_Try, /*On fail goto*//*Label 3257*/ 93675,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3258*/ 93644, // Rule ID 61108 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVSADD_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61108,
        GIR_Done,
      // Label 3258: @93644
      GIM_Try, /*On fail goto*//*Label 3259*/ 93674, // Rule ID 61109 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVSADD_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61109,
        GIR_Done,
      // Label 3259: @93674
      GIM_Reject,
    // Label 3257: @93675
    GIM_Reject,
    // Label 3233: @93676
    GIM_Try, /*On fail goto*//*Label 3260*/ 93759,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3261*/ 93728, // Rule ID 61116 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVSADD_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61116,
        GIR_Done,
      // Label 3261: @93728
      GIM_Try, /*On fail goto*//*Label 3262*/ 93758, // Rule ID 61117 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVSADD_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61117,
        GIR_Done,
      // Label 3262: @93758
      GIM_Reject,
    // Label 3260: @93759
    GIM_Reject,
    // Label 3234: @93760
    GIM_Try, /*On fail goto*//*Label 3263*/ 93843,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3264*/ 93812, // Rule ID 61132 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVSADD_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61132,
        GIR_Done,
      // Label 3264: @93812
      GIM_Try, /*On fail goto*//*Label 3265*/ 93842, // Rule ID 61133 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVSADD_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61133,
        GIR_Done,
      // Label 3265: @93842
      GIM_Reject,
    // Label 3263: @93843
    GIM_Reject,
    // Label 3235: @93844
    GIM_Try, /*On fail goto*//*Label 3266*/ 93927,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3267*/ 93896, // Rule ID 61100 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVSADD_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61100,
        GIR_Done,
      // Label 3267: @93896
      GIM_Try, /*On fail goto*//*Label 3268*/ 93926, // Rule ID 61101 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVSADD_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61101,
        GIR_Done,
      // Label 3268: @93926
      GIM_Reject,
    // Label 3266: @93927
    GIM_Reject,
    // Label 3236: @93928
    GIM_Try, /*On fail goto*//*Label 3269*/ 94011,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3270*/ 93980, // Rule ID 61112 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVSADD_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61112,
        GIR_Done,
      // Label 3270: @93980
      GIM_Try, /*On fail goto*//*Label 3271*/ 94010, // Rule ID 61113 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVSADD_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61113,
        GIR_Done,
      // Label 3271: @94010
      GIM_Reject,
    // Label 3269: @94011
    GIM_Reject,
    // Label 3237: @94012
    GIM_Try, /*On fail goto*//*Label 3272*/ 94095,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3273*/ 94064, // Rule ID 61128 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVSADD_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61128,
        GIR_Done,
      // Label 3273: @94064
      GIM_Try, /*On fail goto*//*Label 3274*/ 94094, // Rule ID 61129 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVSADD_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61129,
        GIR_Done,
      // Label 3274: @94094
      GIM_Reject,
    // Label 3272: @94095
    GIM_Reject,
    // Label 3238: @94096
    GIM_Try, /*On fail goto*//*Label 3275*/ 94179,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3276*/ 94148, // Rule ID 61176 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVSADD_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61176,
        GIR_Done,
      // Label 3276: @94148
      GIM_Try, /*On fail goto*//*Label 3277*/ 94178, // Rule ID 61177 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVSADD_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61177,
        GIR_Done,
      // Label 3277: @94178
      GIM_Reject,
    // Label 3275: @94179
    GIM_Reject,
    // Label 3239: @94180
    GIM_Try, /*On fail goto*//*Label 3278*/ 94263,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3279*/ 94232, // Rule ID 61104 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVSADD_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61104,
        GIR_Done,
      // Label 3279: @94232
      GIM_Try, /*On fail goto*//*Label 3280*/ 94262, // Rule ID 61105 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVSADD_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61105,
        GIR_Done,
      // Label 3280: @94262
      GIM_Reject,
    // Label 3278: @94263
    GIM_Reject,
    // Label 3240: @94264
    GIM_Try, /*On fail goto*//*Label 3281*/ 94347,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3282*/ 94316, // Rule ID 61124 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVSADD_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61124,
        GIR_Done,
      // Label 3282: @94316
      GIM_Try, /*On fail goto*//*Label 3283*/ 94346, // Rule ID 61125 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVSADD_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61125,
        GIR_Done,
      // Label 3283: @94346
      GIM_Reject,
    // Label 3281: @94347
    GIM_Reject,
    // Label 3241: @94348
    GIM_Try, /*On fail goto*//*Label 3284*/ 94431,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3285*/ 94400, // Rule ID 61164 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVSADD_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61164,
        GIR_Done,
      // Label 3285: @94400
      GIM_Try, /*On fail goto*//*Label 3286*/ 94430, // Rule ID 61165 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVSADD_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61165,
        GIR_Done,
      // Label 3286: @94430
      GIM_Reject,
    // Label 3284: @94431
    GIM_Reject,
    // Label 3242: @94432
    GIM_Try, /*On fail goto*//*Label 3287*/ 94515,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3288*/ 94484, // Rule ID 61180 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVSADD_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61180,
        GIR_Done,
      // Label 3288: @94484
      GIM_Try, /*On fail goto*//*Label 3289*/ 94514, // Rule ID 61181 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVSADD_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61181,
        GIR_Done,
      // Label 3289: @94514
      GIM_Reject,
    // Label 3287: @94515
    GIM_Reject,
    // Label 3243: @94516
    GIM_Try, /*On fail goto*//*Label 3290*/ 94599,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3291*/ 94568, // Rule ID 61120 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVSADD_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61120,
        GIR_Done,
      // Label 3291: @94568
      GIM_Try, /*On fail goto*//*Label 3292*/ 94598, // Rule ID 61121 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVSADD_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61121,
        GIR_Done,
      // Label 3292: @94598
      GIM_Reject,
    // Label 3290: @94599
    GIM_Reject,
    // Label 3244: @94600
    GIM_Try, /*On fail goto*//*Label 3293*/ 94683,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3294*/ 94652, // Rule ID 61150 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVSADD_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61150,
        GIR_Done,
      // Label 3294: @94652
      GIM_Try, /*On fail goto*//*Label 3295*/ 94682, // Rule ID 61151 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVSADD_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61151,
        GIR_Done,
      // Label 3295: @94682
      GIM_Reject,
    // Label 3293: @94683
    GIM_Reject,
    // Label 3245: @94684
    GIM_Try, /*On fail goto*//*Label 3296*/ 94767,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3297*/ 94736, // Rule ID 61168 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVSADD_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61168,
        GIR_Done,
      // Label 3297: @94736
      GIM_Try, /*On fail goto*//*Label 3298*/ 94766, // Rule ID 61169 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVSADD_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61169,
        GIR_Done,
      // Label 3298: @94766
      GIM_Reject,
    // Label 3296: @94767
    GIM_Reject,
    // Label 3246: @94768
    GIM_Try, /*On fail goto*//*Label 3299*/ 94851,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3300*/ 94820, // Rule ID 61184 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVSADD_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61184,
        GIR_Done,
      // Label 3300: @94820
      GIM_Try, /*On fail goto*//*Label 3301*/ 94850, // Rule ID 61185 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVSADD_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61185,
        GIR_Done,
      // Label 3301: @94850
      GIM_Reject,
    // Label 3299: @94851
    GIM_Reject,
    // Label 3247: @94852
    GIM_Try, /*On fail goto*//*Label 3302*/ 94935,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3303*/ 94904, // Rule ID 61136 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVSADD_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61136,
        GIR_Done,
      // Label 3303: @94904
      GIM_Try, /*On fail goto*//*Label 3304*/ 94934, // Rule ID 61137 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVSADD_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61137,
        GIR_Done,
      // Label 3304: @94934
      GIM_Reject,
    // Label 3302: @94935
    GIM_Reject,
    // Label 3248: @94936
    GIM_Try, /*On fail goto*//*Label 3305*/ 95019,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3306*/ 94988, // Rule ID 61154 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVSADD_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61154,
        GIR_Done,
      // Label 3306: @94988
      GIM_Try, /*On fail goto*//*Label 3307*/ 95018, // Rule ID 61155 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVSADD_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61155,
        GIR_Done,
      // Label 3307: @95018
      GIM_Reject,
    // Label 3305: @95019
    GIM_Reject,
    // Label 3249: @95020
    GIM_Try, /*On fail goto*//*Label 3308*/ 95103,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3309*/ 95072, // Rule ID 61172 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVSADD_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61172,
        GIR_Done,
      // Label 3309: @95072
      GIM_Try, /*On fail goto*//*Label 3310*/ 95102, // Rule ID 61173 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVSADD_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61173,
        GIR_Done,
      // Label 3310: @95102
      GIM_Reject,
    // Label 3308: @95103
    GIM_Reject,
    // Label 3250: @95104
    GIM_Try, /*On fail goto*//*Label 3311*/ 95187,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3312*/ 95156, // Rule ID 61142 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVSADD_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61142,
        GIR_Done,
      // Label 3312: @95156
      GIM_Try, /*On fail goto*//*Label 3313*/ 95186, // Rule ID 61143 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVSADD_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61143,
        GIR_Done,
      // Label 3313: @95186
      GIM_Reject,
    // Label 3311: @95187
    GIM_Reject,
    // Label 3251: @95188
    GIM_Try, /*On fail goto*//*Label 3314*/ 95271,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3315*/ 95240, // Rule ID 61158 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVSADD_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61158,
        GIR_Done,
      // Label 3315: @95240
      GIM_Try, /*On fail goto*//*Label 3316*/ 95270, // Rule ID 61159 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVSADD_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61159,
        GIR_Done,
      // Label 3316: @95270
      GIM_Reject,
    // Label 3314: @95271
    GIM_Reject,
    // Label 3252: @95272
    GIM_Try, /*On fail goto*//*Label 3317*/ 95355,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv64s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3318*/ 95324, // Rule ID 61146 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVSADD_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61146,
        GIR_Done,
      // Label 3318: @95324
      GIM_Try, /*On fail goto*//*Label 3319*/ 95354, // Rule ID 61147 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (saddsat:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVSADD_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61147,
        GIR_Done,
      // Label 3319: @95354
      GIM_Reject,
    // Label 3317: @95355
    GIM_Reject,
    // Label 3253: @95356
    GIM_Reject,
    // Label 43: @95357
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 32, /*)*//*default:*//*Label 3342*/ 97239,
    /*GILLT_nxv1s8*//*Label 3320*/ 95391,
    /*GILLT_nxv1s16*//*Label 3321*/ 95475,
    /*GILLT_nxv1s32*//*Label 3322*/ 95559,
    /*GILLT_nxv1s64*//*Label 3323*/ 95643, 0,
    /*GILLT_nxv2s8*//*Label 3324*/ 95727,
    /*GILLT_nxv2s16*//*Label 3325*/ 95811,
    /*GILLT_nxv2s32*//*Label 3326*/ 95895,
    /*GILLT_nxv2s64*//*Label 3327*/ 95979, 0,
    /*GILLT_nxv4s8*//*Label 3328*/ 96063,
    /*GILLT_nxv4s16*//*Label 3329*/ 96147,
    /*GILLT_nxv4s32*//*Label 3330*/ 96231,
    /*GILLT_nxv4s64*//*Label 3331*/ 96315, 0,
    /*GILLT_nxv8s8*//*Label 3332*/ 96399,
    /*GILLT_nxv8s16*//*Label 3333*/ 96483,
    /*GILLT_nxv8s32*//*Label 3334*/ 96567,
    /*GILLT_nxv8s64*//*Label 3335*/ 96651, 0,
    /*GILLT_nxv16s8*//*Label 3336*/ 96735,
    /*GILLT_nxv16s16*//*Label 3337*/ 96819,
    /*GILLT_nxv16s32*//*Label 3338*/ 96903, 0,
    /*GILLT_nxv32s8*//*Label 3339*/ 96987,
    /*GILLT_nxv32s16*//*Label 3340*/ 97071, 0,
    /*GILLT_nxv64s8*//*Label 3341*/ 97155,
    // Label 3320: @95391
    GIM_Try, /*On fail goto*//*Label 3343*/ 95474,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3344*/ 95443, // Rule ID 61478 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVSSUBU_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61478,
        GIR_Done,
      // Label 3344: @95443
      GIM_Try, /*On fail goto*//*Label 3345*/ 95473, // Rule ID 61479 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVSSUBU_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61479,
        GIR_Done,
      // Label 3345: @95473
      GIM_Reject,
    // Label 3343: @95474
    GIM_Reject,
    // Label 3321: @95475
    GIM_Try, /*On fail goto*//*Label 3346*/ 95558,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3347*/ 95527, // Rule ID 61492 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVSSUBU_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61492,
        GIR_Done,
      // Label 3347: @95527
      GIM_Try, /*On fail goto*//*Label 3348*/ 95557, // Rule ID 61493 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVSSUBU_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61493,
        GIR_Done,
      // Label 3348: @95557
      GIM_Reject,
    // Label 3346: @95558
    GIM_Reject,
    // Label 3322: @95559
    GIM_Try, /*On fail goto*//*Label 3349*/ 95642,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3350*/ 95611, // Rule ID 61500 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVSSUBU_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61500,
        GIR_Done,
      // Label 3350: @95611
      GIM_Try, /*On fail goto*//*Label 3351*/ 95641, // Rule ID 61501 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVSSUBU_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61501,
        GIR_Done,
      // Label 3351: @95641
      GIM_Reject,
    // Label 3349: @95642
    GIM_Reject,
    // Label 3323: @95643
    GIM_Try, /*On fail goto*//*Label 3352*/ 95726,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3353*/ 95695, // Rule ID 61518 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVSSUBU_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61518,
        GIR_Done,
      // Label 3353: @95695
      GIM_Try, /*On fail goto*//*Label 3354*/ 95725, // Rule ID 61519 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVSSUBU_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61519,
        GIR_Done,
      // Label 3354: @95725
      GIM_Reject,
    // Label 3352: @95726
    GIM_Reject,
    // Label 3324: @95727
    GIM_Try, /*On fail goto*//*Label 3355*/ 95810,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3356*/ 95779, // Rule ID 61484 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVSSUBU_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61484,
        GIR_Done,
      // Label 3356: @95779
      GIM_Try, /*On fail goto*//*Label 3357*/ 95809, // Rule ID 61485 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVSSUBU_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61485,
        GIR_Done,
      // Label 3357: @95809
      GIM_Reject,
    // Label 3355: @95810
    GIM_Reject,
    // Label 3325: @95811
    GIM_Try, /*On fail goto*//*Label 3358*/ 95894,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3359*/ 95863, // Rule ID 61496 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVSSUBU_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61496,
        GIR_Done,
      // Label 3359: @95863
      GIM_Try, /*On fail goto*//*Label 3360*/ 95893, // Rule ID 61497 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVSSUBU_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61497,
        GIR_Done,
      // Label 3360: @95893
      GIM_Reject,
    // Label 3358: @95894
    GIM_Reject,
    // Label 3326: @95895
    GIM_Try, /*On fail goto*//*Label 3361*/ 95978,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3362*/ 95947, // Rule ID 61514 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVSSUBU_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61514,
        GIR_Done,
      // Label 3362: @95947
      GIM_Try, /*On fail goto*//*Label 3363*/ 95977, // Rule ID 61515 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVSSUBU_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61515,
        GIR_Done,
      // Label 3363: @95977
      GIM_Reject,
    // Label 3361: @95978
    GIM_Reject,
    // Label 3327: @95979
    GIM_Try, /*On fail goto*//*Label 3364*/ 96062,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3365*/ 96031, // Rule ID 61562 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVSSUBU_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61562,
        GIR_Done,
      // Label 3365: @96031
      GIM_Try, /*On fail goto*//*Label 3366*/ 96061, // Rule ID 61563 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVSSUBU_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61563,
        GIR_Done,
      // Label 3366: @96061
      GIM_Reject,
    // Label 3364: @96062
    GIM_Reject,
    // Label 3328: @96063
    GIM_Try, /*On fail goto*//*Label 3367*/ 96146,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3368*/ 96115, // Rule ID 61488 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVSSUBU_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61488,
        GIR_Done,
      // Label 3368: @96115
      GIM_Try, /*On fail goto*//*Label 3369*/ 96145, // Rule ID 61489 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVSSUBU_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61489,
        GIR_Done,
      // Label 3369: @96145
      GIM_Reject,
    // Label 3367: @96146
    GIM_Reject,
    // Label 3329: @96147
    GIM_Try, /*On fail goto*//*Label 3370*/ 96230,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3371*/ 96199, // Rule ID 61510 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVSSUBU_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61510,
        GIR_Done,
      // Label 3371: @96199
      GIM_Try, /*On fail goto*//*Label 3372*/ 96229, // Rule ID 61511 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVSSUBU_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61511,
        GIR_Done,
      // Label 3372: @96229
      GIM_Reject,
    // Label 3370: @96230
    GIM_Reject,
    // Label 3330: @96231
    GIM_Try, /*On fail goto*//*Label 3373*/ 96314,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3374*/ 96283, // Rule ID 61550 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVSSUBU_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61550,
        GIR_Done,
      // Label 3374: @96283
      GIM_Try, /*On fail goto*//*Label 3375*/ 96313, // Rule ID 61551 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVSSUBU_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61551,
        GIR_Done,
      // Label 3375: @96313
      GIM_Reject,
    // Label 3373: @96314
    GIM_Reject,
    // Label 3331: @96315
    GIM_Try, /*On fail goto*//*Label 3376*/ 96398,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3377*/ 96367, // Rule ID 61566 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVSSUBU_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61566,
        GIR_Done,
      // Label 3377: @96367
      GIM_Try, /*On fail goto*//*Label 3378*/ 96397, // Rule ID 61567 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVSSUBU_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61567,
        GIR_Done,
      // Label 3378: @96397
      GIM_Reject,
    // Label 3376: @96398
    GIM_Reject,
    // Label 3332: @96399
    GIM_Try, /*On fail goto*//*Label 3379*/ 96482,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3380*/ 96451, // Rule ID 61506 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVSSUBU_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61506,
        GIR_Done,
      // Label 3380: @96451
      GIM_Try, /*On fail goto*//*Label 3381*/ 96481, // Rule ID 61507 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVSSUBU_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61507,
        GIR_Done,
      // Label 3381: @96481
      GIM_Reject,
    // Label 3379: @96482
    GIM_Reject,
    // Label 3333: @96483
    GIM_Try, /*On fail goto*//*Label 3382*/ 96566,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3383*/ 96535, // Rule ID 61536 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVSSUBU_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61536,
        GIR_Done,
      // Label 3383: @96535
      GIM_Try, /*On fail goto*//*Label 3384*/ 96565, // Rule ID 61537 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVSSUBU_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61537,
        GIR_Done,
      // Label 3384: @96565
      GIM_Reject,
    // Label 3382: @96566
    GIM_Reject,
    // Label 3334: @96567
    GIM_Try, /*On fail goto*//*Label 3385*/ 96650,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3386*/ 96619, // Rule ID 61554 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVSSUBU_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61554,
        GIR_Done,
      // Label 3386: @96619
      GIM_Try, /*On fail goto*//*Label 3387*/ 96649, // Rule ID 61555 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVSSUBU_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61555,
        GIR_Done,
      // Label 3387: @96649
      GIM_Reject,
    // Label 3385: @96650
    GIM_Reject,
    // Label 3335: @96651
    GIM_Try, /*On fail goto*//*Label 3388*/ 96734,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3389*/ 96703, // Rule ID 61572 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVSSUBU_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61572,
        GIR_Done,
      // Label 3389: @96703
      GIM_Try, /*On fail goto*//*Label 3390*/ 96733, // Rule ID 61573 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVSSUBU_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61573,
        GIR_Done,
      // Label 3390: @96733
      GIM_Reject,
    // Label 3388: @96734
    GIM_Reject,
    // Label 3336: @96735
    GIM_Try, /*On fail goto*//*Label 3391*/ 96818,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3392*/ 96787, // Rule ID 61522 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVSSUBU_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61522,
        GIR_Done,
      // Label 3392: @96787
      GIM_Try, /*On fail goto*//*Label 3393*/ 96817, // Rule ID 61523 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVSSUBU_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61523,
        GIR_Done,
      // Label 3393: @96817
      GIM_Reject,
    // Label 3391: @96818
    GIM_Reject,
    // Label 3337: @96819
    GIM_Try, /*On fail goto*//*Label 3394*/ 96902,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3395*/ 96871, // Rule ID 61540 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVSSUBU_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61540,
        GIR_Done,
      // Label 3395: @96871
      GIM_Try, /*On fail goto*//*Label 3396*/ 96901, // Rule ID 61541 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVSSUBU_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61541,
        GIR_Done,
      // Label 3396: @96901
      GIM_Reject,
    // Label 3394: @96902
    GIM_Reject,
    // Label 3338: @96903
    GIM_Try, /*On fail goto*//*Label 3397*/ 96986,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3398*/ 96955, // Rule ID 61558 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVSSUBU_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61558,
        GIR_Done,
      // Label 3398: @96955
      GIM_Try, /*On fail goto*//*Label 3399*/ 96985, // Rule ID 61559 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVSSUBU_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61559,
        GIR_Done,
      // Label 3399: @96985
      GIM_Reject,
    // Label 3397: @96986
    GIM_Reject,
    // Label 3339: @96987
    GIM_Try, /*On fail goto*//*Label 3400*/ 97070,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3401*/ 97039, // Rule ID 61528 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVSSUBU_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61528,
        GIR_Done,
      // Label 3401: @97039
      GIM_Try, /*On fail goto*//*Label 3402*/ 97069, // Rule ID 61529 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVSSUBU_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61529,
        GIR_Done,
      // Label 3402: @97069
      GIM_Reject,
    // Label 3400: @97070
    GIM_Reject,
    // Label 3340: @97071
    GIM_Try, /*On fail goto*//*Label 3403*/ 97154,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3404*/ 97123, // Rule ID 61544 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVSSUBU_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61544,
        GIR_Done,
      // Label 3404: @97123
      GIM_Try, /*On fail goto*//*Label 3405*/ 97153, // Rule ID 61545 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVSSUBU_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61545,
        GIR_Done,
      // Label 3405: @97153
      GIM_Reject,
    // Label 3403: @97154
    GIM_Reject,
    // Label 3341: @97155
    GIM_Try, /*On fail goto*//*Label 3406*/ 97238,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv64s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3407*/ 97207, // Rule ID 61532 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVSSUBU_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61532,
        GIR_Done,
      // Label 3407: @97207
      GIM_Try, /*On fail goto*//*Label 3408*/ 97237, // Rule ID 61533 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (usubsat:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVSSUBU_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUBU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61533,
        GIR_Done,
      // Label 3408: @97237
      GIM_Reject,
    // Label 3406: @97238
    GIM_Reject,
    // Label 3342: @97239
    GIM_Reject,
    // Label 44: @97240
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 32, /*)*//*default:*//*Label 3431*/ 99122,
    /*GILLT_nxv1s8*//*Label 3409*/ 97274,
    /*GILLT_nxv1s16*//*Label 3410*/ 97358,
    /*GILLT_nxv1s32*//*Label 3411*/ 97442,
    /*GILLT_nxv1s64*//*Label 3412*/ 97526, 0,
    /*GILLT_nxv2s8*//*Label 3413*/ 97610,
    /*GILLT_nxv2s16*//*Label 3414*/ 97694,
    /*GILLT_nxv2s32*//*Label 3415*/ 97778,
    /*GILLT_nxv2s64*//*Label 3416*/ 97862, 0,
    /*GILLT_nxv4s8*//*Label 3417*/ 97946,
    /*GILLT_nxv4s16*//*Label 3418*/ 98030,
    /*GILLT_nxv4s32*//*Label 3419*/ 98114,
    /*GILLT_nxv4s64*//*Label 3420*/ 98198, 0,
    /*GILLT_nxv8s8*//*Label 3421*/ 98282,
    /*GILLT_nxv8s16*//*Label 3422*/ 98366,
    /*GILLT_nxv8s32*//*Label 3423*/ 98450,
    /*GILLT_nxv8s64*//*Label 3424*/ 98534, 0,
    /*GILLT_nxv16s8*//*Label 3425*/ 98618,
    /*GILLT_nxv16s16*//*Label 3426*/ 98702,
    /*GILLT_nxv16s32*//*Label 3427*/ 98786, 0,
    /*GILLT_nxv32s8*//*Label 3428*/ 98870,
    /*GILLT_nxv32s16*//*Label 3429*/ 98954, 0,
    /*GILLT_nxv64s8*//*Label 3430*/ 99038,
    // Label 3409: @97274
    GIM_Try, /*On fail goto*//*Label 3432*/ 97357,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3433*/ 97326, // Rule ID 61382 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVSSUB_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61382,
        GIR_Done,
      // Label 3433: @97326
      GIM_Try, /*On fail goto*//*Label 3434*/ 97356, // Rule ID 61383 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVSSUB_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61383,
        GIR_Done,
      // Label 3434: @97356
      GIM_Reject,
    // Label 3432: @97357
    GIM_Reject,
    // Label 3410: @97358
    GIM_Try, /*On fail goto*//*Label 3435*/ 97441,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3436*/ 97410, // Rule ID 61394 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVSSUB_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61394,
        GIR_Done,
      // Label 3436: @97410
      GIM_Try, /*On fail goto*//*Label 3437*/ 97440, // Rule ID 61395 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVSSUB_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61395,
        GIR_Done,
      // Label 3437: @97440
      GIM_Reject,
    // Label 3435: @97441
    GIM_Reject,
    // Label 3411: @97442
    GIM_Try, /*On fail goto*//*Label 3438*/ 97525,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3439*/ 97494, // Rule ID 61404 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVSSUB_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61404,
        GIR_Done,
      // Label 3439: @97494
      GIM_Try, /*On fail goto*//*Label 3440*/ 97524, // Rule ID 61405 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVSSUB_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61405,
        GIR_Done,
      // Label 3440: @97524
      GIM_Reject,
    // Label 3438: @97525
    GIM_Reject,
    // Label 3412: @97526
    GIM_Try, /*On fail goto*//*Label 3441*/ 97609,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3442*/ 97578, // Rule ID 61422 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVSSUB_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61422,
        GIR_Done,
      // Label 3442: @97578
      GIM_Try, /*On fail goto*//*Label 3443*/ 97608, // Rule ID 61423 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVSSUB_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61423,
        GIR_Done,
      // Label 3443: @97608
      GIM_Reject,
    // Label 3441: @97609
    GIM_Reject,
    // Label 3413: @97610
    GIM_Try, /*On fail goto*//*Label 3444*/ 97693,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3445*/ 97662, // Rule ID 61386 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVSSUB_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61386,
        GIR_Done,
      // Label 3445: @97662
      GIM_Try, /*On fail goto*//*Label 3446*/ 97692, // Rule ID 61387 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVSSUB_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61387,
        GIR_Done,
      // Label 3446: @97692
      GIM_Reject,
    // Label 3444: @97693
    GIM_Reject,
    // Label 3414: @97694
    GIM_Try, /*On fail goto*//*Label 3447*/ 97777,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3448*/ 97746, // Rule ID 61400 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVSSUB_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61400,
        GIR_Done,
      // Label 3448: @97746
      GIM_Try, /*On fail goto*//*Label 3449*/ 97776, // Rule ID 61401 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVSSUB_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61401,
        GIR_Done,
      // Label 3449: @97776
      GIM_Reject,
    // Label 3447: @97777
    GIM_Reject,
    // Label 3415: @97778
    GIM_Try, /*On fail goto*//*Label 3450*/ 97861,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3451*/ 97830, // Rule ID 61416 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVSSUB_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61416,
        GIR_Done,
      // Label 3451: @97830
      GIM_Try, /*On fail goto*//*Label 3452*/ 97860, // Rule ID 61417 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVSSUB_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61417,
        GIR_Done,
      // Label 3452: @97860
      GIM_Reject,
    // Label 3450: @97861
    GIM_Reject,
    // Label 3416: @97862
    GIM_Try, /*On fail goto*//*Label 3453*/ 97945,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3454*/ 97914, // Rule ID 61466 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVSSUB_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61466,
        GIR_Done,
      // Label 3454: @97914
      GIM_Try, /*On fail goto*//*Label 3455*/ 97944, // Rule ID 61467 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVSSUB_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61467,
        GIR_Done,
      // Label 3455: @97944
      GIM_Reject,
    // Label 3453: @97945
    GIM_Reject,
    // Label 3417: @97946
    GIM_Try, /*On fail goto*//*Label 3456*/ 98029,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3457*/ 97998, // Rule ID 61390 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVSSUB_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61390,
        GIR_Done,
      // Label 3457: @97998
      GIM_Try, /*On fail goto*//*Label 3458*/ 98028, // Rule ID 61391 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVSSUB_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61391,
        GIR_Done,
      // Label 3458: @98028
      GIM_Reject,
    // Label 3456: @98029
    GIM_Reject,
    // Label 3418: @98030
    GIM_Try, /*On fail goto*//*Label 3459*/ 98113,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3460*/ 98082, // Rule ID 61412 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVSSUB_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61412,
        GIR_Done,
      // Label 3460: @98082
      GIM_Try, /*On fail goto*//*Label 3461*/ 98112, // Rule ID 61413 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVSSUB_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61413,
        GIR_Done,
      // Label 3461: @98112
      GIM_Reject,
    // Label 3459: @98113
    GIM_Reject,
    // Label 3419: @98114
    GIM_Try, /*On fail goto*//*Label 3462*/ 98197,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3463*/ 98166, // Rule ID 61452 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVSSUB_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61452,
        GIR_Done,
      // Label 3463: @98166
      GIM_Try, /*On fail goto*//*Label 3464*/ 98196, // Rule ID 61453 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVSSUB_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61453,
        GIR_Done,
      // Label 3464: @98196
      GIM_Reject,
    // Label 3462: @98197
    GIM_Reject,
    // Label 3420: @98198
    GIM_Try, /*On fail goto*//*Label 3465*/ 98281,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3466*/ 98250, // Rule ID 61470 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVSSUB_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61470,
        GIR_Done,
      // Label 3466: @98250
      GIM_Try, /*On fail goto*//*Label 3467*/ 98280, // Rule ID 61471 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVSSUB_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61471,
        GIR_Done,
      // Label 3467: @98280
      GIM_Reject,
    // Label 3465: @98281
    GIM_Reject,
    // Label 3421: @98282
    GIM_Try, /*On fail goto*//*Label 3468*/ 98365,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3469*/ 98334, // Rule ID 61408 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVSSUB_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61408,
        GIR_Done,
      // Label 3469: @98334
      GIM_Try, /*On fail goto*//*Label 3470*/ 98364, // Rule ID 61409 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVSSUB_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61409,
        GIR_Done,
      // Label 3470: @98364
      GIM_Reject,
    // Label 3468: @98365
    GIM_Reject,
    // Label 3422: @98366
    GIM_Try, /*On fail goto*//*Label 3471*/ 98449,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3472*/ 98418, // Rule ID 61438 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVSSUB_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61438,
        GIR_Done,
      // Label 3472: @98418
      GIM_Try, /*On fail goto*//*Label 3473*/ 98448, // Rule ID 61439 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVSSUB_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61439,
        GIR_Done,
      // Label 3473: @98448
      GIM_Reject,
    // Label 3471: @98449
    GIM_Reject,
    // Label 3423: @98450
    GIM_Try, /*On fail goto*//*Label 3474*/ 98533,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3475*/ 98502, // Rule ID 61456 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVSSUB_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61456,
        GIR_Done,
      // Label 3475: @98502
      GIM_Try, /*On fail goto*//*Label 3476*/ 98532, // Rule ID 61457 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVSSUB_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61457,
        GIR_Done,
      // Label 3476: @98532
      GIM_Reject,
    // Label 3474: @98533
    GIM_Reject,
    // Label 3424: @98534
    GIM_Try, /*On fail goto*//*Label 3477*/ 98617,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3478*/ 98586, // Rule ID 61474 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVSSUB_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61474,
        GIR_Done,
      // Label 3478: @98586
      GIM_Try, /*On fail goto*//*Label 3479*/ 98616, // Rule ID 61475 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVSSUB_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61475,
        GIR_Done,
      // Label 3479: @98616
      GIM_Reject,
    // Label 3477: @98617
    GIM_Reject,
    // Label 3425: @98618
    GIM_Try, /*On fail goto*//*Label 3480*/ 98701,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3481*/ 98670, // Rule ID 61426 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVSSUB_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61426,
        GIR_Done,
      // Label 3481: @98670
      GIM_Try, /*On fail goto*//*Label 3482*/ 98700, // Rule ID 61427 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVSSUB_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61427,
        GIR_Done,
      // Label 3482: @98700
      GIM_Reject,
    // Label 3480: @98701
    GIM_Reject,
    // Label 3426: @98702
    GIM_Try, /*On fail goto*//*Label 3483*/ 98785,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3484*/ 98754, // Rule ID 61444 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVSSUB_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61444,
        GIR_Done,
      // Label 3484: @98754
      GIM_Try, /*On fail goto*//*Label 3485*/ 98784, // Rule ID 61445 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVSSUB_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61445,
        GIR_Done,
      // Label 3485: @98784
      GIM_Reject,
    // Label 3483: @98785
    GIM_Reject,
    // Label 3427: @98786
    GIM_Try, /*On fail goto*//*Label 3486*/ 98869,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3487*/ 98838, // Rule ID 61460 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVSSUB_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61460,
        GIR_Done,
      // Label 3487: @98838
      GIM_Try, /*On fail goto*//*Label 3488*/ 98868, // Rule ID 61461 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVSSUB_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61461,
        GIR_Done,
      // Label 3488: @98868
      GIM_Reject,
    // Label 3486: @98869
    GIM_Reject,
    // Label 3428: @98870
    GIM_Try, /*On fail goto*//*Label 3489*/ 98953,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3490*/ 98922, // Rule ID 61430 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVSSUB_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61430,
        GIR_Done,
      // Label 3490: @98922
      GIM_Try, /*On fail goto*//*Label 3491*/ 98952, // Rule ID 61431 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVSSUB_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61431,
        GIR_Done,
      // Label 3491: @98952
      GIM_Reject,
    // Label 3489: @98953
    GIM_Reject,
    // Label 3429: @98954
    GIM_Try, /*On fail goto*//*Label 3492*/ 99037,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3493*/ 99006, // Rule ID 61448 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVSSUB_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61448,
        GIR_Done,
      // Label 3493: @99006
      GIM_Try, /*On fail goto*//*Label 3494*/ 99036, // Rule ID 61449 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVSSUB_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61449,
        GIR_Done,
      // Label 3494: @99036
      GIM_Reject,
    // Label 3492: @99037
    GIM_Reject,
    // Label 3430: @99038
    GIM_Try, /*On fail goto*//*Label 3495*/ 99121,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv64s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3496*/ 99090, // Rule ID 61434 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVSSUB_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61434,
        GIR_Done,
      // Label 3496: @99090
      GIM_Try, /*On fail goto*//*Label 3497*/ 99120, // Rule ID 61435 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (ssubsat:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVSSUB_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVSSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61435,
        GIR_Done,
      // Label 3497: @99120
      GIM_Reject,
    // Label 3495: @99121
    GIM_Reject,
    // Label 3431: @99122
    GIM_Reject,
    // Label 45: @99123
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 30, /*)*//*default:*//*Label 3513*/ 100414,
    /*GILLT_nxv1s16*//*Label 3498*/ 99154,
    /*GILLT_nxv1s32*//*Label 3499*/ 99238,
    /*GILLT_nxv1s64*//*Label 3500*/ 99322, 0, 0,
    /*GILLT_nxv2s16*//*Label 3501*/ 99406,
    /*GILLT_nxv2s32*//*Label 3502*/ 99490,
    /*GILLT_nxv2s64*//*Label 3503*/ 99574, 0, 0,
    /*GILLT_nxv4s16*//*Label 3504*/ 99658,
    /*GILLT_nxv4s32*//*Label 3505*/ 99742,
    /*GILLT_nxv4s64*//*Label 3506*/ 99826, 0, 0,
    /*GILLT_nxv8s16*//*Label 3507*/ 99910,
    /*GILLT_nxv8s32*//*Label 3508*/ 99994,
    /*GILLT_nxv8s64*//*Label 3509*/ 100078, 0, 0,
    /*GILLT_nxv16s16*//*Label 3510*/ 100162,
    /*GILLT_nxv16s32*//*Label 3511*/ 100246, 0, 0,
    /*GILLT_nxv32s16*//*Label 3512*/ 100330,
    // Label 3498: @99154
    GIM_Try, /*On fail goto*//*Label 3514*/ 99237,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3515*/ 99206, // Rule ID 54943 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2)  =>  (PseudoVFADD_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 54943,
        GIR_Done,
      // Label 3515: @99206
      GIM_Try, /*On fail goto*//*Label 3516*/ 99236, // Rule ID 54944 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2)  =>  (PseudoVFADD_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 54944,
        GIR_Done,
      // Label 3516: @99236
      GIM_Reject,
    // Label 3514: @99237
    GIM_Reject,
    // Label 3499: @99238
    GIM_Try, /*On fail goto*//*Label 3517*/ 99321,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3518*/ 99290, // Rule ID 61714 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2)  =>  (PseudoVFADD_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61714,
        GIR_Done,
      // Label 3518: @99290
      GIM_Try, /*On fail goto*//*Label 3519*/ 99320, // Rule ID 61715 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2)  =>  (PseudoVFADD_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61715,
        GIR_Done,
      // Label 3519: @99320
      GIM_Reject,
    // Label 3517: @99321
    GIM_Reject,
    // Label 3500: @99322
    GIM_Try, /*On fail goto*//*Label 3520*/ 99405,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3521*/ 99374, // Rule ID 61726 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2)  =>  (PseudoVFADD_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61726,
        GIR_Done,
      // Label 3521: @99374
      GIM_Try, /*On fail goto*//*Label 3522*/ 99404, // Rule ID 61727 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2)  =>  (PseudoVFADD_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61727,
        GIR_Done,
      // Label 3522: @99404
      GIM_Reject,
    // Label 3520: @99405
    GIM_Reject,
    // Label 3501: @99406
    GIM_Try, /*On fail goto*//*Label 3523*/ 99489,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3524*/ 99458, // Rule ID 61710 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2)  =>  (PseudoVFADD_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61710,
        GIR_Done,
      // Label 3524: @99458
      GIM_Try, /*On fail goto*//*Label 3525*/ 99488, // Rule ID 61711 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2)  =>  (PseudoVFADD_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61711,
        GIR_Done,
      // Label 3525: @99488
      GIM_Reject,
    // Label 3523: @99489
    GIM_Reject,
    // Label 3502: @99490
    GIM_Try, /*On fail goto*//*Label 3526*/ 99573,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3527*/ 99542, // Rule ID 61722 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2)  =>  (PseudoVFADD_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61722,
        GIR_Done,
      // Label 3527: @99542
      GIM_Try, /*On fail goto*//*Label 3528*/ 99572, // Rule ID 61723 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2)  =>  (PseudoVFADD_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61723,
        GIR_Done,
      // Label 3528: @99572
      GIM_Reject,
    // Label 3526: @99573
    GIM_Reject,
    // Label 3503: @99574
    GIM_Try, /*On fail goto*//*Label 3529*/ 99657,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3530*/ 99626, // Rule ID 61756 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2)  =>  (PseudoVFADD_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61756,
        GIR_Done,
      // Label 3530: @99626
      GIM_Try, /*On fail goto*//*Label 3531*/ 99656, // Rule ID 61757 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2)  =>  (PseudoVFADD_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61757,
        GIR_Done,
      // Label 3531: @99656
      GIM_Reject,
    // Label 3529: @99657
    GIM_Reject,
    // Label 3504: @99658
    GIM_Try, /*On fail goto*//*Label 3532*/ 99741,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3533*/ 99710, // Rule ID 61718 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2)  =>  (PseudoVFADD_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61718,
        GIR_Done,
      // Label 3533: @99710
      GIM_Try, /*On fail goto*//*Label 3534*/ 99740, // Rule ID 61719 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2)  =>  (PseudoVFADD_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61719,
        GIR_Done,
      // Label 3534: @99740
      GIM_Reject,
    // Label 3532: @99741
    GIM_Reject,
    // Label 3505: @99742
    GIM_Try, /*On fail goto*//*Label 3535*/ 99825,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3536*/ 99794, // Rule ID 61744 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2)  =>  (PseudoVFADD_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61744,
        GIR_Done,
      // Label 3536: @99794
      GIM_Try, /*On fail goto*//*Label 3537*/ 99824, // Rule ID 61745 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2)  =>  (PseudoVFADD_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61745,
        GIR_Done,
      // Label 3537: @99824
      GIM_Reject,
    // Label 3535: @99825
    GIM_Reject,
    // Label 3506: @99826
    GIM_Try, /*On fail goto*//*Label 3538*/ 99909,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3539*/ 99878, // Rule ID 61760 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2)  =>  (PseudoVFADD_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61760,
        GIR_Done,
      // Label 3539: @99878
      GIM_Try, /*On fail goto*//*Label 3540*/ 99908, // Rule ID 61761 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2)  =>  (PseudoVFADD_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61761,
        GIR_Done,
      // Label 3540: @99908
      GIM_Reject,
    // Label 3538: @99909
    GIM_Reject,
    // Label 3507: @99910
    GIM_Try, /*On fail goto*//*Label 3541*/ 99993,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3542*/ 99962, // Rule ID 61730 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2)  =>  (PseudoVFADD_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61730,
        GIR_Done,
      // Label 3542: @99962
      GIM_Try, /*On fail goto*//*Label 3543*/ 99992, // Rule ID 61731 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2)  =>  (PseudoVFADD_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61731,
        GIR_Done,
      // Label 3543: @99992
      GIM_Reject,
    // Label 3541: @99993
    GIM_Reject,
    // Label 3508: @99994
    GIM_Try, /*On fail goto*//*Label 3544*/ 100077,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3545*/ 100046, // Rule ID 61748 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2)  =>  (PseudoVFADD_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61748,
        GIR_Done,
      // Label 3545: @100046
      GIM_Try, /*On fail goto*//*Label 3546*/ 100076, // Rule ID 61749 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2)  =>  (PseudoVFADD_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61749,
        GIR_Done,
      // Label 3546: @100076
      GIM_Reject,
    // Label 3544: @100077
    GIM_Reject,
    // Label 3509: @100078
    GIM_Try, /*On fail goto*//*Label 3547*/ 100161,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3548*/ 100130, // Rule ID 61764 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2)  =>  (PseudoVFADD_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61764,
        GIR_Done,
      // Label 3548: @100130
      GIM_Try, /*On fail goto*//*Label 3549*/ 100160, // Rule ID 61765 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2)  =>  (PseudoVFADD_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61765,
        GIR_Done,
      // Label 3549: @100160
      GIM_Reject,
    // Label 3547: @100161
    GIM_Reject,
    // Label 3510: @100162
    GIM_Try, /*On fail goto*//*Label 3550*/ 100245,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3551*/ 100214, // Rule ID 61734 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2)  =>  (PseudoVFADD_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61734,
        GIR_Done,
      // Label 3551: @100214
      GIM_Try, /*On fail goto*//*Label 3552*/ 100244, // Rule ID 61735 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2)  =>  (PseudoVFADD_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61735,
        GIR_Done,
      // Label 3552: @100244
      GIM_Reject,
    // Label 3550: @100245
    GIM_Reject,
    // Label 3511: @100246
    GIM_Try, /*On fail goto*//*Label 3553*/ 100329,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3554*/ 100298, // Rule ID 61752 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2)  =>  (PseudoVFADD_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61752,
        GIR_Done,
      // Label 3554: @100298
      GIM_Try, /*On fail goto*//*Label 3555*/ 100328, // Rule ID 61753 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2)  =>  (PseudoVFADD_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61753,
        GIR_Done,
      // Label 3555: @100328
      GIM_Reject,
    // Label 3553: @100329
    GIM_Reject,
    // Label 3512: @100330
    GIM_Try, /*On fail goto*//*Label 3556*/ 100413,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3557*/ 100382, // Rule ID 61740 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2)  =>  (PseudoVFADD_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61740,
        GIR_Done,
      // Label 3557: @100382
      GIM_Try, /*On fail goto*//*Label 3558*/ 100412, // Rule ID 61741 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fadd:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2)  =>  (PseudoVFADD_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61741,
        GIR_Done,
      // Label 3558: @100412
      GIM_Reject,
    // Label 3556: @100413
    GIM_Reject,
    // Label 3513: @100414
    GIM_Reject,
    // Label 46: @100415
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 30, /*)*//*default:*//*Label 3574*/ 101706,
    /*GILLT_nxv1s16*//*Label 3559*/ 100446,
    /*GILLT_nxv1s32*//*Label 3560*/ 100530,
    /*GILLT_nxv1s64*//*Label 3561*/ 100614, 0, 0,
    /*GILLT_nxv2s16*//*Label 3562*/ 100698,
    /*GILLT_nxv2s32*//*Label 3563*/ 100782,
    /*GILLT_nxv2s64*//*Label 3564*/ 100866, 0, 0,
    /*GILLT_nxv4s16*//*Label 3565*/ 100950,
    /*GILLT_nxv4s32*//*Label 3566*/ 101034,
    /*GILLT_nxv4s64*//*Label 3567*/ 101118, 0, 0,
    /*GILLT_nxv8s16*//*Label 3568*/ 101202,
    /*GILLT_nxv8s32*//*Label 3569*/ 101286,
    /*GILLT_nxv8s64*//*Label 3570*/ 101370, 0, 0,
    /*GILLT_nxv16s16*//*Label 3571*/ 101454,
    /*GILLT_nxv16s32*//*Label 3572*/ 101538, 0, 0,
    /*GILLT_nxv32s16*//*Label 3573*/ 101622,
    // Label 3559: @100446
    GIM_Try, /*On fail goto*//*Label 3575*/ 100529,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3576*/ 100498, // Rule ID 61768 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2)  =>  (PseudoVFSUB_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61768,
        GIR_Done,
      // Label 3576: @100498
      GIM_Try, /*On fail goto*//*Label 3577*/ 100528, // Rule ID 61769 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2)  =>  (PseudoVFSUB_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61769,
        GIR_Done,
      // Label 3577: @100528
      GIM_Reject,
    // Label 3575: @100529
    GIM_Reject,
    // Label 3560: @100530
    GIM_Try, /*On fail goto*//*Label 3578*/ 100613,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3579*/ 100582, // Rule ID 61776 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2)  =>  (PseudoVFSUB_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61776,
        GIR_Done,
      // Label 3579: @100582
      GIM_Try, /*On fail goto*//*Label 3580*/ 100612, // Rule ID 61777 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2)  =>  (PseudoVFSUB_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61777,
        GIR_Done,
      // Label 3580: @100612
      GIM_Reject,
    // Label 3578: @100613
    GIM_Reject,
    // Label 3561: @100614
    GIM_Try, /*On fail goto*//*Label 3581*/ 100697,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3582*/ 100666, // Rule ID 61790 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2)  =>  (PseudoVFSUB_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61790,
        GIR_Done,
      // Label 3582: @100666
      GIM_Try, /*On fail goto*//*Label 3583*/ 100696, // Rule ID 61791 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2)  =>  (PseudoVFSUB_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61791,
        GIR_Done,
      // Label 3583: @100696
      GIM_Reject,
    // Label 3581: @100697
    GIM_Reject,
    // Label 3562: @100698
    GIM_Try, /*On fail goto*//*Label 3584*/ 100781,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3585*/ 100750, // Rule ID 61772 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2)  =>  (PseudoVFSUB_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61772,
        GIR_Done,
      // Label 3585: @100750
      GIM_Try, /*On fail goto*//*Label 3586*/ 100780, // Rule ID 61773 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2)  =>  (PseudoVFSUB_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61773,
        GIR_Done,
      // Label 3586: @100780
      GIM_Reject,
    // Label 3584: @100781
    GIM_Reject,
    // Label 3563: @100782
    GIM_Try, /*On fail goto*//*Label 3587*/ 100865,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3588*/ 100834, // Rule ID 61786 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2)  =>  (PseudoVFSUB_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61786,
        GIR_Done,
      // Label 3588: @100834
      GIM_Try, /*On fail goto*//*Label 3589*/ 100864, // Rule ID 61787 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2)  =>  (PseudoVFSUB_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61787,
        GIR_Done,
      // Label 3589: @100864
      GIM_Reject,
    // Label 3587: @100865
    GIM_Reject,
    // Label 3564: @100866
    GIM_Try, /*On fail goto*//*Label 3590*/ 100949,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3591*/ 100918, // Rule ID 61818 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2)  =>  (PseudoVFSUB_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61818,
        GIR_Done,
      // Label 3591: @100918
      GIM_Try, /*On fail goto*//*Label 3592*/ 100948, // Rule ID 61819 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2)  =>  (PseudoVFSUB_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61819,
        GIR_Done,
      // Label 3592: @100948
      GIM_Reject,
    // Label 3590: @100949
    GIM_Reject,
    // Label 3565: @100950
    GIM_Try, /*On fail goto*//*Label 3593*/ 101033,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3594*/ 101002, // Rule ID 61782 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2)  =>  (PseudoVFSUB_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61782,
        GIR_Done,
      // Label 3594: @101002
      GIM_Try, /*On fail goto*//*Label 3595*/ 101032, // Rule ID 61783 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2)  =>  (PseudoVFSUB_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61783,
        GIR_Done,
      // Label 3595: @101032
      GIM_Reject,
    // Label 3593: @101033
    GIM_Reject,
    // Label 3566: @101034
    GIM_Try, /*On fail goto*//*Label 3596*/ 101117,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3597*/ 101086, // Rule ID 61806 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2)  =>  (PseudoVFSUB_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61806,
        GIR_Done,
      // Label 3597: @101086
      GIM_Try, /*On fail goto*//*Label 3598*/ 101116, // Rule ID 61807 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2)  =>  (PseudoVFSUB_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61807,
        GIR_Done,
      // Label 3598: @101116
      GIM_Reject,
    // Label 3596: @101117
    GIM_Reject,
    // Label 3567: @101118
    GIM_Try, /*On fail goto*//*Label 3599*/ 101201,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3600*/ 101170, // Rule ID 61823 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2)  =>  (PseudoVFSUB_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61823,
        GIR_Done,
      // Label 3600: @101170
      GIM_Try, /*On fail goto*//*Label 3601*/ 101200, // Rule ID 61824 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2)  =>  (PseudoVFSUB_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61824,
        GIR_Done,
      // Label 3601: @101200
      GIM_Reject,
    // Label 3599: @101201
    GIM_Reject,
    // Label 3568: @101202
    GIM_Try, /*On fail goto*//*Label 3602*/ 101285,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3603*/ 101254, // Rule ID 61794 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2)  =>  (PseudoVFSUB_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61794,
        GIR_Done,
      // Label 3603: @101254
      GIM_Try, /*On fail goto*//*Label 3604*/ 101284, // Rule ID 61795 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2)  =>  (PseudoVFSUB_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61795,
        GIR_Done,
      // Label 3604: @101284
      GIM_Reject,
    // Label 3602: @101285
    GIM_Reject,
    // Label 3569: @101286
    GIM_Try, /*On fail goto*//*Label 3605*/ 101369,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3606*/ 101338, // Rule ID 61810 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2)  =>  (PseudoVFSUB_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61810,
        GIR_Done,
      // Label 3606: @101338
      GIM_Try, /*On fail goto*//*Label 3607*/ 101368, // Rule ID 61811 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2)  =>  (PseudoVFSUB_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61811,
        GIR_Done,
      // Label 3607: @101368
      GIM_Reject,
    // Label 3605: @101369
    GIM_Reject,
    // Label 3570: @101370
    GIM_Try, /*On fail goto*//*Label 3608*/ 101453,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3609*/ 101422, // Rule ID 61827 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2)  =>  (PseudoVFSUB_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61827,
        GIR_Done,
      // Label 3609: @101422
      GIM_Try, /*On fail goto*//*Label 3610*/ 101452, // Rule ID 61828 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2)  =>  (PseudoVFSUB_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61828,
        GIR_Done,
      // Label 3610: @101452
      GIM_Reject,
    // Label 3608: @101453
    GIM_Reject,
    // Label 3571: @101454
    GIM_Try, /*On fail goto*//*Label 3611*/ 101537,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3612*/ 101506, // Rule ID 61798 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2)  =>  (PseudoVFSUB_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61798,
        GIR_Done,
      // Label 3612: @101506
      GIM_Try, /*On fail goto*//*Label 3613*/ 101536, // Rule ID 61799 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2)  =>  (PseudoVFSUB_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61799,
        GIR_Done,
      // Label 3613: @101536
      GIM_Reject,
    // Label 3611: @101537
    GIM_Reject,
    // Label 3572: @101538
    GIM_Try, /*On fail goto*//*Label 3614*/ 101621,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3615*/ 101590, // Rule ID 61814 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2)  =>  (PseudoVFSUB_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61814,
        GIR_Done,
      // Label 3615: @101590
      GIM_Try, /*On fail goto*//*Label 3616*/ 101620, // Rule ID 61815 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2)  =>  (PseudoVFSUB_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61815,
        GIR_Done,
      // Label 3616: @101620
      GIM_Reject,
    // Label 3614: @101621
    GIM_Reject,
    // Label 3573: @101622
    GIM_Try, /*On fail goto*//*Label 3617*/ 101705,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3618*/ 101674, // Rule ID 61802 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2)  =>  (PseudoVFSUB_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61802,
        GIR_Done,
      // Label 3618: @101674
      GIM_Try, /*On fail goto*//*Label 3619*/ 101704, // Rule ID 61803 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsub:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2)  =>  (PseudoVFSUB_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 61803,
        GIR_Done,
      // Label 3619: @101704
      GIM_Reject,
    // Label 3617: @101705
    GIM_Reject,
    // Label 3574: @101706
    GIM_Reject,
    // Label 47: @101707
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 30, /*)*//*default:*//*Label 3635*/ 102998,
    /*GILLT_nxv1s16*//*Label 3620*/ 101738,
    /*GILLT_nxv1s32*//*Label 3621*/ 101822,
    /*GILLT_nxv1s64*//*Label 3622*/ 101906, 0, 0,
    /*GILLT_nxv2s16*//*Label 3623*/ 101990,
    /*GILLT_nxv2s32*//*Label 3624*/ 102074,
    /*GILLT_nxv2s64*//*Label 3625*/ 102158, 0, 0,
    /*GILLT_nxv4s16*//*Label 3626*/ 102242,
    /*GILLT_nxv4s32*//*Label 3627*/ 102326,
    /*GILLT_nxv4s64*//*Label 3628*/ 102410, 0, 0,
    /*GILLT_nxv8s16*//*Label 3629*/ 102494,
    /*GILLT_nxv8s32*//*Label 3630*/ 102578,
    /*GILLT_nxv8s64*//*Label 3631*/ 102662, 0, 0,
    /*GILLT_nxv16s16*//*Label 3632*/ 102746,
    /*GILLT_nxv16s32*//*Label 3633*/ 102830, 0, 0,
    /*GILLT_nxv32s16*//*Label 3634*/ 102914,
    // Label 3620: @101738
    GIM_Try, /*On fail goto*//*Label 3636*/ 101821,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3637*/ 101790, // Rule ID 62144 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2)  =>  (PseudoVFMUL_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62144,
        GIR_Done,
      // Label 3637: @101790
      GIM_Try, /*On fail goto*//*Label 3638*/ 101820, // Rule ID 62145 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2)  =>  (PseudoVFMUL_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62145,
        GIR_Done,
      // Label 3638: @101820
      GIM_Reject,
    // Label 3636: @101821
    GIM_Reject,
    // Label 3621: @101822
    GIM_Try, /*On fail goto*//*Label 3639*/ 101905,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3640*/ 101874, // Rule ID 62152 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2)  =>  (PseudoVFMUL_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62152,
        GIR_Done,
      // Label 3640: @101874
      GIM_Try, /*On fail goto*//*Label 3641*/ 101904, // Rule ID 62153 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2)  =>  (PseudoVFMUL_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62153,
        GIR_Done,
      // Label 3641: @101904
      GIM_Reject,
    // Label 3639: @101905
    GIM_Reject,
    // Label 3622: @101906
    GIM_Try, /*On fail goto*//*Label 3642*/ 101989,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3643*/ 101958, // Rule ID 62166 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2)  =>  (PseudoVFMUL_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62166,
        GIR_Done,
      // Label 3643: @101958
      GIM_Try, /*On fail goto*//*Label 3644*/ 101988, // Rule ID 62167 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2)  =>  (PseudoVFMUL_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62167,
        GIR_Done,
      // Label 3644: @101988
      GIM_Reject,
    // Label 3642: @101989
    GIM_Reject,
    // Label 3623: @101990
    GIM_Try, /*On fail goto*//*Label 3645*/ 102073,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3646*/ 102042, // Rule ID 62148 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2)  =>  (PseudoVFMUL_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62148,
        GIR_Done,
      // Label 3646: @102042
      GIM_Try, /*On fail goto*//*Label 3647*/ 102072, // Rule ID 62149 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2)  =>  (PseudoVFMUL_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62149,
        GIR_Done,
      // Label 3647: @102072
      GIM_Reject,
    // Label 3645: @102073
    GIM_Reject,
    // Label 3624: @102074
    GIM_Try, /*On fail goto*//*Label 3648*/ 102157,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3649*/ 102126, // Rule ID 62162 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2)  =>  (PseudoVFMUL_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62162,
        GIR_Done,
      // Label 3649: @102126
      GIM_Try, /*On fail goto*//*Label 3650*/ 102156, // Rule ID 62163 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2)  =>  (PseudoVFMUL_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62163,
        GIR_Done,
      // Label 3650: @102156
      GIM_Reject,
    // Label 3648: @102157
    GIM_Reject,
    // Label 3625: @102158
    GIM_Try, /*On fail goto*//*Label 3651*/ 102241,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3652*/ 102210, // Rule ID 62196 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2)  =>  (PseudoVFMUL_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62196,
        GIR_Done,
      // Label 3652: @102210
      GIM_Try, /*On fail goto*//*Label 3653*/ 102240, // Rule ID 62197 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2)  =>  (PseudoVFMUL_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62197,
        GIR_Done,
      // Label 3653: @102240
      GIM_Reject,
    // Label 3651: @102241
    GIM_Reject,
    // Label 3626: @102242
    GIM_Try, /*On fail goto*//*Label 3654*/ 102325,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3655*/ 102294, // Rule ID 62158 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2)  =>  (PseudoVFMUL_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62158,
        GIR_Done,
      // Label 3655: @102294
      GIM_Try, /*On fail goto*//*Label 3656*/ 102324, // Rule ID 62159 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2)  =>  (PseudoVFMUL_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62159,
        GIR_Done,
      // Label 3656: @102324
      GIM_Reject,
    // Label 3654: @102325
    GIM_Reject,
    // Label 3627: @102326
    GIM_Try, /*On fail goto*//*Label 3657*/ 102409,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3658*/ 102378, // Rule ID 62184 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2)  =>  (PseudoVFMUL_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62184,
        GIR_Done,
      // Label 3658: @102378
      GIM_Try, /*On fail goto*//*Label 3659*/ 102408, // Rule ID 62185 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2)  =>  (PseudoVFMUL_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62185,
        GIR_Done,
      // Label 3659: @102408
      GIM_Reject,
    // Label 3657: @102409
    GIM_Reject,
    // Label 3628: @102410
    GIM_Try, /*On fail goto*//*Label 3660*/ 102493,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3661*/ 102462, // Rule ID 62201 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2)  =>  (PseudoVFMUL_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62201,
        GIR_Done,
      // Label 3661: @102462
      GIM_Try, /*On fail goto*//*Label 3662*/ 102492, // Rule ID 62202 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2)  =>  (PseudoVFMUL_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62202,
        GIR_Done,
      // Label 3662: @102492
      GIM_Reject,
    // Label 3660: @102493
    GIM_Reject,
    // Label 3629: @102494
    GIM_Try, /*On fail goto*//*Label 3663*/ 102577,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3664*/ 102546, // Rule ID 62170 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2)  =>  (PseudoVFMUL_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62170,
        GIR_Done,
      // Label 3664: @102546
      GIM_Try, /*On fail goto*//*Label 3665*/ 102576, // Rule ID 62171 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2)  =>  (PseudoVFMUL_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62171,
        GIR_Done,
      // Label 3665: @102576
      GIM_Reject,
    // Label 3663: @102577
    GIM_Reject,
    // Label 3630: @102578
    GIM_Try, /*On fail goto*//*Label 3666*/ 102661,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3667*/ 102630, // Rule ID 62188 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2)  =>  (PseudoVFMUL_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62188,
        GIR_Done,
      // Label 3667: @102630
      GIM_Try, /*On fail goto*//*Label 3668*/ 102660, // Rule ID 62189 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2)  =>  (PseudoVFMUL_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62189,
        GIR_Done,
      // Label 3668: @102660
      GIM_Reject,
    // Label 3666: @102661
    GIM_Reject,
    // Label 3631: @102662
    GIM_Try, /*On fail goto*//*Label 3669*/ 102745,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3670*/ 102714, // Rule ID 62205 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2)  =>  (PseudoVFMUL_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62205,
        GIR_Done,
      // Label 3670: @102714
      GIM_Try, /*On fail goto*//*Label 3671*/ 102744, // Rule ID 62206 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2)  =>  (PseudoVFMUL_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62206,
        GIR_Done,
      // Label 3671: @102744
      GIM_Reject,
    // Label 3669: @102745
    GIM_Reject,
    // Label 3632: @102746
    GIM_Try, /*On fail goto*//*Label 3672*/ 102829,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3673*/ 102798, // Rule ID 62174 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2)  =>  (PseudoVFMUL_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62174,
        GIR_Done,
      // Label 3673: @102798
      GIM_Try, /*On fail goto*//*Label 3674*/ 102828, // Rule ID 62175 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2)  =>  (PseudoVFMUL_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62175,
        GIR_Done,
      // Label 3674: @102828
      GIM_Reject,
    // Label 3672: @102829
    GIM_Reject,
    // Label 3633: @102830
    GIM_Try, /*On fail goto*//*Label 3675*/ 102913,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3676*/ 102882, // Rule ID 62192 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2)  =>  (PseudoVFMUL_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62192,
        GIR_Done,
      // Label 3676: @102882
      GIM_Try, /*On fail goto*//*Label 3677*/ 102912, // Rule ID 62193 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2)  =>  (PseudoVFMUL_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62193,
        GIR_Done,
      // Label 3677: @102912
      GIM_Reject,
    // Label 3675: @102913
    GIM_Reject,
    // Label 3634: @102914
    GIM_Try, /*On fail goto*//*Label 3678*/ 102997,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3679*/ 102966, // Rule ID 62180 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2)  =>  (PseudoVFMUL_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62180,
        GIR_Done,
      // Label 3679: @102966
      GIM_Try, /*On fail goto*//*Label 3680*/ 102996, // Rule ID 62181 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmul:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2)  =>  (PseudoVFMUL_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMUL_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62181,
        GIR_Done,
      // Label 3680: @102996
      GIM_Reject,
    // Label 3678: @102997
    GIM_Reject,
    // Label 3635: @102998
    GIM_Reject,
    // Label 48: @102999
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 30, /*)*//*default:*//*Label 3699*/ 117621,
    /*GILLT_s16*//*Label 3681*/ 103035,
    /*GILLT_s32*//*Label 3682*/ 103667,
    /*GILLT_s64*//*Label 3683*/ 104299, 0, 0,
    /*GILLT_nxv1s16*//*Label 3684*/ 104931,
    /*GILLT_nxv1s32*//*Label 3685*/ 105777,
    /*GILLT_nxv1s64*//*Label 3686*/ 106623, 0, 0,
    /*GILLT_nxv2s16*//*Label 3687*/ 107469,
    /*GILLT_nxv2s32*//*Label 3688*/ 108315,
    /*GILLT_nxv2s64*//*Label 3689*/ 109161, 0, 0,
    /*GILLT_nxv4s16*//*Label 3690*/ 110007,
    /*GILLT_nxv4s32*//*Label 3691*/ 110853,
    /*GILLT_nxv4s64*//*Label 3692*/ 111699, 0, 0,
    /*GILLT_nxv8s16*//*Label 3693*/ 112545,
    /*GILLT_nxv8s32*//*Label 3694*/ 113391,
    /*GILLT_nxv8s64*//*Label 3695*/ 114237, 0, 0,
    /*GILLT_nxv16s16*//*Label 3696*/ 115083,
    /*GILLT_nxv16s32*//*Label 3697*/ 115929, 0, 0,
    /*GILLT_nxv32s16*//*Label 3698*/ 116775,
    // Label 3681: @103035
    GIM_Try, /*On fail goto*//*Label 3700*/ 103666,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR16RegClassID,
      GIM_Try, /*On fail goto*//*Label 3701*/ 103122, // Rule ID 64646 //
        GIM_CheckFeatures, GIFBS_HasStdExtZfh,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR16RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs3))  =>  (FNMADD_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_H,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64646,
        GIR_Done,
      // Label 3701: @103122
      GIM_Try, /*On fail goto*//*Label 3702*/ 103191, // Rule ID 64647 //
        GIM_CheckFeatures, GIFBS_HasStdExtZfh,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR16RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs3))  =>  (FNMADD_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_H,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64647,
        GIR_Done,
      // Label 3702: @103191
      GIM_Try, /*On fail goto*//*Label 3703*/ 103260, // Rule ID 72064 //
        GIM_CheckFeatures, GIFBS_HasStdExtZfh,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs3))  =>  (FNMADD_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_H,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72064,
        GIR_Done,
      // Label 3703: @103260
      GIM_Try, /*On fail goto*//*Label 3704*/ 103329, // Rule ID 72065 //
        GIM_CheckFeatures, GIFBS_HasStdExtZfh,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs3))  =>  (FNMADD_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_H,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72065,
        GIR_Done,
      // Label 3704: @103329
      GIM_Try, /*On fail goto*//*Label 3705*/ 103385, // Rule ID 64642 //
        GIM_CheckFeatures, GIFBS_HasStdExtZfh,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3)  =>  (FNMSUB_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_H,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64642,
        GIR_Done,
      // Label 3705: @103385
      GIM_Try, /*On fail goto*//*Label 3706*/ 103441, // Rule ID 64643 //
        GIM_CheckFeatures, GIFBS_HasStdExtZfh,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3)  =>  (FNMSUB_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_H,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64643,
        GIR_Done,
      // Label 3706: @103441
      GIM_Try, /*On fail goto*//*Label 3707*/ 103497, // Rule ID 72060 //
        GIM_CheckFeatures, GIFBS_HasStdExtZfh,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), FPR16:{ *:[f16] }:$rs3)  =>  (FNMSUB_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_H,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72060,
        GIR_Done,
      // Label 3707: @103497
      GIM_Try, /*On fail goto*//*Label 3708*/ 103553, // Rule ID 72061 //
        GIM_CheckFeatures, GIFBS_HasStdExtZfh,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), FPR16:{ *:[f16] }:$rs3)  =>  (FNMSUB_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_H,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72061,
        GIR_Done,
      // Label 3708: @103553
      GIM_Try, /*On fail goto*//*Label 3709*/ 103609, // Rule ID 64638 //
        GIM_CheckFeatures, GIFBS_HasStdExtZfh,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR16RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs3))  =>  (FMSUB_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_H,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64638,
        GIR_Done,
      // Label 3709: @103609
      GIM_Try, /*On fail goto*//*Label 3710*/ 103665, // Rule ID 64639 //
        GIM_CheckFeatures, GIFBS_HasStdExtZfh,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR16RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs3))  =>  (FMSUB_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_H,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64639,
        GIR_Done,
      // Label 3710: @103665
      GIM_Reject,
    // Label 3700: @103666
    GIM_Reject,
    // Label 3682: @103667
    GIM_Try, /*On fail goto*//*Label 3711*/ 104298,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID,
      GIM_Try, /*On fail goto*//*Label 3712*/ 103754, // Rule ID 65187 //
        GIM_CheckFeatures, GIFBS_HasStdExtF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3))  =>  (FNMADD_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_S,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65187,
        GIR_Done,
      // Label 3712: @103754
      GIM_Try, /*On fail goto*//*Label 3713*/ 103823, // Rule ID 65188 //
        GIM_CheckFeatures, GIFBS_HasStdExtF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3))  =>  (FNMADD_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_S,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65188,
        GIR_Done,
      // Label 3713: @103823
      GIM_Try, /*On fail goto*//*Label 3714*/ 103892, // Rule ID 72074 //
        GIM_CheckFeatures, GIFBS_HasStdExtF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3))  =>  (FNMADD_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_S,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72074,
        GIR_Done,
      // Label 3714: @103892
      GIM_Try, /*On fail goto*//*Label 3715*/ 103961, // Rule ID 72075 //
        GIM_CheckFeatures, GIFBS_HasStdExtF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3))  =>  (FNMADD_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_S,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72075,
        GIR_Done,
      // Label 3715: @103961
      GIM_Try, /*On fail goto*//*Label 3716*/ 104017, // Rule ID 65183 //
        GIM_CheckFeatures, GIFBS_HasStdExtF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3)  =>  (FNMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_S,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65183,
        GIR_Done,
      // Label 3716: @104017
      GIM_Try, /*On fail goto*//*Label 3717*/ 104073, // Rule ID 65184 //
        GIM_CheckFeatures, GIFBS_HasStdExtF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3)  =>  (FNMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_S,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65184,
        GIR_Done,
      // Label 3717: @104073
      GIM_Try, /*On fail goto*//*Label 3718*/ 104129, // Rule ID 72070 //
        GIM_CheckFeatures, GIFBS_HasStdExtF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs3)  =>  (FNMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_S,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72070,
        GIR_Done,
      // Label 3718: @104129
      GIM_Try, /*On fail goto*//*Label 3719*/ 104185, // Rule ID 72071 //
        GIM_CheckFeatures, GIFBS_HasStdExtF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs3)  =>  (FNMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_S,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72071,
        GIR_Done,
      // Label 3719: @104185
      GIM_Try, /*On fail goto*//*Label 3720*/ 104241, // Rule ID 65179 //
        GIM_CheckFeatures, GIFBS_HasStdExtF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3))  =>  (FMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_S,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65179,
        GIR_Done,
      // Label 3720: @104241
      GIM_Try, /*On fail goto*//*Label 3721*/ 104297, // Rule ID 65180 //
        GIM_CheckFeatures, GIFBS_HasStdExtF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3))  =>  (FMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_S,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65180,
        GIR_Done,
      // Label 3721: @104297
      GIM_Reject,
    // Label 3711: @104298
    GIM_Reject,
    // Label 3683: @104299
    GIM_Try, /*On fail goto*//*Label 3722*/ 104930,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
      GIM_Try, /*On fail goto*//*Label 3723*/ 104386, // Rule ID 65333 //
        GIM_CheckFeatures, GIFBS_HasStdExtD,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3))  =>  (FNMADD_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65333,
        GIR_Done,
      // Label 3723: @104386
      GIM_Try, /*On fail goto*//*Label 3724*/ 104455, // Rule ID 65334 //
        GIM_CheckFeatures, GIFBS_HasStdExtD,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3))  =>  (FNMADD_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65334,
        GIR_Done,
      // Label 3724: @104455
      GIM_Try, /*On fail goto*//*Label 3725*/ 104524, // Rule ID 72082 //
        GIM_CheckFeatures, GIFBS_HasStdExtD,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3))  =>  (FNMADD_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72082,
        GIR_Done,
      // Label 3725: @104524
      GIM_Try, /*On fail goto*//*Label 3726*/ 104593, // Rule ID 72083 //
        GIM_CheckFeatures, GIFBS_HasStdExtD,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3))  =>  (FNMADD_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72083,
        GIR_Done,
      // Label 3726: @104593
      GIM_Try, /*On fail goto*//*Label 3727*/ 104649, // Rule ID 65329 //
        GIM_CheckFeatures, GIFBS_HasStdExtD,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3)  =>  (FNMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65329,
        GIR_Done,
      // Label 3727: @104649
      GIM_Try, /*On fail goto*//*Label 3728*/ 104705, // Rule ID 65330 //
        GIM_CheckFeatures, GIFBS_HasStdExtD,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3)  =>  (FNMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65330,
        GIR_Done,
      // Label 3728: @104705
      GIM_Try, /*On fail goto*//*Label 3729*/ 104761, // Rule ID 72078 //
        GIM_CheckFeatures, GIFBS_HasStdExtD,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs3)  =>  (FNMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72078,
        GIR_Done,
      // Label 3729: @104761
      GIM_Try, /*On fail goto*//*Label 3730*/ 104817, // Rule ID 72079 //
        GIM_CheckFeatures, GIFBS_HasStdExtD,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs3)  =>  (FNMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72079,
        GIR_Done,
      // Label 3730: @104817
      GIM_Try, /*On fail goto*//*Label 3731*/ 104873, // Rule ID 65325 //
        GIM_CheckFeatures, GIFBS_HasStdExtD,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3))  =>  (FMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65325,
        GIR_Done,
      // Label 3731: @104873
      GIM_Try, /*On fail goto*//*Label 3732*/ 104929, // Rule ID 65326 //
        GIM_CheckFeatures, GIFBS_HasStdExtD,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3))  =>  (FMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65326,
        GIR_Done,
      // Label 3732: @104929
      GIM_Reject,
    // Label 3722: @104930
    GIM_Reject,
    // Label 3684: @104931
    GIM_Try, /*On fail goto*//*Label 3733*/ 105776,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s16,
      GIM_Try, /*On fail goto*//*Label 3734*/ 105025, // Rule ID 62383 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv1f16] } (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1), VR:{ *:[nxv1f16] }:$rd, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2))  =>  (PseudoVFNMADD_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62383,
        GIR_Done,
      // Label 3734: @105025
      GIM_Try, /*On fail goto*//*Label 3735*/ 105105, // Rule ID 62384 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv1f16] } (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1), VR:{ *:[nxv1f16] }:$rd, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2))  =>  (PseudoVFNMADD_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62384,
        GIR_Done,
      // Label 3735: @105105
      GIM_Try, /*On fail goto*//*Label 3736*/ 105185, // Rule ID 71534 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1), (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2))  =>  (PseudoVFNMADD_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71534,
        GIR_Done,
      // Label 3736: @105185
      GIM_Try, /*On fail goto*//*Label 3737*/ 105265, // Rule ID 71535 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1), (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2))  =>  (PseudoVFNMADD_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71535,
        GIR_Done,
      // Label 3737: @105265
      GIM_Try, /*On fail goto*//*Label 3738*/ 105332, // Rule ID 62385 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv1f16] } (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1), VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs2)  =>  (PseudoVFNMSUB_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62385,
        GIR_Done,
      // Label 3738: @105332
      GIM_Try, /*On fail goto*//*Label 3739*/ 105399, // Rule ID 62386 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv1f16] } (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1), VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs2)  =>  (PseudoVFNMSUB_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62386,
        GIR_Done,
      // Label 3739: @105399
      GIM_Try, /*On fail goto*//*Label 3740*/ 105466, // Rule ID 71536 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1), VR:{ *:[nxv1f16] }:$rs2)  =>  (PseudoVFNMSUB_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71536,
        GIR_Done,
      // Label 3740: @105466
      GIM_Try, /*On fail goto*//*Label 3741*/ 105533, // Rule ID 71537 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1), VR:{ *:[nxv1f16] }:$rs2)  =>  (PseudoVFNMSUB_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71537,
        GIR_Done,
      // Label 3741: @105533
      GIM_Try, /*On fail goto*//*Label 3742*/ 105600, // Rule ID 62381 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rd, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2))  =>  (PseudoVFMSUB_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62381,
        GIR_Done,
      // Label 3742: @105600
      GIM_Try, /*On fail goto*//*Label 3743*/ 105667, // Rule ID 62382 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rd, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2))  =>  (PseudoVFMSUB_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62382,
        GIR_Done,
      // Label 3743: @105667
      GIM_Try, /*On fail goto*//*Label 3744*/ 105721, // Rule ID 62379 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        // (fma:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs2)  =>  (PseudoVFMADD_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62379,
        GIR_Done,
      // Label 3744: @105721
      GIM_Try, /*On fail goto*//*Label 3745*/ 105775, // Rule ID 62380 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        // (fma:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs2)  =>  (PseudoVFMADD_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rd, VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62380,
        GIR_Done,
      // Label 3745: @105775
      GIM_Reject,
    // Label 3733: @105776
    GIM_Reject,
    // Label 3685: @105777
    GIM_Try, /*On fail goto*//*Label 3746*/ 106622,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s32,
      GIM_Try, /*On fail goto*//*Label 3747*/ 105871, // Rule ID 62424 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv1f32] } (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1), VR:{ *:[nxv1f32] }:$rd, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2))  =>  (PseudoVFNMADD_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62424,
        GIR_Done,
      // Label 3747: @105871
      GIM_Try, /*On fail goto*//*Label 3748*/ 105951, // Rule ID 62425 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv1f32] } (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1), VR:{ *:[nxv1f32] }:$rd, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2))  =>  (PseudoVFNMADD_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62425,
        GIR_Done,
      // Label 3748: @105951
      GIM_Try, /*On fail goto*//*Label 3749*/ 106031, // Rule ID 71566 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1), (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2))  =>  (PseudoVFNMADD_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71566,
        GIR_Done,
      // Label 3749: @106031
      GIM_Try, /*On fail goto*//*Label 3750*/ 106111, // Rule ID 71567 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1), (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2))  =>  (PseudoVFNMADD_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71567,
        GIR_Done,
      // Label 3750: @106111
      GIM_Try, /*On fail goto*//*Label 3751*/ 106178, // Rule ID 62426 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv1f32] } (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1), VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs2)  =>  (PseudoVFNMSUB_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62426,
        GIR_Done,
      // Label 3751: @106178
      GIM_Try, /*On fail goto*//*Label 3752*/ 106245, // Rule ID 62427 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv1f32] } (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1), VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs2)  =>  (PseudoVFNMSUB_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62427,
        GIR_Done,
      // Label 3752: @106245
      GIM_Try, /*On fail goto*//*Label 3753*/ 106312, // Rule ID 71568 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1), VR:{ *:[nxv1f32] }:$rs2)  =>  (PseudoVFNMSUB_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71568,
        GIR_Done,
      // Label 3753: @106312
      GIM_Try, /*On fail goto*//*Label 3754*/ 106379, // Rule ID 71569 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1), VR:{ *:[nxv1f32] }:$rs2)  =>  (PseudoVFNMSUB_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71569,
        GIR_Done,
      // Label 3754: @106379
      GIM_Try, /*On fail goto*//*Label 3755*/ 106446, // Rule ID 62422 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rd, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2))  =>  (PseudoVFMSUB_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62422,
        GIR_Done,
      // Label 3755: @106446
      GIM_Try, /*On fail goto*//*Label 3756*/ 106513, // Rule ID 62423 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rd, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2))  =>  (PseudoVFMSUB_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62423,
        GIR_Done,
      // Label 3756: @106513
      GIM_Try, /*On fail goto*//*Label 3757*/ 106567, // Rule ID 62420 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        // (fma:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs2)  =>  (PseudoVFMADD_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62420,
        GIR_Done,
      // Label 3757: @106567
      GIM_Try, /*On fail goto*//*Label 3758*/ 106621, // Rule ID 62421 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        // (fma:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs2)  =>  (PseudoVFMADD_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rd, VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62421,
        GIR_Done,
      // Label 3758: @106621
      GIM_Reject,
    // Label 3746: @106622
    GIM_Reject,
    // Label 3686: @106623
    GIM_Try, /*On fail goto*//*Label 3759*/ 107468,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv1s64,
      GIM_Try, /*On fail goto*//*Label 3760*/ 106717, // Rule ID 62486 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s64,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv1f64] } (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1), VR:{ *:[nxv1f64] }:$rd, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2))  =>  (PseudoVFNMADD_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62486,
        GIR_Done,
      // Label 3760: @106717
      GIM_Try, /*On fail goto*//*Label 3761*/ 106797, // Rule ID 62487 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s64,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv1f64] } (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1), VR:{ *:[nxv1f64] }:$rd, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2))  =>  (PseudoVFNMADD_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62487,
        GIR_Done,
      // Label 3761: @106797
      GIM_Try, /*On fail goto*//*Label 3762*/ 106877, // Rule ID 71614 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s64,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1), (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2))  =>  (PseudoVFNMADD_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71614,
        GIR_Done,
      // Label 3762: @106877
      GIM_Try, /*On fail goto*//*Label 3763*/ 106957, // Rule ID 71615 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv1s64,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1), (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2))  =>  (PseudoVFNMADD_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71615,
        GIR_Done,
      // Label 3763: @106957
      GIM_Try, /*On fail goto*//*Label 3764*/ 107024, // Rule ID 62488 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv1f64] } (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1), VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs2)  =>  (PseudoVFNMSUB_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62488,
        GIR_Done,
      // Label 3764: @107024
      GIM_Try, /*On fail goto*//*Label 3765*/ 107091, // Rule ID 62489 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv1f64] } (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1), VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs2)  =>  (PseudoVFNMSUB_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62489,
        GIR_Done,
      // Label 3765: @107091
      GIM_Try, /*On fail goto*//*Label 3766*/ 107158, // Rule ID 71616 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1), VR:{ *:[nxv1f64] }:$rs2)  =>  (PseudoVFNMSUB_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71616,
        GIR_Done,
      // Label 3766: @107158
      GIM_Try, /*On fail goto*//*Label 3767*/ 107225, // Rule ID 71617 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1), VR:{ *:[nxv1f64] }:$rs2)  =>  (PseudoVFNMSUB_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71617,
        GIR_Done,
      // Label 3767: @107225
      GIM_Try, /*On fail goto*//*Label 3768*/ 107292, // Rule ID 62484 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rd, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2))  =>  (PseudoVFMSUB_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62484,
        GIR_Done,
      // Label 3768: @107292
      GIM_Try, /*On fail goto*//*Label 3769*/ 107359, // Rule ID 62485 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rd, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2))  =>  (PseudoVFMSUB_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62485,
        GIR_Done,
      // Label 3769: @107359
      GIM_Try, /*On fail goto*//*Label 3770*/ 107413, // Rule ID 62482 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        // (fma:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs2)  =>  (PseudoVFMADD_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62482,
        GIR_Done,
      // Label 3770: @107413
      GIM_Try, /*On fail goto*//*Label 3771*/ 107467, // Rule ID 62483 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        // (fma:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs2)  =>  (PseudoVFMADD_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rd, VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62483,
        GIR_Done,
      // Label 3771: @107467
      GIM_Reject,
    // Label 3759: @107468
    GIM_Reject,
    // Label 3687: @107469
    GIM_Try, /*On fail goto*//*Label 3772*/ 108314,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s16,
      GIM_Try, /*On fail goto*//*Label 3773*/ 107563, // Rule ID 62404 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv2f16] } (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1), VR:{ *:[nxv2f16] }:$rd, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2))  =>  (PseudoVFNMADD_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62404,
        GIR_Done,
      // Label 3773: @107563
      GIM_Try, /*On fail goto*//*Label 3774*/ 107643, // Rule ID 62405 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv2f16] } (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1), VR:{ *:[nxv2f16] }:$rd, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2))  =>  (PseudoVFNMADD_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62405,
        GIR_Done,
      // Label 3774: @107643
      GIM_Try, /*On fail goto*//*Label 3775*/ 107723, // Rule ID 71550 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1), (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2))  =>  (PseudoVFNMADD_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71550,
        GIR_Done,
      // Label 3775: @107723
      GIM_Try, /*On fail goto*//*Label 3776*/ 107803, // Rule ID 71551 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1), (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2))  =>  (PseudoVFNMADD_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71551,
        GIR_Done,
      // Label 3776: @107803
      GIM_Try, /*On fail goto*//*Label 3777*/ 107870, // Rule ID 62406 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv2f16] } (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1), VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs2)  =>  (PseudoVFNMSUB_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62406,
        GIR_Done,
      // Label 3777: @107870
      GIM_Try, /*On fail goto*//*Label 3778*/ 107937, // Rule ID 62407 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv2f16] } (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1), VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs2)  =>  (PseudoVFNMSUB_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62407,
        GIR_Done,
      // Label 3778: @107937
      GIM_Try, /*On fail goto*//*Label 3779*/ 108004, // Rule ID 71552 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1), VR:{ *:[nxv2f16] }:$rs2)  =>  (PseudoVFNMSUB_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71552,
        GIR_Done,
      // Label 3779: @108004
      GIM_Try, /*On fail goto*//*Label 3780*/ 108071, // Rule ID 71553 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1), VR:{ *:[nxv2f16] }:$rs2)  =>  (PseudoVFNMSUB_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71553,
        GIR_Done,
      // Label 3780: @108071
      GIM_Try, /*On fail goto*//*Label 3781*/ 108138, // Rule ID 62402 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rd, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2))  =>  (PseudoVFMSUB_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62402,
        GIR_Done,
      // Label 3781: @108138
      GIM_Try, /*On fail goto*//*Label 3782*/ 108205, // Rule ID 62403 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rd, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2))  =>  (PseudoVFMSUB_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62403,
        GIR_Done,
      // Label 3782: @108205
      GIM_Try, /*On fail goto*//*Label 3783*/ 108259, // Rule ID 62400 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        // (fma:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs2)  =>  (PseudoVFMADD_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62400,
        GIR_Done,
      // Label 3783: @108259
      GIM_Try, /*On fail goto*//*Label 3784*/ 108313, // Rule ID 62401 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        // (fma:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs2)  =>  (PseudoVFMADD_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rd, VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62401,
        GIR_Done,
      // Label 3784: @108313
      GIM_Reject,
    // Label 3772: @108314
    GIM_Reject,
    // Label 3688: @108315
    GIM_Try, /*On fail goto*//*Label 3785*/ 109160,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s32,
      GIM_Try, /*On fail goto*//*Label 3786*/ 108409, // Rule ID 62465 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv2f32] } (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1), VR:{ *:[nxv2f32] }:$rd, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2))  =>  (PseudoVFNMADD_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62465,
        GIR_Done,
      // Label 3786: @108409
      GIM_Try, /*On fail goto*//*Label 3787*/ 108489, // Rule ID 62466 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv2f32] } (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1), VR:{ *:[nxv2f32] }:$rd, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2))  =>  (PseudoVFNMADD_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62466,
        GIR_Done,
      // Label 3787: @108489
      GIM_Try, /*On fail goto*//*Label 3788*/ 108569, // Rule ID 71598 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1), (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2))  =>  (PseudoVFNMADD_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71598,
        GIR_Done,
      // Label 3788: @108569
      GIM_Try, /*On fail goto*//*Label 3789*/ 108649, // Rule ID 71599 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1), (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2))  =>  (PseudoVFNMADD_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71599,
        GIR_Done,
      // Label 3789: @108649
      GIM_Try, /*On fail goto*//*Label 3790*/ 108716, // Rule ID 62467 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv2f32] } (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1), VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs2)  =>  (PseudoVFNMSUB_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62467,
        GIR_Done,
      // Label 3790: @108716
      GIM_Try, /*On fail goto*//*Label 3791*/ 108783, // Rule ID 62468 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv2f32] } (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1), VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs2)  =>  (PseudoVFNMSUB_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62468,
        GIR_Done,
      // Label 3791: @108783
      GIM_Try, /*On fail goto*//*Label 3792*/ 108850, // Rule ID 71600 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1), VR:{ *:[nxv2f32] }:$rs2)  =>  (PseudoVFNMSUB_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71600,
        GIR_Done,
      // Label 3792: @108850
      GIM_Try, /*On fail goto*//*Label 3793*/ 108917, // Rule ID 71601 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1), VR:{ *:[nxv2f32] }:$rs2)  =>  (PseudoVFNMSUB_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71601,
        GIR_Done,
      // Label 3793: @108917
      GIM_Try, /*On fail goto*//*Label 3794*/ 108984, // Rule ID 62463 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rd, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2))  =>  (PseudoVFMSUB_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62463,
        GIR_Done,
      // Label 3794: @108984
      GIM_Try, /*On fail goto*//*Label 3795*/ 109051, // Rule ID 62464 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rd, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2))  =>  (PseudoVFMSUB_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62464,
        GIR_Done,
      // Label 3795: @109051
      GIM_Try, /*On fail goto*//*Label 3796*/ 109105, // Rule ID 62461 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        // (fma:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs2)  =>  (PseudoVFMADD_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62461,
        GIR_Done,
      // Label 3796: @109105
      GIM_Try, /*On fail goto*//*Label 3797*/ 109159, // Rule ID 62462 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        // (fma:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs2)  =>  (PseudoVFMADD_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rd, VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62462,
        GIR_Done,
      // Label 3797: @109159
      GIM_Reject,
    // Label 3785: @109160
    GIM_Reject,
    // Label 3689: @109161
    GIM_Try, /*On fail goto*//*Label 3798*/ 110006,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv2s64,
      GIM_Try, /*On fail goto*//*Label 3799*/ 109255, // Rule ID 62630 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv2f64] } (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1), VRM2:{ *:[nxv2f64] }:$rd, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2))  =>  (PseudoVFNMADD_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62630,
        GIR_Done,
      // Label 3799: @109255
      GIM_Try, /*On fail goto*//*Label 3800*/ 109335, // Rule ID 62631 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv2f64] } (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1), VRM2:{ *:[nxv2f64] }:$rd, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2))  =>  (PseudoVFNMADD_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62631,
        GIR_Done,
      // Label 3800: @109335
      GIM_Try, /*On fail goto*//*Label 3801*/ 109415, // Rule ID 71726 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1), (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2))  =>  (PseudoVFNMADD_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71726,
        GIR_Done,
      // Label 3801: @109415
      GIM_Try, /*On fail goto*//*Label 3802*/ 109495, // Rule ID 71727 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1), (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2))  =>  (PseudoVFNMADD_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71727,
        GIR_Done,
      // Label 3802: @109495
      GIM_Try, /*On fail goto*//*Label 3803*/ 109562, // Rule ID 62632 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv2f64] } (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1), VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs2)  =>  (PseudoVFNMSUB_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62632,
        GIR_Done,
      // Label 3803: @109562
      GIM_Try, /*On fail goto*//*Label 3804*/ 109629, // Rule ID 62633 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv2f64] } (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1), VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs2)  =>  (PseudoVFNMSUB_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62633,
        GIR_Done,
      // Label 3804: @109629
      GIM_Try, /*On fail goto*//*Label 3805*/ 109696, // Rule ID 71728 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1), VRM2:{ *:[nxv2f64] }:$rs2)  =>  (PseudoVFNMSUB_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71728,
        GIR_Done,
      // Label 3805: @109696
      GIM_Try, /*On fail goto*//*Label 3806*/ 109763, // Rule ID 71729 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1), VRM2:{ *:[nxv2f64] }:$rs2)  =>  (PseudoVFNMSUB_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71729,
        GIR_Done,
      // Label 3806: @109763
      GIM_Try, /*On fail goto*//*Label 3807*/ 109830, // Rule ID 62628 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rd, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2))  =>  (PseudoVFMSUB_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62628,
        GIR_Done,
      // Label 3807: @109830
      GIM_Try, /*On fail goto*//*Label 3808*/ 109897, // Rule ID 62629 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rd, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2))  =>  (PseudoVFMSUB_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62629,
        GIR_Done,
      // Label 3808: @109897
      GIM_Try, /*On fail goto*//*Label 3809*/ 109951, // Rule ID 62626 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
        // (fma:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs2)  =>  (PseudoVFMADD_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62626,
        GIR_Done,
      // Label 3809: @109951
      GIM_Try, /*On fail goto*//*Label 3810*/ 110005, // Rule ID 62627 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
        // (fma:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs2)  =>  (PseudoVFMADD_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rd, VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62627,
        GIR_Done,
      // Label 3810: @110005
      GIM_Reject,
    // Label 3798: @110006
    GIM_Reject,
    // Label 3690: @110007
    GIM_Try, /*On fail goto*//*Label 3811*/ 110852,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s16,
      GIM_Try, /*On fail goto*//*Label 3812*/ 110101, // Rule ID 62445 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv4f16] } (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1), VR:{ *:[nxv4f16] }:$rd, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2))  =>  (PseudoVFNMADD_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62445,
        GIR_Done,
      // Label 3812: @110101
      GIM_Try, /*On fail goto*//*Label 3813*/ 110181, // Rule ID 62446 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv4f16] } (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1), VR:{ *:[nxv4f16] }:$rd, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2))  =>  (PseudoVFNMADD_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62446,
        GIR_Done,
      // Label 3813: @110181
      GIM_Try, /*On fail goto*//*Label 3814*/ 110261, // Rule ID 71582 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1), (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2))  =>  (PseudoVFNMADD_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71582,
        GIR_Done,
      // Label 3814: @110261
      GIM_Try, /*On fail goto*//*Label 3815*/ 110341, // Rule ID 71583 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1), (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2))  =>  (PseudoVFNMADD_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71583,
        GIR_Done,
      // Label 3815: @110341
      GIM_Try, /*On fail goto*//*Label 3816*/ 110408, // Rule ID 62447 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv4f16] } (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1), VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs2)  =>  (PseudoVFNMSUB_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62447,
        GIR_Done,
      // Label 3816: @110408
      GIM_Try, /*On fail goto*//*Label 3817*/ 110475, // Rule ID 62448 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv4f16] } (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1), VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs2)  =>  (PseudoVFNMSUB_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62448,
        GIR_Done,
      // Label 3817: @110475
      GIM_Try, /*On fail goto*//*Label 3818*/ 110542, // Rule ID 71584 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1), VR:{ *:[nxv4f16] }:$rs2)  =>  (PseudoVFNMSUB_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71584,
        GIR_Done,
      // Label 3818: @110542
      GIM_Try, /*On fail goto*//*Label 3819*/ 110609, // Rule ID 71585 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1), VR:{ *:[nxv4f16] }:$rs2)  =>  (PseudoVFNMSUB_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71585,
        GIR_Done,
      // Label 3819: @110609
      GIM_Try, /*On fail goto*//*Label 3820*/ 110676, // Rule ID 62443 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rd, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2))  =>  (PseudoVFMSUB_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62443,
        GIR_Done,
      // Label 3820: @110676
      GIM_Try, /*On fail goto*//*Label 3821*/ 110743, // Rule ID 62444 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rd, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2))  =>  (PseudoVFMSUB_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62444,
        GIR_Done,
      // Label 3821: @110743
      GIM_Try, /*On fail goto*//*Label 3822*/ 110797, // Rule ID 62441 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        // (fma:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs2)  =>  (PseudoVFMADD_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62441,
        GIR_Done,
      // Label 3822: @110797
      GIM_Try, /*On fail goto*//*Label 3823*/ 110851, // Rule ID 62442 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRRegClassID,
        // (fma:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs2)  =>  (PseudoVFMADD_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rd, VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62442,
        GIR_Done,
      // Label 3823: @110851
      GIM_Reject,
    // Label 3811: @110852
    GIM_Reject,
    // Label 3691: @110853
    GIM_Try, /*On fail goto*//*Label 3824*/ 111698,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s32,
      GIM_Try, /*On fail goto*//*Label 3825*/ 110947, // Rule ID 62568 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv4f32] } (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1), VRM2:{ *:[nxv4f32] }:$rd, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2))  =>  (PseudoVFNMADD_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62568,
        GIR_Done,
      // Label 3825: @110947
      GIM_Try, /*On fail goto*//*Label 3826*/ 111027, // Rule ID 62569 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv4f32] } (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1), VRM2:{ *:[nxv4f32] }:$rd, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2))  =>  (PseudoVFNMADD_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62569,
        GIR_Done,
      // Label 3826: @111027
      GIM_Try, /*On fail goto*//*Label 3827*/ 111107, // Rule ID 71678 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1), (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2))  =>  (PseudoVFNMADD_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71678,
        GIR_Done,
      // Label 3827: @111107
      GIM_Try, /*On fail goto*//*Label 3828*/ 111187, // Rule ID 71679 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1), (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2))  =>  (PseudoVFNMADD_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71679,
        GIR_Done,
      // Label 3828: @111187
      GIM_Try, /*On fail goto*//*Label 3829*/ 111254, // Rule ID 62570 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv4f32] } (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1), VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs2)  =>  (PseudoVFNMSUB_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62570,
        GIR_Done,
      // Label 3829: @111254
      GIM_Try, /*On fail goto*//*Label 3830*/ 111321, // Rule ID 62571 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv4f32] } (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1), VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs2)  =>  (PseudoVFNMSUB_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62571,
        GIR_Done,
      // Label 3830: @111321
      GIM_Try, /*On fail goto*//*Label 3831*/ 111388, // Rule ID 71680 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1), VRM2:{ *:[nxv4f32] }:$rs2)  =>  (PseudoVFNMSUB_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71680,
        GIR_Done,
      // Label 3831: @111388
      GIM_Try, /*On fail goto*//*Label 3832*/ 111455, // Rule ID 71681 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1), VRM2:{ *:[nxv4f32] }:$rs2)  =>  (PseudoVFNMSUB_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71681,
        GIR_Done,
      // Label 3832: @111455
      GIM_Try, /*On fail goto*//*Label 3833*/ 111522, // Rule ID 62566 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rd, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2))  =>  (PseudoVFMSUB_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62566,
        GIR_Done,
      // Label 3833: @111522
      GIM_Try, /*On fail goto*//*Label 3834*/ 111589, // Rule ID 62567 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rd, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2))  =>  (PseudoVFMSUB_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62567,
        GIR_Done,
      // Label 3834: @111589
      GIM_Try, /*On fail goto*//*Label 3835*/ 111643, // Rule ID 62564 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
        // (fma:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs2)  =>  (PseudoVFMADD_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62564,
        GIR_Done,
      // Label 3835: @111643
      GIM_Try, /*On fail goto*//*Label 3836*/ 111697, // Rule ID 62565 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
        // (fma:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs2)  =>  (PseudoVFMADD_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rd, VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62565,
        GIR_Done,
      // Label 3836: @111697
      GIM_Reject,
    // Label 3824: @111698
    GIM_Reject,
    // Label 3692: @111699
    GIM_Try, /*On fail goto*//*Label 3837*/ 112544,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv4s64,
      GIM_Try, /*On fail goto*//*Label 3838*/ 111793, // Rule ID 62650 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s64,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv4f64] } (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1), VRM4:{ *:[nxv4f64] }:$rd, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2))  =>  (PseudoVFNMADD_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62650,
        GIR_Done,
      // Label 3838: @111793
      GIM_Try, /*On fail goto*//*Label 3839*/ 111873, // Rule ID 62651 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s64,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv4f64] } (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1), VRM4:{ *:[nxv4f64] }:$rd, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2))  =>  (PseudoVFNMADD_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62651,
        GIR_Done,
      // Label 3839: @111873
      GIM_Try, /*On fail goto*//*Label 3840*/ 111953, // Rule ID 71742 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s64,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1), (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2))  =>  (PseudoVFNMADD_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71742,
        GIR_Done,
      // Label 3840: @111953
      GIM_Try, /*On fail goto*//*Label 3841*/ 112033, // Rule ID 71743 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s64,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1), (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2))  =>  (PseudoVFNMADD_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71743,
        GIR_Done,
      // Label 3841: @112033
      GIM_Try, /*On fail goto*//*Label 3842*/ 112100, // Rule ID 62652 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv4f64] } (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1), VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs2)  =>  (PseudoVFNMSUB_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62652,
        GIR_Done,
      // Label 3842: @112100
      GIM_Try, /*On fail goto*//*Label 3843*/ 112167, // Rule ID 62653 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv4f64] } (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1), VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs2)  =>  (PseudoVFNMSUB_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62653,
        GIR_Done,
      // Label 3843: @112167
      GIM_Try, /*On fail goto*//*Label 3844*/ 112234, // Rule ID 71744 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1), VRM4:{ *:[nxv4f64] }:$rs2)  =>  (PseudoVFNMSUB_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71744,
        GIR_Done,
      // Label 3844: @112234
      GIM_Try, /*On fail goto*//*Label 3845*/ 112301, // Rule ID 71745 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1), VRM4:{ *:[nxv4f64] }:$rs2)  =>  (PseudoVFNMSUB_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71745,
        GIR_Done,
      // Label 3845: @112301
      GIM_Try, /*On fail goto*//*Label 3846*/ 112368, // Rule ID 62648 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rd, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2))  =>  (PseudoVFMSUB_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62648,
        GIR_Done,
      // Label 3846: @112368
      GIM_Try, /*On fail goto*//*Label 3847*/ 112435, // Rule ID 62649 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rd, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2))  =>  (PseudoVFMSUB_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62649,
        GIR_Done,
      // Label 3847: @112435
      GIM_Try, /*On fail goto*//*Label 3848*/ 112489, // Rule ID 62646 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
        // (fma:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs2)  =>  (PseudoVFMADD_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62646,
        GIR_Done,
      // Label 3848: @112489
      GIM_Try, /*On fail goto*//*Label 3849*/ 112543, // Rule ID 62647 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
        // (fma:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs2)  =>  (PseudoVFMADD_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rd, VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62647,
        GIR_Done,
      // Label 3849: @112543
      GIM_Reject,
    // Label 3837: @112544
    GIM_Reject,
    // Label 3693: @112545
    GIM_Try, /*On fail goto*//*Label 3850*/ 113390,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s16,
      GIM_Try, /*On fail goto*//*Label 3851*/ 112639, // Rule ID 62506 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv8f16] } (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1), VRM2:{ *:[nxv8f16] }:$rd, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2))  =>  (PseudoVFNMADD_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62506,
        GIR_Done,
      // Label 3851: @112639
      GIM_Try, /*On fail goto*//*Label 3852*/ 112719, // Rule ID 62507 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv8f16] } (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1), VRM2:{ *:[nxv8f16] }:$rd, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2))  =>  (PseudoVFNMADD_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62507,
        GIR_Done,
      // Label 3852: @112719
      GIM_Try, /*On fail goto*//*Label 3853*/ 112799, // Rule ID 71630 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1), (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2))  =>  (PseudoVFNMADD_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71630,
        GIR_Done,
      // Label 3853: @112799
      GIM_Try, /*On fail goto*//*Label 3854*/ 112879, // Rule ID 71631 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1), (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2))  =>  (PseudoVFNMADD_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71631,
        GIR_Done,
      // Label 3854: @112879
      GIM_Try, /*On fail goto*//*Label 3855*/ 112946, // Rule ID 62508 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv8f16] } (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1), VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs2)  =>  (PseudoVFNMSUB_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62508,
        GIR_Done,
      // Label 3855: @112946
      GIM_Try, /*On fail goto*//*Label 3856*/ 113013, // Rule ID 62509 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv8f16] } (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1), VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs2)  =>  (PseudoVFNMSUB_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62509,
        GIR_Done,
      // Label 3856: @113013
      GIM_Try, /*On fail goto*//*Label 3857*/ 113080, // Rule ID 71632 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1), VRM2:{ *:[nxv8f16] }:$rs2)  =>  (PseudoVFNMSUB_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71632,
        GIR_Done,
      // Label 3857: @113080
      GIM_Try, /*On fail goto*//*Label 3858*/ 113147, // Rule ID 71633 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1), VRM2:{ *:[nxv8f16] }:$rs2)  =>  (PseudoVFNMSUB_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71633,
        GIR_Done,
      // Label 3858: @113147
      GIM_Try, /*On fail goto*//*Label 3859*/ 113214, // Rule ID 62504 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rd, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2))  =>  (PseudoVFMSUB_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62504,
        GIR_Done,
      // Label 3859: @113214
      GIM_Try, /*On fail goto*//*Label 3860*/ 113281, // Rule ID 62505 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rd, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2))  =>  (PseudoVFMSUB_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62505,
        GIR_Done,
      // Label 3860: @113281
      GIM_Try, /*On fail goto*//*Label 3861*/ 113335, // Rule ID 62502 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
        // (fma:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs2)  =>  (PseudoVFMADD_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62502,
        GIR_Done,
      // Label 3861: @113335
      GIM_Try, /*On fail goto*//*Label 3862*/ 113389, // Rule ID 62503 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM2RegClassID,
        // (fma:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs2)  =>  (PseudoVFMADD_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rd, VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62503,
        GIR_Done,
      // Label 3862: @113389
      GIM_Reject,
    // Label 3850: @113390
    GIM_Reject,
    // Label 3694: @113391
    GIM_Try, /*On fail goto*//*Label 3863*/ 114236,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s32,
      GIM_Try, /*On fail goto*//*Label 3864*/ 113485, // Rule ID 62589 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv8f32] } (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1), VRM4:{ *:[nxv8f32] }:$rd, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2))  =>  (PseudoVFNMADD_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62589,
        GIR_Done,
      // Label 3864: @113485
      GIM_Try, /*On fail goto*//*Label 3865*/ 113565, // Rule ID 62590 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv8f32] } (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1), VRM4:{ *:[nxv8f32] }:$rd, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2))  =>  (PseudoVFNMADD_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62590,
        GIR_Done,
      // Label 3865: @113565
      GIM_Try, /*On fail goto*//*Label 3866*/ 113645, // Rule ID 71694 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1), (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2))  =>  (PseudoVFNMADD_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71694,
        GIR_Done,
      // Label 3866: @113645
      GIM_Try, /*On fail goto*//*Label 3867*/ 113725, // Rule ID 71695 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1), (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2))  =>  (PseudoVFNMADD_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71695,
        GIR_Done,
      // Label 3867: @113725
      GIM_Try, /*On fail goto*//*Label 3868*/ 113792, // Rule ID 62591 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv8f32] } (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1), VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs2)  =>  (PseudoVFNMSUB_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62591,
        GIR_Done,
      // Label 3868: @113792
      GIM_Try, /*On fail goto*//*Label 3869*/ 113859, // Rule ID 62592 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv8f32] } (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1), VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs2)  =>  (PseudoVFNMSUB_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62592,
        GIR_Done,
      // Label 3869: @113859
      GIM_Try, /*On fail goto*//*Label 3870*/ 113926, // Rule ID 71696 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1), VRM4:{ *:[nxv8f32] }:$rs2)  =>  (PseudoVFNMSUB_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71696,
        GIR_Done,
      // Label 3870: @113926
      GIM_Try, /*On fail goto*//*Label 3871*/ 113993, // Rule ID 71697 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1), VRM4:{ *:[nxv8f32] }:$rs2)  =>  (PseudoVFNMSUB_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71697,
        GIR_Done,
      // Label 3871: @113993
      GIM_Try, /*On fail goto*//*Label 3872*/ 114060, // Rule ID 62587 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rd, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2))  =>  (PseudoVFMSUB_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62587,
        GIR_Done,
      // Label 3872: @114060
      GIM_Try, /*On fail goto*//*Label 3873*/ 114127, // Rule ID 62588 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rd, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2))  =>  (PseudoVFMSUB_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62588,
        GIR_Done,
      // Label 3873: @114127
      GIM_Try, /*On fail goto*//*Label 3874*/ 114181, // Rule ID 62585 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
        // (fma:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs2)  =>  (PseudoVFMADD_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62585,
        GIR_Done,
      // Label 3874: @114181
      GIM_Try, /*On fail goto*//*Label 3875*/ 114235, // Rule ID 62586 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
        // (fma:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs2)  =>  (PseudoVFMADD_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rd, VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62586,
        GIR_Done,
      // Label 3875: @114235
      GIM_Reject,
    // Label 3863: @114236
    GIM_Reject,
    // Label 3695: @114237
    GIM_Try, /*On fail goto*//*Label 3876*/ 115082,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv8s64,
      GIM_Try, /*On fail goto*//*Label 3877*/ 114331, // Rule ID 62671 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s64,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv8f64] } (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1), VRM8:{ *:[nxv8f64] }:$rd, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2))  =>  (PseudoVFNMADD_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62671,
        GIR_Done,
      // Label 3877: @114331
      GIM_Try, /*On fail goto*//*Label 3878*/ 114411, // Rule ID 62672 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s64,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv8f64] } (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1), VRM8:{ *:[nxv8f64] }:$rd, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2))  =>  (PseudoVFNMADD_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62672,
        GIR_Done,
      // Label 3878: @114411
      GIM_Try, /*On fail goto*//*Label 3879*/ 114491, // Rule ID 71758 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s64,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1), (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2))  =>  (PseudoVFNMADD_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71758,
        GIR_Done,
      // Label 3879: @114491
      GIM_Try, /*On fail goto*//*Label 3880*/ 114571, // Rule ID 71759 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s64,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1), (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2))  =>  (PseudoVFNMADD_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71759,
        GIR_Done,
      // Label 3880: @114571
      GIM_Try, /*On fail goto*//*Label 3881*/ 114638, // Rule ID 62673 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv8f64] } (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1), VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs2)  =>  (PseudoVFNMSUB_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62673,
        GIR_Done,
      // Label 3881: @114638
      GIM_Try, /*On fail goto*//*Label 3882*/ 114705, // Rule ID 62674 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv8f64] } (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1), VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs2)  =>  (PseudoVFNMSUB_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62674,
        GIR_Done,
      // Label 3882: @114705
      GIM_Try, /*On fail goto*//*Label 3883*/ 114772, // Rule ID 71760 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1), VRM8:{ *:[nxv8f64] }:$rs2)  =>  (PseudoVFNMSUB_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71760,
        GIR_Done,
      // Label 3883: @114772
      GIM_Try, /*On fail goto*//*Label 3884*/ 114839, // Rule ID 71761 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1), VRM8:{ *:[nxv8f64] }:$rs2)  =>  (PseudoVFNMSUB_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71761,
        GIR_Done,
      // Label 3884: @114839
      GIM_Try, /*On fail goto*//*Label 3885*/ 114906, // Rule ID 62669 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rd, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2))  =>  (PseudoVFMSUB_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62669,
        GIR_Done,
      // Label 3885: @114906
      GIM_Try, /*On fail goto*//*Label 3886*/ 114973, // Rule ID 62670 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rd, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2))  =>  (PseudoVFMSUB_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62670,
        GIR_Done,
      // Label 3886: @114973
      GIM_Try, /*On fail goto*//*Label 3887*/ 115027, // Rule ID 62667 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (fma:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs2)  =>  (PseudoVFMADD_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62667,
        GIR_Done,
      // Label 3887: @115027
      GIM_Try, /*On fail goto*//*Label 3888*/ 115081, // Rule ID 62668 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (fma:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs2)  =>  (PseudoVFMADD_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rd, VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62668,
        GIR_Done,
      // Label 3888: @115081
      GIM_Reject,
    // Label 3876: @115082
    GIM_Reject,
    // Label 3696: @115083
    GIM_Try, /*On fail goto*//*Label 3889*/ 115928,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s16,
      GIM_Try, /*On fail goto*//*Label 3890*/ 115177, // Rule ID 62527 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv16f16] } (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1), VRM4:{ *:[nxv16f16] }:$rd, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2))  =>  (PseudoVFNMADD_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62527,
        GIR_Done,
      // Label 3890: @115177
      GIM_Try, /*On fail goto*//*Label 3891*/ 115257, // Rule ID 62528 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv16f16] } (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1), VRM4:{ *:[nxv16f16] }:$rd, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2))  =>  (PseudoVFNMADD_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62528,
        GIR_Done,
      // Label 3891: @115257
      GIM_Try, /*On fail goto*//*Label 3892*/ 115337, // Rule ID 71646 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1), (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2))  =>  (PseudoVFNMADD_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71646,
        GIR_Done,
      // Label 3892: @115337
      GIM_Try, /*On fail goto*//*Label 3893*/ 115417, // Rule ID 71647 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1), (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2))  =>  (PseudoVFNMADD_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71647,
        GIR_Done,
      // Label 3893: @115417
      GIM_Try, /*On fail goto*//*Label 3894*/ 115484, // Rule ID 62529 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv16f16] } (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1), VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs2)  =>  (PseudoVFNMSUB_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62529,
        GIR_Done,
      // Label 3894: @115484
      GIM_Try, /*On fail goto*//*Label 3895*/ 115551, // Rule ID 62530 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv16f16] } (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1), VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs2)  =>  (PseudoVFNMSUB_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62530,
        GIR_Done,
      // Label 3895: @115551
      GIM_Try, /*On fail goto*//*Label 3896*/ 115618, // Rule ID 71648 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1), VRM4:{ *:[nxv16f16] }:$rs2)  =>  (PseudoVFNMSUB_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71648,
        GIR_Done,
      // Label 3896: @115618
      GIM_Try, /*On fail goto*//*Label 3897*/ 115685, // Rule ID 71649 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1), VRM4:{ *:[nxv16f16] }:$rs2)  =>  (PseudoVFNMSUB_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71649,
        GIR_Done,
      // Label 3897: @115685
      GIM_Try, /*On fail goto*//*Label 3898*/ 115752, // Rule ID 62525 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rd, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2))  =>  (PseudoVFMSUB_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62525,
        GIR_Done,
      // Label 3898: @115752
      GIM_Try, /*On fail goto*//*Label 3899*/ 115819, // Rule ID 62526 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rd, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2))  =>  (PseudoVFMSUB_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62526,
        GIR_Done,
      // Label 3899: @115819
      GIM_Try, /*On fail goto*//*Label 3900*/ 115873, // Rule ID 62523 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
        // (fma:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs2)  =>  (PseudoVFMADD_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62523,
        GIR_Done,
      // Label 3900: @115873
      GIM_Try, /*On fail goto*//*Label 3901*/ 115927, // Rule ID 62524 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM4RegClassID,
        // (fma:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs2)  =>  (PseudoVFMADD_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rd, VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62524,
        GIR_Done,
      // Label 3901: @115927
      GIM_Reject,
    // Label 3889: @115928
    GIM_Reject,
    // Label 3697: @115929
    GIM_Try, /*On fail goto*//*Label 3902*/ 116774,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv16s32,
      GIM_Try, /*On fail goto*//*Label 3903*/ 116023, // Rule ID 62609 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv16f32] } (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1), VRM8:{ *:[nxv16f32] }:$rd, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2))  =>  (PseudoVFNMADD_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62609,
        GIR_Done,
      // Label 3903: @116023
      GIM_Try, /*On fail goto*//*Label 3904*/ 116103, // Rule ID 62610 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv16f32] } (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1), VRM8:{ *:[nxv16f32] }:$rd, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2))  =>  (PseudoVFNMADD_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62610,
        GIR_Done,
      // Label 3904: @116103
      GIM_Try, /*On fail goto*//*Label 3905*/ 116183, // Rule ID 71710 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1), (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2))  =>  (PseudoVFNMADD_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71710,
        GIR_Done,
      // Label 3905: @116183
      GIM_Try, /*On fail goto*//*Label 3906*/ 116263, // Rule ID 71711 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1), (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2))  =>  (PseudoVFNMADD_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71711,
        GIR_Done,
      // Label 3906: @116263
      GIM_Try, /*On fail goto*//*Label 3907*/ 116330, // Rule ID 62611 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv16f32] } (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1), VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs2)  =>  (PseudoVFNMSUB_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62611,
        GIR_Done,
      // Label 3907: @116330
      GIM_Try, /*On fail goto*//*Label 3908*/ 116397, // Rule ID 62612 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv16f32] } (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1), VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs2)  =>  (PseudoVFNMSUB_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62612,
        GIR_Done,
      // Label 3908: @116397
      GIM_Try, /*On fail goto*//*Label 3909*/ 116464, // Rule ID 71712 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1), VRM8:{ *:[nxv16f32] }:$rs2)  =>  (PseudoVFNMSUB_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71712,
        GIR_Done,
      // Label 3909: @116464
      GIM_Try, /*On fail goto*//*Label 3910*/ 116531, // Rule ID 71713 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1), VRM8:{ *:[nxv16f32] }:$rs2)  =>  (PseudoVFNMSUB_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71713,
        GIR_Done,
      // Label 3910: @116531
      GIM_Try, /*On fail goto*//*Label 3911*/ 116598, // Rule ID 62607 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rd, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2))  =>  (PseudoVFMSUB_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62607,
        GIR_Done,
      // Label 3911: @116598
      GIM_Try, /*On fail goto*//*Label 3912*/ 116665, // Rule ID 62608 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rd, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2))  =>  (PseudoVFMSUB_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62608,
        GIR_Done,
      // Label 3912: @116665
      GIM_Try, /*On fail goto*//*Label 3913*/ 116719, // Rule ID 62605 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (fma:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs2)  =>  (PseudoVFMADD_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62605,
        GIR_Done,
      // Label 3913: @116719
      GIM_Try, /*On fail goto*//*Label 3914*/ 116773, // Rule ID 62606 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (fma:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs2)  =>  (PseudoVFMADD_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rd, VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62606,
        GIR_Done,
      // Label 3914: @116773
      GIM_Reject,
    // Label 3902: @116774
    GIM_Reject,
    // Label 3698: @116775
    GIM_Try, /*On fail goto*//*Label 3915*/ 117620,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_nxv32s16,
      GIM_Try, /*On fail goto*//*Label 3916*/ 116869, // Rule ID 62547 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv32s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv32f16] } (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1), VRM8:{ *:[nxv32f16] }:$rd, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2))  =>  (PseudoVFNMADD_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62547,
        GIR_Done,
      // Label 3916: @116869
      GIM_Try, /*On fail goto*//*Label 3917*/ 116949, // Rule ID 62548 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv32s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv32f16] } (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1), VRM8:{ *:[nxv32f16] }:$rd, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2))  =>  (PseudoVFNMADD_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62548,
        GIR_Done,
      // Label 3917: @116949
      GIM_Try, /*On fail goto*//*Label 3918*/ 117029, // Rule ID 71662 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv32s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1), (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2))  =>  (PseudoVFNMADD_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71662,
        GIR_Done,
      // Label 3918: @117029
      GIM_Try, /*On fail goto*//*Label 3919*/ 117109, // Rule ID 71663 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv32s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fma:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1), (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2))  =>  (PseudoVFNMADD_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71663,
        GIR_Done,
      // Label 3919: @117109
      GIM_Try, /*On fail goto*//*Label 3920*/ 117176, // Rule ID 62549 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv32f16] } (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1), VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs2)  =>  (PseudoVFNMSUB_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62549,
        GIR_Done,
      // Label 3920: @117176
      GIM_Try, /*On fail goto*//*Label 3921*/ 117243, // Rule ID 62550 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv32f16] } (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1), VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs2)  =>  (PseudoVFNMSUB_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62550,
        GIR_Done,
      // Label 3921: @117243
      GIM_Try, /*On fail goto*//*Label 3922*/ 117310, // Rule ID 71664 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1), VRM8:{ *:[nxv32f16] }:$rs2)  =>  (PseudoVFNMSUB_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71664,
        GIR_Done,
      // Label 3922: @117310
      GIM_Try, /*On fail goto*//*Label 3923*/ 117377, // Rule ID 71665 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1), VRM8:{ *:[nxv32f16] }:$rs2)  =>  (PseudoVFNMSUB_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNMSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 71665,
        GIR_Done,
      // Label 3923: @117377
      GIM_Try, /*On fail goto*//*Label 3924*/ 117444, // Rule ID 62545 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rd, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2))  =>  (PseudoVFMSUB_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62545,
        GIR_Done,
      // Label 3924: @117444
      GIM_Try, /*On fail goto*//*Label 3925*/ 117511, // Rule ID 62546 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fma:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rd, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2))  =>  (PseudoVFMSUB_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMSUB_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62546,
        GIR_Done,
      // Label 3925: @117511
      GIM_Try, /*On fail goto*//*Label 3926*/ 117565, // Rule ID 62543 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (fma:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs2)  =>  (PseudoVFMADD_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] }, 1:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62543,
        GIR_Done,
      // Label 3926: @117565
      GIM_Try, /*On fail goto*//*Label 3927*/ 117619, // Rule ID 62544 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::VRM8RegClassID,
        // (fma:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs2)  =>  (PseudoVFMADD_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rd, VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMADD_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_AddImm, /*InsnID*/0, /*Imm*/1,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62544,
        GIR_Done,
      // Label 3927: @117619
      GIM_Reject,
    // Label 3915: @117620
    GIM_Reject,
    // Label 3699: @117621
    GIM_Reject,
    // Label 49: @117622
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 30, /*)*//*default:*//*Label 3943*/ 118913,
    /*GILLT_nxv1s16*//*Label 3928*/ 117653,
    /*GILLT_nxv1s32*//*Label 3929*/ 117737,
    /*GILLT_nxv1s64*//*Label 3930*/ 117821, 0, 0,
    /*GILLT_nxv2s16*//*Label 3931*/ 117905,
    /*GILLT_nxv2s32*//*Label 3932*/ 117989,
    /*GILLT_nxv2s64*//*Label 3933*/ 118073, 0, 0,
    /*GILLT_nxv4s16*//*Label 3934*/ 118157,
    /*GILLT_nxv4s32*//*Label 3935*/ 118241,
    /*GILLT_nxv4s64*//*Label 3936*/ 118325, 0, 0,
    /*GILLT_nxv8s16*//*Label 3937*/ 118409,
    /*GILLT_nxv8s32*//*Label 3938*/ 118493,
    /*GILLT_nxv8s64*//*Label 3939*/ 118577, 0, 0,
    /*GILLT_nxv16s16*//*Label 3940*/ 118661,
    /*GILLT_nxv16s32*//*Label 3941*/ 118745, 0, 0,
    /*GILLT_nxv32s16*//*Label 3942*/ 118829,
    // Label 3928: @117653
    GIM_Try, /*On fail goto*//*Label 3944*/ 117736,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3945*/ 117705, // Rule ID 62209 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2)  =>  (PseudoVFDIV_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62209,
        GIR_Done,
      // Label 3945: @117705
      GIM_Try, /*On fail goto*//*Label 3946*/ 117735, // Rule ID 62210 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2)  =>  (PseudoVFDIV_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62210,
        GIR_Done,
      // Label 3946: @117735
      GIM_Reject,
    // Label 3944: @117736
    GIM_Reject,
    // Label 3929: @117737
    GIM_Try, /*On fail goto*//*Label 3947*/ 117820,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3948*/ 117789, // Rule ID 62218 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2)  =>  (PseudoVFDIV_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62218,
        GIR_Done,
      // Label 3948: @117789
      GIM_Try, /*On fail goto*//*Label 3949*/ 117819, // Rule ID 62219 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2)  =>  (PseudoVFDIV_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62219,
        GIR_Done,
      // Label 3949: @117819
      GIM_Reject,
    // Label 3947: @117820
    GIM_Reject,
    // Label 3930: @117821
    GIM_Try, /*On fail goto*//*Label 3950*/ 117904,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3951*/ 117873, // Rule ID 62230 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2)  =>  (PseudoVFDIV_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62230,
        GIR_Done,
      // Label 3951: @117873
      GIM_Try, /*On fail goto*//*Label 3952*/ 117903, // Rule ID 62231 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2)  =>  (PseudoVFDIV_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62231,
        GIR_Done,
      // Label 3952: @117903
      GIM_Reject,
    // Label 3950: @117904
    GIM_Reject,
    // Label 3931: @117905
    GIM_Try, /*On fail goto*//*Label 3953*/ 117988,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3954*/ 117957, // Rule ID 62213 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2)  =>  (PseudoVFDIV_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62213,
        GIR_Done,
      // Label 3954: @117957
      GIM_Try, /*On fail goto*//*Label 3955*/ 117987, // Rule ID 62214 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2)  =>  (PseudoVFDIV_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62214,
        GIR_Done,
      // Label 3955: @117987
      GIM_Reject,
    // Label 3953: @117988
    GIM_Reject,
    // Label 3932: @117989
    GIM_Try, /*On fail goto*//*Label 3956*/ 118072,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3957*/ 118041, // Rule ID 62226 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2)  =>  (PseudoVFDIV_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62226,
        GIR_Done,
      // Label 3957: @118041
      GIM_Try, /*On fail goto*//*Label 3958*/ 118071, // Rule ID 62227 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2)  =>  (PseudoVFDIV_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62227,
        GIR_Done,
      // Label 3958: @118071
      GIM_Reject,
    // Label 3956: @118072
    GIM_Reject,
    // Label 3933: @118073
    GIM_Try, /*On fail goto*//*Label 3959*/ 118156,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3960*/ 118125, // Rule ID 62260 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2)  =>  (PseudoVFDIV_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62260,
        GIR_Done,
      // Label 3960: @118125
      GIM_Try, /*On fail goto*//*Label 3961*/ 118155, // Rule ID 62261 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2)  =>  (PseudoVFDIV_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62261,
        GIR_Done,
      // Label 3961: @118155
      GIM_Reject,
    // Label 3959: @118156
    GIM_Reject,
    // Label 3934: @118157
    GIM_Try, /*On fail goto*//*Label 3962*/ 118240,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 3963*/ 118209, // Rule ID 62222 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2)  =>  (PseudoVFDIV_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62222,
        GIR_Done,
      // Label 3963: @118209
      GIM_Try, /*On fail goto*//*Label 3964*/ 118239, // Rule ID 62223 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2)  =>  (PseudoVFDIV_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62223,
        GIR_Done,
      // Label 3964: @118239
      GIM_Reject,
    // Label 3962: @118240
    GIM_Reject,
    // Label 3935: @118241
    GIM_Try, /*On fail goto*//*Label 3965*/ 118324,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3966*/ 118293, // Rule ID 62247 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2)  =>  (PseudoVFDIV_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62247,
        GIR_Done,
      // Label 3966: @118293
      GIM_Try, /*On fail goto*//*Label 3967*/ 118323, // Rule ID 62248 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2)  =>  (PseudoVFDIV_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62248,
        GIR_Done,
      // Label 3967: @118323
      GIM_Reject,
    // Label 3965: @118324
    GIM_Reject,
    // Label 3936: @118325
    GIM_Try, /*On fail goto*//*Label 3968*/ 118408,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3969*/ 118377, // Rule ID 62264 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2)  =>  (PseudoVFDIV_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62264,
        GIR_Done,
      // Label 3969: @118377
      GIM_Try, /*On fail goto*//*Label 3970*/ 118407, // Rule ID 62265 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2)  =>  (PseudoVFDIV_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62265,
        GIR_Done,
      // Label 3970: @118407
      GIM_Reject,
    // Label 3968: @118408
    GIM_Reject,
    // Label 3937: @118409
    GIM_Try, /*On fail goto*//*Label 3971*/ 118492,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 3972*/ 118461, // Rule ID 62234 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2)  =>  (PseudoVFDIV_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62234,
        GIR_Done,
      // Label 3972: @118461
      GIM_Try, /*On fail goto*//*Label 3973*/ 118491, // Rule ID 62235 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2)  =>  (PseudoVFDIV_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62235,
        GIR_Done,
      // Label 3973: @118491
      GIM_Reject,
    // Label 3971: @118492
    GIM_Reject,
    // Label 3938: @118493
    GIM_Try, /*On fail goto*//*Label 3974*/ 118576,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3975*/ 118545, // Rule ID 62251 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2)  =>  (PseudoVFDIV_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62251,
        GIR_Done,
      // Label 3975: @118545
      GIM_Try, /*On fail goto*//*Label 3976*/ 118575, // Rule ID 62252 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2)  =>  (PseudoVFDIV_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62252,
        GIR_Done,
      // Label 3976: @118575
      GIM_Reject,
    // Label 3974: @118576
    GIM_Reject,
    // Label 3939: @118577
    GIM_Try, /*On fail goto*//*Label 3977*/ 118660,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3978*/ 118629, // Rule ID 62268 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2)  =>  (PseudoVFDIV_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62268,
        GIR_Done,
      // Label 3978: @118629
      GIM_Try, /*On fail goto*//*Label 3979*/ 118659, // Rule ID 62269 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2)  =>  (PseudoVFDIV_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62269,
        GIR_Done,
      // Label 3979: @118659
      GIM_Reject,
    // Label 3977: @118660
    GIM_Reject,
    // Label 3940: @118661
    GIM_Try, /*On fail goto*//*Label 3980*/ 118744,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 3981*/ 118713, // Rule ID 62239 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2)  =>  (PseudoVFDIV_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62239,
        GIR_Done,
      // Label 3981: @118713
      GIM_Try, /*On fail goto*//*Label 3982*/ 118743, // Rule ID 62240 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2)  =>  (PseudoVFDIV_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62240,
        GIR_Done,
      // Label 3982: @118743
      GIM_Reject,
    // Label 3980: @118744
    GIM_Reject,
    // Label 3941: @118745
    GIM_Try, /*On fail goto*//*Label 3983*/ 118828,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3984*/ 118797, // Rule ID 62255 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2)  =>  (PseudoVFDIV_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62255,
        GIR_Done,
      // Label 3984: @118797
      GIM_Try, /*On fail goto*//*Label 3985*/ 118827, // Rule ID 62256 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2)  =>  (PseudoVFDIV_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62256,
        GIR_Done,
      // Label 3985: @118827
      GIM_Reject,
    // Label 3983: @118828
    GIM_Reject,
    // Label 3942: @118829
    GIM_Try, /*On fail goto*//*Label 3986*/ 118912,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 3987*/ 118881, // Rule ID 62243 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2)  =>  (PseudoVFDIV_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62243,
        GIR_Done,
      // Label 3987: @118881
      GIM_Try, /*On fail goto*//*Label 3988*/ 118911, // Rule ID 62244 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fdiv:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2)  =>  (PseudoVFDIV_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFDIV_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62244,
        GIR_Done,
      // Label 3988: @118911
      GIM_Reject,
    // Label 3986: @118912
    GIM_Reject,
    // Label 3943: @118913
    GIM_Reject,
    // Label 50: @118914
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 30, /*)*//*default:*//*Label 4004*/ 120085,
    /*GILLT_nxv1s16*//*Label 3989*/ 118945,
    /*GILLT_nxv1s32*//*Label 3990*/ 119021,
    /*GILLT_nxv1s64*//*Label 3991*/ 119097, 0, 0,
    /*GILLT_nxv2s16*//*Label 3992*/ 119173,
    /*GILLT_nxv2s32*//*Label 3993*/ 119249,
    /*GILLT_nxv2s64*//*Label 3994*/ 119325, 0, 0,
    /*GILLT_nxv4s16*//*Label 3995*/ 119401,
    /*GILLT_nxv4s32*//*Label 3996*/ 119477,
    /*GILLT_nxv4s64*//*Label 3997*/ 119553, 0, 0,
    /*GILLT_nxv8s16*//*Label 3998*/ 119629,
    /*GILLT_nxv8s32*//*Label 3999*/ 119705,
    /*GILLT_nxv8s64*//*Label 4000*/ 119781, 0, 0,
    /*GILLT_nxv16s16*//*Label 4001*/ 119857,
    /*GILLT_nxv16s32*//*Label 4002*/ 119933, 0, 0,
    /*GILLT_nxv32s16*//*Label 4003*/ 120009,
    // Label 3989: @118945
    GIM_Try, /*On fail goto*//*Label 4005*/ 119020,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4006*/ 118989, // Rule ID 62951 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs)  =>  (PseudoVFSGNJN_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs, VR:{ *:[nxv1f16] }:$rs, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62951,
        GIR_Done,
      // Label 4006: @118989
      GIM_Try, /*On fail goto*//*Label 4007*/ 119019, // Rule ID 62952 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs)  =>  (PseudoVFSGNJN_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs, VR:{ *:[nxv1f16] }:$rs, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62952,
        GIR_Done,
      // Label 4007: @119019
      GIM_Reject,
    // Label 4005: @119020
    GIM_Reject,
    // Label 3990: @119021
    GIM_Try, /*On fail goto*//*Label 4008*/ 119096,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4009*/ 119065, // Rule ID 62980 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs)  =>  (PseudoVFSGNJN_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs, VR:{ *:[nxv1f32] }:$rs, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62980,
        GIR_Done,
      // Label 4009: @119065
      GIM_Try, /*On fail goto*//*Label 4010*/ 119095, // Rule ID 62981 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs)  =>  (PseudoVFSGNJN_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs, VR:{ *:[nxv1f32] }:$rs, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62981,
        GIR_Done,
      // Label 4010: @119095
      GIM_Reject,
    // Label 4008: @119096
    GIM_Reject,
    // Label 3991: @119097
    GIM_Try, /*On fail goto*//*Label 4011*/ 119172,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4012*/ 119141, // Rule ID 63023 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs)  =>  (PseudoVFSGNJN_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs, VR:{ *:[nxv1f64] }:$rs, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63023,
        GIR_Done,
      // Label 4012: @119141
      GIM_Try, /*On fail goto*//*Label 4013*/ 119171, // Rule ID 63024 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs)  =>  (PseudoVFSGNJN_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs, VR:{ *:[nxv1f64] }:$rs, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63024,
        GIR_Done,
      // Label 4013: @119171
      GIM_Reject,
    // Label 4011: @119172
    GIM_Reject,
    // Label 3992: @119173
    GIM_Try, /*On fail goto*//*Label 4014*/ 119248,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4015*/ 119217, // Rule ID 62965 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs)  =>  (PseudoVFSGNJN_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs, VR:{ *:[nxv2f16] }:$rs, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62965,
        GIR_Done,
      // Label 4015: @119217
      GIM_Try, /*On fail goto*//*Label 4016*/ 119247, // Rule ID 62966 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs)  =>  (PseudoVFSGNJN_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs, VR:{ *:[nxv2f16] }:$rs, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62966,
        GIR_Done,
      // Label 4016: @119247
      GIM_Reject,
    // Label 4014: @119248
    GIM_Reject,
    // Label 3993: @119249
    GIM_Try, /*On fail goto*//*Label 4017*/ 119324,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4018*/ 119293, // Rule ID 63008 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs)  =>  (PseudoVFSGNJN_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs, VR:{ *:[nxv2f32] }:$rs, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63008,
        GIR_Done,
      // Label 4018: @119293
      GIM_Try, /*On fail goto*//*Label 4019*/ 119323, // Rule ID 63009 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs)  =>  (PseudoVFSGNJN_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs, VR:{ *:[nxv2f32] }:$rs, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63009,
        GIR_Done,
      // Label 4019: @119323
      GIM_Reject,
    // Label 4017: @119324
    GIM_Reject,
    // Label 3994: @119325
    GIM_Try, /*On fail goto*//*Label 4020*/ 119400,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4021*/ 119369, // Rule ID 63123 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs)  =>  (PseudoVFSGNJN_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs, VRM2:{ *:[nxv2f64] }:$rs, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63123,
        GIR_Done,
      // Label 4021: @119369
      GIM_Try, /*On fail goto*//*Label 4022*/ 119399, // Rule ID 63124 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs)  =>  (PseudoVFSGNJN_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs, VRM2:{ *:[nxv2f64] }:$rs, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63124,
        GIR_Done,
      // Label 4022: @119399
      GIM_Reject,
    // Label 4020: @119400
    GIM_Reject,
    // Label 3995: @119401
    GIM_Try, /*On fail goto*//*Label 4023*/ 119476,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4024*/ 119445, // Rule ID 62994 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs)  =>  (PseudoVFSGNJN_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs, VR:{ *:[nxv4f16] }:$rs, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62994,
        GIR_Done,
      // Label 4024: @119445
      GIM_Try, /*On fail goto*//*Label 4025*/ 119475, // Rule ID 62995 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs)  =>  (PseudoVFSGNJN_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs, VR:{ *:[nxv4f16] }:$rs, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62995,
        GIR_Done,
      // Label 4025: @119475
      GIM_Reject,
    // Label 4023: @119476
    GIM_Reject,
    // Label 3996: @119477
    GIM_Try, /*On fail goto*//*Label 4026*/ 119552,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4027*/ 119521, // Rule ID 63080 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs)  =>  (PseudoVFSGNJN_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs, VRM2:{ *:[nxv4f32] }:$rs, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63080,
        GIR_Done,
      // Label 4027: @119521
      GIM_Try, /*On fail goto*//*Label 4028*/ 119551, // Rule ID 63081 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs)  =>  (PseudoVFSGNJN_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs, VRM2:{ *:[nxv4f32] }:$rs, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63081,
        GIR_Done,
      // Label 4028: @119551
      GIM_Reject,
    // Label 4026: @119552
    GIM_Reject,
    // Label 3997: @119553
    GIM_Try, /*On fail goto*//*Label 4029*/ 119628,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4030*/ 119597, // Rule ID 63137 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs)  =>  (PseudoVFSGNJN_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs, VRM4:{ *:[nxv4f64] }:$rs, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63137,
        GIR_Done,
      // Label 4030: @119597
      GIM_Try, /*On fail goto*//*Label 4031*/ 119627, // Rule ID 63138 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs)  =>  (PseudoVFSGNJN_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs, VRM4:{ *:[nxv4f64] }:$rs, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63138,
        GIR_Done,
      // Label 4031: @119627
      GIM_Reject,
    // Label 4029: @119628
    GIM_Reject,
    // Label 3998: @119629
    GIM_Try, /*On fail goto*//*Label 4032*/ 119704,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4033*/ 119673, // Rule ID 63037 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs)  =>  (PseudoVFSGNJN_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs, VRM2:{ *:[nxv8f16] }:$rs, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63037,
        GIR_Done,
      // Label 4033: @119673
      GIM_Try, /*On fail goto*//*Label 4034*/ 119703, // Rule ID 63038 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs)  =>  (PseudoVFSGNJN_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs, VRM2:{ *:[nxv8f16] }:$rs, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63038,
        GIR_Done,
      // Label 4034: @119703
      GIM_Reject,
    // Label 4032: @119704
    GIM_Reject,
    // Label 3999: @119705
    GIM_Try, /*On fail goto*//*Label 4035*/ 119780,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4036*/ 119749, // Rule ID 63094 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs)  =>  (PseudoVFSGNJN_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs, VRM4:{ *:[nxv8f32] }:$rs, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63094,
        GIR_Done,
      // Label 4036: @119749
      GIM_Try, /*On fail goto*//*Label 4037*/ 119779, // Rule ID 63095 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs)  =>  (PseudoVFSGNJN_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs, VRM4:{ *:[nxv8f32] }:$rs, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63095,
        GIR_Done,
      // Label 4037: @119779
      GIM_Reject,
    // Label 4035: @119780
    GIM_Reject,
    // Label 4000: @119781
    GIM_Try, /*On fail goto*//*Label 4038*/ 119856,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4039*/ 119825, // Rule ID 63152 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs)  =>  (PseudoVFSGNJN_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs, VRM8:{ *:[nxv8f64] }:$rs, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63152,
        GIR_Done,
      // Label 4039: @119825
      GIM_Try, /*On fail goto*//*Label 4040*/ 119855, // Rule ID 63153 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs)  =>  (PseudoVFSGNJN_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs, VRM8:{ *:[nxv8f64] }:$rs, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63153,
        GIR_Done,
      // Label 4040: @119855
      GIM_Reject,
    // Label 4038: @119856
    GIM_Reject,
    // Label 4001: @119857
    GIM_Try, /*On fail goto*//*Label 4041*/ 119932,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4042*/ 119901, // Rule ID 63051 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs)  =>  (PseudoVFSGNJN_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs, VRM4:{ *:[nxv16f16] }:$rs, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63051,
        GIR_Done,
      // Label 4042: @119901
      GIM_Try, /*On fail goto*//*Label 4043*/ 119931, // Rule ID 63052 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs)  =>  (PseudoVFSGNJN_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs, VRM4:{ *:[nxv16f16] }:$rs, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63052,
        GIR_Done,
      // Label 4043: @119931
      GIM_Reject,
    // Label 4041: @119932
    GIM_Reject,
    // Label 4002: @119933
    GIM_Try, /*On fail goto*//*Label 4044*/ 120008,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4045*/ 119977, // Rule ID 63109 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs)  =>  (PseudoVFSGNJN_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs, VRM8:{ *:[nxv16f32] }:$rs, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63109,
        GIR_Done,
      // Label 4045: @119977
      GIM_Try, /*On fail goto*//*Label 4046*/ 120007, // Rule ID 63110 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs)  =>  (PseudoVFSGNJN_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs, VRM8:{ *:[nxv16f32] }:$rs, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63110,
        GIR_Done,
      // Label 4046: @120007
      GIM_Reject,
    // Label 4044: @120008
    GIM_Reject,
    // Label 4003: @120009
    GIM_Try, /*On fail goto*//*Label 4047*/ 120084,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4048*/ 120053, // Rule ID 63066 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs)  =>  (PseudoVFSGNJN_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs, VRM8:{ *:[nxv32f16] }:$rs, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63066,
        GIR_Done,
      // Label 4048: @120053
      GIM_Try, /*On fail goto*//*Label 4049*/ 120083, // Rule ID 63067 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs)  =>  (PseudoVFSGNJN_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs, VRM8:{ *:[nxv32f16] }:$rs, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63067,
        GIR_Done,
      // Label 4049: @120083
      GIM_Reject,
    // Label 4047: @120084
    GIM_Reject,
    // Label 4004: @120085
    GIM_Reject,
    // Label 51: @120086
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 4052*/ 120165,
    /*GILLT_s32*//*Label 4050*/ 120094,
    /*GILLT_s64*//*Label 4051*/ 120118,
    // Label 4050: @120094
    GIM_Try, /*On fail goto*//*Label 4053*/ 120117, // Rule ID 64711 //
      GIM_CheckFeatures, GIFBS_HasStdExtZfhOrZfhmin,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
      // (fpextend:{ *:[f32] } FPR16:{ *:[f16] }:$rs1)  =>  (FCVT_S_H:{ *:[f32] } FPR16:{ *:[f16] }:$rs1)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FCVT_S_H,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64711,
      GIR_Done,
    // Label 4053: @120117
    GIM_Reject,
    // Label 4051: @120118
    GIM_Try, /*On fail goto*//*Label 4054*/ 120141, // Rule ID 64768 //
      GIM_CheckFeatures, GIFBS_HasStdExtD_HasStdExtZfhOrZfhmin,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
      // (fpextend:{ *:[f64] } FPR16:{ *:[f16] }:$rs1)  =>  (FCVT_D_H:{ *:[f64] } FPR16:{ *:[f16] }:$rs1)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FCVT_D_H,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64768,
      GIR_Done,
    // Label 4054: @120141
    GIM_Try, /*On fail goto*//*Label 4055*/ 120164, // Rule ID 65291 //
      GIM_CheckFeatures, GIFBS_HasStdExtD,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
      // (fpextend:{ *:[f64] } FPR32:{ *:[f32] }:$rs1)  =>  (FCVT_D_S:{ *:[f64] } FPR32:{ *:[f32] }:$rs1)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FCVT_D_S,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65291,
      GIR_Done,
    // Label 4055: @120164
    GIM_Reject,
    // Label 4052: @120165
    GIM_Reject,
    // Label 52: @120166
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 26, /*)*//*default:*//*Label 4067*/ 121013,
    /*GILLT_s16*//*Label 4056*/ 120198,
    /*GILLT_s32*//*Label 4057*/ 120339, 0, 0, 0,
    /*GILLT_nxv1s16*//*Label 4058*/ 120401,
    /*GILLT_nxv1s32*//*Label 4059*/ 120469, 0, 0, 0,
    /*GILLT_nxv2s16*//*Label 4060*/ 120537,
    /*GILLT_nxv2s32*//*Label 4061*/ 120605, 0, 0, 0,
    /*GILLT_nxv4s16*//*Label 4062*/ 120673,
    /*GILLT_nxv4s32*//*Label 4063*/ 120741, 0, 0, 0,
    /*GILLT_nxv8s16*//*Label 4064*/ 120809,
    /*GILLT_nxv8s32*//*Label 4065*/ 120877, 0, 0, 0,
    /*GILLT_nxv16s16*//*Label 4066*/ 120945,
    // Label 4056: @120198
    GIM_Try, /*On fail goto*//*Label 4068*/ 120233, // Rule ID 64708 //
      GIM_CheckFeatures, GIFBS_HasStdExtZfhOrZfhmin,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR16RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
      // (fpround:{ *:[f16] } FPR32:{ *:[f32] }:$rs1)  =>  (FCVT_H_S:{ *:[f16] } FPR32:{ *:[f32] }:$rs1, 7:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_H_S,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/7,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64708,
      GIR_Done,
    // Label 4068: @120233
    GIM_Try, /*On fail goto*//*Label 4069*/ 120268, // Rule ID 64709 //
      GIM_CheckFeatures, GIFBS_HasStdExtZfhOrZfhmin,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR16RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
      // (fpround:{ *:[f16] } FPR32:{ *:[f32] }:$rs1)  =>  (FCVT_H_S:{ *:[f16] } FPR32:{ *:[f32] }:$rs1, 7:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_H_S,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/7,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64709,
      GIR_Done,
    // Label 4069: @120268
    GIM_Try, /*On fail goto*//*Label 4070*/ 120303, // Rule ID 64765 //
      GIM_CheckFeatures, GIFBS_HasStdExtD_HasStdExtZfhOrZfhmin,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR16RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
      // (fpround:{ *:[f16] } FPR64:{ *:[f64] }:$rs1)  =>  (FCVT_H_D:{ *:[f16] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_H_D,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/7,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64765,
      GIR_Done,
    // Label 4070: @120303
    GIM_Try, /*On fail goto*//*Label 4071*/ 120338, // Rule ID 64766 //
      GIM_CheckFeatures, GIFBS_HasStdExtD_HasStdExtZfhOrZfhmin,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR16RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
      // (fpround:{ *:[f16] } FPR64:{ *:[f64] }:$rs1)  =>  (FCVT_H_D:{ *:[f16] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_H_D,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/7,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64766,
      GIR_Done,
    // Label 4071: @120338
    GIM_Reject,
    // Label 4057: @120339
    GIM_Try, /*On fail goto*//*Label 4072*/ 120400,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
      GIM_Try, /*On fail goto*//*Label 4073*/ 120376, // Rule ID 65288 //
        GIM_CheckFeatures, GIFBS_HasStdExtD,
        // (fpround:{ *:[f32] } FPR64:{ *:[f64] }:$rs1)  =>  (FCVT_S_D:{ *:[f32] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_S_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65288,
        GIR_Done,
      // Label 4073: @120376
      GIM_Try, /*On fail goto*//*Label 4074*/ 120399, // Rule ID 65289 //
        GIM_CheckFeatures, GIFBS_HasStdExtD,
        // (fpround:{ *:[f32] } FPR64:{ *:[f64] }:$rs1)  =>  (FCVT_S_D:{ *:[f32] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_S_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65289,
        GIR_Done,
      // Label 4074: @120399
      GIM_Reject,
    // Label 4072: @120400
    GIM_Reject,
    // Label 4058: @120401
    GIM_Try, /*On fail goto*//*Label 4075*/ 120468,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4076*/ 120441, // Rule ID 64472 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fpround:{ *:[nxv1f16] } VR:{ *:[nxv1f32] }:$rs1)  =>  (PseudoVFNCVT_F_F_W_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_F_W_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64472,
        GIR_Done,
      // Label 4076: @120441
      GIM_Try, /*On fail goto*//*Label 4077*/ 120467, // Rule ID 64473 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fpround:{ *:[nxv1f16] } VR:{ *:[nxv1f32] }:$rs1)  =>  (PseudoVFNCVT_F_F_W_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_F_W_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64473,
        GIR_Done,
      // Label 4077: @120467
      GIM_Reject,
    // Label 4075: @120468
    GIM_Reject,
    // Label 4059: @120469
    GIM_Try, /*On fail goto*//*Label 4078*/ 120536,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4079*/ 120509, // Rule ID 64482 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fpround:{ *:[nxv1f32] } VR:{ *:[nxv1f64] }:$rs1)  =>  (PseudoVFNCVT_F_F_W_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_F_W_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64482,
        GIR_Done,
      // Label 4079: @120509
      GIM_Try, /*On fail goto*//*Label 4080*/ 120535, // Rule ID 64483 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fpround:{ *:[nxv1f32] } VR:{ *:[nxv1f64] }:$rs1)  =>  (PseudoVFNCVT_F_F_W_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_F_W_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64483,
        GIR_Done,
      // Label 4080: @120535
      GIM_Reject,
    // Label 4078: @120536
    GIM_Reject,
    // Label 4060: @120537
    GIM_Try, /*On fail goto*//*Label 4081*/ 120604,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4082*/ 120577, // Rule ID 64474 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fpround:{ *:[nxv2f16] } VR:{ *:[nxv2f32] }:$rs1)  =>  (PseudoVFNCVT_F_F_W_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_F_W_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64474,
        GIR_Done,
      // Label 4082: @120577
      GIM_Try, /*On fail goto*//*Label 4083*/ 120603, // Rule ID 64475 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fpround:{ *:[nxv2f16] } VR:{ *:[nxv2f32] }:$rs1)  =>  (PseudoVFNCVT_F_F_W_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_F_W_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64475,
        GIR_Done,
      // Label 4083: @120603
      GIM_Reject,
    // Label 4081: @120604
    GIM_Reject,
    // Label 4061: @120605
    GIM_Try, /*On fail goto*//*Label 4084*/ 120672,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4085*/ 120645, // Rule ID 64484 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fpround:{ *:[nxv2f32] } VRM2:{ *:[nxv2f64] }:$rs1)  =>  (PseudoVFNCVT_F_F_W_M1:{ *:[nxv2f32] } VRM2:{ *:[nxv2f64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_F_W_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64484,
        GIR_Done,
      // Label 4085: @120645
      GIM_Try, /*On fail goto*//*Label 4086*/ 120671, // Rule ID 64485 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fpround:{ *:[nxv2f32] } VRM2:{ *:[nxv2f64] }:$rs1)  =>  (PseudoVFNCVT_F_F_W_M1:{ *:[nxv2f32] } VRM2:{ *:[nxv2f64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_F_W_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64485,
        GIR_Done,
      // Label 4086: @120671
      GIM_Reject,
    // Label 4084: @120672
    GIM_Reject,
    // Label 4062: @120673
    GIM_Try, /*On fail goto*//*Label 4087*/ 120740,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4088*/ 120713, // Rule ID 64476 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fpround:{ *:[nxv4f16] } VRM2:{ *:[nxv4f32] }:$rs1)  =>  (PseudoVFNCVT_F_F_W_M1:{ *:[nxv4f16] } VRM2:{ *:[nxv4f32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_F_W_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64476,
        GIR_Done,
      // Label 4088: @120713
      GIM_Try, /*On fail goto*//*Label 4089*/ 120739, // Rule ID 64477 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fpround:{ *:[nxv4f16] } VRM2:{ *:[nxv4f32] }:$rs1)  =>  (PseudoVFNCVT_F_F_W_M1:{ *:[nxv4f16] } VRM2:{ *:[nxv4f32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_F_W_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64477,
        GIR_Done,
      // Label 4089: @120739
      GIM_Reject,
    // Label 4087: @120740
    GIM_Reject,
    // Label 4063: @120741
    GIM_Try, /*On fail goto*//*Label 4090*/ 120808,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4091*/ 120781, // Rule ID 64488 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fpround:{ *:[nxv4f32] } VRM4:{ *:[nxv4f64] }:$rs1)  =>  (PseudoVFNCVT_F_F_W_M2:{ *:[nxv4f32] } VRM4:{ *:[nxv4f64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_F_W_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64488,
        GIR_Done,
      // Label 4091: @120781
      GIM_Try, /*On fail goto*//*Label 4092*/ 120807, // Rule ID 64489 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fpround:{ *:[nxv4f32] } VRM4:{ *:[nxv4f64] }:$rs1)  =>  (PseudoVFNCVT_F_F_W_M2:{ *:[nxv4f32] } VRM4:{ *:[nxv4f64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_F_W_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64489,
        GIR_Done,
      // Label 4092: @120807
      GIM_Reject,
    // Label 4090: @120808
    GIM_Reject,
    // Label 4064: @120809
    GIM_Try, /*On fail goto*//*Label 4093*/ 120876,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4094*/ 120849, // Rule ID 64478 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fpround:{ *:[nxv8f16] } VRM4:{ *:[nxv8f32] }:$rs1)  =>  (PseudoVFNCVT_F_F_W_M2:{ *:[nxv8f16] } VRM4:{ *:[nxv8f32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_F_W_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64478,
        GIR_Done,
      // Label 4094: @120849
      GIM_Try, /*On fail goto*//*Label 4095*/ 120875, // Rule ID 64479 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fpround:{ *:[nxv8f16] } VRM4:{ *:[nxv8f32] }:$rs1)  =>  (PseudoVFNCVT_F_F_W_M2:{ *:[nxv8f16] } VRM4:{ *:[nxv8f32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_F_W_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64479,
        GIR_Done,
      // Label 4095: @120875
      GIM_Reject,
    // Label 4093: @120876
    GIM_Reject,
    // Label 4065: @120877
    GIM_Try, /*On fail goto*//*Label 4096*/ 120944,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4097*/ 120917, // Rule ID 64490 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fpround:{ *:[nxv8f32] } VRM8:{ *:[nxv8f64] }:$rs1)  =>  (PseudoVFNCVT_F_F_W_M4:{ *:[nxv8f32] } VRM8:{ *:[nxv8f64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_F_W_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64490,
        GIR_Done,
      // Label 4097: @120917
      GIM_Try, /*On fail goto*//*Label 4098*/ 120943, // Rule ID 64491 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fpround:{ *:[nxv8f32] } VRM8:{ *:[nxv8f64] }:$rs1)  =>  (PseudoVFNCVT_F_F_W_M4:{ *:[nxv8f32] } VRM8:{ *:[nxv8f64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_F_W_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64491,
        GIR_Done,
      // Label 4098: @120943
      GIM_Reject,
    // Label 4096: @120944
    GIM_Reject,
    // Label 4066: @120945
    GIM_Try, /*On fail goto*//*Label 4099*/ 121012,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4100*/ 120985, // Rule ID 64480 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fpround:{ *:[nxv16f16] } VRM8:{ *:[nxv16f32] }:$rs1)  =>  (PseudoVFNCVT_F_F_W_M4:{ *:[nxv16f16] } VRM8:{ *:[nxv16f32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_F_W_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64480,
        GIR_Done,
      // Label 4100: @120985
      GIM_Try, /*On fail goto*//*Label 4101*/ 121011, // Rule ID 64481 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fpround:{ *:[nxv16f16] } VRM8:{ *:[nxv16f32] }:$rs1)  =>  (PseudoVFNCVT_F_F_W_M4:{ *:[nxv16f16] } VRM8:{ *:[nxv16f32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_F_W_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64481,
        GIR_Done,
      // Label 4101: @121011
      GIM_Reject,
    // Label 4099: @121012
    GIM_Reject,
    // Label 4067: @121013
    GIM_Reject,
    // Label 53: @121014
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 30, /*)*//*default:*//*Label 4125*/ 124043,
    /*GILLT_s32*//*Label 4102*/ 121049,
    /*GILLT_s64*//*Label 4103*/ 121085, 0,
    /*GILLT_nxv1s8*//*Label 4104*/ 121121,
    /*GILLT_nxv1s16*//*Label 4105*/ 121189,
    /*GILLT_nxv1s32*//*Label 4106*/ 121342,
    /*GILLT_nxv1s64*//*Label 4107*/ 121571, 0,
    /*GILLT_nxv2s8*//*Label 4108*/ 121724,
    /*GILLT_nxv2s16*//*Label 4109*/ 121792,
    /*GILLT_nxv2s32*//*Label 4110*/ 121945,
    /*GILLT_nxv2s64*//*Label 4111*/ 122174, 0,
    /*GILLT_nxv4s8*//*Label 4112*/ 122327,
    /*GILLT_nxv4s16*//*Label 4113*/ 122395,
    /*GILLT_nxv4s32*//*Label 4114*/ 122548,
    /*GILLT_nxv4s64*//*Label 4115*/ 122777, 0,
    /*GILLT_nxv8s8*//*Label 4116*/ 122930,
    /*GILLT_nxv8s16*//*Label 4117*/ 122998,
    /*GILLT_nxv8s32*//*Label 4118*/ 123151,
    /*GILLT_nxv8s64*//*Label 4119*/ 123380, 0,
    /*GILLT_nxv16s8*//*Label 4120*/ 123533,
    /*GILLT_nxv16s16*//*Label 4121*/ 123601,
    /*GILLT_nxv16s32*//*Label 4122*/ 123754, 0,
    /*GILLT_nxv32s8*//*Label 4123*/ 123907,
    /*GILLT_nxv32s16*//*Label 4124*/ 123975,
    // Label 4102: @121049
    GIM_Try, /*On fail goto*//*Label 4126*/ 121084, // Rule ID 65390 //
      GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
      // (fp_to_sint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1)  =>  (FCVT_W_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_W_D,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/1,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65390,
      GIR_Done,
    // Label 4126: @121084
    GIM_Reject,
    // Label 4103: @121085
    GIM_Try, /*On fail goto*//*Label 4127*/ 121120, // Rule ID 65418 //
      GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
      // (fp_to_sint:{ *:[i64] } FPR64:{ *:[f64] }:$rs1)  =>  (FCVT_L_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_L_D,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/1,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65418,
      GIR_Done,
    // Label 4127: @121120
    GIM_Reject,
    // Label 4104: @121121
    GIM_Try, /*On fail goto*//*Label 4128*/ 121188,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4129*/ 121161, // Rule ID 54979 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_sint:{ *:[nxv1i8] } VR:{ *:[nxv1f16] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1f16] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 54979,
        GIR_Done,
      // Label 4129: @121161
      GIM_Try, /*On fail goto*//*Label 4130*/ 121187, // Rule ID 54980 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_sint:{ *:[nxv1i8] } VR:{ *:[nxv1f16] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1f16] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 54980,
        GIR_Done,
      // Label 4130: @121187
      GIM_Reject,
    // Label 4128: @121188
    GIM_Reject,
    // Label 4105: @121189
    GIM_Try, /*On fail goto*//*Label 4131*/ 121227, // Rule ID 54971 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv1i16] } VR:{ *:[nxv1f16] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 54971,
      GIR_Done,
    // Label 4131: @121227
    GIM_Try, /*On fail goto*//*Label 4132*/ 121265, // Rule ID 54972 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv1i16] } VR:{ *:[nxv1f16] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 54972,
      GIR_Done,
    // Label 4132: @121265
    GIM_Try, /*On fail goto*//*Label 4133*/ 121303, // Rule ID 64382 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv1i16] } VR:{ *:[nxv1f32] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1f32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64382,
      GIR_Done,
    // Label 4133: @121303
    GIM_Try, /*On fail goto*//*Label 4134*/ 121341, // Rule ID 64383 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv1i16] } VR:{ *:[nxv1f32] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1f32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64383,
      GIR_Done,
    // Label 4134: @121341
    GIM_Reject,
    // Label 4106: @121342
    GIM_Try, /*On fail goto*//*Label 4135*/ 121380, // Rule ID 54975 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv1i32] } VR:{ *:[nxv1f16] }:$rs1)  =>  (PseudoVFWCVT_RTZ_X_F_V_MF4:{ *:[nxv1i32] } VR:{ *:[nxv1f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_X_F_V_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 54975,
      GIR_Done,
    // Label 4135: @121380
    GIM_Try, /*On fail goto*//*Label 4136*/ 121418, // Rule ID 54976 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv1i32] } VR:{ *:[nxv1f16] }:$rs1)  =>  (PseudoVFWCVT_RTZ_X_F_V_MF4:{ *:[nxv1i32] } VR:{ *:[nxv1f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_X_F_V_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 54976,
      GIR_Done,
    // Label 4136: @121418
    GIM_Try, /*On fail goto*//*Label 4137*/ 121456, // Rule ID 64148 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv1i32] } VR:{ *:[nxv1f32] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64148,
      GIR_Done,
    // Label 4137: @121456
    GIM_Try, /*On fail goto*//*Label 4138*/ 121494, // Rule ID 64149 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv1i32] } VR:{ *:[nxv1f32] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64149,
      GIR_Done,
    // Label 4138: @121494
    GIM_Try, /*On fail goto*//*Label 4139*/ 121532, // Rule ID 64394 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv1i32] } VR:{ *:[nxv1f64] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1f64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64394,
      GIR_Done,
    // Label 4139: @121532
    GIM_Try, /*On fail goto*//*Label 4140*/ 121570, // Rule ID 64395 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv1i32] } VR:{ *:[nxv1f64] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1f64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64395,
      GIR_Done,
    // Label 4140: @121570
    GIM_Reject,
    // Label 4107: @121571
    GIM_Try, /*On fail goto*//*Label 4141*/ 121609, // Rule ID 64154 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv1i64] } VR:{ *:[nxv1f64] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_M1:{ *:[nxv1i64] } VR:{ *:[nxv1f64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64154,
      GIR_Done,
    // Label 4141: @121609
    GIM_Try, /*On fail goto*//*Label 4142*/ 121647, // Rule ID 64155 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv1i64] } VR:{ *:[nxv1f64] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_M1:{ *:[nxv1i64] } VR:{ *:[nxv1f64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64155,
      GIR_Done,
    // Label 4142: @121647
    GIM_Try, /*On fail goto*//*Label 4143*/ 121685, // Rule ID 64280 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv1i64] } VR:{ *:[nxv1f32] }:$rs1)  =>  (PseudoVFWCVT_RTZ_X_F_V_MF2:{ *:[nxv1i64] } VR:{ *:[nxv1f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_X_F_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64280,
      GIR_Done,
    // Label 4143: @121685
    GIM_Try, /*On fail goto*//*Label 4144*/ 121723, // Rule ID 64281 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv1i64] } VR:{ *:[nxv1f32] }:$rs1)  =>  (PseudoVFWCVT_RTZ_X_F_V_MF2:{ *:[nxv1i64] } VR:{ *:[nxv1f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_X_F_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64281,
      GIR_Done,
    // Label 4144: @121723
    GIM_Reject,
    // Label 4108: @121724
    GIM_Try, /*On fail goto*//*Label 4145*/ 121791,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4146*/ 121764, // Rule ID 64372 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_sint:{ *:[nxv2i8] } VR:{ *:[nxv2f16] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2f16] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64372,
        GIR_Done,
      // Label 4146: @121764
      GIM_Try, /*On fail goto*//*Label 4147*/ 121790, // Rule ID 64373 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_sint:{ *:[nxv2i8] } VR:{ *:[nxv2f16] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2f16] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64373,
        GIR_Done,
      // Label 4147: @121790
      GIM_Reject,
    // Label 4145: @121791
    GIM_Reject,
    // Label 4109: @121792
    GIM_Try, /*On fail goto*//*Label 4148*/ 121830, // Rule ID 64146 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv2i16] } VR:{ *:[nxv2f16] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64146,
      GIR_Done,
    // Label 4148: @121830
    GIM_Try, /*On fail goto*//*Label 4149*/ 121868, // Rule ID 64147 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv2i16] } VR:{ *:[nxv2f16] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64147,
      GIR_Done,
    // Label 4149: @121868
    GIM_Try, /*On fail goto*//*Label 4150*/ 121906, // Rule ID 64386 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv2i16] } VR:{ *:[nxv2f32] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2f32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64386,
      GIR_Done,
    // Label 4150: @121906
    GIM_Try, /*On fail goto*//*Label 4151*/ 121944, // Rule ID 64387 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv2i16] } VR:{ *:[nxv2f32] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2f32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64387,
      GIR_Done,
    // Label 4151: @121944
    GIM_Reject,
    // Label 4110: @121945
    GIM_Try, /*On fail goto*//*Label 4152*/ 121983, // Rule ID 64152 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv2i32] } VR:{ *:[nxv2f32] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_M1:{ *:[nxv2i32] } VR:{ *:[nxv2f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64152,
      GIR_Done,
    // Label 4152: @121983
    GIM_Try, /*On fail goto*//*Label 4153*/ 122021, // Rule ID 64153 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv2i32] } VR:{ *:[nxv2f32] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_M1:{ *:[nxv2i32] } VR:{ *:[nxv2f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64153,
      GIR_Done,
    // Label 4153: @122021
    GIM_Try, /*On fail goto*//*Label 4154*/ 122059, // Rule ID 64272 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv2i32] } VR:{ *:[nxv2f16] }:$rs1)  =>  (PseudoVFWCVT_RTZ_X_F_V_MF2:{ *:[nxv2i32] } VR:{ *:[nxv2f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_X_F_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64272,
      GIR_Done,
    // Label 4154: @122059
    GIM_Try, /*On fail goto*//*Label 4155*/ 122097, // Rule ID 64273 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv2i32] } VR:{ *:[nxv2f16] }:$rs1)  =>  (PseudoVFWCVT_RTZ_X_F_V_MF2:{ *:[nxv2i32] } VR:{ *:[nxv2f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_X_F_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64273,
      GIR_Done,
    // Label 4155: @122097
    GIM_Try, /*On fail goto*//*Label 4156*/ 122135, // Rule ID 64396 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_sint:{ *:[nxv2i32] } VRM2:{ *:[nxv2f64] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_M1:{ *:[nxv2i32] } VRM2:{ *:[nxv2f64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64396,
      GIR_Done,
    // Label 4156: @122135
    GIM_Try, /*On fail goto*//*Label 4157*/ 122173, // Rule ID 64397 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_sint:{ *:[nxv2i32] } VRM2:{ *:[nxv2f64] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_M1:{ *:[nxv2i32] } VRM2:{ *:[nxv2f64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64397,
      GIR_Done,
    // Label 4157: @122173
    GIM_Reject,
    // Label 4111: @122174
    GIM_Try, /*On fail goto*//*Label 4158*/ 122212, // Rule ID 64170 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_sint:{ *:[nxv2i64] } VRM2:{ *:[nxv2f64] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2f64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64170,
      GIR_Done,
    // Label 4158: @122212
    GIM_Try, /*On fail goto*//*Label 4159*/ 122250, // Rule ID 64171 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_sint:{ *:[nxv2i64] } VRM2:{ *:[nxv2f64] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2f64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64171,
      GIR_Done,
    // Label 4159: @122250
    GIM_Try, /*On fail goto*//*Label 4160*/ 122288, // Rule ID 64282 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv2i64] } VR:{ *:[nxv2f32] }:$rs1)  =>  (PseudoVFWCVT_RTZ_X_F_V_M1:{ *:[nxv2i64] } VR:{ *:[nxv2f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_X_F_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64282,
      GIR_Done,
    // Label 4160: @122288
    GIM_Try, /*On fail goto*//*Label 4161*/ 122326, // Rule ID 64283 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv2i64] } VR:{ *:[nxv2f32] }:$rs1)  =>  (PseudoVFWCVT_RTZ_X_F_V_M1:{ *:[nxv2i64] } VR:{ *:[nxv2f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_X_F_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64283,
      GIR_Done,
    // Label 4161: @122326
    GIM_Reject,
    // Label 4112: @122327
    GIM_Try, /*On fail goto*//*Label 4162*/ 122394,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4163*/ 122367, // Rule ID 64374 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_sint:{ *:[nxv4i8] } VR:{ *:[nxv4f16] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4f16] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64374,
        GIR_Done,
      // Label 4163: @122367
      GIM_Try, /*On fail goto*//*Label 4164*/ 122393, // Rule ID 64375 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_sint:{ *:[nxv4i8] } VR:{ *:[nxv4f16] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4f16] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64375,
        GIR_Done,
      // Label 4164: @122393
      GIM_Reject,
    // Label 4162: @122394
    GIM_Reject,
    // Label 4113: @122395
    GIM_Try, /*On fail goto*//*Label 4165*/ 122433, // Rule ID 64150 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv4i16] } VR:{ *:[nxv4f16] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_M1:{ *:[nxv4i16] } VR:{ *:[nxv4f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64150,
      GIR_Done,
    // Label 4165: @122433
    GIM_Try, /*On fail goto*//*Label 4166*/ 122471, // Rule ID 64151 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv4i16] } VR:{ *:[nxv4f16] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_M1:{ *:[nxv4i16] } VR:{ *:[nxv4f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64151,
      GIR_Done,
    // Label 4166: @122471
    GIM_Try, /*On fail goto*//*Label 4167*/ 122509, // Rule ID 64388 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_sint:{ *:[nxv4i16] } VRM2:{ *:[nxv4f32] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_M1:{ *:[nxv4i16] } VRM2:{ *:[nxv4f32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64388,
      GIR_Done,
    // Label 4167: @122509
    GIM_Try, /*On fail goto*//*Label 4168*/ 122547, // Rule ID 64389 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_sint:{ *:[nxv4i16] } VRM2:{ *:[nxv4f32] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_M1:{ *:[nxv4i16] } VRM2:{ *:[nxv4f32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64389,
      GIR_Done,
    // Label 4168: @122547
    GIM_Reject,
    // Label 4114: @122548
    GIM_Try, /*On fail goto*//*Label 4169*/ 122586, // Rule ID 64164 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_sint:{ *:[nxv4i32] } VRM2:{ *:[nxv4f32] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64164,
      GIR_Done,
    // Label 4169: @122586
    GIM_Try, /*On fail goto*//*Label 4170*/ 122624, // Rule ID 64165 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_sint:{ *:[nxv4i32] } VRM2:{ *:[nxv4f32] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64165,
      GIR_Done,
    // Label 4170: @122624
    GIM_Try, /*On fail goto*//*Label 4171*/ 122662, // Rule ID 64274 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv4i32] } VR:{ *:[nxv4f16] }:$rs1)  =>  (PseudoVFWCVT_RTZ_X_F_V_M1:{ *:[nxv4i32] } VR:{ *:[nxv4f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_X_F_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64274,
      GIR_Done,
    // Label 4171: @122662
    GIM_Try, /*On fail goto*//*Label 4172*/ 122700, // Rule ID 64275 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_sint:{ *:[nxv4i32] } VR:{ *:[nxv4f16] }:$rs1)  =>  (PseudoVFWCVT_RTZ_X_F_V_M1:{ *:[nxv4i32] } VR:{ *:[nxv4f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_X_F_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64275,
      GIR_Done,
    // Label 4172: @122700
    GIM_Try, /*On fail goto*//*Label 4173*/ 122738, // Rule ID 64398 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_sint:{ *:[nxv4i32] } VRM4:{ *:[nxv4f64] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_M2:{ *:[nxv4i32] } VRM4:{ *:[nxv4f64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64398,
      GIR_Done,
    // Label 4173: @122738
    GIM_Try, /*On fail goto*//*Label 4174*/ 122776, // Rule ID 64399 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_sint:{ *:[nxv4i32] } VRM4:{ *:[nxv4f64] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_M2:{ *:[nxv4i32] } VRM4:{ *:[nxv4f64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64399,
      GIR_Done,
    // Label 4174: @122776
    GIM_Reject,
    // Label 4115: @122777
    GIM_Try, /*On fail goto*//*Label 4175*/ 122815, // Rule ID 64172 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_sint:{ *:[nxv4i64] } VRM4:{ *:[nxv4f64] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4f64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64172,
      GIR_Done,
    // Label 4175: @122815
    GIM_Try, /*On fail goto*//*Label 4176*/ 122853, // Rule ID 64173 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_sint:{ *:[nxv4i64] } VRM4:{ *:[nxv4f64] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4f64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64173,
      GIR_Done,
    // Label 4176: @122853
    GIM_Try, /*On fail goto*//*Label 4177*/ 122891, // Rule ID 64286 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_sint:{ *:[nxv4i64] } VRM2:{ *:[nxv4f32] }:$rs1)  =>  (PseudoVFWCVT_RTZ_X_F_V_M2:{ *:[nxv4i64] } VRM2:{ *:[nxv4f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_X_F_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64286,
      GIR_Done,
    // Label 4177: @122891
    GIM_Try, /*On fail goto*//*Label 4178*/ 122929, // Rule ID 64287 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_sint:{ *:[nxv4i64] } VRM2:{ *:[nxv4f32] }:$rs1)  =>  (PseudoVFWCVT_RTZ_X_F_V_M2:{ *:[nxv4i64] } VRM2:{ *:[nxv4f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_X_F_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64287,
      GIR_Done,
    // Label 4178: @122929
    GIM_Reject,
    // Label 4116: @122930
    GIM_Try, /*On fail goto*//*Label 4179*/ 122997,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4180*/ 122970, // Rule ID 64376 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_sint:{ *:[nxv8i8] } VRM2:{ *:[nxv8f16] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_M1:{ *:[nxv8i8] } VRM2:{ *:[nxv8f16] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64376,
        GIR_Done,
      // Label 4180: @122970
      GIM_Try, /*On fail goto*//*Label 4181*/ 122996, // Rule ID 64377 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_sint:{ *:[nxv8i8] } VRM2:{ *:[nxv8f16] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_M1:{ *:[nxv8i8] } VRM2:{ *:[nxv8f16] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64377,
        GIR_Done,
      // Label 4181: @122996
      GIM_Reject,
    // Label 4179: @122997
    GIM_Reject,
    // Label 4117: @122998
    GIM_Try, /*On fail goto*//*Label 4182*/ 123036, // Rule ID 64156 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_sint:{ *:[nxv8i16] } VRM2:{ *:[nxv8f16] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64156,
      GIR_Done,
    // Label 4182: @123036
    GIM_Try, /*On fail goto*//*Label 4183*/ 123074, // Rule ID 64157 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_sint:{ *:[nxv8i16] } VRM2:{ *:[nxv8f16] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64157,
      GIR_Done,
    // Label 4183: @123074
    GIM_Try, /*On fail goto*//*Label 4184*/ 123112, // Rule ID 64390 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_sint:{ *:[nxv8i16] } VRM4:{ *:[nxv8f32] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_M2:{ *:[nxv8i16] } VRM4:{ *:[nxv8f32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64390,
      GIR_Done,
    // Label 4184: @123112
    GIM_Try, /*On fail goto*//*Label 4185*/ 123150, // Rule ID 64391 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_sint:{ *:[nxv8i16] } VRM4:{ *:[nxv8f32] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_M2:{ *:[nxv8i16] } VRM4:{ *:[nxv8f32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64391,
      GIR_Done,
    // Label 4185: @123150
    GIM_Reject,
    // Label 4118: @123151
    GIM_Try, /*On fail goto*//*Label 4186*/ 123189, // Rule ID 64166 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_sint:{ *:[nxv8i32] } VRM4:{ *:[nxv8f32] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64166,
      GIR_Done,
    // Label 4186: @123189
    GIM_Try, /*On fail goto*//*Label 4187*/ 123227, // Rule ID 64167 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_sint:{ *:[nxv8i32] } VRM4:{ *:[nxv8f32] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64167,
      GIR_Done,
    // Label 4187: @123227
    GIM_Try, /*On fail goto*//*Label 4188*/ 123265, // Rule ID 64276 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_sint:{ *:[nxv8i32] } VRM2:{ *:[nxv8f16] }:$rs1)  =>  (PseudoVFWCVT_RTZ_X_F_V_M2:{ *:[nxv8i32] } VRM2:{ *:[nxv8f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_X_F_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64276,
      GIR_Done,
    // Label 4188: @123265
    GIM_Try, /*On fail goto*//*Label 4189*/ 123303, // Rule ID 64277 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_sint:{ *:[nxv8i32] } VRM2:{ *:[nxv8f16] }:$rs1)  =>  (PseudoVFWCVT_RTZ_X_F_V_M2:{ *:[nxv8i32] } VRM2:{ *:[nxv8f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_X_F_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64277,
      GIR_Done,
    // Label 4189: @123303
    GIM_Try, /*On fail goto*//*Label 4190*/ 123341, // Rule ID 64400 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (fp_to_sint:{ *:[nxv8i32] } VRM8:{ *:[nxv8f64] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_M4:{ *:[nxv8i32] } VRM8:{ *:[nxv8f64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64400,
      GIR_Done,
    // Label 4190: @123341
    GIM_Try, /*On fail goto*//*Label 4191*/ 123379, // Rule ID 64401 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (fp_to_sint:{ *:[nxv8i32] } VRM8:{ *:[nxv8f64] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_M4:{ *:[nxv8i32] } VRM8:{ *:[nxv8f64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64401,
      GIR_Done,
    // Label 4191: @123379
    GIM_Reject,
    // Label 4119: @123380
    GIM_Try, /*On fail goto*//*Label 4192*/ 123418, // Rule ID 64174 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (fp_to_sint:{ *:[nxv8i64] } VRM8:{ *:[nxv8f64] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8f64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64174,
      GIR_Done,
    // Label 4192: @123418
    GIM_Try, /*On fail goto*//*Label 4193*/ 123456, // Rule ID 64175 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (fp_to_sint:{ *:[nxv8i64] } VRM8:{ *:[nxv8f64] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8f64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64175,
      GIR_Done,
    // Label 4193: @123456
    GIM_Try, /*On fail goto*//*Label 4194*/ 123494, // Rule ID 64288 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_sint:{ *:[nxv8i64] } VRM4:{ *:[nxv8f32] }:$rs1)  =>  (PseudoVFWCVT_RTZ_X_F_V_M4:{ *:[nxv8i64] } VRM4:{ *:[nxv8f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_X_F_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64288,
      GIR_Done,
    // Label 4194: @123494
    GIM_Try, /*On fail goto*//*Label 4195*/ 123532, // Rule ID 64289 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_sint:{ *:[nxv8i64] } VRM4:{ *:[nxv8f32] }:$rs1)  =>  (PseudoVFWCVT_RTZ_X_F_V_M4:{ *:[nxv8i64] } VRM4:{ *:[nxv8f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_X_F_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64289,
      GIR_Done,
    // Label 4195: @123532
    GIM_Reject,
    // Label 4120: @123533
    GIM_Try, /*On fail goto*//*Label 4196*/ 123600,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4197*/ 123573, // Rule ID 64378 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_sint:{ *:[nxv16i8] } VRM4:{ *:[nxv16f16] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_M2:{ *:[nxv16i8] } VRM4:{ *:[nxv16f16] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64378,
        GIR_Done,
      // Label 4197: @123573
      GIM_Try, /*On fail goto*//*Label 4198*/ 123599, // Rule ID 64379 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_sint:{ *:[nxv16i8] } VRM4:{ *:[nxv16f16] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_M2:{ *:[nxv16i8] } VRM4:{ *:[nxv16f16] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64379,
        GIR_Done,
      // Label 4198: @123599
      GIM_Reject,
    // Label 4196: @123600
    GIM_Reject,
    // Label 4121: @123601
    GIM_Try, /*On fail goto*//*Label 4199*/ 123639, // Rule ID 64158 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_sint:{ *:[nxv16i16] } VRM4:{ *:[nxv16f16] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64158,
      GIR_Done,
    // Label 4199: @123639
    GIM_Try, /*On fail goto*//*Label 4200*/ 123677, // Rule ID 64159 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_sint:{ *:[nxv16i16] } VRM4:{ *:[nxv16f16] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64159,
      GIR_Done,
    // Label 4200: @123677
    GIM_Try, /*On fail goto*//*Label 4201*/ 123715, // Rule ID 64392 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (fp_to_sint:{ *:[nxv16i16] } VRM8:{ *:[nxv16f32] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_M4:{ *:[nxv16i16] } VRM8:{ *:[nxv16f32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64392,
      GIR_Done,
    // Label 4201: @123715
    GIM_Try, /*On fail goto*//*Label 4202*/ 123753, // Rule ID 64393 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (fp_to_sint:{ *:[nxv16i16] } VRM8:{ *:[nxv16f32] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_M4:{ *:[nxv16i16] } VRM8:{ *:[nxv16f32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64393,
      GIR_Done,
    // Label 4202: @123753
    GIM_Reject,
    // Label 4122: @123754
    GIM_Try, /*On fail goto*//*Label 4203*/ 123792, // Rule ID 64168 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (fp_to_sint:{ *:[nxv16i32] } VRM8:{ *:[nxv16f32] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64168,
      GIR_Done,
    // Label 4203: @123792
    GIM_Try, /*On fail goto*//*Label 4204*/ 123830, // Rule ID 64169 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (fp_to_sint:{ *:[nxv16i32] } VRM8:{ *:[nxv16f32] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64169,
      GIR_Done,
    // Label 4204: @123830
    GIM_Try, /*On fail goto*//*Label 4205*/ 123868, // Rule ID 64278 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_sint:{ *:[nxv16i32] } VRM4:{ *:[nxv16f16] }:$rs1)  =>  (PseudoVFWCVT_RTZ_X_F_V_M4:{ *:[nxv16i32] } VRM4:{ *:[nxv16f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_X_F_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64278,
      GIR_Done,
    // Label 4205: @123868
    GIM_Try, /*On fail goto*//*Label 4206*/ 123906, // Rule ID 64279 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_sint:{ *:[nxv16i32] } VRM4:{ *:[nxv16f16] }:$rs1)  =>  (PseudoVFWCVT_RTZ_X_F_V_M4:{ *:[nxv16i32] } VRM4:{ *:[nxv16f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_X_F_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64279,
      GIR_Done,
    // Label 4206: @123906
    GIM_Reject,
    // Label 4123: @123907
    GIM_Try, /*On fail goto*//*Label 4207*/ 123974,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4208*/ 123947, // Rule ID 64380 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_sint:{ *:[nxv32i8] } VRM8:{ *:[nxv32f16] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_M4:{ *:[nxv32i8] } VRM8:{ *:[nxv32f16] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64380,
        GIR_Done,
      // Label 4208: @123947
      GIM_Try, /*On fail goto*//*Label 4209*/ 123973, // Rule ID 64381 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_sint:{ *:[nxv32i8] } VRM8:{ *:[nxv32f16] }:$rs1)  =>  (PseudoVFNCVT_RTZ_X_F_W_M4:{ *:[nxv32i8] } VRM8:{ *:[nxv32f16] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_X_F_W_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64381,
        GIR_Done,
      // Label 4209: @123973
      GIM_Reject,
    // Label 4207: @123974
    GIM_Reject,
    // Label 4124: @123975
    GIM_Try, /*On fail goto*//*Label 4210*/ 124042,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4211*/ 124015, // Rule ID 64160 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_sint:{ *:[nxv32i16] } VRM8:{ *:[nxv32f16] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64160,
        GIR_Done,
      // Label 4211: @124015
      GIM_Try, /*On fail goto*//*Label 4212*/ 124041, // Rule ID 64161 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_sint:{ *:[nxv32i16] } VRM8:{ *:[nxv32f16] }:$rs1)  =>  (PseudoVFCVT_RTZ_X_F_V_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_X_F_V_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64161,
        GIR_Done,
      // Label 4212: @124041
      GIM_Reject,
    // Label 4210: @124042
    GIM_Reject,
    // Label 4125: @124043
    GIM_Reject,
    // Label 54: @124044
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 30, /*)*//*default:*//*Label 4236*/ 127073,
    /*GILLT_s32*//*Label 4213*/ 124079,
    /*GILLT_s64*//*Label 4214*/ 124115, 0,
    /*GILLT_nxv1s8*//*Label 4215*/ 124151,
    /*GILLT_nxv1s16*//*Label 4216*/ 124219,
    /*GILLT_nxv1s32*//*Label 4217*/ 124372,
    /*GILLT_nxv1s64*//*Label 4218*/ 124601, 0,
    /*GILLT_nxv2s8*//*Label 4219*/ 124754,
    /*GILLT_nxv2s16*//*Label 4220*/ 124822,
    /*GILLT_nxv2s32*//*Label 4221*/ 124975,
    /*GILLT_nxv2s64*//*Label 4222*/ 125204, 0,
    /*GILLT_nxv4s8*//*Label 4223*/ 125357,
    /*GILLT_nxv4s16*//*Label 4224*/ 125425,
    /*GILLT_nxv4s32*//*Label 4225*/ 125578,
    /*GILLT_nxv4s64*//*Label 4226*/ 125807, 0,
    /*GILLT_nxv8s8*//*Label 4227*/ 125960,
    /*GILLT_nxv8s16*//*Label 4228*/ 126028,
    /*GILLT_nxv8s32*//*Label 4229*/ 126181,
    /*GILLT_nxv8s64*//*Label 4230*/ 126410, 0,
    /*GILLT_nxv16s8*//*Label 4231*/ 126563,
    /*GILLT_nxv16s16*//*Label 4232*/ 126631,
    /*GILLT_nxv16s32*//*Label 4233*/ 126784, 0,
    /*GILLT_nxv32s8*//*Label 4234*/ 126937,
    /*GILLT_nxv32s16*//*Label 4235*/ 127005,
    // Label 4213: @124079
    GIM_Try, /*On fail goto*//*Label 4237*/ 124114, // Rule ID 65392 //
      GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
      // (fp_to_uint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1)  =>  (FCVT_WU_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_WU_D,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/1,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65392,
      GIR_Done,
    // Label 4237: @124114
    GIM_Reject,
    // Label 4214: @124115
    GIM_Try, /*On fail goto*//*Label 4238*/ 124150, // Rule ID 65420 //
      GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
      // (fp_to_uint:{ *:[i64] } FPR64:{ *:[f64] }:$rs1)  =>  (FCVT_LU_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_LU_D,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/1,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65420,
      GIR_Done,
    // Label 4238: @124150
    GIM_Reject,
    // Label 4215: @124151
    GIM_Try, /*On fail goto*//*Label 4239*/ 124218,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4240*/ 124191, // Rule ID 64402 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_uint:{ *:[nxv1i8] } VR:{ *:[nxv1f16] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1f16] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64402,
        GIR_Done,
      // Label 4240: @124191
      GIM_Try, /*On fail goto*//*Label 4241*/ 124217, // Rule ID 64403 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_uint:{ *:[nxv1i8] } VR:{ *:[nxv1f16] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1f16] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64403,
        GIR_Done,
      // Label 4241: @124217
      GIM_Reject,
    // Label 4239: @124218
    GIM_Reject,
    // Label 4216: @124219
    GIM_Try, /*On fail goto*//*Label 4242*/ 124257, // Rule ID 64176 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv1i16] } VR:{ *:[nxv1f16] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64176,
      GIR_Done,
    // Label 4242: @124257
    GIM_Try, /*On fail goto*//*Label 4243*/ 124295, // Rule ID 64177 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv1i16] } VR:{ *:[nxv1f16] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64177,
      GIR_Done,
    // Label 4243: @124295
    GIM_Try, /*On fail goto*//*Label 4244*/ 124333, // Rule ID 64416 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv1i16] } VR:{ *:[nxv1f32] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1f32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64416,
      GIR_Done,
    // Label 4244: @124333
    GIM_Try, /*On fail goto*//*Label 4245*/ 124371, // Rule ID 64417 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv1i16] } VR:{ *:[nxv1f32] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1f32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64417,
      GIR_Done,
    // Label 4245: @124371
    GIM_Reject,
    // Label 4217: @124372
    GIM_Try, /*On fail goto*//*Label 4246*/ 124410, // Rule ID 64180 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv1i32] } VR:{ *:[nxv1f32] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64180,
      GIR_Done,
    // Label 4246: @124410
    GIM_Try, /*On fail goto*//*Label 4247*/ 124448, // Rule ID 64181 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv1i32] } VR:{ *:[nxv1f32] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64181,
      GIR_Done,
    // Label 4247: @124448
    GIM_Try, /*On fail goto*//*Label 4248*/ 124486, // Rule ID 64290 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv1i32] } VR:{ *:[nxv1f16] }:$rs1)  =>  (PseudoVFWCVT_RTZ_XU_F_V_MF4:{ *:[nxv1i32] } VR:{ *:[nxv1f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_XU_F_V_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64290,
      GIR_Done,
    // Label 4248: @124486
    GIM_Try, /*On fail goto*//*Label 4249*/ 124524, // Rule ID 64291 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv1i32] } VR:{ *:[nxv1f16] }:$rs1)  =>  (PseudoVFWCVT_RTZ_XU_F_V_MF4:{ *:[nxv1i32] } VR:{ *:[nxv1f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_XU_F_V_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64291,
      GIR_Done,
    // Label 4249: @124524
    GIM_Try, /*On fail goto*//*Label 4250*/ 124562, // Rule ID 64428 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv1i32] } VR:{ *:[nxv1f64] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1f64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64428,
      GIR_Done,
    // Label 4250: @124562
    GIM_Try, /*On fail goto*//*Label 4251*/ 124600, // Rule ID 64429 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv1i32] } VR:{ *:[nxv1f64] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1f64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64429,
      GIR_Done,
    // Label 4251: @124600
    GIM_Reject,
    // Label 4218: @124601
    GIM_Try, /*On fail goto*//*Label 4252*/ 124639, // Rule ID 64188 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv1i64] } VR:{ *:[nxv1f64] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_M1:{ *:[nxv1i64] } VR:{ *:[nxv1f64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64188,
      GIR_Done,
    // Label 4252: @124639
    GIM_Try, /*On fail goto*//*Label 4253*/ 124677, // Rule ID 64189 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv1i64] } VR:{ *:[nxv1f64] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_M1:{ *:[nxv1i64] } VR:{ *:[nxv1f64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64189,
      GIR_Done,
    // Label 4253: @124677
    GIM_Try, /*On fail goto*//*Label 4254*/ 124715, // Rule ID 64300 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv1i64] } VR:{ *:[nxv1f32] }:$rs1)  =>  (PseudoVFWCVT_RTZ_XU_F_V_MF2:{ *:[nxv1i64] } VR:{ *:[nxv1f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_XU_F_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64300,
      GIR_Done,
    // Label 4254: @124715
    GIM_Try, /*On fail goto*//*Label 4255*/ 124753, // Rule ID 64301 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv1i64] } VR:{ *:[nxv1f32] }:$rs1)  =>  (PseudoVFWCVT_RTZ_XU_F_V_MF2:{ *:[nxv1i64] } VR:{ *:[nxv1f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_XU_F_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64301,
      GIR_Done,
    // Label 4255: @124753
    GIM_Reject,
    // Label 4219: @124754
    GIM_Try, /*On fail goto*//*Label 4256*/ 124821,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4257*/ 124794, // Rule ID 64406 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_uint:{ *:[nxv2i8] } VR:{ *:[nxv2f16] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2f16] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64406,
        GIR_Done,
      // Label 4257: @124794
      GIM_Try, /*On fail goto*//*Label 4258*/ 124820, // Rule ID 64407 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_uint:{ *:[nxv2i8] } VR:{ *:[nxv2f16] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2f16] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64407,
        GIR_Done,
      // Label 4258: @124820
      GIM_Reject,
    // Label 4256: @124821
    GIM_Reject,
    // Label 4220: @124822
    GIM_Try, /*On fail goto*//*Label 4259*/ 124860, // Rule ID 64178 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv2i16] } VR:{ *:[nxv2f16] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64178,
      GIR_Done,
    // Label 4259: @124860
    GIM_Try, /*On fail goto*//*Label 4260*/ 124898, // Rule ID 64179 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv2i16] } VR:{ *:[nxv2f16] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64179,
      GIR_Done,
    // Label 4260: @124898
    GIM_Try, /*On fail goto*//*Label 4261*/ 124936, // Rule ID 64418 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv2i16] } VR:{ *:[nxv2f32] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2f32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64418,
      GIR_Done,
    // Label 4261: @124936
    GIM_Try, /*On fail goto*//*Label 4262*/ 124974, // Rule ID 64419 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv2i16] } VR:{ *:[nxv2f32] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2f32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64419,
      GIR_Done,
    // Label 4262: @124974
    GIM_Reject,
    // Label 4221: @124975
    GIM_Try, /*On fail goto*//*Label 4263*/ 125013, // Rule ID 64186 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv2i32] } VR:{ *:[nxv2f32] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_M1:{ *:[nxv2i32] } VR:{ *:[nxv2f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64186,
      GIR_Done,
    // Label 4263: @125013
    GIM_Try, /*On fail goto*//*Label 4264*/ 125051, // Rule ID 64187 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv2i32] } VR:{ *:[nxv2f32] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_M1:{ *:[nxv2i32] } VR:{ *:[nxv2f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64187,
      GIR_Done,
    // Label 4264: @125051
    GIM_Try, /*On fail goto*//*Label 4265*/ 125089, // Rule ID 64292 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv2i32] } VR:{ *:[nxv2f16] }:$rs1)  =>  (PseudoVFWCVT_RTZ_XU_F_V_MF2:{ *:[nxv2i32] } VR:{ *:[nxv2f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_XU_F_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64292,
      GIR_Done,
    // Label 4265: @125089
    GIM_Try, /*On fail goto*//*Label 4266*/ 125127, // Rule ID 64293 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv2i32] } VR:{ *:[nxv2f16] }:$rs1)  =>  (PseudoVFWCVT_RTZ_XU_F_V_MF2:{ *:[nxv2i32] } VR:{ *:[nxv2f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_XU_F_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64293,
      GIR_Done,
    // Label 4266: @125127
    GIM_Try, /*On fail goto*//*Label 4267*/ 125165, // Rule ID 64430 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_uint:{ *:[nxv2i32] } VRM2:{ *:[nxv2f64] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_M1:{ *:[nxv2i32] } VRM2:{ *:[nxv2f64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64430,
      GIR_Done,
    // Label 4267: @125165
    GIM_Try, /*On fail goto*//*Label 4268*/ 125203, // Rule ID 64431 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_uint:{ *:[nxv2i32] } VRM2:{ *:[nxv2f64] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_M1:{ *:[nxv2i32] } VRM2:{ *:[nxv2f64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64431,
      GIR_Done,
    // Label 4268: @125203
    GIM_Reject,
    // Label 4222: @125204
    GIM_Try, /*On fail goto*//*Label 4269*/ 125242, // Rule ID 64202 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_uint:{ *:[nxv2i64] } VRM2:{ *:[nxv2f64] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2f64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64202,
      GIR_Done,
    // Label 4269: @125242
    GIM_Try, /*On fail goto*//*Label 4270*/ 125280, // Rule ID 64203 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_uint:{ *:[nxv2i64] } VRM2:{ *:[nxv2f64] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2f64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64203,
      GIR_Done,
    // Label 4270: @125280
    GIM_Try, /*On fail goto*//*Label 4271*/ 125318, // Rule ID 64302 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv2i64] } VR:{ *:[nxv2f32] }:$rs1)  =>  (PseudoVFWCVT_RTZ_XU_F_V_M1:{ *:[nxv2i64] } VR:{ *:[nxv2f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_XU_F_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64302,
      GIR_Done,
    // Label 4271: @125318
    GIM_Try, /*On fail goto*//*Label 4272*/ 125356, // Rule ID 64303 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv2i64] } VR:{ *:[nxv2f32] }:$rs1)  =>  (PseudoVFWCVT_RTZ_XU_F_V_M1:{ *:[nxv2i64] } VR:{ *:[nxv2f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_XU_F_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64303,
      GIR_Done,
    // Label 4272: @125356
    GIM_Reject,
    // Label 4223: @125357
    GIM_Try, /*On fail goto*//*Label 4273*/ 125424,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4274*/ 125397, // Rule ID 64408 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_uint:{ *:[nxv4i8] } VR:{ *:[nxv4f16] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4f16] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64408,
        GIR_Done,
      // Label 4274: @125397
      GIM_Try, /*On fail goto*//*Label 4275*/ 125423, // Rule ID 64409 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_uint:{ *:[nxv4i8] } VR:{ *:[nxv4f16] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4f16] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64409,
        GIR_Done,
      // Label 4275: @125423
      GIM_Reject,
    // Label 4273: @125424
    GIM_Reject,
    // Label 4224: @125425
    GIM_Try, /*On fail goto*//*Label 4276*/ 125463, // Rule ID 64184 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv4i16] } VR:{ *:[nxv4f16] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_M1:{ *:[nxv4i16] } VR:{ *:[nxv4f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64184,
      GIR_Done,
    // Label 4276: @125463
    GIM_Try, /*On fail goto*//*Label 4277*/ 125501, // Rule ID 64185 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv4i16] } VR:{ *:[nxv4f16] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_M1:{ *:[nxv4i16] } VR:{ *:[nxv4f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64185,
      GIR_Done,
    // Label 4277: @125501
    GIM_Try, /*On fail goto*//*Label 4278*/ 125539, // Rule ID 64420 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_uint:{ *:[nxv4i16] } VRM2:{ *:[nxv4f32] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_M1:{ *:[nxv4i16] } VRM2:{ *:[nxv4f32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64420,
      GIR_Done,
    // Label 4278: @125539
    GIM_Try, /*On fail goto*//*Label 4279*/ 125577, // Rule ID 64421 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_uint:{ *:[nxv4i16] } VRM2:{ *:[nxv4f32] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_M1:{ *:[nxv4i16] } VRM2:{ *:[nxv4f32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64421,
      GIR_Done,
    // Label 4279: @125577
    GIM_Reject,
    // Label 4225: @125578
    GIM_Try, /*On fail goto*//*Label 4280*/ 125616, // Rule ID 64196 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_uint:{ *:[nxv4i32] } VRM2:{ *:[nxv4f32] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64196,
      GIR_Done,
    // Label 4280: @125616
    GIM_Try, /*On fail goto*//*Label 4281*/ 125654, // Rule ID 64197 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_uint:{ *:[nxv4i32] } VRM2:{ *:[nxv4f32] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64197,
      GIR_Done,
    // Label 4281: @125654
    GIM_Try, /*On fail goto*//*Label 4282*/ 125692, // Rule ID 64294 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv4i32] } VR:{ *:[nxv4f16] }:$rs1)  =>  (PseudoVFWCVT_RTZ_XU_F_V_M1:{ *:[nxv4i32] } VR:{ *:[nxv4f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_XU_F_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64294,
      GIR_Done,
    // Label 4282: @125692
    GIM_Try, /*On fail goto*//*Label 4283*/ 125730, // Rule ID 64295 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (fp_to_uint:{ *:[nxv4i32] } VR:{ *:[nxv4f16] }:$rs1)  =>  (PseudoVFWCVT_RTZ_XU_F_V_M1:{ *:[nxv4i32] } VR:{ *:[nxv4f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_XU_F_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64295,
      GIR_Done,
    // Label 4283: @125730
    GIM_Try, /*On fail goto*//*Label 4284*/ 125768, // Rule ID 64432 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_uint:{ *:[nxv4i32] } VRM4:{ *:[nxv4f64] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_M2:{ *:[nxv4i32] } VRM4:{ *:[nxv4f64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64432,
      GIR_Done,
    // Label 4284: @125768
    GIM_Try, /*On fail goto*//*Label 4285*/ 125806, // Rule ID 64433 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_uint:{ *:[nxv4i32] } VRM4:{ *:[nxv4f64] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_M2:{ *:[nxv4i32] } VRM4:{ *:[nxv4f64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64433,
      GIR_Done,
    // Label 4285: @125806
    GIM_Reject,
    // Label 4226: @125807
    GIM_Try, /*On fail goto*//*Label 4286*/ 125845, // Rule ID 64204 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_uint:{ *:[nxv4i64] } VRM4:{ *:[nxv4f64] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4f64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64204,
      GIR_Done,
    // Label 4286: @125845
    GIM_Try, /*On fail goto*//*Label 4287*/ 125883, // Rule ID 64205 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_uint:{ *:[nxv4i64] } VRM4:{ *:[nxv4f64] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4f64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64205,
      GIR_Done,
    // Label 4287: @125883
    GIM_Try, /*On fail goto*//*Label 4288*/ 125921, // Rule ID 64306 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_uint:{ *:[nxv4i64] } VRM2:{ *:[nxv4f32] }:$rs1)  =>  (PseudoVFWCVT_RTZ_XU_F_V_M2:{ *:[nxv4i64] } VRM2:{ *:[nxv4f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_XU_F_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64306,
      GIR_Done,
    // Label 4288: @125921
    GIM_Try, /*On fail goto*//*Label 4289*/ 125959, // Rule ID 64307 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_uint:{ *:[nxv4i64] } VRM2:{ *:[nxv4f32] }:$rs1)  =>  (PseudoVFWCVT_RTZ_XU_F_V_M2:{ *:[nxv4i64] } VRM2:{ *:[nxv4f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_XU_F_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64307,
      GIR_Done,
    // Label 4289: @125959
    GIM_Reject,
    // Label 4227: @125960
    GIM_Try, /*On fail goto*//*Label 4290*/ 126027,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4291*/ 126000, // Rule ID 64410 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_uint:{ *:[nxv8i8] } VRM2:{ *:[nxv8f16] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_M1:{ *:[nxv8i8] } VRM2:{ *:[nxv8f16] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64410,
        GIR_Done,
      // Label 4291: @126000
      GIM_Try, /*On fail goto*//*Label 4292*/ 126026, // Rule ID 64411 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_uint:{ *:[nxv8i8] } VRM2:{ *:[nxv8f16] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_M1:{ *:[nxv8i8] } VRM2:{ *:[nxv8f16] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64411,
        GIR_Done,
      // Label 4292: @126026
      GIM_Reject,
    // Label 4290: @126027
    GIM_Reject,
    // Label 4228: @126028
    GIM_Try, /*On fail goto*//*Label 4293*/ 126066, // Rule ID 64190 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_uint:{ *:[nxv8i16] } VRM2:{ *:[nxv8f16] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64190,
      GIR_Done,
    // Label 4293: @126066
    GIM_Try, /*On fail goto*//*Label 4294*/ 126104, // Rule ID 64191 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_uint:{ *:[nxv8i16] } VRM2:{ *:[nxv8f16] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64191,
      GIR_Done,
    // Label 4294: @126104
    GIM_Try, /*On fail goto*//*Label 4295*/ 126142, // Rule ID 64422 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_uint:{ *:[nxv8i16] } VRM4:{ *:[nxv8f32] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_M2:{ *:[nxv8i16] } VRM4:{ *:[nxv8f32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64422,
      GIR_Done,
    // Label 4295: @126142
    GIM_Try, /*On fail goto*//*Label 4296*/ 126180, // Rule ID 64423 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_uint:{ *:[nxv8i16] } VRM4:{ *:[nxv8f32] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_M2:{ *:[nxv8i16] } VRM4:{ *:[nxv8f32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64423,
      GIR_Done,
    // Label 4296: @126180
    GIM_Reject,
    // Label 4229: @126181
    GIM_Try, /*On fail goto*//*Label 4297*/ 126219, // Rule ID 64198 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_uint:{ *:[nxv8i32] } VRM4:{ *:[nxv8f32] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64198,
      GIR_Done,
    // Label 4297: @126219
    GIM_Try, /*On fail goto*//*Label 4298*/ 126257, // Rule ID 64199 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_uint:{ *:[nxv8i32] } VRM4:{ *:[nxv8f32] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64199,
      GIR_Done,
    // Label 4298: @126257
    GIM_Try, /*On fail goto*//*Label 4299*/ 126295, // Rule ID 64296 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_uint:{ *:[nxv8i32] } VRM2:{ *:[nxv8f16] }:$rs1)  =>  (PseudoVFWCVT_RTZ_XU_F_V_M2:{ *:[nxv8i32] } VRM2:{ *:[nxv8f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_XU_F_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64296,
      GIR_Done,
    // Label 4299: @126295
    GIM_Try, /*On fail goto*//*Label 4300*/ 126333, // Rule ID 64297 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (fp_to_uint:{ *:[nxv8i32] } VRM2:{ *:[nxv8f16] }:$rs1)  =>  (PseudoVFWCVT_RTZ_XU_F_V_M2:{ *:[nxv8i32] } VRM2:{ *:[nxv8f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_XU_F_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64297,
      GIR_Done,
    // Label 4300: @126333
    GIM_Try, /*On fail goto*//*Label 4301*/ 126371, // Rule ID 64434 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (fp_to_uint:{ *:[nxv8i32] } VRM8:{ *:[nxv8f64] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_M4:{ *:[nxv8i32] } VRM8:{ *:[nxv8f64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64434,
      GIR_Done,
    // Label 4301: @126371
    GIM_Try, /*On fail goto*//*Label 4302*/ 126409, // Rule ID 64435 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (fp_to_uint:{ *:[nxv8i32] } VRM8:{ *:[nxv8f64] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_M4:{ *:[nxv8i32] } VRM8:{ *:[nxv8f64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64435,
      GIR_Done,
    // Label 4302: @126409
    GIM_Reject,
    // Label 4230: @126410
    GIM_Try, /*On fail goto*//*Label 4303*/ 126448, // Rule ID 64206 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (fp_to_uint:{ *:[nxv8i64] } VRM8:{ *:[nxv8f64] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8f64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64206,
      GIR_Done,
    // Label 4303: @126448
    GIM_Try, /*On fail goto*//*Label 4304*/ 126486, // Rule ID 64207 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (fp_to_uint:{ *:[nxv8i64] } VRM8:{ *:[nxv8f64] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8f64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64207,
      GIR_Done,
    // Label 4304: @126486
    GIM_Try, /*On fail goto*//*Label 4305*/ 126524, // Rule ID 64308 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_uint:{ *:[nxv8i64] } VRM4:{ *:[nxv8f32] }:$rs1)  =>  (PseudoVFWCVT_RTZ_XU_F_V_M4:{ *:[nxv8i64] } VRM4:{ *:[nxv8f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_XU_F_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64308,
      GIR_Done,
    // Label 4305: @126524
    GIM_Try, /*On fail goto*//*Label 4306*/ 126562, // Rule ID 64309 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_uint:{ *:[nxv8i64] } VRM4:{ *:[nxv8f32] }:$rs1)  =>  (PseudoVFWCVT_RTZ_XU_F_V_M4:{ *:[nxv8i64] } VRM4:{ *:[nxv8f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_XU_F_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64309,
      GIR_Done,
    // Label 4306: @126562
    GIM_Reject,
    // Label 4231: @126563
    GIM_Try, /*On fail goto*//*Label 4307*/ 126630,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4308*/ 126603, // Rule ID 64412 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_uint:{ *:[nxv16i8] } VRM4:{ *:[nxv16f16] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_M2:{ *:[nxv16i8] } VRM4:{ *:[nxv16f16] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64412,
        GIR_Done,
      // Label 4308: @126603
      GIM_Try, /*On fail goto*//*Label 4309*/ 126629, // Rule ID 64413 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_uint:{ *:[nxv16i8] } VRM4:{ *:[nxv16f16] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_M2:{ *:[nxv16i8] } VRM4:{ *:[nxv16f16] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64413,
        GIR_Done,
      // Label 4309: @126629
      GIM_Reject,
    // Label 4307: @126630
    GIM_Reject,
    // Label 4232: @126631
    GIM_Try, /*On fail goto*//*Label 4310*/ 126669, // Rule ID 64192 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_uint:{ *:[nxv16i16] } VRM4:{ *:[nxv16f16] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64192,
      GIR_Done,
    // Label 4310: @126669
    GIM_Try, /*On fail goto*//*Label 4311*/ 126707, // Rule ID 64193 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_uint:{ *:[nxv16i16] } VRM4:{ *:[nxv16f16] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64193,
      GIR_Done,
    // Label 4311: @126707
    GIM_Try, /*On fail goto*//*Label 4312*/ 126745, // Rule ID 64424 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (fp_to_uint:{ *:[nxv16i16] } VRM8:{ *:[nxv16f32] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_M4:{ *:[nxv16i16] } VRM8:{ *:[nxv16f32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64424,
      GIR_Done,
    // Label 4312: @126745
    GIM_Try, /*On fail goto*//*Label 4313*/ 126783, // Rule ID 64425 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (fp_to_uint:{ *:[nxv16i16] } VRM8:{ *:[nxv16f32] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_M4:{ *:[nxv16i16] } VRM8:{ *:[nxv16f32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64425,
      GIR_Done,
    // Label 4313: @126783
    GIM_Reject,
    // Label 4233: @126784
    GIM_Try, /*On fail goto*//*Label 4314*/ 126822, // Rule ID 64200 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (fp_to_uint:{ *:[nxv16i32] } VRM8:{ *:[nxv16f32] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16f32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64200,
      GIR_Done,
    // Label 4314: @126822
    GIM_Try, /*On fail goto*//*Label 4315*/ 126860, // Rule ID 64201 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (fp_to_uint:{ *:[nxv16i32] } VRM8:{ *:[nxv16f32] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16f32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64201,
      GIR_Done,
    // Label 4315: @126860
    GIM_Try, /*On fail goto*//*Label 4316*/ 126898, // Rule ID 64298 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_uint:{ *:[nxv16i32] } VRM4:{ *:[nxv16f16] }:$rs1)  =>  (PseudoVFWCVT_RTZ_XU_F_V_M4:{ *:[nxv16i32] } VRM4:{ *:[nxv16f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_XU_F_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64298,
      GIR_Done,
    // Label 4316: @126898
    GIM_Try, /*On fail goto*//*Label 4317*/ 126936, // Rule ID 64299 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (fp_to_uint:{ *:[nxv16i32] } VRM4:{ *:[nxv16f16] }:$rs1)  =>  (PseudoVFWCVT_RTZ_XU_F_V_M4:{ *:[nxv16i32] } VRM4:{ *:[nxv16f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_RTZ_XU_F_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64299,
      GIR_Done,
    // Label 4317: @126936
    GIM_Reject,
    // Label 4234: @126937
    GIM_Try, /*On fail goto*//*Label 4318*/ 127004,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4319*/ 126977, // Rule ID 64414 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_uint:{ *:[nxv32i8] } VRM8:{ *:[nxv32f16] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_M4:{ *:[nxv32i8] } VRM8:{ *:[nxv32f16] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64414,
        GIR_Done,
      // Label 4319: @126977
      GIM_Try, /*On fail goto*//*Label 4320*/ 127003, // Rule ID 64415 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_uint:{ *:[nxv32i8] } VRM8:{ *:[nxv32f16] }:$rs1)  =>  (PseudoVFNCVT_RTZ_XU_F_W_M4:{ *:[nxv32i8] } VRM8:{ *:[nxv32f16] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_RTZ_XU_F_W_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64415,
        GIR_Done,
      // Label 4320: @127003
      GIM_Reject,
    // Label 4318: @127004
    GIM_Reject,
    // Label 4235: @127005
    GIM_Try, /*On fail goto*//*Label 4321*/ 127072,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4322*/ 127045, // Rule ID 64194 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_uint:{ *:[nxv32i16] } VRM8:{ *:[nxv32f16] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32f16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64194,
        GIR_Done,
      // Label 4322: @127045
      GIM_Try, /*On fail goto*//*Label 4323*/ 127071, // Rule ID 64195 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fp_to_uint:{ *:[nxv32i16] } VRM8:{ *:[nxv32f16] }:$rs1)  =>  (PseudoVFCVT_RTZ_XU_F_V_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32f16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_RTZ_XU_F_V_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64195,
        GIR_Done,
      // Label 4323: @127071
      GIM_Reject,
    // Label 4321: @127072
    GIM_Reject,
    // Label 4236: @127073
    GIM_Reject,
    // Label 55: @127074
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 30, /*)*//*default:*//*Label 4340*/ 130146,
    /*GILLT_s64*//*Label 4324*/ 127108, 0, 0,
    /*GILLT_nxv1s16*//*Label 4325*/ 127167,
    /*GILLT_nxv1s32*//*Label 4326*/ 127396,
    /*GILLT_nxv1s64*//*Label 4327*/ 127625, 0, 0,
    /*GILLT_nxv2s16*//*Label 4328*/ 127778,
    /*GILLT_nxv2s32*//*Label 4329*/ 128007,
    /*GILLT_nxv2s64*//*Label 4330*/ 128236, 0, 0,
    /*GILLT_nxv4s16*//*Label 4331*/ 128389,
    /*GILLT_nxv4s32*//*Label 4332*/ 128618,
    /*GILLT_nxv4s64*//*Label 4333*/ 128847, 0, 0,
    /*GILLT_nxv8s16*//*Label 4334*/ 129000,
    /*GILLT_nxv8s32*//*Label 4335*/ 129229,
    /*GILLT_nxv8s64*//*Label 4336*/ 129458, 0, 0,
    /*GILLT_nxv16s16*//*Label 4337*/ 129611,
    /*GILLT_nxv16s32*//*Label 4338*/ 129840, 0, 0,
    /*GILLT_nxv32s16*//*Label 4339*/ 129993,
    // Label 4324: @127108
    GIM_Try, /*On fail goto*//*Label 4341*/ 127131, // Rule ID 65400 //
      GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1)  =>  (FCVT_D_W:{ *:[f64] } GPR:{ *:[i32] }:$rs1)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FCVT_D_W,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65400,
      GIR_Done,
    // Label 4341: @127131
    GIM_Try, /*On fail goto*//*Label 4342*/ 127166, // Rule ID 65430 //
      GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      // (sint_to_fp:{ *:[f64] } GPR:{ *:[i64] }:$rs1)  =>  (FCVT_D_L:{ *:[f64] } GPR:{ *:[i64] }:$rs1, 7:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_D_L,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/7,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65430,
      GIR_Done,
    // Label 4342: @127166
    GIM_Reject,
    // Label 4325: @127167
    GIM_Try, /*On fail goto*//*Label 4343*/ 127205, // Rule ID 54969 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv1f16] } VR:{ *:[nxv1i16] }:$rs1)  =>  (PseudoVFCVT_F_X_V_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 54969,
      GIR_Done,
    // Label 4343: @127205
    GIM_Try, /*On fail goto*//*Label 4344*/ 127243, // Rule ID 54970 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv1f16] } VR:{ *:[nxv1i16] }:$rs1)  =>  (PseudoVFCVT_F_X_V_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 54970,
      GIR_Done,
    // Label 4344: @127243
    GIM_Try, /*On fail goto*//*Label 4345*/ 127281, // Rule ID 54973 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv1f16] } VR:{ *:[nxv1i8] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_MF8:{ *:[nxv1f16] } VR:{ *:[nxv1i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_MF8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 54973,
      GIR_Done,
    // Label 4345: @127281
    GIM_Try, /*On fail goto*//*Label 4346*/ 127319, // Rule ID 54974 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv1f16] } VR:{ *:[nxv1i8] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_MF8:{ *:[nxv1f16] } VR:{ *:[nxv1i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_MF8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 54974,
      GIR_Done,
    // Label 4346: @127319
    GIM_Try, /*On fail goto*//*Label 4347*/ 127357, // Rule ID 54977 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv1f16] } VR:{ *:[nxv1i32] }:$rs1)  =>  (PseudoVFNCVT_F_X_W_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1i32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_X_W_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 54977,
      GIR_Done,
    // Label 4347: @127357
    GIM_Try, /*On fail goto*//*Label 4348*/ 127395, // Rule ID 54978 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv1f16] } VR:{ *:[nxv1i32] }:$rs1)  =>  (PseudoVFNCVT_F_X_W_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_X_W_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 54978,
      GIR_Done,
    // Label 4348: @127395
    GIM_Reject,
    // Label 4326: @127396
    GIM_Try, /*On fail goto*//*Label 4349*/ 127434, // Rule ID 64210 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv1f32] } VR:{ *:[nxv1i32] }:$rs1)  =>  (PseudoVFCVT_F_X_V_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64210,
      GIR_Done,
    // Label 4349: @127434
    GIM_Try, /*On fail goto*//*Label 4350*/ 127472, // Rule ID 64211 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv1f32] } VR:{ *:[nxv1i32] }:$rs1)  =>  (PseudoVFCVT_F_X_V_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64211,
      GIR_Done,
    // Label 4350: @127472
    GIM_Try, /*On fail goto*//*Label 4351*/ 127510, // Rule ID 64320 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv1f32] } VR:{ *:[nxv1i16] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_MF4:{ *:[nxv1f32] } VR:{ *:[nxv1i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64320,
      GIR_Done,
    // Label 4351: @127510
    GIM_Try, /*On fail goto*//*Label 4352*/ 127548, // Rule ID 64321 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv1f32] } VR:{ *:[nxv1i16] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_MF4:{ *:[nxv1f32] } VR:{ *:[nxv1i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64321,
      GIR_Done,
    // Label 4352: @127548
    GIM_Try, /*On fail goto*//*Label 4353*/ 127586, // Rule ID 64444 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv1f32] } VR:{ *:[nxv1i64] }:$rs1)  =>  (PseudoVFNCVT_F_X_W_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1i64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_X_W_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64444,
      GIR_Done,
    // Label 4353: @127586
    GIM_Try, /*On fail goto*//*Label 4354*/ 127624, // Rule ID 64445 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv1f32] } VR:{ *:[nxv1i64] }:$rs1)  =>  (PseudoVFNCVT_F_X_W_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1i64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_X_W_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64445,
      GIR_Done,
    // Label 4354: @127624
    GIM_Reject,
    // Label 4327: @127625
    GIM_Try, /*On fail goto*//*Label 4355*/ 127663, // Rule ID 64216 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv1f64] } VR:{ *:[nxv1i64] }:$rs1)  =>  (PseudoVFCVT_F_X_V_M1:{ *:[nxv1f64] } VR:{ *:[nxv1i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64216,
      GIR_Done,
    // Label 4355: @127663
    GIM_Try, /*On fail goto*//*Label 4356*/ 127701, // Rule ID 64217 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv1f64] } VR:{ *:[nxv1i64] }:$rs1)  =>  (PseudoVFCVT_F_X_V_M1:{ *:[nxv1f64] } VR:{ *:[nxv1i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64217,
      GIR_Done,
    // Label 4356: @127701
    GIM_Try, /*On fail goto*//*Label 4357*/ 127739, // Rule ID 64330 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv1f64] } VR:{ *:[nxv1i32] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_MF2:{ *:[nxv1f64] } VR:{ *:[nxv1i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64330,
      GIR_Done,
    // Label 4357: @127739
    GIM_Try, /*On fail goto*//*Label 4358*/ 127777, // Rule ID 64331 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv1f64] } VR:{ *:[nxv1i32] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_MF2:{ *:[nxv1f64] } VR:{ *:[nxv1i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64331,
      GIR_Done,
    // Label 4358: @127777
    GIM_Reject,
    // Label 4328: @127778
    GIM_Try, /*On fail goto*//*Label 4359*/ 127816, // Rule ID 64208 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv2f16] } VR:{ *:[nxv2i16] }:$rs1)  =>  (PseudoVFCVT_F_X_V_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64208,
      GIR_Done,
    // Label 4359: @127816
    GIM_Try, /*On fail goto*//*Label 4360*/ 127854, // Rule ID 64209 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv2f16] } VR:{ *:[nxv2i16] }:$rs1)  =>  (PseudoVFCVT_F_X_V_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64209,
      GIR_Done,
    // Label 4360: @127854
    GIM_Try, /*On fail goto*//*Label 4361*/ 127892, // Rule ID 64310 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv2f16] } VR:{ *:[nxv2i8] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_MF4:{ *:[nxv2f16] } VR:{ *:[nxv2i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64310,
      GIR_Done,
    // Label 4361: @127892
    GIM_Try, /*On fail goto*//*Label 4362*/ 127930, // Rule ID 64311 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv2f16] } VR:{ *:[nxv2i8] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_MF4:{ *:[nxv2f16] } VR:{ *:[nxv2i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64311,
      GIR_Done,
    // Label 4362: @127930
    GIM_Try, /*On fail goto*//*Label 4363*/ 127968, // Rule ID 64436 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv2f16] } VR:{ *:[nxv2i32] }:$rs1)  =>  (PseudoVFNCVT_F_X_W_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2i32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_X_W_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64436,
      GIR_Done,
    // Label 4363: @127968
    GIM_Try, /*On fail goto*//*Label 4364*/ 128006, // Rule ID 64437 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv2f16] } VR:{ *:[nxv2i32] }:$rs1)  =>  (PseudoVFNCVT_F_X_W_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_X_W_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64437,
      GIR_Done,
    // Label 4364: @128006
    GIM_Reject,
    // Label 4329: @128007
    GIM_Try, /*On fail goto*//*Label 4365*/ 128045, // Rule ID 64214 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv2f32] } VR:{ *:[nxv2i32] }:$rs1)  =>  (PseudoVFCVT_F_X_V_M1:{ *:[nxv2f32] } VR:{ *:[nxv2i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64214,
      GIR_Done,
    // Label 4365: @128045
    GIM_Try, /*On fail goto*//*Label 4366*/ 128083, // Rule ID 64215 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv2f32] } VR:{ *:[nxv2i32] }:$rs1)  =>  (PseudoVFCVT_F_X_V_M1:{ *:[nxv2f32] } VR:{ *:[nxv2i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64215,
      GIR_Done,
    // Label 4366: @128083
    GIM_Try, /*On fail goto*//*Label 4367*/ 128121, // Rule ID 64322 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv2f32] } VR:{ *:[nxv2i16] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_MF2:{ *:[nxv2f32] } VR:{ *:[nxv2i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64322,
      GIR_Done,
    // Label 4367: @128121
    GIM_Try, /*On fail goto*//*Label 4368*/ 128159, // Rule ID 64323 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv2f32] } VR:{ *:[nxv2i16] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_MF2:{ *:[nxv2f32] } VR:{ *:[nxv2i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64323,
      GIR_Done,
    // Label 4368: @128159
    GIM_Try, /*On fail goto*//*Label 4369*/ 128197, // Rule ID 64446 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (sint_to_fp:{ *:[nxv2f32] } VRM2:{ *:[nxv2i64] }:$rs1)  =>  (PseudoVFNCVT_F_X_W_M1:{ *:[nxv2f32] } VRM2:{ *:[nxv2i64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_X_W_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64446,
      GIR_Done,
    // Label 4369: @128197
    GIM_Try, /*On fail goto*//*Label 4370*/ 128235, // Rule ID 64447 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (sint_to_fp:{ *:[nxv2f32] } VRM2:{ *:[nxv2i64] }:$rs1)  =>  (PseudoVFNCVT_F_X_W_M1:{ *:[nxv2f32] } VRM2:{ *:[nxv2i64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_X_W_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64447,
      GIR_Done,
    // Label 4370: @128235
    GIM_Reject,
    // Label 4330: @128236
    GIM_Try, /*On fail goto*//*Label 4371*/ 128274, // Rule ID 64232 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (sint_to_fp:{ *:[nxv2f64] } VRM2:{ *:[nxv2i64] }:$rs1)  =>  (PseudoVFCVT_F_X_V_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64232,
      GIR_Done,
    // Label 4371: @128274
    GIM_Try, /*On fail goto*//*Label 4372*/ 128312, // Rule ID 64233 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (sint_to_fp:{ *:[nxv2f64] } VRM2:{ *:[nxv2i64] }:$rs1)  =>  (PseudoVFCVT_F_X_V_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64233,
      GIR_Done,
    // Label 4372: @128312
    GIM_Try, /*On fail goto*//*Label 4373*/ 128350, // Rule ID 64332 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv2f64] } VR:{ *:[nxv2i32] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_M1:{ *:[nxv2f64] } VR:{ *:[nxv2i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64332,
      GIR_Done,
    // Label 4373: @128350
    GIM_Try, /*On fail goto*//*Label 4374*/ 128388, // Rule ID 64333 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv2f64] } VR:{ *:[nxv2i32] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_M1:{ *:[nxv2f64] } VR:{ *:[nxv2i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64333,
      GIR_Done,
    // Label 4374: @128388
    GIM_Reject,
    // Label 4331: @128389
    GIM_Try, /*On fail goto*//*Label 4375*/ 128427, // Rule ID 64212 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv4f16] } VR:{ *:[nxv4i16] }:$rs1)  =>  (PseudoVFCVT_F_X_V_M1:{ *:[nxv4f16] } VR:{ *:[nxv4i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64212,
      GIR_Done,
    // Label 4375: @128427
    GIM_Try, /*On fail goto*//*Label 4376*/ 128465, // Rule ID 64213 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv4f16] } VR:{ *:[nxv4i16] }:$rs1)  =>  (PseudoVFCVT_F_X_V_M1:{ *:[nxv4f16] } VR:{ *:[nxv4i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64213,
      GIR_Done,
    // Label 4376: @128465
    GIM_Try, /*On fail goto*//*Label 4377*/ 128503, // Rule ID 64312 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv4f16] } VR:{ *:[nxv4i8] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_MF2:{ *:[nxv4f16] } VR:{ *:[nxv4i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64312,
      GIR_Done,
    // Label 4377: @128503
    GIM_Try, /*On fail goto*//*Label 4378*/ 128541, // Rule ID 64313 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv4f16] } VR:{ *:[nxv4i8] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_MF2:{ *:[nxv4f16] } VR:{ *:[nxv4i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64313,
      GIR_Done,
    // Label 4378: @128541
    GIM_Try, /*On fail goto*//*Label 4379*/ 128579, // Rule ID 64438 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (sint_to_fp:{ *:[nxv4f16] } VRM2:{ *:[nxv4i32] }:$rs1)  =>  (PseudoVFNCVT_F_X_W_M1:{ *:[nxv4f16] } VRM2:{ *:[nxv4i32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_X_W_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64438,
      GIR_Done,
    // Label 4379: @128579
    GIM_Try, /*On fail goto*//*Label 4380*/ 128617, // Rule ID 64439 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (sint_to_fp:{ *:[nxv4f16] } VRM2:{ *:[nxv4i32] }:$rs1)  =>  (PseudoVFNCVT_F_X_W_M1:{ *:[nxv4f16] } VRM2:{ *:[nxv4i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_X_W_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64439,
      GIR_Done,
    // Label 4380: @128617
    GIM_Reject,
    // Label 4332: @128618
    GIM_Try, /*On fail goto*//*Label 4381*/ 128656, // Rule ID 64226 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (sint_to_fp:{ *:[nxv4f32] } VRM2:{ *:[nxv4i32] }:$rs1)  =>  (PseudoVFCVT_F_X_V_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64226,
      GIR_Done,
    // Label 4381: @128656
    GIM_Try, /*On fail goto*//*Label 4382*/ 128694, // Rule ID 64227 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (sint_to_fp:{ *:[nxv4f32] } VRM2:{ *:[nxv4i32] }:$rs1)  =>  (PseudoVFCVT_F_X_V_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64227,
      GIR_Done,
    // Label 4382: @128694
    GIM_Try, /*On fail goto*//*Label 4383*/ 128732, // Rule ID 64324 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv4f32] } VR:{ *:[nxv4i16] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_M1:{ *:[nxv4f32] } VR:{ *:[nxv4i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64324,
      GIR_Done,
    // Label 4383: @128732
    GIM_Try, /*On fail goto*//*Label 4384*/ 128770, // Rule ID 64325 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv4f32] } VR:{ *:[nxv4i16] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_M1:{ *:[nxv4f32] } VR:{ *:[nxv4i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64325,
      GIR_Done,
    // Label 4384: @128770
    GIM_Try, /*On fail goto*//*Label 4385*/ 128808, // Rule ID 64448 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (sint_to_fp:{ *:[nxv4f32] } VRM4:{ *:[nxv4i64] }:$rs1)  =>  (PseudoVFNCVT_F_X_W_M2:{ *:[nxv4f32] } VRM4:{ *:[nxv4i64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_X_W_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64448,
      GIR_Done,
    // Label 4385: @128808
    GIM_Try, /*On fail goto*//*Label 4386*/ 128846, // Rule ID 64449 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (sint_to_fp:{ *:[nxv4f32] } VRM4:{ *:[nxv4i64] }:$rs1)  =>  (PseudoVFNCVT_F_X_W_M2:{ *:[nxv4f32] } VRM4:{ *:[nxv4i64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_X_W_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64449,
      GIR_Done,
    // Label 4386: @128846
    GIM_Reject,
    // Label 4333: @128847
    GIM_Try, /*On fail goto*//*Label 4387*/ 128885, // Rule ID 64234 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (sint_to_fp:{ *:[nxv4f64] } VRM4:{ *:[nxv4i64] }:$rs1)  =>  (PseudoVFCVT_F_X_V_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64234,
      GIR_Done,
    // Label 4387: @128885
    GIM_Try, /*On fail goto*//*Label 4388*/ 128923, // Rule ID 64235 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (sint_to_fp:{ *:[nxv4f64] } VRM4:{ *:[nxv4i64] }:$rs1)  =>  (PseudoVFCVT_F_X_V_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64235,
      GIR_Done,
    // Label 4388: @128923
    GIM_Try, /*On fail goto*//*Label 4389*/ 128961, // Rule ID 64334 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (sint_to_fp:{ *:[nxv4f64] } VRM2:{ *:[nxv4i32] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_M2:{ *:[nxv4f64] } VRM2:{ *:[nxv4i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64334,
      GIR_Done,
    // Label 4389: @128961
    GIM_Try, /*On fail goto*//*Label 4390*/ 128999, // Rule ID 64335 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (sint_to_fp:{ *:[nxv4f64] } VRM2:{ *:[nxv4i32] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_M2:{ *:[nxv4f64] } VRM2:{ *:[nxv4i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64335,
      GIR_Done,
    // Label 4390: @128999
    GIM_Reject,
    // Label 4334: @129000
    GIM_Try, /*On fail goto*//*Label 4391*/ 129038, // Rule ID 64218 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (sint_to_fp:{ *:[nxv8f16] } VRM2:{ *:[nxv8i16] }:$rs1)  =>  (PseudoVFCVT_F_X_V_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64218,
      GIR_Done,
    // Label 4391: @129038
    GIM_Try, /*On fail goto*//*Label 4392*/ 129076, // Rule ID 64219 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (sint_to_fp:{ *:[nxv8f16] } VRM2:{ *:[nxv8i16] }:$rs1)  =>  (PseudoVFCVT_F_X_V_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64219,
      GIR_Done,
    // Label 4392: @129076
    GIM_Try, /*On fail goto*//*Label 4393*/ 129114, // Rule ID 64314 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv8f16] } VR:{ *:[nxv8i8] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_M1:{ *:[nxv8f16] } VR:{ *:[nxv8i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64314,
      GIR_Done,
    // Label 4393: @129114
    GIM_Try, /*On fail goto*//*Label 4394*/ 129152, // Rule ID 64315 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (sint_to_fp:{ *:[nxv8f16] } VR:{ *:[nxv8i8] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_M1:{ *:[nxv8f16] } VR:{ *:[nxv8i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64315,
      GIR_Done,
    // Label 4394: @129152
    GIM_Try, /*On fail goto*//*Label 4395*/ 129190, // Rule ID 64440 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (sint_to_fp:{ *:[nxv8f16] } VRM4:{ *:[nxv8i32] }:$rs1)  =>  (PseudoVFNCVT_F_X_W_M2:{ *:[nxv8f16] } VRM4:{ *:[nxv8i32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_X_W_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64440,
      GIR_Done,
    // Label 4395: @129190
    GIM_Try, /*On fail goto*//*Label 4396*/ 129228, // Rule ID 64441 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (sint_to_fp:{ *:[nxv8f16] } VRM4:{ *:[nxv8i32] }:$rs1)  =>  (PseudoVFNCVT_F_X_W_M2:{ *:[nxv8f16] } VRM4:{ *:[nxv8i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_X_W_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64441,
      GIR_Done,
    // Label 4396: @129228
    GIM_Reject,
    // Label 4335: @129229
    GIM_Try, /*On fail goto*//*Label 4397*/ 129267, // Rule ID 64228 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (sint_to_fp:{ *:[nxv8f32] } VRM4:{ *:[nxv8i32] }:$rs1)  =>  (PseudoVFCVT_F_X_V_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64228,
      GIR_Done,
    // Label 4397: @129267
    GIM_Try, /*On fail goto*//*Label 4398*/ 129305, // Rule ID 64229 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (sint_to_fp:{ *:[nxv8f32] } VRM4:{ *:[nxv8i32] }:$rs1)  =>  (PseudoVFCVT_F_X_V_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64229,
      GIR_Done,
    // Label 4398: @129305
    GIM_Try, /*On fail goto*//*Label 4399*/ 129343, // Rule ID 64326 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (sint_to_fp:{ *:[nxv8f32] } VRM2:{ *:[nxv8i16] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_M2:{ *:[nxv8f32] } VRM2:{ *:[nxv8i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64326,
      GIR_Done,
    // Label 4399: @129343
    GIM_Try, /*On fail goto*//*Label 4400*/ 129381, // Rule ID 64327 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (sint_to_fp:{ *:[nxv8f32] } VRM2:{ *:[nxv8i16] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_M2:{ *:[nxv8f32] } VRM2:{ *:[nxv8i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64327,
      GIR_Done,
    // Label 4400: @129381
    GIM_Try, /*On fail goto*//*Label 4401*/ 129419, // Rule ID 64450 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (sint_to_fp:{ *:[nxv8f32] } VRM8:{ *:[nxv8i64] }:$rs1)  =>  (PseudoVFNCVT_F_X_W_M4:{ *:[nxv8f32] } VRM8:{ *:[nxv8i64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_X_W_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64450,
      GIR_Done,
    // Label 4401: @129419
    GIM_Try, /*On fail goto*//*Label 4402*/ 129457, // Rule ID 64451 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (sint_to_fp:{ *:[nxv8f32] } VRM8:{ *:[nxv8i64] }:$rs1)  =>  (PseudoVFNCVT_F_X_W_M4:{ *:[nxv8f32] } VRM8:{ *:[nxv8i64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_X_W_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64451,
      GIR_Done,
    // Label 4402: @129457
    GIM_Reject,
    // Label 4336: @129458
    GIM_Try, /*On fail goto*//*Label 4403*/ 129496, // Rule ID 64236 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (sint_to_fp:{ *:[nxv8f64] } VRM8:{ *:[nxv8i64] }:$rs1)  =>  (PseudoVFCVT_F_X_V_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64236,
      GIR_Done,
    // Label 4403: @129496
    GIM_Try, /*On fail goto*//*Label 4404*/ 129534, // Rule ID 64237 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (sint_to_fp:{ *:[nxv8f64] } VRM8:{ *:[nxv8i64] }:$rs1)  =>  (PseudoVFCVT_F_X_V_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64237,
      GIR_Done,
    // Label 4404: @129534
    GIM_Try, /*On fail goto*//*Label 4405*/ 129572, // Rule ID 64336 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (sint_to_fp:{ *:[nxv8f64] } VRM4:{ *:[nxv8i32] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_M4:{ *:[nxv8f64] } VRM4:{ *:[nxv8i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64336,
      GIR_Done,
    // Label 4405: @129572
    GIM_Try, /*On fail goto*//*Label 4406*/ 129610, // Rule ID 64337 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (sint_to_fp:{ *:[nxv8f64] } VRM4:{ *:[nxv8i32] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_M4:{ *:[nxv8f64] } VRM4:{ *:[nxv8i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64337,
      GIR_Done,
    // Label 4406: @129610
    GIM_Reject,
    // Label 4337: @129611
    GIM_Try, /*On fail goto*//*Label 4407*/ 129649, // Rule ID 64220 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (sint_to_fp:{ *:[nxv16f16] } VRM4:{ *:[nxv16i16] }:$rs1)  =>  (PseudoVFCVT_F_X_V_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64220,
      GIR_Done,
    // Label 4407: @129649
    GIM_Try, /*On fail goto*//*Label 4408*/ 129687, // Rule ID 64221 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (sint_to_fp:{ *:[nxv16f16] } VRM4:{ *:[nxv16i16] }:$rs1)  =>  (PseudoVFCVT_F_X_V_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64221,
      GIR_Done,
    // Label 4408: @129687
    GIM_Try, /*On fail goto*//*Label 4409*/ 129725, // Rule ID 64316 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (sint_to_fp:{ *:[nxv16f16] } VRM2:{ *:[nxv16i8] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_M2:{ *:[nxv16f16] } VRM2:{ *:[nxv16i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64316,
      GIR_Done,
    // Label 4409: @129725
    GIM_Try, /*On fail goto*//*Label 4410*/ 129763, // Rule ID 64317 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (sint_to_fp:{ *:[nxv16f16] } VRM2:{ *:[nxv16i8] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_M2:{ *:[nxv16f16] } VRM2:{ *:[nxv16i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64317,
      GIR_Done,
    // Label 4410: @129763
    GIM_Try, /*On fail goto*//*Label 4411*/ 129801, // Rule ID 64442 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (sint_to_fp:{ *:[nxv16f16] } VRM8:{ *:[nxv16i32] }:$rs1)  =>  (PseudoVFNCVT_F_X_W_M4:{ *:[nxv16f16] } VRM8:{ *:[nxv16i32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_X_W_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64442,
      GIR_Done,
    // Label 4411: @129801
    GIM_Try, /*On fail goto*//*Label 4412*/ 129839, // Rule ID 64443 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (sint_to_fp:{ *:[nxv16f16] } VRM8:{ *:[nxv16i32] }:$rs1)  =>  (PseudoVFNCVT_F_X_W_M4:{ *:[nxv16f16] } VRM8:{ *:[nxv16i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_X_W_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64443,
      GIR_Done,
    // Label 4412: @129839
    GIM_Reject,
    // Label 4338: @129840
    GIM_Try, /*On fail goto*//*Label 4413*/ 129878, // Rule ID 64230 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (sint_to_fp:{ *:[nxv16f32] } VRM8:{ *:[nxv16i32] }:$rs1)  =>  (PseudoVFCVT_F_X_V_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64230,
      GIR_Done,
    // Label 4413: @129878
    GIM_Try, /*On fail goto*//*Label 4414*/ 129916, // Rule ID 64231 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (sint_to_fp:{ *:[nxv16f32] } VRM8:{ *:[nxv16i32] }:$rs1)  =>  (PseudoVFCVT_F_X_V_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64231,
      GIR_Done,
    // Label 4414: @129916
    GIM_Try, /*On fail goto*//*Label 4415*/ 129954, // Rule ID 64328 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (sint_to_fp:{ *:[nxv16f32] } VRM4:{ *:[nxv16i16] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_M4:{ *:[nxv16f32] } VRM4:{ *:[nxv16i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64328,
      GIR_Done,
    // Label 4415: @129954
    GIM_Try, /*On fail goto*//*Label 4416*/ 129992, // Rule ID 64329 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (sint_to_fp:{ *:[nxv16f32] } VRM4:{ *:[nxv16i16] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_M4:{ *:[nxv16f32] } VRM4:{ *:[nxv16i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64329,
      GIR_Done,
    // Label 4416: @129992
    GIM_Reject,
    // Label 4339: @129993
    GIM_Try, /*On fail goto*//*Label 4417*/ 130031, // Rule ID 64224 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (sint_to_fp:{ *:[nxv32f16] } VRM8:{ *:[nxv32i16] }:$rs1)  =>  (PseudoVFCVT_F_X_V_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64224,
      GIR_Done,
    // Label 4417: @130031
    GIM_Try, /*On fail goto*//*Label 4418*/ 130069, // Rule ID 64225 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (sint_to_fp:{ *:[nxv32f16] } VRM8:{ *:[nxv32i16] }:$rs1)  =>  (PseudoVFCVT_F_X_V_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_X_V_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64225,
      GIR_Done,
    // Label 4418: @130069
    GIM_Try, /*On fail goto*//*Label 4419*/ 130107, // Rule ID 64318 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (sint_to_fp:{ *:[nxv32f16] } VRM4:{ *:[nxv32i8] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_M4:{ *:[nxv32f16] } VRM4:{ *:[nxv32i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64318,
      GIR_Done,
    // Label 4419: @130107
    GIM_Try, /*On fail goto*//*Label 4420*/ 130145, // Rule ID 64319 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (sint_to_fp:{ *:[nxv32f16] } VRM4:{ *:[nxv32i8] }:$rs1)  =>  (PseudoVFWCVT_F_X_V_M4:{ *:[nxv32f16] } VRM4:{ *:[nxv32i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_X_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64319,
      GIR_Done,
    // Label 4420: @130145
    GIM_Reject,
    // Label 4340: @130146
    GIM_Reject,
    // Label 56: @130147
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/2, 30, /*)*//*default:*//*Label 4437*/ 133219,
    /*GILLT_s64*//*Label 4421*/ 130181, 0, 0,
    /*GILLT_nxv1s16*//*Label 4422*/ 130240,
    /*GILLT_nxv1s32*//*Label 4423*/ 130469,
    /*GILLT_nxv1s64*//*Label 4424*/ 130698, 0, 0,
    /*GILLT_nxv2s16*//*Label 4425*/ 130851,
    /*GILLT_nxv2s32*//*Label 4426*/ 131080,
    /*GILLT_nxv2s64*//*Label 4427*/ 131309, 0, 0,
    /*GILLT_nxv4s16*//*Label 4428*/ 131462,
    /*GILLT_nxv4s32*//*Label 4429*/ 131691,
    /*GILLT_nxv4s64*//*Label 4430*/ 131920, 0, 0,
    /*GILLT_nxv8s16*//*Label 4431*/ 132073,
    /*GILLT_nxv8s32*//*Label 4432*/ 132302,
    /*GILLT_nxv8s64*//*Label 4433*/ 132531, 0, 0,
    /*GILLT_nxv16s16*//*Label 4434*/ 132684,
    /*GILLT_nxv16s32*//*Label 4435*/ 132913, 0, 0,
    /*GILLT_nxv32s16*//*Label 4436*/ 133066,
    // Label 4421: @130181
    GIM_Try, /*On fail goto*//*Label 4438*/ 130204, // Rule ID 65402 //
      GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1)  =>  (FCVT_D_WU:{ *:[f64] } GPR:{ *:[i32] }:$rs1)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FCVT_D_WU,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65402,
      GIR_Done,
    // Label 4438: @130204
    GIM_Try, /*On fail goto*//*Label 4439*/ 130239, // Rule ID 65432 //
      GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      // (uint_to_fp:{ *:[f64] } GPR:{ *:[i64] }:$rs1)  =>  (FCVT_D_LU:{ *:[f64] } GPR:{ *:[i64] }:$rs1, 7:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_D_LU,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/7,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65432,
      GIR_Done,
    // Label 4439: @130239
    GIM_Reject,
    // Label 4422: @130240
    GIM_Try, /*On fail goto*//*Label 4440*/ 130278, // Rule ID 64238 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv1f16] } VR:{ *:[nxv1i16] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64238,
      GIR_Done,
    // Label 4440: @130278
    GIM_Try, /*On fail goto*//*Label 4441*/ 130316, // Rule ID 64239 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv1f16] } VR:{ *:[nxv1i16] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64239,
      GIR_Done,
    // Label 4441: @130316
    GIM_Try, /*On fail goto*//*Label 4442*/ 130354, // Rule ID 64338 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv1f16] } VR:{ *:[nxv1i8] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_MF8:{ *:[nxv1f16] } VR:{ *:[nxv1i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_MF8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64338,
      GIR_Done,
    // Label 4442: @130354
    GIM_Try, /*On fail goto*//*Label 4443*/ 130392, // Rule ID 64339 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv1f16] } VR:{ *:[nxv1i8] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_MF8:{ *:[nxv1f16] } VR:{ *:[nxv1i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_MF8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64339,
      GIR_Done,
    // Label 4443: @130392
    GIM_Try, /*On fail goto*//*Label 4444*/ 130430, // Rule ID 64452 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv1f16] } VR:{ *:[nxv1i32] }:$rs1)  =>  (PseudoVFNCVT_F_XU_W_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1i32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_XU_W_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64452,
      GIR_Done,
    // Label 4444: @130430
    GIM_Try, /*On fail goto*//*Label 4445*/ 130468, // Rule ID 64453 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv1f16] } VR:{ *:[nxv1i32] }:$rs1)  =>  (PseudoVFNCVT_F_XU_W_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_XU_W_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64453,
      GIR_Done,
    // Label 4445: @130468
    GIM_Reject,
    // Label 4423: @130469
    GIM_Try, /*On fail goto*//*Label 4446*/ 130507, // Rule ID 64244 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv1f32] } VR:{ *:[nxv1i32] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64244,
      GIR_Done,
    // Label 4446: @130507
    GIM_Try, /*On fail goto*//*Label 4447*/ 130545, // Rule ID 64245 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv1f32] } VR:{ *:[nxv1i32] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64245,
      GIR_Done,
    // Label 4447: @130545
    GIM_Try, /*On fail goto*//*Label 4448*/ 130583, // Rule ID 64352 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv1f32] } VR:{ *:[nxv1i16] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_MF4:{ *:[nxv1f32] } VR:{ *:[nxv1i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64352,
      GIR_Done,
    // Label 4448: @130583
    GIM_Try, /*On fail goto*//*Label 4449*/ 130621, // Rule ID 64353 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv1f32] } VR:{ *:[nxv1i16] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_MF4:{ *:[nxv1f32] } VR:{ *:[nxv1i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64353,
      GIR_Done,
    // Label 4449: @130621
    GIM_Try, /*On fail goto*//*Label 4450*/ 130659, // Rule ID 64462 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv1f32] } VR:{ *:[nxv1i64] }:$rs1)  =>  (PseudoVFNCVT_F_XU_W_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1i64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_XU_W_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64462,
      GIR_Done,
    // Label 4450: @130659
    GIM_Try, /*On fail goto*//*Label 4451*/ 130697, // Rule ID 64463 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv1f32] } VR:{ *:[nxv1i64] }:$rs1)  =>  (PseudoVFNCVT_F_XU_W_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1i64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_XU_W_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64463,
      GIR_Done,
    // Label 4451: @130697
    GIM_Reject,
    // Label 4424: @130698
    GIM_Try, /*On fail goto*//*Label 4452*/ 130736, // Rule ID 64250 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv1f64] } VR:{ *:[nxv1i64] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_M1:{ *:[nxv1f64] } VR:{ *:[nxv1i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64250,
      GIR_Done,
    // Label 4452: @130736
    GIM_Try, /*On fail goto*//*Label 4453*/ 130774, // Rule ID 64251 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv1f64] } VR:{ *:[nxv1i64] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_M1:{ *:[nxv1f64] } VR:{ *:[nxv1i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64251,
      GIR_Done,
    // Label 4453: @130774
    GIM_Try, /*On fail goto*//*Label 4454*/ 130812, // Rule ID 64362 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv1f64] } VR:{ *:[nxv1i32] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_MF2:{ *:[nxv1f64] } VR:{ *:[nxv1i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64362,
      GIR_Done,
    // Label 4454: @130812
    GIM_Try, /*On fail goto*//*Label 4455*/ 130850, // Rule ID 64363 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv1f64] } VR:{ *:[nxv1i32] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_MF2:{ *:[nxv1f64] } VR:{ *:[nxv1i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64363,
      GIR_Done,
    // Label 4455: @130850
    GIM_Reject,
    // Label 4425: @130851
    GIM_Try, /*On fail goto*//*Label 4456*/ 130889, // Rule ID 64240 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv2f16] } VR:{ *:[nxv2i16] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64240,
      GIR_Done,
    // Label 4456: @130889
    GIM_Try, /*On fail goto*//*Label 4457*/ 130927, // Rule ID 64241 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv2f16] } VR:{ *:[nxv2i16] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64241,
      GIR_Done,
    // Label 4457: @130927
    GIM_Try, /*On fail goto*//*Label 4458*/ 130965, // Rule ID 64340 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv2f16] } VR:{ *:[nxv2i8] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_MF4:{ *:[nxv2f16] } VR:{ *:[nxv2i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64340,
      GIR_Done,
    // Label 4458: @130965
    GIM_Try, /*On fail goto*//*Label 4459*/ 131003, // Rule ID 64341 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv2f16] } VR:{ *:[nxv2i8] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_MF4:{ *:[nxv2f16] } VR:{ *:[nxv2i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_MF4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64341,
      GIR_Done,
    // Label 4459: @131003
    GIM_Try, /*On fail goto*//*Label 4460*/ 131041, // Rule ID 64454 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv2f16] } VR:{ *:[nxv2i32] }:$rs1)  =>  (PseudoVFNCVT_F_XU_W_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2i32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_XU_W_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64454,
      GIR_Done,
    // Label 4460: @131041
    GIM_Try, /*On fail goto*//*Label 4461*/ 131079, // Rule ID 64455 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv2f16] } VR:{ *:[nxv2i32] }:$rs1)  =>  (PseudoVFNCVT_F_XU_W_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_XU_W_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64455,
      GIR_Done,
    // Label 4461: @131079
    GIM_Reject,
    // Label 4426: @131080
    GIM_Try, /*On fail goto*//*Label 4462*/ 131118, // Rule ID 64248 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv2f32] } VR:{ *:[nxv2i32] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_M1:{ *:[nxv2f32] } VR:{ *:[nxv2i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64248,
      GIR_Done,
    // Label 4462: @131118
    GIM_Try, /*On fail goto*//*Label 4463*/ 131156, // Rule ID 64249 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv2f32] } VR:{ *:[nxv2i32] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_M1:{ *:[nxv2f32] } VR:{ *:[nxv2i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64249,
      GIR_Done,
    // Label 4463: @131156
    GIM_Try, /*On fail goto*//*Label 4464*/ 131194, // Rule ID 64354 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv2f32] } VR:{ *:[nxv2i16] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_MF2:{ *:[nxv2f32] } VR:{ *:[nxv2i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64354,
      GIR_Done,
    // Label 4464: @131194
    GIM_Try, /*On fail goto*//*Label 4465*/ 131232, // Rule ID 64355 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv2f32] } VR:{ *:[nxv2i16] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_MF2:{ *:[nxv2f32] } VR:{ *:[nxv2i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64355,
      GIR_Done,
    // Label 4465: @131232
    GIM_Try, /*On fail goto*//*Label 4466*/ 131270, // Rule ID 64466 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (uint_to_fp:{ *:[nxv2f32] } VRM2:{ *:[nxv2i64] }:$rs1)  =>  (PseudoVFNCVT_F_XU_W_M1:{ *:[nxv2f32] } VRM2:{ *:[nxv2i64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_XU_W_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64466,
      GIR_Done,
    // Label 4466: @131270
    GIM_Try, /*On fail goto*//*Label 4467*/ 131308, // Rule ID 64467 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (uint_to_fp:{ *:[nxv2f32] } VRM2:{ *:[nxv2i64] }:$rs1)  =>  (PseudoVFNCVT_F_XU_W_M1:{ *:[nxv2f32] } VRM2:{ *:[nxv2i64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_XU_W_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64467,
      GIR_Done,
    // Label 4467: @131308
    GIM_Reject,
    // Label 4427: @131309
    GIM_Try, /*On fail goto*//*Label 4468*/ 131347, // Rule ID 64266 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (uint_to_fp:{ *:[nxv2f64] } VRM2:{ *:[nxv2i64] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64266,
      GIR_Done,
    // Label 4468: @131347
    GIM_Try, /*On fail goto*//*Label 4469*/ 131385, // Rule ID 64267 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (uint_to_fp:{ *:[nxv2f64] } VRM2:{ *:[nxv2i64] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64267,
      GIR_Done,
    // Label 4469: @131385
    GIM_Try, /*On fail goto*//*Label 4470*/ 131423, // Rule ID 64366 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv2f64] } VR:{ *:[nxv2i32] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_M1:{ *:[nxv2f64] } VR:{ *:[nxv2i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64366,
      GIR_Done,
    // Label 4470: @131423
    GIM_Try, /*On fail goto*//*Label 4471*/ 131461, // Rule ID 64367 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv2f64] } VR:{ *:[nxv2i32] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_M1:{ *:[nxv2f64] } VR:{ *:[nxv2i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64367,
      GIR_Done,
    // Label 4471: @131461
    GIM_Reject,
    // Label 4428: @131462
    GIM_Try, /*On fail goto*//*Label 4472*/ 131500, // Rule ID 64246 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv4f16] } VR:{ *:[nxv4i16] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_M1:{ *:[nxv4f16] } VR:{ *:[nxv4i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64246,
      GIR_Done,
    // Label 4472: @131500
    GIM_Try, /*On fail goto*//*Label 4473*/ 131538, // Rule ID 64247 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv4f16] } VR:{ *:[nxv4i16] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_M1:{ *:[nxv4f16] } VR:{ *:[nxv4i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64247,
      GIR_Done,
    // Label 4473: @131538
    GIM_Try, /*On fail goto*//*Label 4474*/ 131576, // Rule ID 64344 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv4f16] } VR:{ *:[nxv4i8] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_MF2:{ *:[nxv4f16] } VR:{ *:[nxv4i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64344,
      GIR_Done,
    // Label 4474: @131576
    GIM_Try, /*On fail goto*//*Label 4475*/ 131614, // Rule ID 64345 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv4f16] } VR:{ *:[nxv4i8] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_MF2:{ *:[nxv4f16] } VR:{ *:[nxv4i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_MF2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64345,
      GIR_Done,
    // Label 4475: @131614
    GIM_Try, /*On fail goto*//*Label 4476*/ 131652, // Rule ID 64456 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (uint_to_fp:{ *:[nxv4f16] } VRM2:{ *:[nxv4i32] }:$rs1)  =>  (PseudoVFNCVT_F_XU_W_M1:{ *:[nxv4f16] } VRM2:{ *:[nxv4i32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_XU_W_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64456,
      GIR_Done,
    // Label 4476: @131652
    GIM_Try, /*On fail goto*//*Label 4477*/ 131690, // Rule ID 64457 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (uint_to_fp:{ *:[nxv4f16] } VRM2:{ *:[nxv4i32] }:$rs1)  =>  (PseudoVFNCVT_F_XU_W_M1:{ *:[nxv4f16] } VRM2:{ *:[nxv4i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_XU_W_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64457,
      GIR_Done,
    // Label 4477: @131690
    GIM_Reject,
    // Label 4429: @131691
    GIM_Try, /*On fail goto*//*Label 4478*/ 131729, // Rule ID 64258 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (uint_to_fp:{ *:[nxv4f32] } VRM2:{ *:[nxv4i32] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64258,
      GIR_Done,
    // Label 4478: @131729
    GIM_Try, /*On fail goto*//*Label 4479*/ 131767, // Rule ID 64259 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (uint_to_fp:{ *:[nxv4f32] } VRM2:{ *:[nxv4i32] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64259,
      GIR_Done,
    // Label 4479: @131767
    GIM_Try, /*On fail goto*//*Label 4480*/ 131805, // Rule ID 64356 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv4f32] } VR:{ *:[nxv4i16] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_M1:{ *:[nxv4f32] } VR:{ *:[nxv4i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64356,
      GIR_Done,
    // Label 4480: @131805
    GIM_Try, /*On fail goto*//*Label 4481*/ 131843, // Rule ID 64357 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv4f32] } VR:{ *:[nxv4i16] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_M1:{ *:[nxv4f32] } VR:{ *:[nxv4i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64357,
      GIR_Done,
    // Label 4481: @131843
    GIM_Try, /*On fail goto*//*Label 4482*/ 131881, // Rule ID 64468 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (uint_to_fp:{ *:[nxv4f32] } VRM4:{ *:[nxv4i64] }:$rs1)  =>  (PseudoVFNCVT_F_XU_W_M2:{ *:[nxv4f32] } VRM4:{ *:[nxv4i64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_XU_W_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64468,
      GIR_Done,
    // Label 4482: @131881
    GIM_Try, /*On fail goto*//*Label 4483*/ 131919, // Rule ID 64469 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (uint_to_fp:{ *:[nxv4f32] } VRM4:{ *:[nxv4i64] }:$rs1)  =>  (PseudoVFNCVT_F_XU_W_M2:{ *:[nxv4f32] } VRM4:{ *:[nxv4i64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_XU_W_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64469,
      GIR_Done,
    // Label 4483: @131919
    GIM_Reject,
    // Label 4430: @131920
    GIM_Try, /*On fail goto*//*Label 4484*/ 131958, // Rule ID 64268 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (uint_to_fp:{ *:[nxv4f64] } VRM4:{ *:[nxv4i64] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64268,
      GIR_Done,
    // Label 4484: @131958
    GIM_Try, /*On fail goto*//*Label 4485*/ 131996, // Rule ID 64269 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (uint_to_fp:{ *:[nxv4f64] } VRM4:{ *:[nxv4i64] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64269,
      GIR_Done,
    // Label 4485: @131996
    GIM_Try, /*On fail goto*//*Label 4486*/ 132034, // Rule ID 64368 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (uint_to_fp:{ *:[nxv4f64] } VRM2:{ *:[nxv4i32] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_M2:{ *:[nxv4f64] } VRM2:{ *:[nxv4i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64368,
      GIR_Done,
    // Label 4486: @132034
    GIM_Try, /*On fail goto*//*Label 4487*/ 132072, // Rule ID 64369 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (uint_to_fp:{ *:[nxv4f64] } VRM2:{ *:[nxv4i32] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_M2:{ *:[nxv4f64] } VRM2:{ *:[nxv4i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64369,
      GIR_Done,
    // Label 4487: @132072
    GIM_Reject,
    // Label 4431: @132073
    GIM_Try, /*On fail goto*//*Label 4488*/ 132111, // Rule ID 64252 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (uint_to_fp:{ *:[nxv8f16] } VRM2:{ *:[nxv8i16] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64252,
      GIR_Done,
    // Label 4488: @132111
    GIM_Try, /*On fail goto*//*Label 4489*/ 132149, // Rule ID 64253 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (uint_to_fp:{ *:[nxv8f16] } VRM2:{ *:[nxv8i16] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64253,
      GIR_Done,
    // Label 4489: @132149
    GIM_Try, /*On fail goto*//*Label 4490*/ 132187, // Rule ID 64346 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv8f16] } VR:{ *:[nxv8i8] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_M1:{ *:[nxv8f16] } VR:{ *:[nxv8i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64346,
      GIR_Done,
    // Label 4490: @132187
    GIM_Try, /*On fail goto*//*Label 4491*/ 132225, // Rule ID 64347 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      // (uint_to_fp:{ *:[nxv8f16] } VR:{ *:[nxv8i8] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_M1:{ *:[nxv8f16] } VR:{ *:[nxv8i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_M1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64347,
      GIR_Done,
    // Label 4491: @132225
    GIM_Try, /*On fail goto*//*Label 4492*/ 132263, // Rule ID 64458 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (uint_to_fp:{ *:[nxv8f16] } VRM4:{ *:[nxv8i32] }:$rs1)  =>  (PseudoVFNCVT_F_XU_W_M2:{ *:[nxv8f16] } VRM4:{ *:[nxv8i32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_XU_W_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64458,
      GIR_Done,
    // Label 4492: @132263
    GIM_Try, /*On fail goto*//*Label 4493*/ 132301, // Rule ID 64459 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (uint_to_fp:{ *:[nxv8f16] } VRM4:{ *:[nxv8i32] }:$rs1)  =>  (PseudoVFNCVT_F_XU_W_M2:{ *:[nxv8f16] } VRM4:{ *:[nxv8i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_XU_W_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64459,
      GIR_Done,
    // Label 4493: @132301
    GIM_Reject,
    // Label 4432: @132302
    GIM_Try, /*On fail goto*//*Label 4494*/ 132340, // Rule ID 64260 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (uint_to_fp:{ *:[nxv8f32] } VRM4:{ *:[nxv8i32] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64260,
      GIR_Done,
    // Label 4494: @132340
    GIM_Try, /*On fail goto*//*Label 4495*/ 132378, // Rule ID 64261 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (uint_to_fp:{ *:[nxv8f32] } VRM4:{ *:[nxv8i32] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64261,
      GIR_Done,
    // Label 4495: @132378
    GIM_Try, /*On fail goto*//*Label 4496*/ 132416, // Rule ID 64358 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (uint_to_fp:{ *:[nxv8f32] } VRM2:{ *:[nxv8i16] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_M2:{ *:[nxv8f32] } VRM2:{ *:[nxv8i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64358,
      GIR_Done,
    // Label 4496: @132416
    GIM_Try, /*On fail goto*//*Label 4497*/ 132454, // Rule ID 64359 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (uint_to_fp:{ *:[nxv8f32] } VRM2:{ *:[nxv8i16] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_M2:{ *:[nxv8f32] } VRM2:{ *:[nxv8i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64359,
      GIR_Done,
    // Label 4497: @132454
    GIM_Try, /*On fail goto*//*Label 4498*/ 132492, // Rule ID 64470 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (uint_to_fp:{ *:[nxv8f32] } VRM8:{ *:[nxv8i64] }:$rs1)  =>  (PseudoVFNCVT_F_XU_W_M4:{ *:[nxv8f32] } VRM8:{ *:[nxv8i64] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_XU_W_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64470,
      GIR_Done,
    // Label 4498: @132492
    GIM_Try, /*On fail goto*//*Label 4499*/ 132530, // Rule ID 64471 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (uint_to_fp:{ *:[nxv8f32] } VRM8:{ *:[nxv8i64] }:$rs1)  =>  (PseudoVFNCVT_F_XU_W_M4:{ *:[nxv8f32] } VRM8:{ *:[nxv8i64] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_XU_W_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64471,
      GIR_Done,
    // Label 4499: @132530
    GIM_Reject,
    // Label 4433: @132531
    GIM_Try, /*On fail goto*//*Label 4500*/ 132569, // Rule ID 64270 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (uint_to_fp:{ *:[nxv8f64] } VRM8:{ *:[nxv8i64] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8i64] }:$rs1, -1:{ *:[i64] }, 6:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64270,
      GIR_Done,
    // Label 4500: @132569
    GIM_Try, /*On fail goto*//*Label 4501*/ 132607, // Rule ID 64271 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (uint_to_fp:{ *:[nxv8f64] } VRM8:{ *:[nxv8i64] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8i64] }:$rs1, -1:{ *:[i32] }, 6:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/6,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64271,
      GIR_Done,
    // Label 4501: @132607
    GIM_Try, /*On fail goto*//*Label 4502*/ 132645, // Rule ID 64370 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (uint_to_fp:{ *:[nxv8f64] } VRM4:{ *:[nxv8i32] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_M4:{ *:[nxv8f64] } VRM4:{ *:[nxv8i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64370,
      GIR_Done,
    // Label 4502: @132645
    GIM_Try, /*On fail goto*//*Label 4503*/ 132683, // Rule ID 64371 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (uint_to_fp:{ *:[nxv8f64] } VRM4:{ *:[nxv8i32] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_M4:{ *:[nxv8f64] } VRM4:{ *:[nxv8i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64371,
      GIR_Done,
    // Label 4503: @132683
    GIM_Reject,
    // Label 4434: @132684
    GIM_Try, /*On fail goto*//*Label 4504*/ 132722, // Rule ID 64254 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (uint_to_fp:{ *:[nxv16f16] } VRM4:{ *:[nxv16i16] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64254,
      GIR_Done,
    // Label 4504: @132722
    GIM_Try, /*On fail goto*//*Label 4505*/ 132760, // Rule ID 64255 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (uint_to_fp:{ *:[nxv16f16] } VRM4:{ *:[nxv16i16] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64255,
      GIR_Done,
    // Label 4505: @132760
    GIM_Try, /*On fail goto*//*Label 4506*/ 132798, // Rule ID 64348 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (uint_to_fp:{ *:[nxv16f16] } VRM2:{ *:[nxv16i8] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_M2:{ *:[nxv16f16] } VRM2:{ *:[nxv16i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64348,
      GIR_Done,
    // Label 4506: @132798
    GIM_Try, /*On fail goto*//*Label 4507*/ 132836, // Rule ID 64349 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      // (uint_to_fp:{ *:[nxv16f16] } VRM2:{ *:[nxv16i8] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_M2:{ *:[nxv16f16] } VRM2:{ *:[nxv16i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_M2,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64349,
      GIR_Done,
    // Label 4507: @132836
    GIM_Try, /*On fail goto*//*Label 4508*/ 132874, // Rule ID 64460 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (uint_to_fp:{ *:[nxv16f16] } VRM8:{ *:[nxv16i32] }:$rs1)  =>  (PseudoVFNCVT_F_XU_W_M4:{ *:[nxv16f16] } VRM8:{ *:[nxv16i32] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_XU_W_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64460,
      GIR_Done,
    // Label 4508: @132874
    GIM_Try, /*On fail goto*//*Label 4509*/ 132912, // Rule ID 64461 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (uint_to_fp:{ *:[nxv16f16] } VRM8:{ *:[nxv16i32] }:$rs1)  =>  (PseudoVFNCVT_F_XU_W_M4:{ *:[nxv16f16] } VRM8:{ *:[nxv16i32] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFNCVT_F_XU_W_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64461,
      GIR_Done,
    // Label 4509: @132912
    GIM_Reject,
    // Label 4435: @132913
    GIM_Try, /*On fail goto*//*Label 4510*/ 132951, // Rule ID 64262 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (uint_to_fp:{ *:[nxv16f32] } VRM8:{ *:[nxv16i32] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16i32] }:$rs1, -1:{ *:[i64] }, 5:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64262,
      GIR_Done,
    // Label 4510: @132951
    GIM_Try, /*On fail goto*//*Label 4511*/ 132989, // Rule ID 64263 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (uint_to_fp:{ *:[nxv16f32] } VRM8:{ *:[nxv16i32] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16i32] }:$rs1, -1:{ *:[i32] }, 5:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/5,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64263,
      GIR_Done,
    // Label 4511: @132989
    GIM_Try, /*On fail goto*//*Label 4512*/ 133027, // Rule ID 64360 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (uint_to_fp:{ *:[nxv16f32] } VRM4:{ *:[nxv16i16] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_M4:{ *:[nxv16f32] } VRM4:{ *:[nxv16i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64360,
      GIR_Done,
    // Label 4512: @133027
    GIM_Try, /*On fail goto*//*Label 4513*/ 133065, // Rule ID 64361 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (uint_to_fp:{ *:[nxv16f32] } VRM4:{ *:[nxv16i16] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_M4:{ *:[nxv16f32] } VRM4:{ *:[nxv16i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64361,
      GIR_Done,
    // Label 4513: @133065
    GIM_Reject,
    // Label 4436: @133066
    GIM_Try, /*On fail goto*//*Label 4514*/ 133104, // Rule ID 64256 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (uint_to_fp:{ *:[nxv32f16] } VRM8:{ *:[nxv32i16] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32i16] }:$rs1, -1:{ *:[i64] }, 4:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64256,
      GIR_Done,
    // Label 4514: @133104
    GIM_Try, /*On fail goto*//*Label 4515*/ 133142, // Rule ID 64257 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      // (uint_to_fp:{ *:[nxv32f16] } VRM8:{ *:[nxv32i16] }:$rs1)  =>  (PseudoVFCVT_F_XU_V_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32i16] }:$rs1, -1:{ *:[i32] }, 4:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFCVT_F_XU_V_M8,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/4,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64257,
      GIR_Done,
    // Label 4515: @133142
    GIM_Try, /*On fail goto*//*Label 4516*/ 133180, // Rule ID 64350 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (uint_to_fp:{ *:[nxv32f16] } VRM4:{ *:[nxv32i8] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_M4:{ *:[nxv32f16] } VRM4:{ *:[nxv32i8] }:$rs1, -1:{ *:[i64] }, 3:{ *:[i64] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64350,
      GIR_Done,
    // Label 4516: @133180
    GIM_Try, /*On fail goto*//*Label 4517*/ 133218, // Rule ID 64351 //
      GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      // (uint_to_fp:{ *:[nxv32f16] } VRM4:{ *:[nxv32i8] }:$rs1)  =>  (PseudoVFWCVT_F_XU_V_M4:{ *:[nxv32f16] } VRM4:{ *:[nxv32i8] }:$rs1, -1:{ *:[i32] }, 3:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFWCVT_F_XU_V_M4,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
      GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
      GIR_AddImm, /*InsnID*/0, /*Imm*/3,
      GIR_EraseFromParent, /*InsnID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 64351,
      GIR_Done,
    // Label 4517: @133218
    GIM_Reject,
    // Label 4437: @133219
    GIM_Reject,
    // Label 57: @133220
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 30, /*)*//*default:*//*Label 4533*/ 134391,
    /*GILLT_nxv1s16*//*Label 4518*/ 133251,
    /*GILLT_nxv1s32*//*Label 4519*/ 133327,
    /*GILLT_nxv1s64*//*Label 4520*/ 133403, 0, 0,
    /*GILLT_nxv2s16*//*Label 4521*/ 133479,
    /*GILLT_nxv2s32*//*Label 4522*/ 133555,
    /*GILLT_nxv2s64*//*Label 4523*/ 133631, 0, 0,
    /*GILLT_nxv4s16*//*Label 4524*/ 133707,
    /*GILLT_nxv4s32*//*Label 4525*/ 133783,
    /*GILLT_nxv4s64*//*Label 4526*/ 133859, 0, 0,
    /*GILLT_nxv8s16*//*Label 4527*/ 133935,
    /*GILLT_nxv8s32*//*Label 4528*/ 134011,
    /*GILLT_nxv8s64*//*Label 4529*/ 134087, 0, 0,
    /*GILLT_nxv16s16*//*Label 4530*/ 134163,
    /*GILLT_nxv16s32*//*Label 4531*/ 134239, 0, 0,
    /*GILLT_nxv32s16*//*Label 4532*/ 134315,
    // Label 4518: @133251
    GIM_Try, /*On fail goto*//*Label 4534*/ 133326,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4535*/ 133295, // Rule ID 62949 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs)  =>  (PseudoVFSGNJX_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs, VR:{ *:[nxv1f16] }:$rs, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62949,
        GIR_Done,
      // Label 4535: @133295
      GIM_Try, /*On fail goto*//*Label 4536*/ 133325, // Rule ID 62950 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs)  =>  (PseudoVFSGNJX_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs, VR:{ *:[nxv1f16] }:$rs, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62950,
        GIR_Done,
      // Label 4536: @133325
      GIM_Reject,
    // Label 4534: @133326
    GIM_Reject,
    // Label 4519: @133327
    GIM_Try, /*On fail goto*//*Label 4537*/ 133402,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4538*/ 133371, // Rule ID 62977 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs)  =>  (PseudoVFSGNJX_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs, VR:{ *:[nxv1f32] }:$rs, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62977,
        GIR_Done,
      // Label 4538: @133371
      GIM_Try, /*On fail goto*//*Label 4539*/ 133401, // Rule ID 62978 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs)  =>  (PseudoVFSGNJX_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs, VR:{ *:[nxv1f32] }:$rs, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62978,
        GIR_Done,
      // Label 4539: @133401
      GIM_Reject,
    // Label 4537: @133402
    GIM_Reject,
    // Label 4520: @133403
    GIM_Try, /*On fail goto*//*Label 4540*/ 133478,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4541*/ 133447, // Rule ID 63021 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs)  =>  (PseudoVFSGNJX_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs, VR:{ *:[nxv1f64] }:$rs, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63021,
        GIR_Done,
      // Label 4541: @133447
      GIM_Try, /*On fail goto*//*Label 4542*/ 133477, // Rule ID 63022 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs)  =>  (PseudoVFSGNJX_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs, VR:{ *:[nxv1f64] }:$rs, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63022,
        GIR_Done,
      // Label 4542: @133477
      GIM_Reject,
    // Label 4540: @133478
    GIM_Reject,
    // Label 4521: @133479
    GIM_Try, /*On fail goto*//*Label 4543*/ 133554,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4544*/ 133523, // Rule ID 62963 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs)  =>  (PseudoVFSGNJX_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs, VR:{ *:[nxv2f16] }:$rs, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62963,
        GIR_Done,
      // Label 4544: @133523
      GIM_Try, /*On fail goto*//*Label 4545*/ 133553, // Rule ID 62964 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs)  =>  (PseudoVFSGNJX_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs, VR:{ *:[nxv2f16] }:$rs, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62964,
        GIR_Done,
      // Label 4545: @133553
      GIM_Reject,
    // Label 4543: @133554
    GIM_Reject,
    // Label 4522: @133555
    GIM_Try, /*On fail goto*//*Label 4546*/ 133630,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4547*/ 133599, // Rule ID 63006 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs)  =>  (PseudoVFSGNJX_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs, VR:{ *:[nxv2f32] }:$rs, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63006,
        GIR_Done,
      // Label 4547: @133599
      GIM_Try, /*On fail goto*//*Label 4548*/ 133629, // Rule ID 63007 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs)  =>  (PseudoVFSGNJX_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs, VR:{ *:[nxv2f32] }:$rs, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63007,
        GIR_Done,
      // Label 4548: @133629
      GIM_Reject,
    // Label 4546: @133630
    GIM_Reject,
    // Label 4523: @133631
    GIM_Try, /*On fail goto*//*Label 4549*/ 133706,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4550*/ 133675, // Rule ID 63121 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs)  =>  (PseudoVFSGNJX_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs, VRM2:{ *:[nxv2f64] }:$rs, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63121,
        GIR_Done,
      // Label 4550: @133675
      GIM_Try, /*On fail goto*//*Label 4551*/ 133705, // Rule ID 63122 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs)  =>  (PseudoVFSGNJX_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs, VRM2:{ *:[nxv2f64] }:$rs, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63122,
        GIR_Done,
      // Label 4551: @133705
      GIM_Reject,
    // Label 4549: @133706
    GIM_Reject,
    // Label 4524: @133707
    GIM_Try, /*On fail goto*//*Label 4552*/ 133782,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4553*/ 133751, // Rule ID 62992 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs)  =>  (PseudoVFSGNJX_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs, VR:{ *:[nxv4f16] }:$rs, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62992,
        GIR_Done,
      // Label 4553: @133751
      GIM_Try, /*On fail goto*//*Label 4554*/ 133781, // Rule ID 62993 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs)  =>  (PseudoVFSGNJX_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs, VR:{ *:[nxv4f16] }:$rs, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62993,
        GIR_Done,
      // Label 4554: @133781
      GIM_Reject,
    // Label 4552: @133782
    GIM_Reject,
    // Label 4525: @133783
    GIM_Try, /*On fail goto*//*Label 4555*/ 133858,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4556*/ 133827, // Rule ID 63078 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs)  =>  (PseudoVFSGNJX_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs, VRM2:{ *:[nxv4f32] }:$rs, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63078,
        GIR_Done,
      // Label 4556: @133827
      GIM_Try, /*On fail goto*//*Label 4557*/ 133857, // Rule ID 63079 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs)  =>  (PseudoVFSGNJX_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs, VRM2:{ *:[nxv4f32] }:$rs, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63079,
        GIR_Done,
      // Label 4557: @133857
      GIM_Reject,
    // Label 4555: @133858
    GIM_Reject,
    // Label 4526: @133859
    GIM_Try, /*On fail goto*//*Label 4558*/ 133934,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4559*/ 133903, // Rule ID 63135 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs)  =>  (PseudoVFSGNJX_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs, VRM4:{ *:[nxv4f64] }:$rs, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63135,
        GIR_Done,
      // Label 4559: @133903
      GIM_Try, /*On fail goto*//*Label 4560*/ 133933, // Rule ID 63136 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs)  =>  (PseudoVFSGNJX_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs, VRM4:{ *:[nxv4f64] }:$rs, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63136,
        GIR_Done,
      // Label 4560: @133933
      GIM_Reject,
    // Label 4558: @133934
    GIM_Reject,
    // Label 4527: @133935
    GIM_Try, /*On fail goto*//*Label 4561*/ 134010,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4562*/ 133979, // Rule ID 63035 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs)  =>  (PseudoVFSGNJX_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs, VRM2:{ *:[nxv8f16] }:$rs, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63035,
        GIR_Done,
      // Label 4562: @133979
      GIM_Try, /*On fail goto*//*Label 4563*/ 134009, // Rule ID 63036 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs)  =>  (PseudoVFSGNJX_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs, VRM2:{ *:[nxv8f16] }:$rs, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63036,
        GIR_Done,
      // Label 4563: @134009
      GIM_Reject,
    // Label 4561: @134010
    GIM_Reject,
    // Label 4528: @134011
    GIM_Try, /*On fail goto*//*Label 4564*/ 134086,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4565*/ 134055, // Rule ID 63092 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs)  =>  (PseudoVFSGNJX_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs, VRM4:{ *:[nxv8f32] }:$rs, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63092,
        GIR_Done,
      // Label 4565: @134055
      GIM_Try, /*On fail goto*//*Label 4566*/ 134085, // Rule ID 63093 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs)  =>  (PseudoVFSGNJX_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs, VRM4:{ *:[nxv8f32] }:$rs, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63093,
        GIR_Done,
      // Label 4566: @134085
      GIM_Reject,
    // Label 4564: @134086
    GIM_Reject,
    // Label 4529: @134087
    GIM_Try, /*On fail goto*//*Label 4567*/ 134162,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4568*/ 134131, // Rule ID 63150 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs)  =>  (PseudoVFSGNJX_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs, VRM8:{ *:[nxv8f64] }:$rs, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63150,
        GIR_Done,
      // Label 4568: @134131
      GIM_Try, /*On fail goto*//*Label 4569*/ 134161, // Rule ID 63151 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs)  =>  (PseudoVFSGNJX_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs, VRM8:{ *:[nxv8f64] }:$rs, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63151,
        GIR_Done,
      // Label 4569: @134161
      GIM_Reject,
    // Label 4567: @134162
    GIM_Reject,
    // Label 4530: @134163
    GIM_Try, /*On fail goto*//*Label 4570*/ 134238,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4571*/ 134207, // Rule ID 63049 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs)  =>  (PseudoVFSGNJX_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs, VRM4:{ *:[nxv16f16] }:$rs, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63049,
        GIR_Done,
      // Label 4571: @134207
      GIM_Try, /*On fail goto*//*Label 4572*/ 134237, // Rule ID 63050 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs)  =>  (PseudoVFSGNJX_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs, VRM4:{ *:[nxv16f16] }:$rs, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63050,
        GIR_Done,
      // Label 4572: @134237
      GIM_Reject,
    // Label 4570: @134238
    GIM_Reject,
    // Label 4531: @134239
    GIM_Try, /*On fail goto*//*Label 4573*/ 134314,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4574*/ 134283, // Rule ID 63107 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs)  =>  (PseudoVFSGNJX_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs, VRM8:{ *:[nxv16f32] }:$rs, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63107,
        GIR_Done,
      // Label 4574: @134283
      GIM_Try, /*On fail goto*//*Label 4575*/ 134313, // Rule ID 63108 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs)  =>  (PseudoVFSGNJX_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs, VRM8:{ *:[nxv16f32] }:$rs, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63108,
        GIR_Done,
      // Label 4575: @134313
      GIM_Reject,
    // Label 4573: @134314
    GIM_Reject,
    // Label 4532: @134315
    GIM_Try, /*On fail goto*//*Label 4576*/ 134390,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4577*/ 134359, // Rule ID 63064 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs)  =>  (PseudoVFSGNJX_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs, VRM8:{ *:[nxv32f16] }:$rs, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63064,
        GIR_Done,
      // Label 4577: @134359
      GIM_Try, /*On fail goto*//*Label 4578*/ 134389, // Rule ID 63065 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fabs:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs)  =>  (PseudoVFSGNJX_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs, VRM8:{ *:[nxv32f16] }:$rs, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJX_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63065,
        GIR_Done,
      // Label 4578: @134389
      GIM_Reject,
    // Label 4576: @134390
    GIM_Reject,
    // Label 4533: @134391
    GIM_Reject,
    // Label 58: @134392
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 30, /*)*//*default:*//*Label 4594*/ 137153,
    /*GILLT_nxv1s16*//*Label 4579*/ 134423,
    /*GILLT_nxv1s32*//*Label 4580*/ 134605,
    /*GILLT_nxv1s64*//*Label 4581*/ 134787, 0, 0,
    /*GILLT_nxv2s16*//*Label 4582*/ 134969,
    /*GILLT_nxv2s32*//*Label 4583*/ 135151,
    /*GILLT_nxv2s64*//*Label 4584*/ 135333, 0, 0,
    /*GILLT_nxv4s16*//*Label 4585*/ 135515,
    /*GILLT_nxv4s32*//*Label 4586*/ 135697,
    /*GILLT_nxv4s64*//*Label 4587*/ 135879, 0, 0,
    /*GILLT_nxv8s16*//*Label 4588*/ 136061,
    /*GILLT_nxv8s32*//*Label 4589*/ 136243,
    /*GILLT_nxv8s64*//*Label 4590*/ 136425, 0, 0,
    /*GILLT_nxv16s16*//*Label 4591*/ 136607,
    /*GILLT_nxv16s32*//*Label 4592*/ 136789, 0, 0,
    /*GILLT_nxv32s16*//*Label 4593*/ 136971,
    // Label 4579: @134423
    GIM_Try, /*On fail goto*//*Label 4595*/ 134604,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4596*/ 134488, // Rule ID 62957 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2))  =>  (PseudoVFSGNJN_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62957,
        GIR_Done,
      // Label 4596: @134488
      GIM_Try, /*On fail goto*//*Label 4597*/ 134535, // Rule ID 62958 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, (fneg:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2))  =>  (PseudoVFSGNJN_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62958,
        GIR_Done,
      // Label 4597: @134535
      GIM_Try, /*On fail goto*//*Label 4598*/ 134569, // Rule ID 62953 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        // (fcopysign:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2)  =>  (PseudoVFSGNJ_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62953,
        GIR_Done,
      // Label 4598: @134569
      GIM_Try, /*On fail goto*//*Label 4599*/ 134603, // Rule ID 62954 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        // (fcopysign:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2)  =>  (PseudoVFSGNJ_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62954,
        GIR_Done,
      // Label 4599: @134603
      GIM_Reject,
    // Label 4595: @134604
    GIM_Reject,
    // Label 4580: @134605
    GIM_Try, /*On fail goto*//*Label 4600*/ 134786,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4601*/ 134670, // Rule ID 62986 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2))  =>  (PseudoVFSGNJN_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62986,
        GIR_Done,
      // Label 4601: @134670
      GIM_Try, /*On fail goto*//*Label 4602*/ 134717, // Rule ID 62987 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, (fneg:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2))  =>  (PseudoVFSGNJN_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62987,
        GIR_Done,
      // Label 4602: @134717
      GIM_Try, /*On fail goto*//*Label 4603*/ 134751, // Rule ID 62982 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        // (fcopysign:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2)  =>  (PseudoVFSGNJ_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62982,
        GIR_Done,
      // Label 4603: @134751
      GIM_Try, /*On fail goto*//*Label 4604*/ 134785, // Rule ID 62983 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        // (fcopysign:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2)  =>  (PseudoVFSGNJ_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62983,
        GIR_Done,
      // Label 4604: @134785
      GIM_Reject,
    // Label 4600: @134786
    GIM_Reject,
    // Label 4581: @134787
    GIM_Try, /*On fail goto*//*Label 4605*/ 134968,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4606*/ 134852, // Rule ID 63029 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2))  =>  (PseudoVFSGNJN_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63029,
        GIR_Done,
      // Label 4606: @134852
      GIM_Try, /*On fail goto*//*Label 4607*/ 134899, // Rule ID 63030 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, (fneg:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2))  =>  (PseudoVFSGNJN_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63030,
        GIR_Done,
      // Label 4607: @134899
      GIM_Try, /*On fail goto*//*Label 4608*/ 134933, // Rule ID 63025 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        // (fcopysign:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2)  =>  (PseudoVFSGNJ_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63025,
        GIR_Done,
      // Label 4608: @134933
      GIM_Try, /*On fail goto*//*Label 4609*/ 134967, // Rule ID 63026 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        // (fcopysign:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2)  =>  (PseudoVFSGNJ_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63026,
        GIR_Done,
      // Label 4609: @134967
      GIM_Reject,
    // Label 4605: @134968
    GIM_Reject,
    // Label 4582: @134969
    GIM_Try, /*On fail goto*//*Label 4610*/ 135150,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4611*/ 135034, // Rule ID 62971 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2))  =>  (PseudoVFSGNJN_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62971,
        GIR_Done,
      // Label 4611: @135034
      GIM_Try, /*On fail goto*//*Label 4612*/ 135081, // Rule ID 62972 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, (fneg:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2))  =>  (PseudoVFSGNJN_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62972,
        GIR_Done,
      // Label 4612: @135081
      GIM_Try, /*On fail goto*//*Label 4613*/ 135115, // Rule ID 62967 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        // (fcopysign:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2)  =>  (PseudoVFSGNJ_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62967,
        GIR_Done,
      // Label 4613: @135115
      GIM_Try, /*On fail goto*//*Label 4614*/ 135149, // Rule ID 62968 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        // (fcopysign:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2)  =>  (PseudoVFSGNJ_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62968,
        GIR_Done,
      // Label 4614: @135149
      GIM_Reject,
    // Label 4610: @135150
    GIM_Reject,
    // Label 4583: @135151
    GIM_Try, /*On fail goto*//*Label 4615*/ 135332,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4616*/ 135216, // Rule ID 63014 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2))  =>  (PseudoVFSGNJN_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63014,
        GIR_Done,
      // Label 4616: @135216
      GIM_Try, /*On fail goto*//*Label 4617*/ 135263, // Rule ID 63015 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, (fneg:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2))  =>  (PseudoVFSGNJN_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63015,
        GIR_Done,
      // Label 4617: @135263
      GIM_Try, /*On fail goto*//*Label 4618*/ 135297, // Rule ID 63010 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        // (fcopysign:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2)  =>  (PseudoVFSGNJ_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63010,
        GIR_Done,
      // Label 4618: @135297
      GIM_Try, /*On fail goto*//*Label 4619*/ 135331, // Rule ID 63011 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        // (fcopysign:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2)  =>  (PseudoVFSGNJ_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63011,
        GIR_Done,
      // Label 4619: @135331
      GIM_Reject,
    // Label 4615: @135332
    GIM_Reject,
    // Label 4584: @135333
    GIM_Try, /*On fail goto*//*Label 4620*/ 135514,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4621*/ 135398, // Rule ID 63129 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2))  =>  (PseudoVFSGNJN_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63129,
        GIR_Done,
      // Label 4621: @135398
      GIM_Try, /*On fail goto*//*Label 4622*/ 135445, // Rule ID 63130 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, (fneg:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2))  =>  (PseudoVFSGNJN_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63130,
        GIR_Done,
      // Label 4622: @135445
      GIM_Try, /*On fail goto*//*Label 4623*/ 135479, // Rule ID 63125 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        // (fcopysign:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2)  =>  (PseudoVFSGNJ_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63125,
        GIR_Done,
      // Label 4623: @135479
      GIM_Try, /*On fail goto*//*Label 4624*/ 135513, // Rule ID 63126 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        // (fcopysign:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2)  =>  (PseudoVFSGNJ_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63126,
        GIR_Done,
      // Label 4624: @135513
      GIM_Reject,
    // Label 4620: @135514
    GIM_Reject,
    // Label 4585: @135515
    GIM_Try, /*On fail goto*//*Label 4625*/ 135696,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4626*/ 135580, // Rule ID 63000 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2))  =>  (PseudoVFSGNJN_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63000,
        GIR_Done,
      // Label 4626: @135580
      GIM_Try, /*On fail goto*//*Label 4627*/ 135627, // Rule ID 63001 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRRegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, (fneg:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2))  =>  (PseudoVFSGNJN_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63001,
        GIR_Done,
      // Label 4627: @135627
      GIM_Try, /*On fail goto*//*Label 4628*/ 135661, // Rule ID 62996 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        // (fcopysign:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2)  =>  (PseudoVFSGNJ_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62996,
        GIR_Done,
      // Label 4628: @135661
      GIM_Try, /*On fail goto*//*Label 4629*/ 135695, // Rule ID 62997 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
        // (fcopysign:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2)  =>  (PseudoVFSGNJ_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62997,
        GIR_Done,
      // Label 4629: @135695
      GIM_Reject,
    // Label 4625: @135696
    GIM_Reject,
    // Label 4586: @135697
    GIM_Try, /*On fail goto*//*Label 4630*/ 135878,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4631*/ 135762, // Rule ID 63086 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2))  =>  (PseudoVFSGNJN_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63086,
        GIR_Done,
      // Label 4631: @135762
      GIM_Try, /*On fail goto*//*Label 4632*/ 135809, // Rule ID 63087 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, (fneg:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2))  =>  (PseudoVFSGNJN_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63087,
        GIR_Done,
      // Label 4632: @135809
      GIM_Try, /*On fail goto*//*Label 4633*/ 135843, // Rule ID 63082 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        // (fcopysign:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2)  =>  (PseudoVFSGNJ_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63082,
        GIR_Done,
      // Label 4633: @135843
      GIM_Try, /*On fail goto*//*Label 4634*/ 135877, // Rule ID 63083 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        // (fcopysign:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2)  =>  (PseudoVFSGNJ_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63083,
        GIR_Done,
      // Label 4634: @135877
      GIM_Reject,
    // Label 4630: @135878
    GIM_Reject,
    // Label 4587: @135879
    GIM_Try, /*On fail goto*//*Label 4635*/ 136060,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4636*/ 135944, // Rule ID 63144 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2))  =>  (PseudoVFSGNJN_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63144,
        GIR_Done,
      // Label 4636: @135944
      GIM_Try, /*On fail goto*//*Label 4637*/ 135991, // Rule ID 63145 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, (fneg:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2))  =>  (PseudoVFSGNJN_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63145,
        GIR_Done,
      // Label 4637: @135991
      GIM_Try, /*On fail goto*//*Label 4638*/ 136025, // Rule ID 63139 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        // (fcopysign:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2)  =>  (PseudoVFSGNJ_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63139,
        GIR_Done,
      // Label 4638: @136025
      GIM_Try, /*On fail goto*//*Label 4639*/ 136059, // Rule ID 63140 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        // (fcopysign:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2)  =>  (PseudoVFSGNJ_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63140,
        GIR_Done,
      // Label 4639: @136059
      GIM_Reject,
    // Label 4635: @136060
    GIM_Reject,
    // Label 4588: @136061
    GIM_Try, /*On fail goto*//*Label 4640*/ 136242,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4641*/ 136126, // Rule ID 63043 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2))  =>  (PseudoVFSGNJN_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63043,
        GIR_Done,
      // Label 4641: @136126
      GIM_Try, /*On fail goto*//*Label 4642*/ 136173, // Rule ID 63044 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, (fneg:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2))  =>  (PseudoVFSGNJN_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63044,
        GIR_Done,
      // Label 4642: @136173
      GIM_Try, /*On fail goto*//*Label 4643*/ 136207, // Rule ID 63039 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        // (fcopysign:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2)  =>  (PseudoVFSGNJ_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63039,
        GIR_Done,
      // Label 4643: @136207
      GIM_Try, /*On fail goto*//*Label 4644*/ 136241, // Rule ID 63040 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
        // (fcopysign:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2)  =>  (PseudoVFSGNJ_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63040,
        GIR_Done,
      // Label 4644: @136241
      GIM_Reject,
    // Label 4640: @136242
    GIM_Reject,
    // Label 4589: @136243
    GIM_Try, /*On fail goto*//*Label 4645*/ 136424,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4646*/ 136308, // Rule ID 63100 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2))  =>  (PseudoVFSGNJN_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63100,
        GIR_Done,
      // Label 4646: @136308
      GIM_Try, /*On fail goto*//*Label 4647*/ 136355, // Rule ID 63101 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, (fneg:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2))  =>  (PseudoVFSGNJN_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63101,
        GIR_Done,
      // Label 4647: @136355
      GIM_Try, /*On fail goto*//*Label 4648*/ 136389, // Rule ID 63096 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        // (fcopysign:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2)  =>  (PseudoVFSGNJ_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63096,
        GIR_Done,
      // Label 4648: @136389
      GIM_Try, /*On fail goto*//*Label 4649*/ 136423, // Rule ID 63097 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        // (fcopysign:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2)  =>  (PseudoVFSGNJ_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63097,
        GIR_Done,
      // Label 4649: @136423
      GIM_Reject,
    // Label 4645: @136424
    GIM_Reject,
    // Label 4590: @136425
    GIM_Try, /*On fail goto*//*Label 4650*/ 136606,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4651*/ 136490, // Rule ID 63158 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2))  =>  (PseudoVFSGNJN_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63158,
        GIR_Done,
      // Label 4651: @136490
      GIM_Try, /*On fail goto*//*Label 4652*/ 136537, // Rule ID 63159 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, (fneg:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2))  =>  (PseudoVFSGNJN_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63159,
        GIR_Done,
      // Label 4652: @136537
      GIM_Try, /*On fail goto*//*Label 4653*/ 136571, // Rule ID 63154 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        // (fcopysign:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2)  =>  (PseudoVFSGNJ_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63154,
        GIR_Done,
      // Label 4653: @136571
      GIM_Try, /*On fail goto*//*Label 4654*/ 136605, // Rule ID 63155 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        // (fcopysign:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2)  =>  (PseudoVFSGNJ_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63155,
        GIR_Done,
      // Label 4654: @136605
      GIM_Reject,
    // Label 4650: @136606
    GIM_Reject,
    // Label 4591: @136607
    GIM_Try, /*On fail goto*//*Label 4655*/ 136788,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4656*/ 136672, // Rule ID 63057 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2))  =>  (PseudoVFSGNJN_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63057,
        GIR_Done,
      // Label 4656: @136672
      GIM_Try, /*On fail goto*//*Label 4657*/ 136719, // Rule ID 63058 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, (fneg:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2))  =>  (PseudoVFSGNJN_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63058,
        GIR_Done,
      // Label 4657: @136719
      GIM_Try, /*On fail goto*//*Label 4658*/ 136753, // Rule ID 63053 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        // (fcopysign:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2)  =>  (PseudoVFSGNJ_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63053,
        GIR_Done,
      // Label 4658: @136753
      GIM_Try, /*On fail goto*//*Label 4659*/ 136787, // Rule ID 63054 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
        // (fcopysign:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2)  =>  (PseudoVFSGNJ_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63054,
        GIR_Done,
      // Label 4659: @136787
      GIM_Reject,
    // Label 4655: @136788
    GIM_Reject,
    // Label 4592: @136789
    GIM_Try, /*On fail goto*//*Label 4660*/ 136970,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4661*/ 136854, // Rule ID 63115 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2))  =>  (PseudoVFSGNJN_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63115,
        GIR_Done,
      // Label 4661: @136854
      GIM_Try, /*On fail goto*//*Label 4662*/ 136901, // Rule ID 63116 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, (fneg:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2))  =>  (PseudoVFSGNJN_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63116,
        GIR_Done,
      // Label 4662: @136901
      GIM_Try, /*On fail goto*//*Label 4663*/ 136935, // Rule ID 63111 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        // (fcopysign:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2)  =>  (PseudoVFSGNJ_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63111,
        GIR_Done,
      // Label 4663: @136935
      GIM_Try, /*On fail goto*//*Label 4664*/ 136969, // Rule ID 63112 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        // (fcopysign:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2)  =>  (PseudoVFSGNJ_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63112,
        GIR_Done,
      // Label 4664: @136969
      GIM_Reject,
    // Label 4660: @136970
    GIM_Reject,
    // Label 4593: @136971
    GIM_Try, /*On fail goto*//*Label 4665*/ 137152,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4666*/ 137036, // Rule ID 63072 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2))  =>  (PseudoVFSGNJN_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63072,
        GIR_Done,
      // Label 4666: @137036
      GIM_Try, /*On fail goto*//*Label 4667*/ 137083, // Rule ID 63073 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv32s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fcopysign:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, (fneg:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2))  =>  (PseudoVFSGNJN_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJN_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63073,
        GIR_Done,
      // Label 4667: @137083
      GIM_Try, /*On fail goto*//*Label 4668*/ 137117, // Rule ID 63068 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        // (fcopysign:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2)  =>  (PseudoVFSGNJ_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63068,
        GIR_Done,
      // Label 4668: @137117
      GIM_Try, /*On fail goto*//*Label 4669*/ 137151, // Rule ID 63069 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
        // (fcopysign:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2)  =>  (PseudoVFSGNJ_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSGNJ_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63069,
        GIR_Done,
      // Label 4669: @137151
      GIM_Reject,
    // Label 4665: @137152
    GIM_Reject,
    // Label 4594: @137153
    GIM_Reject,
    // Label 59: @137154
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 30, /*)*//*default:*//*Label 4685*/ 138445,
    /*GILLT_nxv1s16*//*Label 4670*/ 137185,
    /*GILLT_nxv1s32*//*Label 4671*/ 137269,
    /*GILLT_nxv1s64*//*Label 4672*/ 137353, 0, 0,
    /*GILLT_nxv2s16*//*Label 4673*/ 137437,
    /*GILLT_nxv2s32*//*Label 4674*/ 137521,
    /*GILLT_nxv2s64*//*Label 4675*/ 137605, 0, 0,
    /*GILLT_nxv4s16*//*Label 4676*/ 137689,
    /*GILLT_nxv4s32*//*Label 4677*/ 137773,
    /*GILLT_nxv4s64*//*Label 4678*/ 137857, 0, 0,
    /*GILLT_nxv8s16*//*Label 4679*/ 137941,
    /*GILLT_nxv8s32*//*Label 4680*/ 138025,
    /*GILLT_nxv8s64*//*Label 4681*/ 138109, 0, 0,
    /*GILLT_nxv16s16*//*Label 4682*/ 138193,
    /*GILLT_nxv16s32*//*Label 4683*/ 138277, 0, 0,
    /*GILLT_nxv32s16*//*Label 4684*/ 138361,
    // Label 4670: @137185
    GIM_Try, /*On fail goto*//*Label 4686*/ 137268,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4687*/ 137237, // Rule ID 63163 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2)  =>  (PseudoVFMIN_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63163,
        GIR_Done,
      // Label 4687: @137237
      GIM_Try, /*On fail goto*//*Label 4688*/ 137267, // Rule ID 63164 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2)  =>  (PseudoVFMIN_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63164,
        GIR_Done,
      // Label 4688: @137267
      GIM_Reject,
    // Label 4686: @137268
    GIM_Reject,
    // Label 4671: @137269
    GIM_Try, /*On fail goto*//*Label 4689*/ 137352,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4690*/ 137321, // Rule ID 63171 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2)  =>  (PseudoVFMIN_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63171,
        GIR_Done,
      // Label 4690: @137321
      GIM_Try, /*On fail goto*//*Label 4691*/ 137351, // Rule ID 63172 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2)  =>  (PseudoVFMIN_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63172,
        GIR_Done,
      // Label 4691: @137351
      GIM_Reject,
    // Label 4689: @137352
    GIM_Reject,
    // Label 4672: @137353
    GIM_Try, /*On fail goto*//*Label 4692*/ 137436,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4693*/ 137405, // Rule ID 63184 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2)  =>  (PseudoVFMIN_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63184,
        GIR_Done,
      // Label 4693: @137405
      GIM_Try, /*On fail goto*//*Label 4694*/ 137435, // Rule ID 63185 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2)  =>  (PseudoVFMIN_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63185,
        GIR_Done,
      // Label 4694: @137435
      GIM_Reject,
    // Label 4692: @137436
    GIM_Reject,
    // Label 4673: @137437
    GIM_Try, /*On fail goto*//*Label 4695*/ 137520,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4696*/ 137489, // Rule ID 63167 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2)  =>  (PseudoVFMIN_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63167,
        GIR_Done,
      // Label 4696: @137489
      GIM_Try, /*On fail goto*//*Label 4697*/ 137519, // Rule ID 63168 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2)  =>  (PseudoVFMIN_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63168,
        GIR_Done,
      // Label 4697: @137519
      GIM_Reject,
    // Label 4695: @137520
    GIM_Reject,
    // Label 4674: @137521
    GIM_Try, /*On fail goto*//*Label 4698*/ 137604,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4699*/ 137573, // Rule ID 63179 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2)  =>  (PseudoVFMIN_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63179,
        GIR_Done,
      // Label 4699: @137573
      GIM_Try, /*On fail goto*//*Label 4700*/ 137603, // Rule ID 63180 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2)  =>  (PseudoVFMIN_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63180,
        GIR_Done,
      // Label 4700: @137603
      GIM_Reject,
    // Label 4698: @137604
    GIM_Reject,
    // Label 4675: @137605
    GIM_Try, /*On fail goto*//*Label 4701*/ 137688,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4702*/ 137657, // Rule ID 63213 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2)  =>  (PseudoVFMIN_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63213,
        GIR_Done,
      // Label 4702: @137657
      GIM_Try, /*On fail goto*//*Label 4703*/ 137687, // Rule ID 63214 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2)  =>  (PseudoVFMIN_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63214,
        GIR_Done,
      // Label 4703: @137687
      GIM_Reject,
    // Label 4701: @137688
    GIM_Reject,
    // Label 4676: @137689
    GIM_Try, /*On fail goto*//*Label 4704*/ 137772,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4705*/ 137741, // Rule ID 63175 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2)  =>  (PseudoVFMIN_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63175,
        GIR_Done,
      // Label 4705: @137741
      GIM_Try, /*On fail goto*//*Label 4706*/ 137771, // Rule ID 63176 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2)  =>  (PseudoVFMIN_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63176,
        GIR_Done,
      // Label 4706: @137771
      GIM_Reject,
    // Label 4704: @137772
    GIM_Reject,
    // Label 4677: @137773
    GIM_Try, /*On fail goto*//*Label 4707*/ 137856,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4708*/ 137825, // Rule ID 63200 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2)  =>  (PseudoVFMIN_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63200,
        GIR_Done,
      // Label 4708: @137825
      GIM_Try, /*On fail goto*//*Label 4709*/ 137855, // Rule ID 63201 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2)  =>  (PseudoVFMIN_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63201,
        GIR_Done,
      // Label 4709: @137855
      GIM_Reject,
    // Label 4707: @137856
    GIM_Reject,
    // Label 4678: @137857
    GIM_Try, /*On fail goto*//*Label 4710*/ 137940,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4711*/ 137909, // Rule ID 63217 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2)  =>  (PseudoVFMIN_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63217,
        GIR_Done,
      // Label 4711: @137909
      GIM_Try, /*On fail goto*//*Label 4712*/ 137939, // Rule ID 63218 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2)  =>  (PseudoVFMIN_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63218,
        GIR_Done,
      // Label 4712: @137939
      GIM_Reject,
    // Label 4710: @137940
    GIM_Reject,
    // Label 4679: @137941
    GIM_Try, /*On fail goto*//*Label 4713*/ 138024,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4714*/ 137993, // Rule ID 63188 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2)  =>  (PseudoVFMIN_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63188,
        GIR_Done,
      // Label 4714: @137993
      GIM_Try, /*On fail goto*//*Label 4715*/ 138023, // Rule ID 63189 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2)  =>  (PseudoVFMIN_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63189,
        GIR_Done,
      // Label 4715: @138023
      GIM_Reject,
    // Label 4713: @138024
    GIM_Reject,
    // Label 4680: @138025
    GIM_Try, /*On fail goto*//*Label 4716*/ 138108,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4717*/ 138077, // Rule ID 63205 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2)  =>  (PseudoVFMIN_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63205,
        GIR_Done,
      // Label 4717: @138077
      GIM_Try, /*On fail goto*//*Label 4718*/ 138107, // Rule ID 63206 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2)  =>  (PseudoVFMIN_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63206,
        GIR_Done,
      // Label 4718: @138107
      GIM_Reject,
    // Label 4716: @138108
    GIM_Reject,
    // Label 4681: @138109
    GIM_Try, /*On fail goto*//*Label 4719*/ 138192,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4720*/ 138161, // Rule ID 63221 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2)  =>  (PseudoVFMIN_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63221,
        GIR_Done,
      // Label 4720: @138161
      GIM_Try, /*On fail goto*//*Label 4721*/ 138191, // Rule ID 63222 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2)  =>  (PseudoVFMIN_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63222,
        GIR_Done,
      // Label 4721: @138191
      GIM_Reject,
    // Label 4719: @138192
    GIM_Reject,
    // Label 4682: @138193
    GIM_Try, /*On fail goto*//*Label 4722*/ 138276,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4723*/ 138245, // Rule ID 63192 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2)  =>  (PseudoVFMIN_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63192,
        GIR_Done,
      // Label 4723: @138245
      GIM_Try, /*On fail goto*//*Label 4724*/ 138275, // Rule ID 63193 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2)  =>  (PseudoVFMIN_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63193,
        GIR_Done,
      // Label 4724: @138275
      GIM_Reject,
    // Label 4722: @138276
    GIM_Reject,
    // Label 4683: @138277
    GIM_Try, /*On fail goto*//*Label 4725*/ 138360,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4726*/ 138329, // Rule ID 63209 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2)  =>  (PseudoVFMIN_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63209,
        GIR_Done,
      // Label 4726: @138329
      GIM_Try, /*On fail goto*//*Label 4727*/ 138359, // Rule ID 63210 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2)  =>  (PseudoVFMIN_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63210,
        GIR_Done,
      // Label 4727: @138359
      GIM_Reject,
    // Label 4725: @138360
    GIM_Reject,
    // Label 4684: @138361
    GIM_Try, /*On fail goto*//*Label 4728*/ 138444,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4729*/ 138413, // Rule ID 63196 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2)  =>  (PseudoVFMIN_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63196,
        GIR_Done,
      // Label 4729: @138413
      GIM_Try, /*On fail goto*//*Label 4730*/ 138443, // Rule ID 63197 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fminnum:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2)  =>  (PseudoVFMIN_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMIN_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63197,
        GIR_Done,
      // Label 4730: @138443
      GIM_Reject,
    // Label 4728: @138444
    GIM_Reject,
    // Label 4685: @138445
    GIM_Reject,
    // Label 60: @138446
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/5, 30, /*)*//*default:*//*Label 4746*/ 139737,
    /*GILLT_nxv1s16*//*Label 4731*/ 138477,
    /*GILLT_nxv1s32*//*Label 4732*/ 138561,
    /*GILLT_nxv1s64*//*Label 4733*/ 138645, 0, 0,
    /*GILLT_nxv2s16*//*Label 4734*/ 138729,
    /*GILLT_nxv2s32*//*Label 4735*/ 138813,
    /*GILLT_nxv2s64*//*Label 4736*/ 138897, 0, 0,
    /*GILLT_nxv4s16*//*Label 4737*/ 138981,
    /*GILLT_nxv4s32*//*Label 4738*/ 139065,
    /*GILLT_nxv4s64*//*Label 4739*/ 139149, 0, 0,
    /*GILLT_nxv8s16*//*Label 4740*/ 139233,
    /*GILLT_nxv8s32*//*Label 4741*/ 139317,
    /*GILLT_nxv8s64*//*Label 4742*/ 139401, 0, 0,
    /*GILLT_nxv16s16*//*Label 4743*/ 139485,
    /*GILLT_nxv16s32*//*Label 4744*/ 139569, 0, 0,
    /*GILLT_nxv32s16*//*Label 4745*/ 139653,
    // Label 4731: @138477
    GIM_Try, /*On fail goto*//*Label 4747*/ 138560,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4748*/ 138529, // Rule ID 63227 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2)  =>  (PseudoVFMAX_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63227,
        GIR_Done,
      // Label 4748: @138529
      GIM_Try, /*On fail goto*//*Label 4749*/ 138559, // Rule ID 63228 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2)  =>  (PseudoVFMAX_VV_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs1, VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63228,
        GIR_Done,
      // Label 4749: @138559
      GIM_Reject,
    // Label 4747: @138560
    GIM_Reject,
    // Label 4732: @138561
    GIM_Try, /*On fail goto*//*Label 4750*/ 138644,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4751*/ 138613, // Rule ID 63235 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2)  =>  (PseudoVFMAX_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63235,
        GIR_Done,
      // Label 4751: @138613
      GIM_Try, /*On fail goto*//*Label 4752*/ 138643, // Rule ID 63236 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2)  =>  (PseudoVFMAX_VV_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs1, VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63236,
        GIR_Done,
      // Label 4752: @138643
      GIM_Reject,
    // Label 4750: @138644
    GIM_Reject,
    // Label 4733: @138645
    GIM_Try, /*On fail goto*//*Label 4753*/ 138728,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4754*/ 138697, // Rule ID 63248 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2)  =>  (PseudoVFMAX_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63248,
        GIR_Done,
      // Label 4754: @138697
      GIM_Try, /*On fail goto*//*Label 4755*/ 138727, // Rule ID 63249 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2)  =>  (PseudoVFMAX_VV_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs1, VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63249,
        GIR_Done,
      // Label 4755: @138727
      GIM_Reject,
    // Label 4753: @138728
    GIM_Reject,
    // Label 4734: @138729
    GIM_Try, /*On fail goto*//*Label 4756*/ 138812,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4757*/ 138781, // Rule ID 63231 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2)  =>  (PseudoVFMAX_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63231,
        GIR_Done,
      // Label 4757: @138781
      GIM_Try, /*On fail goto*//*Label 4758*/ 138811, // Rule ID 63232 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2)  =>  (PseudoVFMAX_VV_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs1, VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63232,
        GIR_Done,
      // Label 4758: @138811
      GIM_Reject,
    // Label 4756: @138812
    GIM_Reject,
    // Label 4735: @138813
    GIM_Try, /*On fail goto*//*Label 4759*/ 138896,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4760*/ 138865, // Rule ID 63243 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2)  =>  (PseudoVFMAX_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63243,
        GIR_Done,
      // Label 4760: @138865
      GIM_Try, /*On fail goto*//*Label 4761*/ 138895, // Rule ID 63244 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2)  =>  (PseudoVFMAX_VV_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs1, VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63244,
        GIR_Done,
      // Label 4761: @138895
      GIM_Reject,
    // Label 4759: @138896
    GIM_Reject,
    // Label 4736: @138897
    GIM_Try, /*On fail goto*//*Label 4762*/ 138980,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4763*/ 138949, // Rule ID 63278 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2)  =>  (PseudoVFMAX_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63278,
        GIR_Done,
      // Label 4763: @138949
      GIM_Try, /*On fail goto*//*Label 4764*/ 138979, // Rule ID 63279 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2)  =>  (PseudoVFMAX_VV_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs1, VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63279,
        GIR_Done,
      // Label 4764: @138979
      GIM_Reject,
    // Label 4762: @138980
    GIM_Reject,
    // Label 4737: @138981
    GIM_Try, /*On fail goto*//*Label 4765*/ 139064,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4766*/ 139033, // Rule ID 63239 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2)  =>  (PseudoVFMAX_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63239,
        GIR_Done,
      // Label 4766: @139033
      GIM_Try, /*On fail goto*//*Label 4767*/ 139063, // Rule ID 63240 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2)  =>  (PseudoVFMAX_VV_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs1, VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63240,
        GIR_Done,
      // Label 4767: @139063
      GIM_Reject,
    // Label 4765: @139064
    GIM_Reject,
    // Label 4738: @139065
    GIM_Try, /*On fail goto*//*Label 4768*/ 139148,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4769*/ 139117, // Rule ID 63264 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2)  =>  (PseudoVFMAX_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63264,
        GIR_Done,
      // Label 4769: @139117
      GIM_Try, /*On fail goto*//*Label 4770*/ 139147, // Rule ID 63265 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2)  =>  (PseudoVFMAX_VV_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs1, VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63265,
        GIR_Done,
      // Label 4770: @139147
      GIM_Reject,
    // Label 4768: @139148
    GIM_Reject,
    // Label 4739: @139149
    GIM_Try, /*On fail goto*//*Label 4771*/ 139232,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4772*/ 139201, // Rule ID 63282 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2)  =>  (PseudoVFMAX_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63282,
        GIR_Done,
      // Label 4772: @139201
      GIM_Try, /*On fail goto*//*Label 4773*/ 139231, // Rule ID 63283 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2)  =>  (PseudoVFMAX_VV_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs1, VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63283,
        GIR_Done,
      // Label 4773: @139231
      GIM_Reject,
    // Label 4771: @139232
    GIM_Reject,
    // Label 4740: @139233
    GIM_Try, /*On fail goto*//*Label 4774*/ 139316,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4775*/ 139285, // Rule ID 63252 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2)  =>  (PseudoVFMAX_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63252,
        GIR_Done,
      // Label 4775: @139285
      GIM_Try, /*On fail goto*//*Label 4776*/ 139315, // Rule ID 63253 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2)  =>  (PseudoVFMAX_VV_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs1, VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63253,
        GIR_Done,
      // Label 4776: @139315
      GIM_Reject,
    // Label 4774: @139316
    GIM_Reject,
    // Label 4741: @139317
    GIM_Try, /*On fail goto*//*Label 4777*/ 139400,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4778*/ 139369, // Rule ID 63270 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2)  =>  (PseudoVFMAX_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63270,
        GIR_Done,
      // Label 4778: @139369
      GIM_Try, /*On fail goto*//*Label 4779*/ 139399, // Rule ID 63271 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2)  =>  (PseudoVFMAX_VV_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs1, VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63271,
        GIR_Done,
      // Label 4779: @139399
      GIM_Reject,
    // Label 4777: @139400
    GIM_Reject,
    // Label 4742: @139401
    GIM_Try, /*On fail goto*//*Label 4780*/ 139484,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4781*/ 139453, // Rule ID 63286 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2)  =>  (PseudoVFMAX_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63286,
        GIR_Done,
      // Label 4781: @139453
      GIM_Try, /*On fail goto*//*Label 4782*/ 139483, // Rule ID 63287 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2)  =>  (PseudoVFMAX_VV_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs1, VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63287,
        GIR_Done,
      // Label 4782: @139483
      GIM_Reject,
    // Label 4780: @139484
    GIM_Reject,
    // Label 4743: @139485
    GIM_Try, /*On fail goto*//*Label 4783*/ 139568,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4784*/ 139537, // Rule ID 63256 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2)  =>  (PseudoVFMAX_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63256,
        GIR_Done,
      // Label 4784: @139537
      GIM_Try, /*On fail goto*//*Label 4785*/ 139567, // Rule ID 63257 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2)  =>  (PseudoVFMAX_VV_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs1, VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63257,
        GIR_Done,
      // Label 4785: @139567
      GIM_Reject,
    // Label 4783: @139568
    GIM_Reject,
    // Label 4744: @139569
    GIM_Try, /*On fail goto*//*Label 4786*/ 139652,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4787*/ 139621, // Rule ID 63274 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2)  =>  (PseudoVFMAX_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63274,
        GIR_Done,
      // Label 4787: @139621
      GIM_Try, /*On fail goto*//*Label 4788*/ 139651, // Rule ID 63275 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2)  =>  (PseudoVFMAX_VV_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs1, VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63275,
        GIR_Done,
      // Label 4788: @139651
      GIM_Reject,
    // Label 4786: @139652
    GIM_Reject,
    // Label 4745: @139653
    GIM_Try, /*On fail goto*//*Label 4789*/ 139736,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4790*/ 139705, // Rule ID 63260 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2)  =>  (PseudoVFMAX_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63260,
        GIR_Done,
      // Label 4790: @139705
      GIM_Try, /*On fail goto*//*Label 4791*/ 139735, // Rule ID 63261 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fmaxnum:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2)  =>  (PseudoVFMAX_VV_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs1, VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFMAX_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63261,
        GIR_Done,
      // Label 4791: @139735
      GIM_Reject,
    // Label 4789: @139736
    GIM_Reject,
    // Label 4746: @139737
    GIM_Reject,
    // Label 61: @139738
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 32, /*)*//*default:*//*Label 4816*/ 141687,
    /*GILLT_s32*//*Label 4792*/ 139775,
    /*GILLT_s64*//*Label 4793*/ 139807, 0,
    /*GILLT_nxv1s8*//*Label 4794*/ 139839,
    /*GILLT_nxv1s16*//*Label 4795*/ 139923,
    /*GILLT_nxv1s32*//*Label 4796*/ 140007,
    /*GILLT_nxv1s64*//*Label 4797*/ 140091, 0,
    /*GILLT_nxv2s8*//*Label 4798*/ 140175,
    /*GILLT_nxv2s16*//*Label 4799*/ 140259,
    /*GILLT_nxv2s32*//*Label 4800*/ 140343,
    /*GILLT_nxv2s64*//*Label 4801*/ 140427, 0,
    /*GILLT_nxv4s8*//*Label 4802*/ 140511,
    /*GILLT_nxv4s16*//*Label 4803*/ 140595,
    /*GILLT_nxv4s32*//*Label 4804*/ 140679,
    /*GILLT_nxv4s64*//*Label 4805*/ 140763, 0,
    /*GILLT_nxv8s8*//*Label 4806*/ 140847,
    /*GILLT_nxv8s16*//*Label 4807*/ 140931,
    /*GILLT_nxv8s32*//*Label 4808*/ 141015,
    /*GILLT_nxv8s64*//*Label 4809*/ 141099, 0,
    /*GILLT_nxv16s8*//*Label 4810*/ 141183,
    /*GILLT_nxv16s16*//*Label 4811*/ 141267,
    /*GILLT_nxv16s32*//*Label 4812*/ 141351, 0,
    /*GILLT_nxv32s8*//*Label 4813*/ 141435,
    /*GILLT_nxv32s16*//*Label 4814*/ 141519, 0,
    /*GILLT_nxv64s8*//*Label 4815*/ 141603,
    // Label 4792: @139775
    GIM_Try, /*On fail goto*//*Label 4817*/ 139806, // Rule ID 65506 //
      GIM_CheckFeatures, GIFBS_HasStdExtZbb,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
      // (smin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (MIN:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MIN,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65506,
      GIR_Done,
    // Label 4817: @139806
    GIM_Reject,
    // Label 4793: @139807
    GIM_Try, /*On fail goto*//*Label 4818*/ 139838, // Rule ID 65505 //
      GIM_CheckFeatures, GIFBS_HasStdExtZbb,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
      // (smin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (MIN:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MIN,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65505,
      GIR_Done,
    // Label 4818: @139838
    GIM_Reject,
    // Label 4794: @139839
    GIM_Try, /*On fail goto*//*Label 4819*/ 139922,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4820*/ 139891, // Rule ID 59237 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVMIN_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59237,
        GIR_Done,
      // Label 4820: @139891
      GIM_Try, /*On fail goto*//*Label 4821*/ 139921, // Rule ID 59238 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVMIN_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59238,
        GIR_Done,
      // Label 4821: @139921
      GIM_Reject,
    // Label 4819: @139922
    GIM_Reject,
    // Label 4795: @139923
    GIM_Try, /*On fail goto*//*Label 4822*/ 140006,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4823*/ 139975, // Rule ID 59249 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVMIN_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59249,
        GIR_Done,
      // Label 4823: @139975
      GIM_Try, /*On fail goto*//*Label 4824*/ 140005, // Rule ID 59250 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVMIN_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59250,
        GIR_Done,
      // Label 4824: @140005
      GIM_Reject,
    // Label 4822: @140006
    GIM_Reject,
    // Label 4796: @140007
    GIM_Try, /*On fail goto*//*Label 4825*/ 140090,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4826*/ 140059, // Rule ID 59257 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVMIN_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59257,
        GIR_Done,
      // Label 4826: @140059
      GIM_Try, /*On fail goto*//*Label 4827*/ 140089, // Rule ID 59258 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVMIN_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59258,
        GIR_Done,
      // Label 4827: @140089
      GIM_Reject,
    // Label 4825: @140090
    GIM_Reject,
    // Label 4797: @140091
    GIM_Try, /*On fail goto*//*Label 4828*/ 140174,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4829*/ 140143, // Rule ID 59273 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVMIN_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59273,
        GIR_Done,
      // Label 4829: @140143
      GIM_Try, /*On fail goto*//*Label 4830*/ 140173, // Rule ID 59274 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVMIN_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59274,
        GIR_Done,
      // Label 4830: @140173
      GIM_Reject,
    // Label 4828: @140174
    GIM_Reject,
    // Label 4798: @140175
    GIM_Try, /*On fail goto*//*Label 4831*/ 140258,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4832*/ 140227, // Rule ID 59241 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVMIN_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59241,
        GIR_Done,
      // Label 4832: @140227
      GIM_Try, /*On fail goto*//*Label 4833*/ 140257, // Rule ID 59242 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVMIN_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59242,
        GIR_Done,
      // Label 4833: @140257
      GIM_Reject,
    // Label 4831: @140258
    GIM_Reject,
    // Label 4799: @140259
    GIM_Try, /*On fail goto*//*Label 4834*/ 140342,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4835*/ 140311, // Rule ID 59253 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVMIN_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59253,
        GIR_Done,
      // Label 4835: @140311
      GIM_Try, /*On fail goto*//*Label 4836*/ 140341, // Rule ID 59254 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVMIN_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59254,
        GIR_Done,
      // Label 4836: @140341
      GIM_Reject,
    // Label 4834: @140342
    GIM_Reject,
    // Label 4800: @140343
    GIM_Try, /*On fail goto*//*Label 4837*/ 140426,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4838*/ 140395, // Rule ID 59269 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVMIN_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59269,
        GIR_Done,
      // Label 4838: @140395
      GIM_Try, /*On fail goto*//*Label 4839*/ 140425, // Rule ID 59270 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVMIN_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59270,
        GIR_Done,
      // Label 4839: @140425
      GIM_Reject,
    // Label 4837: @140426
    GIM_Reject,
    // Label 4801: @140427
    GIM_Try, /*On fail goto*//*Label 4840*/ 140510,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4841*/ 140479, // Rule ID 59313 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVMIN_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59313,
        GIR_Done,
      // Label 4841: @140479
      GIM_Try, /*On fail goto*//*Label 4842*/ 140509, // Rule ID 59314 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVMIN_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59314,
        GIR_Done,
      // Label 4842: @140509
      GIM_Reject,
    // Label 4840: @140510
    GIM_Reject,
    // Label 4802: @140511
    GIM_Try, /*On fail goto*//*Label 4843*/ 140594,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4844*/ 140563, // Rule ID 59245 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVMIN_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59245,
        GIR_Done,
      // Label 4844: @140563
      GIM_Try, /*On fail goto*//*Label 4845*/ 140593, // Rule ID 59246 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVMIN_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59246,
        GIR_Done,
      // Label 4845: @140593
      GIM_Reject,
    // Label 4843: @140594
    GIM_Reject,
    // Label 4803: @140595
    GIM_Try, /*On fail goto*//*Label 4846*/ 140678,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4847*/ 140647, // Rule ID 59265 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVMIN_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59265,
        GIR_Done,
      // Label 4847: @140647
      GIM_Try, /*On fail goto*//*Label 4848*/ 140677, // Rule ID 59266 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVMIN_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59266,
        GIR_Done,
      // Label 4848: @140677
      GIM_Reject,
    // Label 4846: @140678
    GIM_Reject,
    // Label 4804: @140679
    GIM_Try, /*On fail goto*//*Label 4849*/ 140762,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4850*/ 140731, // Rule ID 59301 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVMIN_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59301,
        GIR_Done,
      // Label 4850: @140731
      GIM_Try, /*On fail goto*//*Label 4851*/ 140761, // Rule ID 59302 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVMIN_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59302,
        GIR_Done,
      // Label 4851: @140761
      GIM_Reject,
    // Label 4849: @140762
    GIM_Reject,
    // Label 4805: @140763
    GIM_Try, /*On fail goto*//*Label 4852*/ 140846,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4853*/ 140815, // Rule ID 59317 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVMIN_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59317,
        GIR_Done,
      // Label 4853: @140815
      GIM_Try, /*On fail goto*//*Label 4854*/ 140845, // Rule ID 59318 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVMIN_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59318,
        GIR_Done,
      // Label 4854: @140845
      GIM_Reject,
    // Label 4852: @140846
    GIM_Reject,
    // Label 4806: @140847
    GIM_Try, /*On fail goto*//*Label 4855*/ 140930,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4856*/ 140899, // Rule ID 59261 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVMIN_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59261,
        GIR_Done,
      // Label 4856: @140899
      GIM_Try, /*On fail goto*//*Label 4857*/ 140929, // Rule ID 59262 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVMIN_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59262,
        GIR_Done,
      // Label 4857: @140929
      GIM_Reject,
    // Label 4855: @140930
    GIM_Reject,
    // Label 4807: @140931
    GIM_Try, /*On fail goto*//*Label 4858*/ 141014,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4859*/ 140983, // Rule ID 59289 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVMIN_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59289,
        GIR_Done,
      // Label 4859: @140983
      GIM_Try, /*On fail goto*//*Label 4860*/ 141013, // Rule ID 59290 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVMIN_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59290,
        GIR_Done,
      // Label 4860: @141013
      GIM_Reject,
    // Label 4858: @141014
    GIM_Reject,
    // Label 4808: @141015
    GIM_Try, /*On fail goto*//*Label 4861*/ 141098,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4862*/ 141067, // Rule ID 59305 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVMIN_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59305,
        GIR_Done,
      // Label 4862: @141067
      GIM_Try, /*On fail goto*//*Label 4863*/ 141097, // Rule ID 59306 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVMIN_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59306,
        GIR_Done,
      // Label 4863: @141097
      GIM_Reject,
    // Label 4861: @141098
    GIM_Reject,
    // Label 4809: @141099
    GIM_Try, /*On fail goto*//*Label 4864*/ 141182,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4865*/ 141151, // Rule ID 59321 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVMIN_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59321,
        GIR_Done,
      // Label 4865: @141151
      GIM_Try, /*On fail goto*//*Label 4866*/ 141181, // Rule ID 59322 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVMIN_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59322,
        GIR_Done,
      // Label 4866: @141181
      GIM_Reject,
    // Label 4864: @141182
    GIM_Reject,
    // Label 4810: @141183
    GIM_Try, /*On fail goto*//*Label 4867*/ 141266,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4868*/ 141235, // Rule ID 59277 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVMIN_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59277,
        GIR_Done,
      // Label 4868: @141235
      GIM_Try, /*On fail goto*//*Label 4869*/ 141265, // Rule ID 59278 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVMIN_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59278,
        GIR_Done,
      // Label 4869: @141265
      GIM_Reject,
    // Label 4867: @141266
    GIM_Reject,
    // Label 4811: @141267
    GIM_Try, /*On fail goto*//*Label 4870*/ 141350,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4871*/ 141319, // Rule ID 59293 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVMIN_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59293,
        GIR_Done,
      // Label 4871: @141319
      GIM_Try, /*On fail goto*//*Label 4872*/ 141349, // Rule ID 59294 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVMIN_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59294,
        GIR_Done,
      // Label 4872: @141349
      GIM_Reject,
    // Label 4870: @141350
    GIM_Reject,
    // Label 4812: @141351
    GIM_Try, /*On fail goto*//*Label 4873*/ 141434,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4874*/ 141403, // Rule ID 59309 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVMIN_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59309,
        GIR_Done,
      // Label 4874: @141403
      GIM_Try, /*On fail goto*//*Label 4875*/ 141433, // Rule ID 59310 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVMIN_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59310,
        GIR_Done,
      // Label 4875: @141433
      GIM_Reject,
    // Label 4873: @141434
    GIM_Reject,
    // Label 4813: @141435
    GIM_Try, /*On fail goto*//*Label 4876*/ 141518,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4877*/ 141487, // Rule ID 59281 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVMIN_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59281,
        GIR_Done,
      // Label 4877: @141487
      GIM_Try, /*On fail goto*//*Label 4878*/ 141517, // Rule ID 59282 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVMIN_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59282,
        GIR_Done,
      // Label 4878: @141517
      GIM_Reject,
    // Label 4876: @141518
    GIM_Reject,
    // Label 4814: @141519
    GIM_Try, /*On fail goto*//*Label 4879*/ 141602,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4880*/ 141571, // Rule ID 59297 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVMIN_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59297,
        GIR_Done,
      // Label 4880: @141571
      GIM_Try, /*On fail goto*//*Label 4881*/ 141601, // Rule ID 59298 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVMIN_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59298,
        GIR_Done,
      // Label 4881: @141601
      GIM_Reject,
    // Label 4879: @141602
    GIM_Reject,
    // Label 4815: @141603
    GIM_Try, /*On fail goto*//*Label 4882*/ 141686,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv64s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4883*/ 141655, // Rule ID 59285 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVMIN_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59285,
        GIR_Done,
      // Label 4883: @141655
      GIM_Try, /*On fail goto*//*Label 4884*/ 141685, // Rule ID 59286 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smin:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVMIN_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMIN_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59286,
        GIR_Done,
      // Label 4884: @141685
      GIM_Reject,
    // Label 4882: @141686
    GIM_Reject,
    // Label 4816: @141687
    GIM_Reject,
    // Label 62: @141688
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 32, /*)*//*default:*//*Label 4909*/ 143637,
    /*GILLT_s32*//*Label 4885*/ 141725,
    /*GILLT_s64*//*Label 4886*/ 141757, 0,
    /*GILLT_nxv1s8*//*Label 4887*/ 141789,
    /*GILLT_nxv1s16*//*Label 4888*/ 141873,
    /*GILLT_nxv1s32*//*Label 4889*/ 141957,
    /*GILLT_nxv1s64*//*Label 4890*/ 142041, 0,
    /*GILLT_nxv2s8*//*Label 4891*/ 142125,
    /*GILLT_nxv2s16*//*Label 4892*/ 142209,
    /*GILLT_nxv2s32*//*Label 4893*/ 142293,
    /*GILLT_nxv2s64*//*Label 4894*/ 142377, 0,
    /*GILLT_nxv4s8*//*Label 4895*/ 142461,
    /*GILLT_nxv4s16*//*Label 4896*/ 142545,
    /*GILLT_nxv4s32*//*Label 4897*/ 142629,
    /*GILLT_nxv4s64*//*Label 4898*/ 142713, 0,
    /*GILLT_nxv8s8*//*Label 4899*/ 142797,
    /*GILLT_nxv8s16*//*Label 4900*/ 142881,
    /*GILLT_nxv8s32*//*Label 4901*/ 142965,
    /*GILLT_nxv8s64*//*Label 4902*/ 143049, 0,
    /*GILLT_nxv16s8*//*Label 4903*/ 143133,
    /*GILLT_nxv16s16*//*Label 4904*/ 143217,
    /*GILLT_nxv16s32*//*Label 4905*/ 143301, 0,
    /*GILLT_nxv32s8*//*Label 4906*/ 143385,
    /*GILLT_nxv32s16*//*Label 4907*/ 143469, 0,
    /*GILLT_nxv64s8*//*Label 4908*/ 143553,
    // Label 4885: @141725
    GIM_Try, /*On fail goto*//*Label 4910*/ 141756, // Rule ID 65508 //
      GIM_CheckFeatures, GIFBS_HasStdExtZbb,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
      // (smax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (MAX:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MAX,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65508,
      GIR_Done,
    // Label 4910: @141756
    GIM_Reject,
    // Label 4886: @141757
    GIM_Try, /*On fail goto*//*Label 4911*/ 141788, // Rule ID 65507 //
      GIM_CheckFeatures, GIFBS_HasStdExtZbb,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
      // (smax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (MAX:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MAX,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65507,
      GIR_Done,
    // Label 4911: @141788
    GIM_Reject,
    // Label 4887: @141789
    GIM_Try, /*On fail goto*//*Label 4912*/ 141872,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4913*/ 141841, // Rule ID 59413 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVMAX_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59413,
        GIR_Done,
      // Label 4913: @141841
      GIM_Try, /*On fail goto*//*Label 4914*/ 141871, // Rule ID 59414 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVMAX_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59414,
        GIR_Done,
      // Label 4914: @141871
      GIM_Reject,
    // Label 4912: @141872
    GIM_Reject,
    // Label 4888: @141873
    GIM_Try, /*On fail goto*//*Label 4915*/ 141956,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4916*/ 141925, // Rule ID 59425 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVMAX_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59425,
        GIR_Done,
      // Label 4916: @141925
      GIM_Try, /*On fail goto*//*Label 4917*/ 141955, // Rule ID 59426 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVMAX_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59426,
        GIR_Done,
      // Label 4917: @141955
      GIM_Reject,
    // Label 4915: @141956
    GIM_Reject,
    // Label 4889: @141957
    GIM_Try, /*On fail goto*//*Label 4918*/ 142040,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4919*/ 142009, // Rule ID 59433 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVMAX_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59433,
        GIR_Done,
      // Label 4919: @142009
      GIM_Try, /*On fail goto*//*Label 4920*/ 142039, // Rule ID 59434 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVMAX_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59434,
        GIR_Done,
      // Label 4920: @142039
      GIM_Reject,
    // Label 4918: @142040
    GIM_Reject,
    // Label 4890: @142041
    GIM_Try, /*On fail goto*//*Label 4921*/ 142124,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4922*/ 142093, // Rule ID 59449 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVMAX_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59449,
        GIR_Done,
      // Label 4922: @142093
      GIM_Try, /*On fail goto*//*Label 4923*/ 142123, // Rule ID 59450 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVMAX_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59450,
        GIR_Done,
      // Label 4923: @142123
      GIM_Reject,
    // Label 4921: @142124
    GIM_Reject,
    // Label 4891: @142125
    GIM_Try, /*On fail goto*//*Label 4924*/ 142208,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4925*/ 142177, // Rule ID 59417 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVMAX_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59417,
        GIR_Done,
      // Label 4925: @142177
      GIM_Try, /*On fail goto*//*Label 4926*/ 142207, // Rule ID 59418 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVMAX_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59418,
        GIR_Done,
      // Label 4926: @142207
      GIM_Reject,
    // Label 4924: @142208
    GIM_Reject,
    // Label 4892: @142209
    GIM_Try, /*On fail goto*//*Label 4927*/ 142292,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4928*/ 142261, // Rule ID 59429 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVMAX_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59429,
        GIR_Done,
      // Label 4928: @142261
      GIM_Try, /*On fail goto*//*Label 4929*/ 142291, // Rule ID 59430 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVMAX_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59430,
        GIR_Done,
      // Label 4929: @142291
      GIM_Reject,
    // Label 4927: @142292
    GIM_Reject,
    // Label 4893: @142293
    GIM_Try, /*On fail goto*//*Label 4930*/ 142376,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4931*/ 142345, // Rule ID 59445 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVMAX_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59445,
        GIR_Done,
      // Label 4931: @142345
      GIM_Try, /*On fail goto*//*Label 4932*/ 142375, // Rule ID 59446 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVMAX_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59446,
        GIR_Done,
      // Label 4932: @142375
      GIM_Reject,
    // Label 4930: @142376
    GIM_Reject,
    // Label 4894: @142377
    GIM_Try, /*On fail goto*//*Label 4933*/ 142460,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4934*/ 142429, // Rule ID 59489 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVMAX_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59489,
        GIR_Done,
      // Label 4934: @142429
      GIM_Try, /*On fail goto*//*Label 4935*/ 142459, // Rule ID 59490 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVMAX_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59490,
        GIR_Done,
      // Label 4935: @142459
      GIM_Reject,
    // Label 4933: @142460
    GIM_Reject,
    // Label 4895: @142461
    GIM_Try, /*On fail goto*//*Label 4936*/ 142544,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4937*/ 142513, // Rule ID 59421 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVMAX_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59421,
        GIR_Done,
      // Label 4937: @142513
      GIM_Try, /*On fail goto*//*Label 4938*/ 142543, // Rule ID 59422 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVMAX_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59422,
        GIR_Done,
      // Label 4938: @142543
      GIM_Reject,
    // Label 4936: @142544
    GIM_Reject,
    // Label 4896: @142545
    GIM_Try, /*On fail goto*//*Label 4939*/ 142628,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4940*/ 142597, // Rule ID 59441 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVMAX_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59441,
        GIR_Done,
      // Label 4940: @142597
      GIM_Try, /*On fail goto*//*Label 4941*/ 142627, // Rule ID 59442 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVMAX_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59442,
        GIR_Done,
      // Label 4941: @142627
      GIM_Reject,
    // Label 4939: @142628
    GIM_Reject,
    // Label 4897: @142629
    GIM_Try, /*On fail goto*//*Label 4942*/ 142712,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4943*/ 142681, // Rule ID 59477 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVMAX_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59477,
        GIR_Done,
      // Label 4943: @142681
      GIM_Try, /*On fail goto*//*Label 4944*/ 142711, // Rule ID 59478 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVMAX_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59478,
        GIR_Done,
      // Label 4944: @142711
      GIM_Reject,
    // Label 4942: @142712
    GIM_Reject,
    // Label 4898: @142713
    GIM_Try, /*On fail goto*//*Label 4945*/ 142796,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4946*/ 142765, // Rule ID 59493 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVMAX_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59493,
        GIR_Done,
      // Label 4946: @142765
      GIM_Try, /*On fail goto*//*Label 4947*/ 142795, // Rule ID 59494 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVMAX_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59494,
        GIR_Done,
      // Label 4947: @142795
      GIM_Reject,
    // Label 4945: @142796
    GIM_Reject,
    // Label 4899: @142797
    GIM_Try, /*On fail goto*//*Label 4948*/ 142880,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 4949*/ 142849, // Rule ID 59437 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVMAX_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59437,
        GIR_Done,
      // Label 4949: @142849
      GIM_Try, /*On fail goto*//*Label 4950*/ 142879, // Rule ID 59438 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVMAX_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59438,
        GIR_Done,
      // Label 4950: @142879
      GIM_Reject,
    // Label 4948: @142880
    GIM_Reject,
    // Label 4900: @142881
    GIM_Try, /*On fail goto*//*Label 4951*/ 142964,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4952*/ 142933, // Rule ID 59465 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVMAX_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59465,
        GIR_Done,
      // Label 4952: @142933
      GIM_Try, /*On fail goto*//*Label 4953*/ 142963, // Rule ID 59466 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVMAX_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59466,
        GIR_Done,
      // Label 4953: @142963
      GIM_Reject,
    // Label 4951: @142964
    GIM_Reject,
    // Label 4901: @142965
    GIM_Try, /*On fail goto*//*Label 4954*/ 143048,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4955*/ 143017, // Rule ID 59481 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVMAX_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59481,
        GIR_Done,
      // Label 4955: @143017
      GIM_Try, /*On fail goto*//*Label 4956*/ 143047, // Rule ID 59482 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVMAX_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59482,
        GIR_Done,
      // Label 4956: @143047
      GIM_Reject,
    // Label 4954: @143048
    GIM_Reject,
    // Label 4902: @143049
    GIM_Try, /*On fail goto*//*Label 4957*/ 143132,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4958*/ 143101, // Rule ID 59497 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVMAX_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59497,
        GIR_Done,
      // Label 4958: @143101
      GIM_Try, /*On fail goto*//*Label 4959*/ 143131, // Rule ID 59498 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVMAX_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59498,
        GIR_Done,
      // Label 4959: @143131
      GIM_Reject,
    // Label 4957: @143132
    GIM_Reject,
    // Label 4903: @143133
    GIM_Try, /*On fail goto*//*Label 4960*/ 143216,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 4961*/ 143185, // Rule ID 59453 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVMAX_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59453,
        GIR_Done,
      // Label 4961: @143185
      GIM_Try, /*On fail goto*//*Label 4962*/ 143215, // Rule ID 59454 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVMAX_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59454,
        GIR_Done,
      // Label 4962: @143215
      GIM_Reject,
    // Label 4960: @143216
    GIM_Reject,
    // Label 4904: @143217
    GIM_Try, /*On fail goto*//*Label 4963*/ 143300,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4964*/ 143269, // Rule ID 59469 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVMAX_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59469,
        GIR_Done,
      // Label 4964: @143269
      GIM_Try, /*On fail goto*//*Label 4965*/ 143299, // Rule ID 59470 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVMAX_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59470,
        GIR_Done,
      // Label 4965: @143299
      GIM_Reject,
    // Label 4963: @143300
    GIM_Reject,
    // Label 4905: @143301
    GIM_Try, /*On fail goto*//*Label 4966*/ 143384,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4967*/ 143353, // Rule ID 59485 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVMAX_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59485,
        GIR_Done,
      // Label 4967: @143353
      GIM_Try, /*On fail goto*//*Label 4968*/ 143383, // Rule ID 59486 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVMAX_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59486,
        GIR_Done,
      // Label 4968: @143383
      GIM_Reject,
    // Label 4966: @143384
    GIM_Reject,
    // Label 4906: @143385
    GIM_Try, /*On fail goto*//*Label 4969*/ 143468,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 4970*/ 143437, // Rule ID 59457 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVMAX_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59457,
        GIR_Done,
      // Label 4970: @143437
      GIM_Try, /*On fail goto*//*Label 4971*/ 143467, // Rule ID 59458 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVMAX_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59458,
        GIR_Done,
      // Label 4971: @143467
      GIM_Reject,
    // Label 4969: @143468
    GIM_Reject,
    // Label 4907: @143469
    GIM_Try, /*On fail goto*//*Label 4972*/ 143552,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4973*/ 143521, // Rule ID 59473 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVMAX_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59473,
        GIR_Done,
      // Label 4973: @143521
      GIM_Try, /*On fail goto*//*Label 4974*/ 143551, // Rule ID 59474 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVMAX_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59474,
        GIR_Done,
      // Label 4974: @143551
      GIM_Reject,
    // Label 4972: @143552
    GIM_Reject,
    // Label 4908: @143553
    GIM_Try, /*On fail goto*//*Label 4975*/ 143636,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv64s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 4976*/ 143605, // Rule ID 59461 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVMAX_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59461,
        GIR_Done,
      // Label 4976: @143605
      GIM_Try, /*On fail goto*//*Label 4977*/ 143635, // Rule ID 59462 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (smax:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVMAX_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAX_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59462,
        GIR_Done,
      // Label 4977: @143635
      GIM_Reject,
    // Label 4975: @143636
    GIM_Reject,
    // Label 4909: @143637
    GIM_Reject,
    // Label 63: @143638
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 32, /*)*//*default:*//*Label 5002*/ 145587,
    /*GILLT_s32*//*Label 4978*/ 143675,
    /*GILLT_s64*//*Label 4979*/ 143707, 0,
    /*GILLT_nxv1s8*//*Label 4980*/ 143739,
    /*GILLT_nxv1s16*//*Label 4981*/ 143823,
    /*GILLT_nxv1s32*//*Label 4982*/ 143907,
    /*GILLT_nxv1s64*//*Label 4983*/ 143991, 0,
    /*GILLT_nxv2s8*//*Label 4984*/ 144075,
    /*GILLT_nxv2s16*//*Label 4985*/ 144159,
    /*GILLT_nxv2s32*//*Label 4986*/ 144243,
    /*GILLT_nxv2s64*//*Label 4987*/ 144327, 0,
    /*GILLT_nxv4s8*//*Label 4988*/ 144411,
    /*GILLT_nxv4s16*//*Label 4989*/ 144495,
    /*GILLT_nxv4s32*//*Label 4990*/ 144579,
    /*GILLT_nxv4s64*//*Label 4991*/ 144663, 0,
    /*GILLT_nxv8s8*//*Label 4992*/ 144747,
    /*GILLT_nxv8s16*//*Label 4993*/ 144831,
    /*GILLT_nxv8s32*//*Label 4994*/ 144915,
    /*GILLT_nxv8s64*//*Label 4995*/ 144999, 0,
    /*GILLT_nxv16s8*//*Label 4996*/ 145083,
    /*GILLT_nxv16s16*//*Label 4997*/ 145167,
    /*GILLT_nxv16s32*//*Label 4998*/ 145251, 0,
    /*GILLT_nxv32s8*//*Label 4999*/ 145335,
    /*GILLT_nxv32s16*//*Label 5000*/ 145419, 0,
    /*GILLT_nxv64s8*//*Label 5001*/ 145503,
    // Label 4978: @143675
    GIM_Try, /*On fail goto*//*Label 5003*/ 143706, // Rule ID 65510 //
      GIM_CheckFeatures, GIFBS_HasStdExtZbb,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
      // (umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (MINU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MINU,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65510,
      GIR_Done,
    // Label 5003: @143706
    GIM_Reject,
    // Label 4979: @143707
    GIM_Try, /*On fail goto*//*Label 5004*/ 143738, // Rule ID 65509 //
      GIM_CheckFeatures, GIFBS_HasStdExtZbb,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
      // (umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (MINU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MINU,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65509,
      GIR_Done,
    // Label 5004: @143738
    GIM_Reject,
    // Label 4980: @143739
    GIM_Try, /*On fail goto*//*Label 5005*/ 143822,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 5006*/ 143791, // Rule ID 59149 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVMINU_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59149,
        GIR_Done,
      // Label 5006: @143791
      GIM_Try, /*On fail goto*//*Label 5007*/ 143821, // Rule ID 59150 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVMINU_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59150,
        GIR_Done,
      // Label 5007: @143821
      GIM_Reject,
    // Label 5005: @143822
    GIM_Reject,
    // Label 4981: @143823
    GIM_Try, /*On fail goto*//*Label 5008*/ 143906,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 5009*/ 143875, // Rule ID 59161 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVMINU_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59161,
        GIR_Done,
      // Label 5009: @143875
      GIM_Try, /*On fail goto*//*Label 5010*/ 143905, // Rule ID 59162 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVMINU_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59162,
        GIR_Done,
      // Label 5010: @143905
      GIM_Reject,
    // Label 5008: @143906
    GIM_Reject,
    // Label 4982: @143907
    GIM_Try, /*On fail goto*//*Label 5011*/ 143990,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 5012*/ 143959, // Rule ID 59169 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVMINU_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59169,
        GIR_Done,
      // Label 5012: @143959
      GIM_Try, /*On fail goto*//*Label 5013*/ 143989, // Rule ID 59170 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVMINU_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59170,
        GIR_Done,
      // Label 5013: @143989
      GIM_Reject,
    // Label 5011: @143990
    GIM_Reject,
    // Label 4983: @143991
    GIM_Try, /*On fail goto*//*Label 5014*/ 144074,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 5015*/ 144043, // Rule ID 59185 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVMINU_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59185,
        GIR_Done,
      // Label 5015: @144043
      GIM_Try, /*On fail goto*//*Label 5016*/ 144073, // Rule ID 59186 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVMINU_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59186,
        GIR_Done,
      // Label 5016: @144073
      GIM_Reject,
    // Label 5014: @144074
    GIM_Reject,
    // Label 4984: @144075
    GIM_Try, /*On fail goto*//*Label 5017*/ 144158,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 5018*/ 144127, // Rule ID 59153 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVMINU_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59153,
        GIR_Done,
      // Label 5018: @144127
      GIM_Try, /*On fail goto*//*Label 5019*/ 144157, // Rule ID 59154 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVMINU_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59154,
        GIR_Done,
      // Label 5019: @144157
      GIM_Reject,
    // Label 5017: @144158
    GIM_Reject,
    // Label 4985: @144159
    GIM_Try, /*On fail goto*//*Label 5020*/ 144242,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 5021*/ 144211, // Rule ID 59165 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVMINU_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59165,
        GIR_Done,
      // Label 5021: @144211
      GIM_Try, /*On fail goto*//*Label 5022*/ 144241, // Rule ID 59166 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVMINU_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59166,
        GIR_Done,
      // Label 5022: @144241
      GIM_Reject,
    // Label 5020: @144242
    GIM_Reject,
    // Label 4986: @144243
    GIM_Try, /*On fail goto*//*Label 5023*/ 144326,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 5024*/ 144295, // Rule ID 59181 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVMINU_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59181,
        GIR_Done,
      // Label 5024: @144295
      GIM_Try, /*On fail goto*//*Label 5025*/ 144325, // Rule ID 59182 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVMINU_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59182,
        GIR_Done,
      // Label 5025: @144325
      GIM_Reject,
    // Label 5023: @144326
    GIM_Reject,
    // Label 4987: @144327
    GIM_Try, /*On fail goto*//*Label 5026*/ 144410,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 5027*/ 144379, // Rule ID 59225 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVMINU_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59225,
        GIR_Done,
      // Label 5027: @144379
      GIM_Try, /*On fail goto*//*Label 5028*/ 144409, // Rule ID 59226 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVMINU_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59226,
        GIR_Done,
      // Label 5028: @144409
      GIM_Reject,
    // Label 5026: @144410
    GIM_Reject,
    // Label 4988: @144411
    GIM_Try, /*On fail goto*//*Label 5029*/ 144494,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 5030*/ 144463, // Rule ID 59157 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVMINU_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59157,
        GIR_Done,
      // Label 5030: @144463
      GIM_Try, /*On fail goto*//*Label 5031*/ 144493, // Rule ID 59158 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVMINU_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59158,
        GIR_Done,
      // Label 5031: @144493
      GIM_Reject,
    // Label 5029: @144494
    GIM_Reject,
    // Label 4989: @144495
    GIM_Try, /*On fail goto*//*Label 5032*/ 144578,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 5033*/ 144547, // Rule ID 59177 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVMINU_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59177,
        GIR_Done,
      // Label 5033: @144547
      GIM_Try, /*On fail goto*//*Label 5034*/ 144577, // Rule ID 59178 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVMINU_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59178,
        GIR_Done,
      // Label 5034: @144577
      GIM_Reject,
    // Label 5032: @144578
    GIM_Reject,
    // Label 4990: @144579
    GIM_Try, /*On fail goto*//*Label 5035*/ 144662,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 5036*/ 144631, // Rule ID 59213 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVMINU_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59213,
        GIR_Done,
      // Label 5036: @144631
      GIM_Try, /*On fail goto*//*Label 5037*/ 144661, // Rule ID 59214 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVMINU_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59214,
        GIR_Done,
      // Label 5037: @144661
      GIM_Reject,
    // Label 5035: @144662
    GIM_Reject,
    // Label 4991: @144663
    GIM_Try, /*On fail goto*//*Label 5038*/ 144746,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 5039*/ 144715, // Rule ID 59229 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVMINU_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59229,
        GIR_Done,
      // Label 5039: @144715
      GIM_Try, /*On fail goto*//*Label 5040*/ 144745, // Rule ID 59230 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVMINU_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59230,
        GIR_Done,
      // Label 5040: @144745
      GIM_Reject,
    // Label 5038: @144746
    GIM_Reject,
    // Label 4992: @144747
    GIM_Try, /*On fail goto*//*Label 5041*/ 144830,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 5042*/ 144799, // Rule ID 59173 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVMINU_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59173,
        GIR_Done,
      // Label 5042: @144799
      GIM_Try, /*On fail goto*//*Label 5043*/ 144829, // Rule ID 59174 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVMINU_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59174,
        GIR_Done,
      // Label 5043: @144829
      GIM_Reject,
    // Label 5041: @144830
    GIM_Reject,
    // Label 4993: @144831
    GIM_Try, /*On fail goto*//*Label 5044*/ 144914,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 5045*/ 144883, // Rule ID 59201 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVMINU_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59201,
        GIR_Done,
      // Label 5045: @144883
      GIM_Try, /*On fail goto*//*Label 5046*/ 144913, // Rule ID 59202 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVMINU_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59202,
        GIR_Done,
      // Label 5046: @144913
      GIM_Reject,
    // Label 5044: @144914
    GIM_Reject,
    // Label 4994: @144915
    GIM_Try, /*On fail goto*//*Label 5047*/ 144998,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 5048*/ 144967, // Rule ID 59217 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVMINU_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59217,
        GIR_Done,
      // Label 5048: @144967
      GIM_Try, /*On fail goto*//*Label 5049*/ 144997, // Rule ID 59218 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVMINU_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59218,
        GIR_Done,
      // Label 5049: @144997
      GIM_Reject,
    // Label 5047: @144998
    GIM_Reject,
    // Label 4995: @144999
    GIM_Try, /*On fail goto*//*Label 5050*/ 145082,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 5051*/ 145051, // Rule ID 59233 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVMINU_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59233,
        GIR_Done,
      // Label 5051: @145051
      GIM_Try, /*On fail goto*//*Label 5052*/ 145081, // Rule ID 59234 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVMINU_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59234,
        GIR_Done,
      // Label 5052: @145081
      GIM_Reject,
    // Label 5050: @145082
    GIM_Reject,
    // Label 4996: @145083
    GIM_Try, /*On fail goto*//*Label 5053*/ 145166,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 5054*/ 145135, // Rule ID 59189 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVMINU_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59189,
        GIR_Done,
      // Label 5054: @145135
      GIM_Try, /*On fail goto*//*Label 5055*/ 145165, // Rule ID 59190 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVMINU_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59190,
        GIR_Done,
      // Label 5055: @145165
      GIM_Reject,
    // Label 5053: @145166
    GIM_Reject,
    // Label 4997: @145167
    GIM_Try, /*On fail goto*//*Label 5056*/ 145250,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 5057*/ 145219, // Rule ID 59205 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVMINU_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59205,
        GIR_Done,
      // Label 5057: @145219
      GIM_Try, /*On fail goto*//*Label 5058*/ 145249, // Rule ID 59206 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVMINU_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59206,
        GIR_Done,
      // Label 5058: @145249
      GIM_Reject,
    // Label 5056: @145250
    GIM_Reject,
    // Label 4998: @145251
    GIM_Try, /*On fail goto*//*Label 5059*/ 145334,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 5060*/ 145303, // Rule ID 59221 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVMINU_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59221,
        GIR_Done,
      // Label 5060: @145303
      GIM_Try, /*On fail goto*//*Label 5061*/ 145333, // Rule ID 59222 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVMINU_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59222,
        GIR_Done,
      // Label 5061: @145333
      GIM_Reject,
    // Label 5059: @145334
    GIM_Reject,
    // Label 4999: @145335
    GIM_Try, /*On fail goto*//*Label 5062*/ 145418,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 5063*/ 145387, // Rule ID 59193 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVMINU_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59193,
        GIR_Done,
      // Label 5063: @145387
      GIM_Try, /*On fail goto*//*Label 5064*/ 145417, // Rule ID 59194 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVMINU_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59194,
        GIR_Done,
      // Label 5064: @145417
      GIM_Reject,
    // Label 5062: @145418
    GIM_Reject,
    // Label 5000: @145419
    GIM_Try, /*On fail goto*//*Label 5065*/ 145502,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 5066*/ 145471, // Rule ID 59209 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVMINU_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59209,
        GIR_Done,
      // Label 5066: @145471
      GIM_Try, /*On fail goto*//*Label 5067*/ 145501, // Rule ID 59210 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVMINU_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59210,
        GIR_Done,
      // Label 5067: @145501
      GIM_Reject,
    // Label 5065: @145502
    GIM_Reject,
    // Label 5001: @145503
    GIM_Try, /*On fail goto*//*Label 5068*/ 145586,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv64s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 5069*/ 145555, // Rule ID 59197 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVMINU_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59197,
        GIR_Done,
      // Label 5069: @145555
      GIM_Try, /*On fail goto*//*Label 5070*/ 145585, // Rule ID 59198 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umin:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVMINU_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMINU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59198,
        GIR_Done,
      // Label 5070: @145585
      GIM_Reject,
    // Label 5068: @145586
    GIM_Reject,
    // Label 5002: @145587
    GIM_Reject,
    // Label 64: @145588
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 32, /*)*//*default:*//*Label 5095*/ 147537,
    /*GILLT_s32*//*Label 5071*/ 145625,
    /*GILLT_s64*//*Label 5072*/ 145657, 0,
    /*GILLT_nxv1s8*//*Label 5073*/ 145689,
    /*GILLT_nxv1s16*//*Label 5074*/ 145773,
    /*GILLT_nxv1s32*//*Label 5075*/ 145857,
    /*GILLT_nxv1s64*//*Label 5076*/ 145941, 0,
    /*GILLT_nxv2s8*//*Label 5077*/ 146025,
    /*GILLT_nxv2s16*//*Label 5078*/ 146109,
    /*GILLT_nxv2s32*//*Label 5079*/ 146193,
    /*GILLT_nxv2s64*//*Label 5080*/ 146277, 0,
    /*GILLT_nxv4s8*//*Label 5081*/ 146361,
    /*GILLT_nxv4s16*//*Label 5082*/ 146445,
    /*GILLT_nxv4s32*//*Label 5083*/ 146529,
    /*GILLT_nxv4s64*//*Label 5084*/ 146613, 0,
    /*GILLT_nxv8s8*//*Label 5085*/ 146697,
    /*GILLT_nxv8s16*//*Label 5086*/ 146781,
    /*GILLT_nxv8s32*//*Label 5087*/ 146865,
    /*GILLT_nxv8s64*//*Label 5088*/ 146949, 0,
    /*GILLT_nxv16s8*//*Label 5089*/ 147033,
    /*GILLT_nxv16s16*//*Label 5090*/ 147117,
    /*GILLT_nxv16s32*//*Label 5091*/ 147201, 0,
    /*GILLT_nxv32s8*//*Label 5092*/ 147285,
    /*GILLT_nxv32s16*//*Label 5093*/ 147369, 0,
    /*GILLT_nxv64s8*//*Label 5094*/ 147453,
    // Label 5071: @145625
    GIM_Try, /*On fail goto*//*Label 5096*/ 145656, // Rule ID 65512 //
      GIM_CheckFeatures, GIFBS_HasStdExtZbb,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
      // (umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)  =>  (MAXU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MAXU,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65512,
      GIR_Done,
    // Label 5096: @145656
    GIM_Reject,
    // Label 5072: @145657
    GIM_Try, /*On fail goto*//*Label 5097*/ 145688, // Rule ID 65511 //
      GIM_CheckFeatures, GIFBS_HasStdExtZbb,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
      // (umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)  =>  (MAXU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MAXU,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65511,
      GIR_Done,
    // Label 5097: @145688
    GIM_Reject,
    // Label 5073: @145689
    GIM_Try, /*On fail goto*//*Label 5098*/ 145772,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 5099*/ 145741, // Rule ID 59325 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVMAXU_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59325,
        GIR_Done,
      // Label 5099: @145741
      GIM_Try, /*On fail goto*//*Label 5100*/ 145771, // Rule ID 59326 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2)  =>  (PseudoVMAXU_VV_MF8:{ *:[nxv1i8] } VR:{ *:[nxv1i8] }:$rs1, VR:{ *:[nxv1i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_MF8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59326,
        GIR_Done,
      // Label 5100: @145771
      GIM_Reject,
    // Label 5098: @145772
    GIM_Reject,
    // Label 5074: @145773
    GIM_Try, /*On fail goto*//*Label 5101*/ 145856,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 5102*/ 145825, // Rule ID 59337 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVMAXU_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59337,
        GIR_Done,
      // Label 5102: @145825
      GIM_Try, /*On fail goto*//*Label 5103*/ 145855, // Rule ID 59338 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2)  =>  (PseudoVMAXU_VV_MF4:{ *:[nxv1i16] } VR:{ *:[nxv1i16] }:$rs1, VR:{ *:[nxv1i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59338,
        GIR_Done,
      // Label 5103: @145855
      GIM_Reject,
    // Label 5101: @145856
    GIM_Reject,
    // Label 5075: @145857
    GIM_Try, /*On fail goto*//*Label 5104*/ 145940,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 5105*/ 145909, // Rule ID 59345 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVMAXU_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59345,
        GIR_Done,
      // Label 5105: @145909
      GIM_Try, /*On fail goto*//*Label 5106*/ 145939, // Rule ID 59346 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2)  =>  (PseudoVMAXU_VV_MF2:{ *:[nxv1i32] } VR:{ *:[nxv1i32] }:$rs1, VR:{ *:[nxv1i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59346,
        GIR_Done,
      // Label 5106: @145939
      GIM_Reject,
    // Label 5104: @145940
    GIM_Reject,
    // Label 5076: @145941
    GIM_Try, /*On fail goto*//*Label 5107*/ 146024,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 5108*/ 145993, // Rule ID 59361 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVMAXU_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59361,
        GIR_Done,
      // Label 5108: @145993
      GIM_Try, /*On fail goto*//*Label 5109*/ 146023, // Rule ID 59362 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2)  =>  (PseudoVMAXU_VV_M1:{ *:[nxv1i64] } VR:{ *:[nxv1i64] }:$rs1, VR:{ *:[nxv1i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59362,
        GIR_Done,
      // Label 5109: @146023
      GIM_Reject,
    // Label 5107: @146024
    GIM_Reject,
    // Label 5077: @146025
    GIM_Try, /*On fail goto*//*Label 5110*/ 146108,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 5111*/ 146077, // Rule ID 59329 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVMAXU_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59329,
        GIR_Done,
      // Label 5111: @146077
      GIM_Try, /*On fail goto*//*Label 5112*/ 146107, // Rule ID 59330 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2)  =>  (PseudoVMAXU_VV_MF4:{ *:[nxv2i8] } VR:{ *:[nxv2i8] }:$rs1, VR:{ *:[nxv2i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59330,
        GIR_Done,
      // Label 5112: @146107
      GIM_Reject,
    // Label 5110: @146108
    GIM_Reject,
    // Label 5078: @146109
    GIM_Try, /*On fail goto*//*Label 5113*/ 146192,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 5114*/ 146161, // Rule ID 59341 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVMAXU_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59341,
        GIR_Done,
      // Label 5114: @146161
      GIM_Try, /*On fail goto*//*Label 5115*/ 146191, // Rule ID 59342 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2)  =>  (PseudoVMAXU_VV_MF2:{ *:[nxv2i16] } VR:{ *:[nxv2i16] }:$rs1, VR:{ *:[nxv2i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59342,
        GIR_Done,
      // Label 5115: @146191
      GIM_Reject,
    // Label 5113: @146192
    GIM_Reject,
    // Label 5079: @146193
    GIM_Try, /*On fail goto*//*Label 5116*/ 146276,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 5117*/ 146245, // Rule ID 59357 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVMAXU_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59357,
        GIR_Done,
      // Label 5117: @146245
      GIM_Try, /*On fail goto*//*Label 5118*/ 146275, // Rule ID 59358 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2)  =>  (PseudoVMAXU_VV_M1:{ *:[nxv2i32] } VR:{ *:[nxv2i32] }:$rs1, VR:{ *:[nxv2i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59358,
        GIR_Done,
      // Label 5118: @146275
      GIM_Reject,
    // Label 5116: @146276
    GIM_Reject,
    // Label 5080: @146277
    GIM_Try, /*On fail goto*//*Label 5119*/ 146360,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 5120*/ 146329, // Rule ID 59401 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVMAXU_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59401,
        GIR_Done,
      // Label 5120: @146329
      GIM_Try, /*On fail goto*//*Label 5121*/ 146359, // Rule ID 59402 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2)  =>  (PseudoVMAXU_VV_M2:{ *:[nxv2i64] } VRM2:{ *:[nxv2i64] }:$rs1, VRM2:{ *:[nxv2i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59402,
        GIR_Done,
      // Label 5121: @146359
      GIM_Reject,
    // Label 5119: @146360
    GIM_Reject,
    // Label 5081: @146361
    GIM_Try, /*On fail goto*//*Label 5122*/ 146444,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 5123*/ 146413, // Rule ID 59333 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVMAXU_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59333,
        GIR_Done,
      // Label 5123: @146413
      GIM_Try, /*On fail goto*//*Label 5124*/ 146443, // Rule ID 59334 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2)  =>  (PseudoVMAXU_VV_MF2:{ *:[nxv4i8] } VR:{ *:[nxv4i8] }:$rs1, VR:{ *:[nxv4i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59334,
        GIR_Done,
      // Label 5124: @146443
      GIM_Reject,
    // Label 5122: @146444
    GIM_Reject,
    // Label 5082: @146445
    GIM_Try, /*On fail goto*//*Label 5125*/ 146528,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 5126*/ 146497, // Rule ID 59353 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVMAXU_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59353,
        GIR_Done,
      // Label 5126: @146497
      GIM_Try, /*On fail goto*//*Label 5127*/ 146527, // Rule ID 59354 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2)  =>  (PseudoVMAXU_VV_M1:{ *:[nxv4i16] } VR:{ *:[nxv4i16] }:$rs1, VR:{ *:[nxv4i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59354,
        GIR_Done,
      // Label 5127: @146527
      GIM_Reject,
    // Label 5125: @146528
    GIM_Reject,
    // Label 5083: @146529
    GIM_Try, /*On fail goto*//*Label 5128*/ 146612,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 5129*/ 146581, // Rule ID 59389 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVMAXU_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59389,
        GIR_Done,
      // Label 5129: @146581
      GIM_Try, /*On fail goto*//*Label 5130*/ 146611, // Rule ID 59390 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2)  =>  (PseudoVMAXU_VV_M2:{ *:[nxv4i32] } VRM2:{ *:[nxv4i32] }:$rs1, VRM2:{ *:[nxv4i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59390,
        GIR_Done,
      // Label 5130: @146611
      GIM_Reject,
    // Label 5128: @146612
    GIM_Reject,
    // Label 5084: @146613
    GIM_Try, /*On fail goto*//*Label 5131*/ 146696,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 5132*/ 146665, // Rule ID 59405 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVMAXU_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59405,
        GIR_Done,
      // Label 5132: @146665
      GIM_Try, /*On fail goto*//*Label 5133*/ 146695, // Rule ID 59406 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2)  =>  (PseudoVMAXU_VV_M4:{ *:[nxv4i64] } VRM4:{ *:[nxv4i64] }:$rs1, VRM4:{ *:[nxv4i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59406,
        GIR_Done,
      // Label 5133: @146695
      GIM_Reject,
    // Label 5131: @146696
    GIM_Reject,
    // Label 5085: @146697
    GIM_Try, /*On fail goto*//*Label 5134*/ 146780,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 5135*/ 146749, // Rule ID 59349 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVMAXU_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59349,
        GIR_Done,
      // Label 5135: @146749
      GIM_Try, /*On fail goto*//*Label 5136*/ 146779, // Rule ID 59350 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2)  =>  (PseudoVMAXU_VV_M1:{ *:[nxv8i8] } VR:{ *:[nxv8i8] }:$rs1, VR:{ *:[nxv8i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59350,
        GIR_Done,
      // Label 5136: @146779
      GIM_Reject,
    // Label 5134: @146780
    GIM_Reject,
    // Label 5086: @146781
    GIM_Try, /*On fail goto*//*Label 5137*/ 146864,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 5138*/ 146833, // Rule ID 59377 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVMAXU_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59377,
        GIR_Done,
      // Label 5138: @146833
      GIM_Try, /*On fail goto*//*Label 5139*/ 146863, // Rule ID 59378 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2)  =>  (PseudoVMAXU_VV_M2:{ *:[nxv8i16] } VRM2:{ *:[nxv8i16] }:$rs1, VRM2:{ *:[nxv8i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59378,
        GIR_Done,
      // Label 5139: @146863
      GIM_Reject,
    // Label 5137: @146864
    GIM_Reject,
    // Label 5087: @146865
    GIM_Try, /*On fail goto*//*Label 5140*/ 146948,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 5141*/ 146917, // Rule ID 59393 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVMAXU_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59393,
        GIR_Done,
      // Label 5141: @146917
      GIM_Try, /*On fail goto*//*Label 5142*/ 146947, // Rule ID 59394 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2)  =>  (PseudoVMAXU_VV_M4:{ *:[nxv8i32] } VRM4:{ *:[nxv8i32] }:$rs1, VRM4:{ *:[nxv8i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59394,
        GIR_Done,
      // Label 5142: @146947
      GIM_Reject,
    // Label 5140: @146948
    GIM_Reject,
    // Label 5088: @146949
    GIM_Try, /*On fail goto*//*Label 5143*/ 147032,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 5144*/ 147001, // Rule ID 59409 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVMAXU_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59409,
        GIR_Done,
      // Label 5144: @147001
      GIM_Try, /*On fail goto*//*Label 5145*/ 147031, // Rule ID 59410 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2)  =>  (PseudoVMAXU_VV_M8:{ *:[nxv8i64] } VRM8:{ *:[nxv8i64] }:$rs1, VRM8:{ *:[nxv8i64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59410,
        GIR_Done,
      // Label 5145: @147031
      GIM_Reject,
    // Label 5143: @147032
    GIM_Reject,
    // Label 5089: @147033
    GIM_Try, /*On fail goto*//*Label 5146*/ 147116,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 5147*/ 147085, // Rule ID 59365 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVMAXU_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59365,
        GIR_Done,
      // Label 5147: @147085
      GIM_Try, /*On fail goto*//*Label 5148*/ 147115, // Rule ID 59366 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2)  =>  (PseudoVMAXU_VV_M2:{ *:[nxv16i8] } VRM2:{ *:[nxv16i8] }:$rs1, VRM2:{ *:[nxv16i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59366,
        GIR_Done,
      // Label 5148: @147115
      GIM_Reject,
    // Label 5146: @147116
    GIM_Reject,
    // Label 5090: @147117
    GIM_Try, /*On fail goto*//*Label 5149*/ 147200,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 5150*/ 147169, // Rule ID 59381 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVMAXU_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59381,
        GIR_Done,
      // Label 5150: @147169
      GIM_Try, /*On fail goto*//*Label 5151*/ 147199, // Rule ID 59382 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2)  =>  (PseudoVMAXU_VV_M4:{ *:[nxv16i16] } VRM4:{ *:[nxv16i16] }:$rs1, VRM4:{ *:[nxv16i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59382,
        GIR_Done,
      // Label 5151: @147199
      GIM_Reject,
    // Label 5149: @147200
    GIM_Reject,
    // Label 5091: @147201
    GIM_Try, /*On fail goto*//*Label 5152*/ 147284,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 5153*/ 147253, // Rule ID 59397 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVMAXU_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59397,
        GIR_Done,
      // Label 5153: @147253
      GIM_Try, /*On fail goto*//*Label 5154*/ 147283, // Rule ID 59398 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2)  =>  (PseudoVMAXU_VV_M8:{ *:[nxv16i32] } VRM8:{ *:[nxv16i32] }:$rs1, VRM8:{ *:[nxv16i32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59398,
        GIR_Done,
      // Label 5154: @147283
      GIM_Reject,
    // Label 5152: @147284
    GIM_Reject,
    // Label 5092: @147285
    GIM_Try, /*On fail goto*//*Label 5155*/ 147368,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 5156*/ 147337, // Rule ID 59369 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVMAXU_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59369,
        GIR_Done,
      // Label 5156: @147337
      GIM_Try, /*On fail goto*//*Label 5157*/ 147367, // Rule ID 59370 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2)  =>  (PseudoVMAXU_VV_M4:{ *:[nxv32i8] } VRM4:{ *:[nxv32i8] }:$rs1, VRM4:{ *:[nxv32i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59370,
        GIR_Done,
      // Label 5157: @147367
      GIM_Reject,
    // Label 5155: @147368
    GIM_Reject,
    // Label 5093: @147369
    GIM_Try, /*On fail goto*//*Label 5158*/ 147452,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 5159*/ 147421, // Rule ID 59385 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVMAXU_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59385,
        GIR_Done,
      // Label 5159: @147421
      GIM_Try, /*On fail goto*//*Label 5160*/ 147451, // Rule ID 59386 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2)  =>  (PseudoVMAXU_VV_M8:{ *:[nxv32i16] } VRM8:{ *:[nxv32i16] }:$rs1, VRM8:{ *:[nxv32i16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59386,
        GIR_Done,
      // Label 5160: @147451
      GIM_Reject,
    // Label 5158: @147452
    GIM_Reject,
    // Label 5094: @147453
    GIM_Try, /*On fail goto*//*Label 5161*/ 147536,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv64s8,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_nxv64s8,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 5162*/ 147505, // Rule ID 59373 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVMAXU_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i64] }, 3:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59373,
        GIR_Done,
      // Label 5162: @147505
      GIM_Try, /*On fail goto*//*Label 5163*/ 147535, // Rule ID 59374 //
        GIM_CheckFeatures, GIFBS_HasVInstructions,
        // (umax:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2)  =>  (PseudoVMAXU_VV_M8:{ *:[nxv64i8] } VRM8:{ *:[nxv64i8] }:$rs1, VRM8:{ *:[nxv64i8] }:$rs2, -1:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVMAXU_VV_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/3,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59374,
        GIR_Done,
      // Label 5163: @147535
      GIM_Reject,
    // Label 5161: @147536
    GIM_Reject,
    // Label 5095: @147537
    GIM_Reject,
    // Label 65: @147538
    GIM_Try, /*On fail goto*//*Label 5164*/ 147550, // Rule ID 4 //
      // MIs[0] imm20
      GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
      // (br (bb:{ *:[Other] }):$imm20)  =>  (PseudoBR (bb:{ *:[Other] }):$imm20)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::PseudoBR,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 4,
      GIR_Done,
    // Label 5164: @147550
    GIM_Reject,
    // Label 66: @147551
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 5167*/ 147607,
    /*GILLT_s32*//*Label 5165*/ 147559,
    /*GILLT_s64*//*Label 5166*/ 147583,
    // Label 5165: @147559
    GIM_Try, /*On fail goto*//*Label 5168*/ 147582, // Rule ID 65494 //
      GIM_CheckFeatures, GIFBS_HasStdExtZbb,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      // (cttz:{ *:[i32] } GPR:{ *:[i32] }:$rs1)  =>  (CTZ:{ *:[i32] } GPR:{ *:[i32] }:$rs1)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::CTZ,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65494,
      GIR_Done,
    // Label 5168: @147582
    GIM_Reject,
    // Label 5166: @147583
    GIM_Try, /*On fail goto*//*Label 5169*/ 147606, // Rule ID 65493 //
      GIM_CheckFeatures, GIFBS_HasStdExtZbb,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      // (cttz:{ *:[i64] } GPR:{ *:[i64] }:$rs1)  =>  (CTZ:{ *:[i64] } GPR:{ *:[i64] }:$rs1)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::CTZ,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65493,
      GIR_Done,
    // Label 5169: @147606
    GIM_Reject,
    // Label 5167: @147607
    GIM_Reject,
    // Label 67: @147608
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 5172*/ 147664,
    /*GILLT_s32*//*Label 5170*/ 147616,
    /*GILLT_s64*//*Label 5171*/ 147640,
    // Label 5170: @147616
    GIM_Try, /*On fail goto*//*Label 5173*/ 147639, // Rule ID 65492 //
      GIM_CheckFeatures, GIFBS_HasStdExtZbb,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      // (ctlz:{ *:[i32] } GPR:{ *:[i32] }:$rs1)  =>  (CLZ:{ *:[i32] } GPR:{ *:[i32] }:$rs1)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::CLZ,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65492,
      GIR_Done,
    // Label 5173: @147639
    GIM_Reject,
    // Label 5171: @147640
    GIM_Try, /*On fail goto*//*Label 5174*/ 147663, // Rule ID 65491 //
      GIM_CheckFeatures, GIFBS_HasStdExtZbb,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      // (ctlz:{ *:[i64] } GPR:{ *:[i64] }:$rs1)  =>  (CLZ:{ *:[i64] } GPR:{ *:[i64] }:$rs1)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::CLZ,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65491,
      GIR_Done,
    // Label 5174: @147663
    GIM_Reject,
    // Label 5172: @147664
    GIM_Reject,
    // Label 68: @147665
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 5177*/ 147721,
    /*GILLT_s32*//*Label 5175*/ 147673,
    /*GILLT_s64*//*Label 5176*/ 147697,
    // Label 5175: @147673
    GIM_Try, /*On fail goto*//*Label 5178*/ 147696, // Rule ID 65496 //
      GIM_CheckFeatures, GIFBS_HasStdExtZbb,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      // (ctpop:{ *:[i32] } GPR:{ *:[i32] }:$rs1)  =>  (CPOP:{ *:[i32] } GPR:{ *:[i32] }:$rs1)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::CPOP,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65496,
      GIR_Done,
    // Label 5178: @147696
    GIM_Reject,
    // Label 5176: @147697
    GIM_Try, /*On fail goto*//*Label 5179*/ 147720, // Rule ID 65495 //
      GIM_CheckFeatures, GIFBS_HasStdExtZbb,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      // (ctpop:{ *:[i64] } GPR:{ *:[i64] }:$rs1)  =>  (CPOP:{ *:[i64] } GPR:{ *:[i64] }:$rs1)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::CPOP,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65495,
      GIR_Done,
    // Label 5179: @147720
    GIM_Reject,
    // Label 5177: @147721
    GIM_Reject,
    // Label 69: @147722
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 5182*/ 147778,
    /*GILLT_s32*//*Label 5180*/ 147730,
    /*GILLT_s64*//*Label 5181*/ 147754,
    // Label 5180: @147730
    GIM_Try, /*On fail goto*//*Label 5183*/ 147753, // Rule ID 65513 //
      GIM_CheckFeatures, GIFBS_HasStdExtZbbOrZbkb_IsRV32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      // (bswap:{ *:[i32] } GPR:{ *:[i32] }:$rs1)  =>  (REV8_RV32:{ *:[i32] } GPR:{ *:[i32] }:$rs1)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::REV8_RV32,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65513,
      GIR_Done,
    // Label 5183: @147753
    GIM_Reject,
    // Label 5181: @147754
    GIM_Try, /*On fail goto*//*Label 5184*/ 147777, // Rule ID 65514 //
      GIM_CheckFeatures, GIFBS_HasStdExtZbbOrZbkb_IsRV64,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
      // (bswap:{ *:[i64] } GPR:{ *:[i64] }:$rs1)  =>  (REV8_RV64:{ *:[i64] } GPR:{ *:[i64] }:$rs1)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::REV8_RV64,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 65514,
      GIR_Done,
    // Label 5184: @147777
    GIM_Reject,
    // Label 5182: @147778
    GIM_Reject,
    // Label 70: @147779
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 30, /*)*//*default:*//*Label 5203*/ 149021,
    /*GILLT_s16*//*Label 5185*/ 147815,
    /*GILLT_s32*//*Label 5186*/ 147877,
    /*GILLT_s64*//*Label 5187*/ 147939, 0, 0,
    /*GILLT_nxv1s16*//*Label 5188*/ 148001,
    /*GILLT_nxv1s32*//*Label 5189*/ 148069,
    /*GILLT_nxv1s64*//*Label 5190*/ 148137, 0, 0,
    /*GILLT_nxv2s16*//*Label 5191*/ 148205,
    /*GILLT_nxv2s32*//*Label 5192*/ 148273,
    /*GILLT_nxv2s64*//*Label 5193*/ 148341, 0, 0,
    /*GILLT_nxv4s16*//*Label 5194*/ 148409,
    /*GILLT_nxv4s32*//*Label 5195*/ 148477,
    /*GILLT_nxv4s64*//*Label 5196*/ 148545, 0, 0,
    /*GILLT_nxv8s16*//*Label 5197*/ 148613,
    /*GILLT_nxv8s32*//*Label 5198*/ 148681,
    /*GILLT_nxv8s64*//*Label 5199*/ 148749, 0, 0,
    /*GILLT_nxv16s16*//*Label 5200*/ 148817,
    /*GILLT_nxv16s32*//*Label 5201*/ 148885, 0, 0,
    /*GILLT_nxv32s16*//*Label 5202*/ 148953,
    // Label 5185: @147815
    GIM_Try, /*On fail goto*//*Label 5204*/ 147876,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR16RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
      GIM_Try, /*On fail goto*//*Label 5205*/ 147852, // Rule ID 64622 //
        GIM_CheckFeatures, GIFBS_HasStdExtZfh,
        // (fsqrt:{ *:[f16] } FPR16:{ *:[f16] }:$rs1)  =>  (FSQRT_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_H,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64622,
        GIR_Done,
      // Label 5205: @147852
      GIM_Try, /*On fail goto*//*Label 5206*/ 147875, // Rule ID 64623 //
        GIM_CheckFeatures, GIFBS_HasStdExtZfh,
        // (fsqrt:{ *:[f16] } FPR16:{ *:[f16] }:$rs1)  =>  (FSQRT_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_H,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64623,
        GIR_Done,
      // Label 5206: @147875
      GIM_Reject,
    // Label 5204: @147876
    GIM_Reject,
    // Label 5186: @147877
    GIM_Try, /*On fail goto*//*Label 5207*/ 147938,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
      GIM_Try, /*On fail goto*//*Label 5208*/ 147914, // Rule ID 65167 //
        GIM_CheckFeatures, GIFBS_HasStdExtF,
        // (fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$rs1)  =>  (FSQRT_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_S,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65167,
        GIR_Done,
      // Label 5208: @147914
      GIM_Try, /*On fail goto*//*Label 5209*/ 147937, // Rule ID 65168 //
        GIM_CheckFeatures, GIFBS_HasStdExtF,
        // (fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$rs1)  =>  (FSQRT_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_S,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65168,
        GIR_Done,
      // Label 5209: @147937
      GIM_Reject,
    // Label 5207: @147938
    GIM_Reject,
    // Label 5187: @147939
    GIM_Try, /*On fail goto*//*Label 5210*/ 148000,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
      GIM_Try, /*On fail goto*//*Label 5211*/ 147976, // Rule ID 65310 //
        GIM_CheckFeatures, GIFBS_HasStdExtD,
        // (fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$rs1)  =>  (FSQRT_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65310,
        GIR_Done,
      // Label 5211: @147976
      GIM_Try, /*On fail goto*//*Label 5212*/ 147999, // Rule ID 65311 //
        GIM_CheckFeatures, GIFBS_HasStdExtD,
        // (fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$rs1)  =>  (FSQRT_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65311,
        GIR_Done,
      // Label 5212: @147999
      GIM_Reject,
    // Label 5210: @148000
    GIM_Reject,
    // Label 5188: @148001
    GIM_Try, /*On fail goto*//*Label 5213*/ 148068,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 5214*/ 148041, // Rule ID 62947 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2)  =>  (PseudoVFSQRT_V_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62947,
        GIR_Done,
      // Label 5214: @148041
      GIM_Try, /*On fail goto*//*Label 5215*/ 148067, // Rule ID 62948 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2)  =>  (PseudoVFSQRT_V_MF4:{ *:[nxv1f16] } VR:{ *:[nxv1f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_MF4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62948,
        GIR_Done,
      // Label 5215: @148067
      GIM_Reject,
    // Label 5213: @148068
    GIM_Reject,
    // Label 5189: @148069
    GIM_Try, /*On fail goto*//*Label 5216*/ 148136,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 5217*/ 148109, // Rule ID 62975 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2)  =>  (PseudoVFSQRT_V_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62975,
        GIR_Done,
      // Label 5217: @148109
      GIM_Try, /*On fail goto*//*Label 5218*/ 148135, // Rule ID 62976 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2)  =>  (PseudoVFSQRT_V_MF2:{ *:[nxv1f32] } VR:{ *:[nxv1f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62976,
        GIR_Done,
      // Label 5218: @148135
      GIM_Reject,
    // Label 5216: @148136
    GIM_Reject,
    // Label 5190: @148137
    GIM_Try, /*On fail goto*//*Label 5219*/ 148204,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv1s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 5220*/ 148177, // Rule ID 63018 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2)  =>  (PseudoVFSQRT_V_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63018,
        GIR_Done,
      // Label 5220: @148177
      GIM_Try, /*On fail goto*//*Label 5221*/ 148203, // Rule ID 63019 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2)  =>  (PseudoVFSQRT_V_M1:{ *:[nxv1f64] } VR:{ *:[nxv1f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63019,
        GIR_Done,
      // Label 5221: @148203
      GIM_Reject,
    // Label 5219: @148204
    GIM_Reject,
    // Label 5191: @148205
    GIM_Try, /*On fail goto*//*Label 5222*/ 148272,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 5223*/ 148245, // Rule ID 62961 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2)  =>  (PseudoVFSQRT_V_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62961,
        GIR_Done,
      // Label 5223: @148245
      GIM_Try, /*On fail goto*//*Label 5224*/ 148271, // Rule ID 62962 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2)  =>  (PseudoVFSQRT_V_MF2:{ *:[nxv2f16] } VR:{ *:[nxv2f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_MF2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62962,
        GIR_Done,
      // Label 5224: @148271
      GIM_Reject,
    // Label 5222: @148272
    GIM_Reject,
    // Label 5192: @148273
    GIM_Try, /*On fail goto*//*Label 5225*/ 148340,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 5226*/ 148313, // Rule ID 63004 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2)  =>  (PseudoVFSQRT_V_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63004,
        GIR_Done,
      // Label 5226: @148313
      GIM_Try, /*On fail goto*//*Label 5227*/ 148339, // Rule ID 63005 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2)  =>  (PseudoVFSQRT_V_M1:{ *:[nxv2f32] } VR:{ *:[nxv2f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63005,
        GIR_Done,
      // Label 5227: @148339
      GIM_Reject,
    // Label 5225: @148340
    GIM_Reject,
    // Label 5193: @148341
    GIM_Try, /*On fail goto*//*Label 5228*/ 148408,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 5229*/ 148381, // Rule ID 63119 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2)  =>  (PseudoVFSQRT_V_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63119,
        GIR_Done,
      // Label 5229: @148381
      GIM_Try, /*On fail goto*//*Label 5230*/ 148407, // Rule ID 63120 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2)  =>  (PseudoVFSQRT_V_M2:{ *:[nxv2f64] } VRM2:{ *:[nxv2f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63120,
        GIR_Done,
      // Label 5230: @148407
      GIM_Reject,
    // Label 5228: @148408
    GIM_Reject,
    // Label 5194: @148409
    GIM_Try, /*On fail goto*//*Label 5231*/ 148476,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRRegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRRegClassID,
      GIM_Try, /*On fail goto*//*Label 5232*/ 148449, // Rule ID 62990 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2)  =>  (PseudoVFSQRT_V_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62990,
        GIR_Done,
      // Label 5232: @148449
      GIM_Try, /*On fail goto*//*Label 5233*/ 148475, // Rule ID 62991 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2)  =>  (PseudoVFSQRT_V_M1:{ *:[nxv4f16] } VR:{ *:[nxv4f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_M1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 62991,
        GIR_Done,
      // Label 5233: @148475
      GIM_Reject,
    // Label 5231: @148476
    GIM_Reject,
    // Label 5195: @148477
    GIM_Try, /*On fail goto*//*Label 5234*/ 148544,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 5235*/ 148517, // Rule ID 63076 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2)  =>  (PseudoVFSQRT_V_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63076,
        GIR_Done,
      // Label 5235: @148517
      GIM_Try, /*On fail goto*//*Label 5236*/ 148543, // Rule ID 63077 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2)  =>  (PseudoVFSQRT_V_M2:{ *:[nxv4f32] } VRM2:{ *:[nxv4f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63077,
        GIR_Done,
      // Label 5236: @148543
      GIM_Reject,
    // Label 5234: @148544
    GIM_Reject,
    // Label 5196: @148545
    GIM_Try, /*On fail goto*//*Label 5237*/ 148612,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 5238*/ 148585, // Rule ID 63133 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2)  =>  (PseudoVFSQRT_V_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63133,
        GIR_Done,
      // Label 5238: @148585
      GIM_Try, /*On fail goto*//*Label 5239*/ 148611, // Rule ID 63134 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2)  =>  (PseudoVFSQRT_V_M4:{ *:[nxv4f64] } VRM4:{ *:[nxv4f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63134,
        GIR_Done,
      // Label 5239: @148611
      GIM_Reject,
    // Label 5237: @148612
    GIM_Reject,
    // Label 5197: @148613
    GIM_Try, /*On fail goto*//*Label 5240*/ 148680,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM2RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM2RegClassID,
      GIM_Try, /*On fail goto*//*Label 5241*/ 148653, // Rule ID 63033 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2)  =>  (PseudoVFSQRT_V_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63033,
        GIR_Done,
      // Label 5241: @148653
      GIM_Try, /*On fail goto*//*Label 5242*/ 148679, // Rule ID 63034 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2)  =>  (PseudoVFSQRT_V_M2:{ *:[nxv8f16] } VRM2:{ *:[nxv8f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_M2,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63034,
        GIR_Done,
      // Label 5242: @148679
      GIM_Reject,
    // Label 5240: @148680
    GIM_Reject,
    // Label 5198: @148681
    GIM_Try, /*On fail goto*//*Label 5243*/ 148748,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 5244*/ 148721, // Rule ID 63090 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2)  =>  (PseudoVFSQRT_V_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63090,
        GIR_Done,
      // Label 5244: @148721
      GIM_Try, /*On fail goto*//*Label 5245*/ 148747, // Rule ID 63091 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2)  =>  (PseudoVFSQRT_V_M4:{ *:[nxv8f32] } VRM4:{ *:[nxv8f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63091,
        GIR_Done,
      // Label 5245: @148747
      GIM_Reject,
    // Label 5243: @148748
    GIM_Reject,
    // Label 5199: @148749
    GIM_Try, /*On fail goto*//*Label 5246*/ 148816,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 5247*/ 148789, // Rule ID 63148 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2)  =>  (PseudoVFSQRT_V_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i64] }, 6:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63148,
        GIR_Done,
      // Label 5247: @148789
      GIM_Try, /*On fail goto*//*Label 5248*/ 148815, // Rule ID 63149 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2)  =>  (PseudoVFSQRT_V_M8:{ *:[nxv8f64] } VRM8:{ *:[nxv8f64] }:$rs2, -1:{ *:[i32] }, 6:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/6,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63149,
        GIR_Done,
      // Label 5248: @148815
      GIM_Reject,
    // Label 5246: @148816
    GIM_Reject,
    // Label 5200: @148817
    GIM_Try, /*On fail goto*//*Label 5249*/ 148884,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM4RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM4RegClassID,
      GIM_Try, /*On fail goto*//*Label 5250*/ 148857, // Rule ID 63047 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2)  =>  (PseudoVFSQRT_V_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63047,
        GIR_Done,
      // Label 5250: @148857
      GIM_Try, /*On fail goto*//*Label 5251*/ 148883, // Rule ID 63048 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2)  =>  (PseudoVFSQRT_V_M4:{ *:[nxv16f16] } VRM4:{ *:[nxv16f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_M4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63048,
        GIR_Done,
      // Label 5251: @148883
      GIM_Reject,
    // Label 5249: @148884
    GIM_Reject,
    // Label 5201: @148885
    GIM_Try, /*On fail goto*//*Label 5252*/ 148952,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 5253*/ 148925, // Rule ID 63105 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2)  =>  (PseudoVFSQRT_V_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i64] }, 5:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63105,
        GIR_Done,
      // Label 5253: @148925
      GIM_Try, /*On fail goto*//*Label 5254*/ 148951, // Rule ID 63106 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2)  =>  (PseudoVFSQRT_V_M8:{ *:[nxv16f32] } VRM8:{ *:[nxv16f32] }:$rs2, -1:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/5,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63106,
        GIR_Done,
      // Label 5254: @148951
      GIM_Reject,
    // Label 5252: @148952
    GIM_Reject,
    // Label 5202: @148953
    GIM_Try, /*On fail goto*//*Label 5255*/ 149020,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_nxv32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::VRM8RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::VRM8RegClassID,
      GIM_Try, /*On fail goto*//*Label 5256*/ 148993, // Rule ID 63062 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2)  =>  (PseudoVFSQRT_V_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i64] }, 4:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63062,
        GIR_Done,
      // Label 5256: @148993
      GIM_Try, /*On fail goto*//*Label 5257*/ 149019, // Rule ID 63063 //
        GIM_CheckFeatures, GIFBS_HasVInstructionsAnyF,
        // (fsqrt:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2)  =>  (PseudoVFSQRT_V_M8:{ *:[nxv32f16] } VRM8:{ *:[nxv32f16] }:$rs2, -1:{ *:[i32] }, 4:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::PseudoVFSQRT_V_M8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
        GIR_AddImm, /*InsnID*/0, /*Imm*/4,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 63063,
        GIR_Done,
      // Label 5257: @149019
      GIM_Reject,
    // Label 5255: @149020
    GIM_Reject,
    // Label 5203: @149021
    GIM_Reject,
    // Label 71: @149022
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 5261*/ 150927,
    /*GILLT_s16*//*Label 5258*/ 149031,
    /*GILLT_s32*//*Label 5259*/ 149663,
    /*GILLT_s64*//*Label 5260*/ 150295,
    // Label 5258: @149031
    GIM_Try, /*On fail goto*//*Label 5262*/ 149662,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR16RegClassID,
      GIM_Try, /*On fail goto*//*Label 5263*/ 149118, // Rule ID 64644 //
        GIM_CheckFeatures, GIFBS_HasStdExtZfh,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR16RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs3))  =>  (FNMADD_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_H,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64644,
        GIR_Done,
      // Label 5263: @149118
      GIM_Try, /*On fail goto*//*Label 5264*/ 149187, // Rule ID 64645 //
        GIM_CheckFeatures, GIFBS_HasStdExtZfh,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR16RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs3))  =>  (FNMADD_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_H,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64645,
        GIR_Done,
      // Label 5264: @149187
      GIM_Try, /*On fail goto*//*Label 5265*/ 149256, // Rule ID 72062 //
        GIM_CheckFeatures, GIFBS_HasStdExtZfh,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs3))  =>  (FNMADD_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_H,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72062,
        GIR_Done,
      // Label 5265: @149256
      GIM_Try, /*On fail goto*//*Label 5266*/ 149325, // Rule ID 72063 //
        GIM_CheckFeatures, GIFBS_HasStdExtZfh,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs3))  =>  (FNMADD_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_H,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72063,
        GIR_Done,
      // Label 5266: @149325
      GIM_Try, /*On fail goto*//*Label 5267*/ 149381, // Rule ID 64640 //
        GIM_CheckFeatures, GIFBS_HasStdExtZfh,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3)  =>  (FNMSUB_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_H,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64640,
        GIR_Done,
      // Label 5267: @149381
      GIM_Try, /*On fail goto*//*Label 5268*/ 149437, // Rule ID 64641 //
        GIM_CheckFeatures, GIFBS_HasStdExtZfh,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3)  =>  (FNMSUB_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_H,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64641,
        GIR_Done,
      // Label 5268: @149437
      GIM_Try, /*On fail goto*//*Label 5269*/ 149493, // Rule ID 72058 //
        GIM_CheckFeatures, GIFBS_HasStdExtZfh,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), FPR16:{ *:[f16] }:$rs3)  =>  (FNMSUB_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_H,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72058,
        GIR_Done,
      // Label 5269: @149493
      GIM_Try, /*On fail goto*//*Label 5270*/ 149549, // Rule ID 72059 //
        GIM_CheckFeatures, GIFBS_HasStdExtZfh,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs1), FPR16:{ *:[f16] }:$rs3)  =>  (FNMSUB_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_H,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72059,
        GIR_Done,
      // Label 5270: @149549
      GIM_Try, /*On fail goto*//*Label 5271*/ 149605, // Rule ID 64636 //
        GIM_CheckFeatures, GIFBS_HasStdExtZfh,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR16RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs3))  =>  (FMSUB_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_H,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64636,
        GIR_Done,
      // Label 5271: @149605
      GIM_Try, /*On fail goto*//*Label 5272*/ 149661, // Rule ID 64637 //
        GIM_CheckFeatures, GIFBS_HasStdExtZfh,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR16RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$rs3))  =>  (FMSUB_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, FPR16:{ *:[f16] }:$rs2, FPR16:{ *:[f16] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_H,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64637,
        GIR_Done,
      // Label 5272: @149661
      GIM_Reject,
    // Label 5262: @149662
    GIM_Reject,
    // Label 5259: @149663
    GIM_Try, /*On fail goto*//*Label 5273*/ 150294,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID,
      GIM_Try, /*On fail goto*//*Label 5274*/ 149750, // Rule ID 65185 //
        GIM_CheckFeatures, GIFBS_HasStdExtF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3))  =>  (FNMADD_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_S,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65185,
        GIR_Done,
      // Label 5274: @149750
      GIM_Try, /*On fail goto*//*Label 5275*/ 149819, // Rule ID 65186 //
        GIM_CheckFeatures, GIFBS_HasStdExtF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3))  =>  (FNMADD_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_S,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65186,
        GIR_Done,
      // Label 5275: @149819
      GIM_Try, /*On fail goto*//*Label 5276*/ 149888, // Rule ID 72072 //
        GIM_CheckFeatures, GIFBS_HasStdExtF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3))  =>  (FNMADD_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_S,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72072,
        GIR_Done,
      // Label 5276: @149888
      GIM_Try, /*On fail goto*//*Label 5277*/ 149957, // Rule ID 72073 //
        GIM_CheckFeatures, GIFBS_HasStdExtF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3))  =>  (FNMADD_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_S,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72073,
        GIR_Done,
      // Label 5277: @149957
      GIM_Try, /*On fail goto*//*Label 5278*/ 150013, // Rule ID 65181 //
        GIM_CheckFeatures, GIFBS_HasStdExtF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3)  =>  (FNMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_S,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65181,
        GIR_Done,
      // Label 5278: @150013
      GIM_Try, /*On fail goto*//*Label 5279*/ 150069, // Rule ID 65182 //
        GIM_CheckFeatures, GIFBS_HasStdExtF,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3)  =>  (FNMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_S,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65182,
        GIR_Done,
      // Label 5279: @150069
      GIM_Try, /*On fail goto*//*Label 5280*/ 150125, // Rule ID 72068 //
        GIM_CheckFeatures, GIFBS_HasStdExtF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs3)  =>  (FNMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_S,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72068,
        GIR_Done,
      // Label 5280: @150125
      GIM_Try, /*On fail goto*//*Label 5281*/ 150181, // Rule ID 72069 //
        GIM_CheckFeatures, GIFBS_HasStdExtF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs3)  =>  (FNMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_S,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72069,
        GIR_Done,
      // Label 5281: @150181
      GIM_Try, /*On fail goto*//*Label 5282*/ 150237, // Rule ID 65177 //
        GIM_CheckFeatures, GIFBS_HasStdExtF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3))  =>  (FMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_S,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65177,
        GIR_Done,
      // Label 5282: @150237
      GIM_Try, /*On fail goto*//*Label 5283*/ 150293, // Rule ID 65178 //
        GIM_CheckFeatures, GIFBS_HasStdExtF,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3))  =>  (FMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_S,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65178,
        GIR_Done,
      // Label 5283: @150293
      GIM_Reject,
    // Label 5273: @150294
    GIM_Reject,
    // Label 5260: @150295
    GIM_Try, /*On fail goto*//*Label 5284*/ 150926,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
      GIM_Try, /*On fail goto*//*Label 5285*/ 150382, // Rule ID 65331 //
        GIM_CheckFeatures, GIFBS_HasStdExtD,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3))  =>  (FNMADD_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65331,
        GIR_Done,
      // Label 5285: @150382
      GIM_Try, /*On fail goto*//*Label 5286*/ 150451, // Rule ID 65332 //
        GIM_CheckFeatures, GIFBS_HasStdExtD,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3))  =>  (FNMADD_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65332,
        GIR_Done,
      // Label 5286: @150451
      GIM_Try, /*On fail goto*//*Label 5287*/ 150520, // Rule ID 72080 //
        GIM_CheckFeatures, GIFBS_HasStdExtD,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3))  =>  (FNMADD_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72080,
        GIR_Done,
      // Label 5287: @150520
      GIM_Try, /*On fail goto*//*Label 5288*/ 150589, // Rule ID 72081 //
        GIM_CheckFeatures, GIFBS_HasStdExtD,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3))  =>  (FNMADD_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72081,
        GIR_Done,
      // Label 5288: @150589
      GIM_Try, /*On fail goto*//*Label 5289*/ 150645, // Rule ID 65327 //
        GIM_CheckFeatures, GIFBS_HasStdExtD,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3)  =>  (FNMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65327,
        GIR_Done,
      // Label 5289: @150645
      GIM_Try, /*On fail goto*//*Label 5290*/ 150701, // Rule ID 65328 //
        GIM_CheckFeatures, GIFBS_HasStdExtD,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3)  =>  (FNMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65328,
        GIR_Done,
      // Label 5290: @150701
      GIM_Try, /*On fail goto*//*Label 5291*/ 150757, // Rule ID 72076 //
        GIM_CheckFeatures, GIFBS_HasStdExtD,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs3)  =>  (FNMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72076,
        GIR_Done,
      // Label 5291: @150757
      GIM_Try, /*On fail goto*//*Label 5292*/ 150813, // Rule ID 72077 //
        GIM_CheckFeatures, GIFBS_HasStdExtD,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs3)  =>  (FNMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72077,
        GIR_Done,
      // Label 5292: @150813
      GIM_Try, /*On fail goto*//*Label 5293*/ 150869, // Rule ID 65323 //
        GIM_CheckFeatures, GIFBS_HasStdExtD,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3))  =>  (FMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65323,
        GIR_Done,
      // Label 5293: @150869
      GIM_Try, /*On fail goto*//*Label 5294*/ 150925, // Rule ID 65324 //
        GIM_CheckFeatures, GIFBS_HasStdExtD,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3))  =>  (FMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65324,
        GIR_Done,
      // Label 5294: @150925
      GIM_Reject,
    // Label 5284: @150926
    GIM_Reject,
    // Label 5261: @150927
    GIM_Reject,
    // Label 72: @150928
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 3, /*)*//*default:*//*Label 5298*/ 151123,
    /*GILLT_s16*//*Label 5295*/ 150937,
    /*GILLT_s32*//*Label 5296*/ 150999,
    /*GILLT_s64*//*Label 5297*/ 151061,
    // Label 5295: @150937
    GIM_Try, /*On fail goto*//*Label 5299*/ 150998,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR16RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR16RegClassID,
      GIM_Try, /*On fail goto*//*Label 5300*/ 150974, // Rule ID 64620 //
        GIM_CheckFeatures, GIFBS_HasStdExtZfh,
        // (strict_fsqrt:{ *:[f16] } FPR16:{ *:[f16] }:$rs1)  =>  (FSQRT_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_H,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64620,
        GIR_Done,
      // Label 5300: @150974
      GIM_Try, /*On fail goto*//*Label 5301*/ 150997, // Rule ID 64621 //
        GIM_CheckFeatures, GIFBS_HasStdExtZfh,
        // (strict_fsqrt:{ *:[f16] } FPR16:{ *:[f16] }:$rs1)  =>  (FSQRT_H:{ *:[f16] } FPR16:{ *:[f16] }:$rs1, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_H,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 64621,
        GIR_Done,
      // Label 5301: @150997
      GIM_Reject,
    // Label 5299: @150998
    GIM_Reject,
    // Label 5296: @150999
    GIM_Try, /*On fail goto*//*Label 5302*/ 151060,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
      GIM_Try, /*On fail goto*//*Label 5303*/ 151036, // Rule ID 65165 //
        GIM_CheckFeatures, GIFBS_HasStdExtF,
        // (strict_fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$rs1)  =>  (FSQRT_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_S,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65165,
        GIR_Done,
      // Label 5303: @151036
      GIM_Try, /*On fail goto*//*Label 5304*/ 151059, // Rule ID 65166 //
        GIM_CheckFeatures, GIFBS_HasStdExtF,
        // (strict_fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$rs1)  =>  (FSQRT_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_S,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65166,
        GIR_Done,
      // Label 5304: @151059
      GIM_Reject,
    // Label 5302: @151060
    GIM_Reject,
    // Label 5297: @151061
    GIM_Try, /*On fail goto*//*Label 5305*/ 151122,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
      GIM_Try, /*On fail goto*//*Label 5306*/ 151098, // Rule ID 65308 //
        GIM_CheckFeatures, GIFBS_HasStdExtD,
        // (strict_fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$rs1)  =>  (FSQRT_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65308,
        GIR_Done,
      // Label 5306: @151098
      GIM_Try, /*On fail goto*//*Label 5307*/ 151121, // Rule ID 65309 //
        GIM_CheckFeatures, GIFBS_HasStdExtD,
        // (strict_fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$rs1)  =>  (FSQRT_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_D,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
        GIR_AddImm, /*InsnID*/0, /*Imm*/7,
        GIR_EraseFromParent, /*InsnID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 65309,
        GIR_Done,
      // Label 5307: @151121
      GIM_Reject,
    // Label 5305: @151122
    GIM_Reject,
    // Label 5298: @151123
    GIM_Reject,
    // Label 73: @151124
    GIM_Reject,
    };
  return MatchTable0;
}
#endif // ifdef GET_GLOBALISEL_IMPL
#ifdef GET_GLOBALISEL_PREDICATES_DECL
PredicateBitset AvailableModuleFeatures;
mutable PredicateBitset AvailableFunctionFeatures;
PredicateBitset getAvailableFeatures() const {
  return AvailableModuleFeatures | AvailableFunctionFeatures;
}
PredicateBitset
computeAvailableModuleFeatures(const RISCVSubtarget *Subtarget) const;
PredicateBitset
computeAvailableFunctionFeatures(const RISCVSubtarget *Subtarget,
                                 const MachineFunction *MF) const;
void setupGeneratedPerFunctionState(MachineFunction &MF) override;
#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL
#ifdef GET_GLOBALISEL_PREDICATES_INIT
AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
AvailableFunctionFeatures()
#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT