| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* Assembly Matcher Source Fragment *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| |
| #ifdef GET_ASSEMBLER_HEADER |
| #undef GET_ASSEMBLER_HEADER |
| // This should be included into the middle of the declaration of |
| // your subclasses implementation of MCTargetAsmParser. |
| FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const; |
| void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, |
| const OperandVector &Operands); |
| void convertToMapAndConstraints(unsigned Kind, |
| const OperandVector &Operands) override; |
| unsigned MatchInstructionImpl(const OperandVector &Operands, |
| MCInst &Inst, |
| uint64_t &ErrorInfo, |
| FeatureBitset &MissingFeatures, |
| bool matchingInlineAsm, |
| unsigned VariantID = 0); |
| unsigned MatchInstructionImpl(const OperandVector &Operands, |
| MCInst &Inst, |
| uint64_t &ErrorInfo, |
| bool matchingInlineAsm, |
| unsigned VariantID = 0) { |
| FeatureBitset MissingFeatures; |
| return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures, |
| matchingInlineAsm, VariantID); |
| } |
| |
| #endif // GET_ASSEMBLER_HEADER_INFO |
| |
| |
| #ifdef GET_OPERAND_DIAGNOSTIC_TYPES |
| #undef GET_OPERAND_DIAGNOSTIC_TYPES |
| |
| #endif // GET_OPERAND_DIAGNOSTIC_TYPES |
| |
| |
| #ifdef GET_REGISTER_MATCHER |
| #undef GET_REGISTER_MATCHER |
| |
| // Bits for subtarget features that participate in instruction matching. |
| enum SubtargetFeatureBits : uint8_t { |
| Feature_ModernAsBit = 0, |
| }; |
| |
| #endif // GET_REGISTER_MATCHER |
| |
| |
| #ifdef GET_SUBTARGET_FEATURE_NAME |
| #undef GET_SUBTARGET_FEATURE_NAME |
| |
| // User-level names for subtarget features that participate in |
| // instruction matching. |
| static const char *getSubtargetFeatureName(uint64_t Val) { |
| switch(Val) { |
| case Feature_ModernAsBit: return ""; |
| default: return "(unknown)"; |
| } |
| } |
| |
| #endif // GET_SUBTARGET_FEATURE_NAME |
| |
| |
| #ifdef GET_MATCHER_IMPLEMENTATION |
| #undef GET_MATCHER_IMPLEMENTATION |
| |
| static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID) { |
| switch (VariantID) { |
| case 0: |
| switch (Mnemonic.size()) { |
| default: break; |
| case 5: // 1 string to match. |
| if (memcmp(Mnemonic.data()+0, "cntlz", 5) != 0) |
| break; |
| Mnemonic = "cntlzw"; // "cntlz" |
| return; |
| case 6: // 1 string to match. |
| if (memcmp(Mnemonic.data()+0, "cntlz.", 6) != 0) |
| break; |
| Mnemonic = "cntlzw."; // "cntlz." |
| return; |
| } |
| break; |
| } |
| switch (Mnemonic.size()) { |
| default: break; |
| case 5: // 1 string to match. |
| if (memcmp(Mnemonic.data()+0, "cntlz", 5) != 0) |
| break; |
| Mnemonic = "cntlzw"; // "cntlz" |
| return; |
| case 6: // 1 string to match. |
| if (memcmp(Mnemonic.data()+0, "cntlz.", 6) != 0) |
| break; |
| Mnemonic = "cntlzw."; // "cntlz." |
| return; |
| } |
| } |
| |
| enum { |
| Tie0_1_1, |
| }; |
| |
| static const uint8_t TiedAsmOperandTable[][3] = { |
| /* Tie0_1_1 */ { 0, 1, 1 }, |
| }; |
| |
| namespace { |
| enum OperatorConversionKind { |
| CVT_Done, |
| CVT_Reg, |
| CVT_Tied, |
| CVT_95_addRegG8RCOperands, |
| CVT_95_addTLSRegOperands, |
| CVT_95_addRegGPRCOperands, |
| CVT_95_addImmOperands, |
| CVT_95_addRegGPRCNoR0Operands, |
| CVT_95_addS16ImmOperands, |
| CVT_95_addU16ImmOperands, |
| CVT_95_addBranchTargetOperands, |
| CVT_95_addRegCRBITRCOperands, |
| CVT_imm_95_3, |
| CVT_imm_95_2, |
| CVT_imm_95_0, |
| CVT_95_addRegVRRCOperands, |
| CVT_imm_95_8, |
| CVT_imm_95_10, |
| CVT_imm_95_76, |
| CVT_regCR0, |
| CVT_95_addRegCRRCOperands, |
| CVT_imm_95_79, |
| CVT_imm_95_78, |
| CVT_imm_95_4, |
| CVT_imm_95_7, |
| CVT_imm_95_6, |
| CVT_imm_95_44, |
| CVT_imm_95_47, |
| CVT_imm_95_46, |
| CVT_imm_95_36, |
| CVT_imm_95_39, |
| CVT_imm_95_38, |
| CVT_imm_95_12, |
| CVT_imm_95_15, |
| CVT_imm_95_14, |
| CVT_imm_95_68, |
| CVT_imm_95_71, |
| CVT_imm_95_70, |
| CVT_imm_95_100, |
| CVT_imm_95_103, |
| CVT_imm_95_102, |
| CVT_imm_95_108, |
| CVT_imm_95_111, |
| CVT_imm_95_110, |
| CVT_imm_95_31, |
| CVT_95_addRegGxRCNoR0Operands, |
| CVT_95_addRegGxRCOperands, |
| CVT_regR0, |
| CVT_95_addRegDMRRCOperands, |
| CVT_95_addRegVSRpRCOperands, |
| CVT_95_addRegDMRROWpRCOperands, |
| CVT_95_addRegACCRCOperands, |
| CVT_95_addRegSPERCOperands, |
| CVT_95_addRegSPE4RCOperands, |
| CVT_95_addRegF4RCOperands, |
| CVT_95_addRegF8RCOperands, |
| CVT_95_addRegG8RCNoX0Operands, |
| CVT_regCR0EQ, |
| CVT_regCR0GT, |
| CVT_regCR0LT, |
| CVT_regZERO8, |
| CVT_regZERO, |
| CVT_95_addRegG8pRCOperands, |
| CVT_imm_95_1, |
| CVT_95_addRegVFRCOperands, |
| CVT_95_addRegVSFRCOperands, |
| CVT_95_addRegVSSRCOperands, |
| CVT_95_addRegVSRCOperands, |
| CVT_imm_95_29, |
| CVT_imm_95_280, |
| CVT_imm_95_128, |
| CVT_imm_95_129, |
| CVT_imm_95_130, |
| CVT_imm_95_131, |
| CVT_imm_95_132, |
| CVT_imm_95_133, |
| CVT_imm_95_134, |
| CVT_imm_95_135, |
| CVT_imm_95_28, |
| CVT_imm_95_9, |
| CVT_imm_95_19, |
| CVT_imm_95_537, |
| CVT_imm_95_539, |
| CVT_imm_95_541, |
| CVT_imm_95_543, |
| CVT_imm_95_536, |
| CVT_imm_95_538, |
| CVT_imm_95_540, |
| CVT_imm_95_542, |
| CVT_imm_95_1018, |
| CVT_imm_95_981, |
| CVT_imm_95_22, |
| CVT_imm_95_17, |
| CVT_imm_95_18, |
| CVT_imm_95_980, |
| CVT_imm_95_529, |
| CVT_imm_95_531, |
| CVT_imm_95_533, |
| CVT_imm_95_535, |
| CVT_imm_95_528, |
| CVT_imm_95_530, |
| CVT_imm_95_532, |
| CVT_imm_95_534, |
| CVT_imm_95_1019, |
| CVT_95_addCRBitMaskOperands, |
| CVT_imm_95_48, |
| CVT_imm_95_896, |
| CVT_imm_95_287, |
| CVT_imm_95_5, |
| CVT_imm_95_25, |
| CVT_imm_95_512, |
| CVT_imm_95_272, |
| CVT_imm_95_273, |
| CVT_imm_95_274, |
| CVT_imm_95_275, |
| CVT_imm_95_260, |
| CVT_imm_95_261, |
| CVT_imm_95_262, |
| CVT_imm_95_263, |
| CVT_imm_95_26, |
| CVT_imm_95_27, |
| CVT_imm_95_990, |
| CVT_imm_95_991, |
| CVT_imm_95_268, |
| CVT_imm_95_988, |
| CVT_imm_95_989, |
| CVT_imm_95_269, |
| CVT_imm_95_986, |
| CVT_imm_95_13, |
| CVT_imm_95_255, |
| CVT_imm_95_284, |
| CVT_imm_95_285, |
| CVT_regX0, |
| CVT_95_addRegVSRpEvenRCOperands, |
| CVT_imm_95_20, |
| CVT_imm_95_16, |
| CVT_imm_95_24, |
| CVT_NUM_CONVERTERS |
| }; |
| |
| enum InstructionConversionKind { |
| Convert__RegG8RC1_0__RegG8RC1_1__TLSReg1_2, |
| Convert__RegGPRC1_0__RegGPRC1_1__RegGPRC1_2, |
| Convert__RegGPRC1_1__RegGPRC1_2__RegGPRC1_3, |
| Convert__RegGPRC1_0__RegGPRC1_1__RegGPRC1_2__U2Imm1_3, |
| Convert__RegGPRC1_0__RegGPRCNoR01_1__S16Imm1_2, |
| Convert__RegGPRC1_0__RegGPRC1_1__S16Imm1_2, |
| Convert__RegGPRC1_1__RegGPRC1_2__S16Imm1_3, |
| Convert__RegGPRC1_0__RegGPRCNoR01_1__S17Imm1_2, |
| Convert__RegGPRC1_0__RegGPRC1_1, |
| Convert__RegGPRC1_1__RegGPRC1_2, |
| Convert__RegG8RC1_0__Imm1_1, |
| Convert__RegGPRC1_1__RegGPRC1_2__U16Imm1_3, |
| Convert_NoOperands, |
| Convert__DirectBr1_0, |
| Convert__U5Imm1_0__RegCRBITRC1_1__CondBr1_2, |
| Convert__U5Imm1_1__ATBitsAsHint1_0__RegCRBITRC1_2__CondBr1_3, |
| Convert__U5Imm1_0__imm_95_3__RegCRBITRC1_1__CondBr1_2, |
| Convert__U5Imm1_0__imm_95_2__RegCRBITRC1_1__CondBr1_2, |
| Convert__U5Imm1_0__RegCRBITRC1_1__imm_95_0, |
| Convert__U5Imm1_0__RegCRBITRC1_1__Imm1_2, |
| Convert__RegVRRC1_1__RegVRRC1_2__RegVRRC1_3__U1Imm1_4, |
| Convert__RegVRRC1_1__RegVRRC1_2__U1Imm1_3, |
| Convert__RegVRRC1_1__RegVRRC1_2__RegVRRC1_3, |
| Convert__RegVRRC1_1__RegVRRC1_2, |
| Convert__CondBr1_0, |
| Convert__imm_95_0__RegCRBITRC1_0__CondBr1_1, |
| Convert__imm_95_0__RegCRBITRC1_0__imm_95_0, |
| Convert__imm_95_8__RegCRBITRC1_0__CondBr1_1, |
| Convert__imm_95_8__RegCRBITRC1_0__imm_95_0, |
| Convert__imm_95_2__RegCRBITRC1_0__CondBr1_1, |
| Convert__imm_95_2__RegCRBITRC1_0__imm_95_0, |
| Convert__imm_95_10__RegCRBITRC1_0__CondBr1_1, |
| Convert__imm_95_10__RegCRBITRC1_0__imm_95_0, |
| Convert__imm_95_76__regCR0__CondBr1_0, |
| Convert__imm_95_76__RegCRRC1_0__CondBr1_1, |
| Convert__imm_95_79__regCR0__CondBr1_0, |
| Convert__imm_95_79__RegCRRC1_0__CondBr1_1, |
| Convert__imm_95_78__regCR0__CondBr1_0, |
| Convert__imm_95_78__RegCRRC1_0__CondBr1_1, |
| Convert__imm_95_76__regCR0, |
| Convert__imm_95_76__RegCRRC1_0, |
| Convert__imm_95_79__regCR0, |
| Convert__imm_95_79__RegCRRC1_0, |
| Convert__imm_95_78__regCR0, |
| Convert__imm_95_78__RegCRRC1_0, |
| Convert__imm_95_4__RegCRBITRC1_0__CondBr1_1, |
| Convert__imm_95_7__RegCRBITRC1_0__CondBr1_1, |
| Convert__imm_95_6__RegCRBITRC1_0__CondBr1_1, |
| Convert__imm_95_4__RegCRBITRC1_0__imm_95_0, |
| Convert__imm_95_7__RegCRBITRC1_0__imm_95_0, |
| Convert__imm_95_6__RegCRBITRC1_0__imm_95_0, |
| Convert__imm_95_4__regCR0__CondBr1_0, |
| Convert__imm_95_4__RegCRRC1_0__CondBr1_1, |
| Convert__imm_95_7__regCR0__CondBr1_0, |
| Convert__imm_95_7__RegCRRC1_0__CondBr1_1, |
| Convert__imm_95_6__regCR0__CondBr1_0, |
| Convert__imm_95_6__RegCRRC1_0__CondBr1_1, |
| Convert__imm_95_4__regCR0, |
| Convert__imm_95_4__RegCRRC1_0, |
| Convert__imm_95_7__regCR0, |
| Convert__imm_95_7__RegCRRC1_0, |
| Convert__imm_95_6__regCR0, |
| Convert__imm_95_6__RegCRRC1_0, |
| Convert__imm_95_44__regCR0__CondBr1_0, |
| Convert__imm_95_44__RegCRRC1_0__CondBr1_1, |
| Convert__imm_95_47__regCR0__CondBr1_0, |
| Convert__imm_95_47__RegCRRC1_0__CondBr1_1, |
| Convert__imm_95_46__regCR0__CondBr1_0, |
| Convert__imm_95_46__RegCRRC1_0__CondBr1_1, |
| Convert__imm_95_44__regCR0, |
| Convert__imm_95_44__RegCRRC1_0, |
| Convert__imm_95_47__regCR0, |
| Convert__imm_95_47__RegCRRC1_0, |
| Convert__imm_95_46__regCR0, |
| Convert__imm_95_46__RegCRRC1_0, |
| Convert__DirectBr1_0__Imm1_1, |
| Convert__imm_95_36__regCR0__CondBr1_0, |
| Convert__imm_95_36__RegCRRC1_0__CondBr1_1, |
| Convert__imm_95_39__regCR0__CondBr1_0, |
| Convert__imm_95_39__RegCRRC1_0__CondBr1_1, |
| Convert__imm_95_38__regCR0__CondBr1_0, |
| Convert__imm_95_38__RegCRRC1_0__CondBr1_1, |
| Convert__imm_95_36__regCR0, |
| Convert__imm_95_36__RegCRRC1_0, |
| Convert__imm_95_39__regCR0, |
| Convert__imm_95_39__RegCRRC1_0, |
| Convert__imm_95_38__regCR0, |
| Convert__imm_95_38__RegCRRC1_0, |
| Convert__imm_95_12__regCR0__CondBr1_0, |
| Convert__imm_95_12__RegCRRC1_0__CondBr1_1, |
| Convert__imm_95_15__regCR0__CondBr1_0, |
| Convert__imm_95_15__RegCRRC1_0__CondBr1_1, |
| Convert__imm_95_14__regCR0__CondBr1_0, |
| Convert__imm_95_14__RegCRRC1_0__CondBr1_1, |
| Convert__imm_95_12__regCR0, |
| Convert__imm_95_12__RegCRRC1_0, |
| Convert__imm_95_15__regCR0, |
| Convert__imm_95_15__RegCRRC1_0, |
| Convert__imm_95_14__regCR0, |
| Convert__imm_95_14__RegCRRC1_0, |
| Convert__imm_95_68__regCR0__CondBr1_0, |
| Convert__imm_95_68__RegCRRC1_0__CondBr1_1, |
| Convert__imm_95_71__regCR0__CondBr1_0, |
| Convert__imm_95_71__RegCRRC1_0__CondBr1_1, |
| Convert__imm_95_70__regCR0__CondBr1_0, |
| Convert__imm_95_70__RegCRRC1_0__CondBr1_1, |
| Convert__imm_95_68__regCR0, |
| Convert__imm_95_68__RegCRRC1_0, |
| Convert__imm_95_71__regCR0, |
| Convert__imm_95_71__RegCRRC1_0, |
| Convert__imm_95_70__regCR0, |
| Convert__imm_95_70__RegCRRC1_0, |
| Convert__imm_95_100__regCR0__CondBr1_0, |
| Convert__imm_95_100__RegCRRC1_0__CondBr1_1, |
| Convert__imm_95_103__regCR0__CondBr1_0, |
| Convert__imm_95_103__RegCRRC1_0__CondBr1_1, |
| Convert__imm_95_102__regCR0__CondBr1_0, |
| Convert__imm_95_102__RegCRRC1_0__CondBr1_1, |
| Convert__imm_95_100__regCR0, |
| Convert__imm_95_100__RegCRRC1_0, |
| Convert__imm_95_103__regCR0, |
| Convert__imm_95_103__RegCRRC1_0, |
| Convert__imm_95_102__regCR0, |
| Convert__imm_95_102__RegCRRC1_0, |
| Convert__RegG8RC1_0__RegG8RC1_1__RegG8RC1_2, |
| Convert__RegG8RC1_0__RegG8RC1_1, |
| Convert__imm_95_108__regCR0__CondBr1_0, |
| Convert__imm_95_108__RegCRRC1_0__CondBr1_1, |
| Convert__imm_95_111__regCR0__CondBr1_0, |
| Convert__imm_95_111__RegCRRC1_0__CondBr1_1, |
| Convert__imm_95_110__regCR0__CondBr1_0, |
| Convert__imm_95_110__RegCRRC1_0__CondBr1_1, |
| Convert__imm_95_108__regCR0, |
| Convert__imm_95_108__RegCRRC1_0, |
| Convert__imm_95_111__regCR0, |
| Convert__imm_95_111__RegCRRC1_0, |
| Convert__imm_95_110__regCR0, |
| Convert__imm_95_110__RegCRRC1_0, |
| Convert__imm_95_12__RegCRBITRC1_0__CondBr1_1, |
| Convert__imm_95_15__RegCRBITRC1_0__CondBr1_1, |
| Convert__imm_95_14__RegCRBITRC1_0__CondBr1_1, |
| Convert__imm_95_12__RegCRBITRC1_0__imm_95_0, |
| Convert__imm_95_15__RegCRBITRC1_0__imm_95_0, |
| Convert__imm_95_14__RegCRBITRC1_0__imm_95_0, |
| Convert__RegG8RC1_0__RegG8RC1_1__imm_95_0__U6Imm1_2, |
| Convert__RegG8RC1_0__RegGPRC1_1__imm_95_0__U6Imm1_2, |
| Convert__RegG8RC1_1__RegG8RC1_2__imm_95_0__U6Imm1_3, |
| Convert__RegG8RC1_0__RegG8RC1_1__U6Imm1_2__U6Imm1_3, |
| Convert__RegG8RC1_1__RegG8RC1_2__U6Imm1_3__U6Imm1_4, |
| Convert__RegGPRC1_0__RegGPRC1_1__U5Imm1_2__U5Imm1_3, |
| Convert__RegGPRC1_1__RegGPRC1_2__U5Imm1_3__U5Imm1_4, |
| Convert__RegG8RC1_0__RegG8RC1_1__imm_95_0__U5Imm1_2__imm_95_31, |
| Convert__RegGPRC1_0__RegGPRC1_1__imm_95_0__U5Imm1_2__imm_95_31, |
| Convert__RegG8RC1_1__RegG8RC1_2__imm_95_0__U5Imm1_3__imm_95_31, |
| Convert__RegGPRC1_1__RegGPRC1_2__imm_95_0__U5Imm1_3__imm_95_31, |
| Convert__RegG8RC1_0__RegG8RC1_1__U6Imm1_2, |
| Convert__RegG8RC1_1__RegG8RC1_2__U6Imm1_3, |
| Convert__RegGPRC1_0__RegGPRC1_1__U5Imm1_2, |
| Convert__RegGPRC1_1__RegGPRC1_2__U5Imm1_3, |
| Convert__RegCRRC1_0__RegGPRC1_2__RegGPRC1_3, |
| Convert__RegCRRC1_0__RegG8RC1_2__RegG8RC1_3, |
| Convert__regCR0__RegG8RC1_0__RegG8RC1_1, |
| Convert__RegCRRC1_0__RegG8RC1_1__RegG8RC1_2, |
| Convert__regCR0__RegG8RC1_0__S16Imm1_1, |
| Convert__RegCRRC1_0__RegG8RC1_1__S16Imm1_2, |
| Convert__RegCRRC1_0__RegGPRC1_2__S16Imm1_3, |
| Convert__RegCRRC1_0__RegG8RC1_2__S16Imm1_3, |
| Convert__regCR0__RegG8RC1_0__U16Imm1_1, |
| Convert__RegCRRC1_0__RegG8RC1_1__U16Imm1_2, |
| Convert__RegCRRC1_0__RegGPRC1_2__U16Imm1_3, |
| Convert__RegCRRC1_0__RegG8RC1_2__U16Imm1_3, |
| Convert__regCR0__RegGPRC1_0__RegGPRC1_1, |
| Convert__RegCRRC1_0__RegGPRC1_1__RegGPRC1_2, |
| Convert__regCR0__RegGPRC1_0__U16Imm1_1, |
| Convert__RegCRRC1_0__RegGPRC1_1__U16Imm1_2, |
| Convert__RegCRRC1_0__U1Imm1_1__RegGPRC1_2__RegGPRC1_3, |
| Convert__regCR0__RegGPRC1_0__S16Imm1_1, |
| Convert__RegCRRC1_0__RegGPRC1_1__S16Imm1_2, |
| Convert__RegG8RC1_1__RegG8RC1_2, |
| Convert__RegGPRC1_0__RegGPRC1_1__imm_95_0, |
| Convert__RegCRBITRC1_0__RegCRBITRC1_1__RegCRBITRC1_2, |
| Convert__RegCRBITRC1_0__RegCRBITRC1_0__RegCRBITRC1_0, |
| Convert__RegCRBITRC1_0__RegCRBITRC1_1__RegCRBITRC1_1, |
| Convert__RegG8RC1_0__U2Imm1_1, |
| Convert__RegGxRCNoR01_0__RegGxRC1_1, |
| Convert__U3Imm1_2__RegGxRCNoR01_0__RegGxRC1_1, |
| Convert__U5Imm1_2__RegGxRCNoR01_0__RegGxRC1_1, |
| Convert__RegGxRCNoR01_0__RegGxRC1_1__U5Imm1_2, |
| Convert__RegGxRCNoR01_1__RegGxRC1_2__U5Imm1_0, |
| Convert__regR0__regR0, |
| Convert__RegG8RC1_1__RegG8RC1_2__RegG8RC1_3, |
| Convert__RegDMRRC1_0__RegDMRRC1_1, |
| Convert__RegDMRRC1_0, |
| Convert__RegDMRRC1_0__Tie0_1_1__RegDMRRC1_1, |
| Convert__RegVSRpRC1_1__RegDMRROWpRC1_0__U2Imm1_2, |
| Convert__RegVSRpRC1_1__RegVSRpRC1_2__RegACCRC1_0, |
| Convert__RegDMRROWpRC1_0__RegVSRpRC1_1__U2Imm1_2, |
| Convert__RegACCRC1_0__RegVSRpRC1_1__RegVSRpRC1_2, |
| Convert__U5Imm1_0, |
| Convert__U5Imm1_2__RegGPRC1_0__RegGPRC1_1, |
| Convert__RegSPERC1_0__RegSPERC1_1, |
| Convert__RegSPERC1_0__RegSPERC1_1__RegSPERC1_2, |
| Convert__RegSPERC1_0__RegSPE4RC1_1, |
| Convert__RegSPERC1_0__RegGPRC1_1, |
| Convert__RegCRRC1_0__RegSPERC1_1__RegSPERC1_2, |
| Convert__RegGPRC1_0__RegSPERC1_1, |
| Convert__RegSPE4RC1_0__RegSPE4RC1_1, |
| Convert__RegSPE4RC1_0__RegSPE4RC1_1__RegSPE4RC1_2, |
| Convert__RegSPE4RC1_0__RegSPERC1_1, |
| Convert__RegSPE4RC1_0__RegGPRC1_1, |
| Convert__RegCRRC1_0__RegSPE4RC1_1__RegSPE4RC1_2, |
| Convert__RegGPRC1_0__RegSPE4RC1_1, |
| Convert__RegSPERC1_0__RegSPERC1_2__U5Imm1_1, |
| Convert__RegSPERC1_0__DispSPE81_1__RegGxRCNoR01_2, |
| Convert__RegSPERC1_0__RegGxRCNoR01_1__RegGxRC1_2, |
| Convert__RegSPERC1_0__DispSPE21_1__RegGxRCNoR01_2, |
| Convert__RegSPERC1_0__DispSPE41_1__RegGxRCNoR01_2, |
| Convert__RegSPERC1_0__RegGPRC1_1__RegGPRC1_2, |
| Convert__RegSPERC1_0__RegSPERC1_1__U5Imm1_2, |
| Convert__RegSPERC1_1__RegSPERC1_2__RegSPERC1_3__imm_95_0, |
| Convert__RegSPERC1_0__S5Imm1_1, |
| Convert__RegSPERC1_0__U5Imm1_1__RegSPERC1_2, |
| Convert__RegF4RC1_0__RegF4RC1_1, |
| Convert__RegF4RC1_1__RegF4RC1_2, |
| Convert__RegF8RC1_0__RegF8RC1_1__RegF8RC1_2, |
| Convert__RegF8RC1_1__RegF8RC1_2__RegF8RC1_3, |
| Convert__RegF4RC1_0__RegF4RC1_1__RegF4RC1_2, |
| Convert__RegF4RC1_1__RegF4RC1_2__RegF4RC1_3, |
| Convert__RegF8RC1_0__RegF8RC1_1, |
| Convert__RegF8RC1_1__RegF8RC1_2, |
| Convert__RegF4RC1_0__RegF8RC1_1, |
| Convert__RegF4RC1_1__RegF8RC1_2, |
| Convert__RegCRRC1_0__RegF4RC1_1__RegF4RC1_2, |
| Convert__RegF8RC1_0__RegF8RC1_1__RegF8RC1_2__RegF8RC1_3, |
| Convert__RegF8RC1_1__RegF8RC1_2__RegF8RC1_3__RegF8RC1_4, |
| Convert__RegF4RC1_0__RegF4RC1_1__RegF4RC1_2__RegF4RC1_3, |
| Convert__RegF4RC1_1__RegF4RC1_2__RegF4RC1_3__RegF4RC1_4, |
| Convert__RegF4RC1_0__RegF8RC1_1__RegF4RC1_2__RegF4RC1_3, |
| Convert__RegF4RC1_1__RegF8RC1_2__RegF4RC1_3__RegF4RC1_4, |
| Convert__RegCRRC1_0__RegF8RC1_1__RegF8RC1_2, |
| Convert__RegCRRC1_0__RegF8RC1_1, |
| Convert__RegGPRC1_0__DispRIHash1_1__RegGxRCNoR01_2, |
| Convert__imm_95_0, |
| Convert__U4Imm1_0__RegGxRCNoR01_1__RegGxRC1_2, |
| Convert__U4Imm1_1__RegGxRCNoR01_2__RegGxRC1_3, |
| Convert__RegGPRC1_0__RegGPRCNoR01_1__RegGPRC1_2__RegCRBITRC1_3, |
| Convert__RegG8RC1_0__RegG8RCNoX01_1__RegG8RC1_2__regCR0EQ, |
| Convert__RegGPRC1_0__RegGPRCNoR01_1__RegGPRC1_2__regCR0EQ, |
| Convert__RegG8RC1_0__RegG8RCNoX01_1__RegG8RC1_2__regCR0GT, |
| Convert__RegGPRC1_0__RegGPRCNoR01_1__RegGPRC1_2__regCR0GT, |
| Convert__RegG8RC1_0__RegG8RCNoX01_1__RegG8RC1_2__regCR0LT, |
| Convert__RegGPRC1_0__RegGPRCNoR01_1__RegGPRC1_2__regCR0LT, |
| Convert__RegGPRC1_0__DispRI1_1__RegGxRCNoR01_2, |
| Convert__RegGPRC1_0__RegGxRCNoR01_1__RegGxRC1_2, |
| Convert__RegGPRC1_0__imm_95_0__DispRI1_1__RegGxRCNoR01_2, |
| Convert__RegGPRC1_0__imm_95_0__RegGxRCNoR01_1__RegGxRC1_2, |
| Convert__RegG8RC1_0__RegGxRCNoR01_1__TLSReg1_2, |
| Convert__RegG8RC1_0__DispRIX1_1__RegGxRCNoR01_2, |
| Convert__RegG8RC1_0__RegGxRCNoR01_1__RegGxRC1_2, |
| Convert__RegG8RC1_0__RegG8RC1_1__U5Imm1_2, |
| Convert__RegG8RC1_0__imm_95_0__DispRIX1_1__RegGxRCNoR01_2, |
| Convert__RegG8RC1_0__imm_95_0__RegGxRCNoR01_1__RegGxRC1_2, |
| Convert__RegF8RC1_0__DispRI1_1__RegGxRCNoR01_2, |
| Convert__RegF8RC1_0__RegGxRCNoR01_1__RegGxRC1_2, |
| Convert__RegF8RC1_0__imm_95_0__DispRI1_1__RegGxRCNoR01_2, |
| Convert__RegF8RC1_0__imm_95_0__RegGxRCNoR01_1__RegGxRC1_2, |
| Convert__RegF4RC1_0__DispRI1_1__RegGxRCNoR01_2, |
| Convert__RegF4RC1_0__imm_95_0__DispRI1_1__RegGxRCNoR01_2, |
| Convert__RegF4RC1_0__imm_95_0__RegGxRCNoR01_1__RegGxRC1_2, |
| Convert__RegF4RC1_0__RegGxRCNoR01_1__RegGxRC1_2, |
| Convert__RegG8RC1_0__regZERO8__S16Imm1_1, |
| Convert__RegGPRC1_0__S16Imm1_1, |
| Convert__RegGPRC1_0__regZERO__S16Imm1_1, |
| Convert__RegG8RC1_0__regZERO8__S17Imm1_1, |
| Convert__RegGPRC1_0__S17Imm1_1, |
| Convert__RegGPRC1_0__regZERO__S17Imm1_1, |
| Convert__RegG8RC1_0__imm_95_0, |
| Convert__RegG8pRC1_0__DispRIX161_1__RegGxRCNoR01_2, |
| Convert__RegG8pRC1_0__RegGxRCNoR01_1__RegGxRC1_2, |
| Convert__RegVRRC1_0__RegGxRCNoR01_1__RegGxRC1_2, |
| Convert__imm_95_1, |
| Convert__RegSPE4RC1_0__DispRI1_1__RegGxRCNoR01_2, |
| Convert__RegSPE4RC1_0__RegGxRCNoR01_1__RegGxRC1_2, |
| Convert__RegVFRC1_0__DispRIX1_1__RegGxRCNoR01_2, |
| Convert__RegVSFRC1_0__RegGxRCNoR01_1__RegGxRC1_2, |
| Convert__RegVSSRC1_0__RegGxRCNoR01_1__RegGxRC1_2, |
| Convert__RegVSRC1_0__DispRIX161_1__RegGxRCNoR01_2, |
| Convert__RegVSRC1_0__RegGxRCNoR01_1__RegGxRC1_2, |
| Convert__RegVSRC1_0__U5Imm1_1, |
| Convert__RegVSRC1_0__Imm1_1__RegG8RC1_2, |
| Convert__RegVSRpRC1_0__DispRIX161_1__RegGxRCNoR01_2, |
| Convert__RegVSRpRC1_0__Imm1_1__RegG8RC1_2, |
| Convert__RegVSRpRC1_0__RegGxRCNoR01_1__RegGxRC1_2, |
| Convert__RegG8RC1_0__RegG8RC1_1__RegG8RC1_2__RegG8RC1_3, |
| Convert__RegGPRC1_0__RegGPRC1_1__RegGPRC1_2__RegGPRC1_3, |
| Convert__RegCRRC1_0__RegCRRC1_1, |
| Convert__RegCRRC1_0, |
| Convert__RegG8RC1_0__imm_95_29, |
| Convert__RegGPRC1_0__imm_95_29, |
| Convert__RegG8RC1_0__imm_95_280, |
| Convert__RegGPRC1_0__imm_95_280, |
| Convert__RegGPRC1_0__U10Imm1_1__imm_95_0, |
| Convert__RegGPRC1_0__imm_95_128, |
| Convert__RegGPRC1_0__imm_95_129, |
| Convert__RegGPRC1_0__imm_95_130, |
| Convert__RegGPRC1_0__imm_95_131, |
| Convert__RegGPRC1_0__imm_95_132, |
| Convert__RegGPRC1_0__imm_95_133, |
| Convert__RegGPRC1_0__imm_95_134, |
| Convert__RegGPRC1_0__imm_95_135, |
| Convert__RegG8RC1_0__imm_95_28, |
| Convert__RegGPRC1_0__imm_95_28, |
| Convert__RegGPRC1_0, |
| Convert__RegG8RC1_0__imm_95_9, |
| Convert__RegGPRC1_0__imm_95_9, |
| Convert__RegG8RC1_0__imm_95_19, |
| Convert__RegGPRC1_0__imm_95_19, |
| Convert__RegGPRC1_0__imm_95_537, |
| Convert__RegGPRC1_0__imm_95_539, |
| Convert__RegGPRC1_0__imm_95_541, |
| Convert__RegGPRC1_0__imm_95_543, |
| Convert__RegGPRC1_0__imm_95_536, |
| Convert__RegGPRC1_0__imm_95_538, |
| Convert__RegGPRC1_0__imm_95_540, |
| Convert__RegGPRC1_0__imm_95_542, |
| Convert__RegGPRC1_0__imm_95_1018, |
| Convert__RegGPRC1_0__Imm1_1, |
| Convert__RegGPRC1_0__imm_95_981, |
| Convert__RegG8RC1_0__imm_95_22, |
| Convert__RegGPRC1_0__imm_95_22, |
| Convert__RegG8RC1_0__imm_95_17, |
| Convert__RegGPRC1_0__imm_95_17, |
| Convert__RegG8RC1_0__imm_95_18, |
| Convert__RegGPRC1_0__imm_95_18, |
| Convert__RegGPRC1_0__imm_95_980, |
| Convert__RegG8RC1_0__RegF8RC1_1, |
| Convert__RegGPRC1_0__RegF8RC1_1, |
| Convert__RegF8RC1_0, |
| Convert__RegF8RC1_1, |
| Convert__RegF8RC1_0__U3Imm1_1, |
| Convert__RegF8RC1_0__U2Imm1_1, |
| Convert__RegGPRC1_0__imm_95_529, |
| Convert__RegGPRC1_0__imm_95_531, |
| Convert__RegGPRC1_0__imm_95_533, |
| Convert__RegGPRC1_0__imm_95_535, |
| Convert__RegGPRC1_0__imm_95_528, |
| Convert__RegGPRC1_0__imm_95_530, |
| Convert__RegGPRC1_0__imm_95_532, |
| Convert__RegGPRC1_0__imm_95_534, |
| Convert__RegGPRC1_0__imm_95_1019, |
| Convert__RegG8RC1_0__imm_95_8, |
| Convert__RegGPRC1_0__imm_95_8, |
| Convert__RegGPRC1_0__CRBitMask1_1, |
| Convert__RegGPRC1_0__imm_95_48, |
| Convert__RegGPRC1_0__imm_95_896, |
| Convert__RegG8RC1_0__imm_95_287, |
| Convert__RegGPRC1_0__imm_95_287, |
| Convert__RegG8RC1_0__imm_95_5, |
| Convert__RegGPRC1_0__imm_95_5, |
| Convert__RegG8RC1_0__imm_95_4, |
| Convert__RegGPRC1_0__imm_95_4, |
| Convert__RegG8RC1_0__imm_95_25, |
| Convert__RegGPRC1_0__imm_95_25, |
| Convert__RegG8RC1_0__imm_95_512, |
| Convert__RegGPRC1_0__imm_95_512, |
| Convert__RegG8RC1_0__imm_95_272, |
| Convert__RegG8RC1_0__imm_95_273, |
| Convert__RegG8RC1_0__imm_95_274, |
| Convert__RegG8RC1_0__imm_95_275, |
| Convert__RegGPRC1_0__imm_95_272, |
| Convert__RegGPRC1_0__imm_95_273, |
| Convert__RegGPRC1_0__imm_95_274, |
| Convert__RegGPRC1_0__imm_95_275, |
| Convert__RegGPRC1_0__imm_95_260, |
| Convert__RegGPRC1_0__imm_95_261, |
| Convert__RegGPRC1_0__imm_95_262, |
| Convert__RegGPRC1_0__imm_95_263, |
| Convert__RegGPRC1_0__U4Imm1_1, |
| Convert__RegG8RC1_0__imm_95_26, |
| Convert__RegGPRC1_0__imm_95_26, |
| Convert__RegG8RC1_0__imm_95_27, |
| Convert__RegGPRC1_0__imm_95_27, |
| Convert__RegGPRC1_0__imm_95_990, |
| Convert__RegGPRC1_0__imm_95_991, |
| Convert__RegGPRC1_0__imm_95_268, |
| Convert__RegGPRC1_0__imm_95_988, |
| Convert__RegGPRC1_0__imm_95_989, |
| Convert__RegGPRC1_0__imm_95_269, |
| Convert__RegGPRC1_0__imm_95_986, |
| Convert__RegG8RC1_0__imm_95_13, |
| Convert__RegGPRC1_0__imm_95_13, |
| Convert__RegG8RC1_0__imm_95_3, |
| Convert__RegGPRC1_0__imm_95_3, |
| Convert__RegG8RC1_0__RegVRRC1_1, |
| Convert__RegGPRC1_0__RegVRRC1_1, |
| Convert__RegVRRC1_0, |
| Convert__RegG8RC1_0__RegVSFRC1_1, |
| Convert__RegG8RC1_0__RegVSRC1_1, |
| Convert__RegGPRC1_0__RegVSFRC1_1, |
| Convert__RegG8RC1_0__imm_95_1, |
| Convert__RegGPRC1_0__imm_95_1, |
| Convert__RegG8RC1_0__RegG8RC1_1__RegG8RC1_1, |
| Convert__RegGPRC1_0__RegGPRC1_1__RegGPRC1_1, |
| Convert__RegG8RC1_1__RegG8RC1_2__RegG8RC1_2, |
| Convert__RegGPRC1_1__RegGPRC1_2__RegGPRC1_2, |
| Convert__imm_95_29__RegG8RC1_0, |
| Convert__imm_95_29__RegGPRC1_0, |
| Convert__imm_95_280__RegG8RC1_0, |
| Convert__imm_95_280__RegGPRC1_0, |
| Convert__imm_95_28__RegG8RC1_0, |
| Convert__imm_95_28__RegGPRC1_0, |
| Convert__imm_95_255__RegG8RC1_0, |
| Convert__imm_95_255__RegGPRC1_0, |
| Convert__Imm1_0__RegGPRC1_1, |
| Convert__imm_95_9__RegG8RC1_0, |
| Convert__imm_95_9__RegGPRC1_0, |
| Convert__imm_95_19__RegG8RC1_0, |
| Convert__imm_95_19__RegGPRC1_0, |
| Convert__imm_95_537__RegGPRC1_1, |
| Convert__imm_95_539__RegGPRC1_1, |
| Convert__imm_95_541__RegGPRC1_1, |
| Convert__imm_95_543__RegGPRC1_1, |
| Convert__imm_95_536__RegGPRC1_1, |
| Convert__imm_95_538__RegGPRC1_1, |
| Convert__imm_95_540__RegGPRC1_1, |
| Convert__imm_95_542__RegGPRC1_1, |
| Convert__imm_95_1018__RegGPRC1_0, |
| Convert__RegGPRC1_1__Imm1_0, |
| Convert__imm_95_981__RegGPRC1_0, |
| Convert__imm_95_22__RegG8RC1_0, |
| Convert__imm_95_22__RegGPRC1_0, |
| Convert__imm_95_17__RegG8RC1_0, |
| Convert__imm_95_17__RegGPRC1_0, |
| Convert__imm_95_18__RegG8RC1_0, |
| Convert__imm_95_18__RegGPRC1_0, |
| Convert__imm_95_980__RegGPRC1_0, |
| Convert__RegF8RC1_0__RegG8RC1_1, |
| Convert__RegF8RC1_0__RegGPRC1_1, |
| Convert__Imm1_0__RegF8RC1_1__imm_95_0__imm_95_0, |
| Convert__Imm1_1__RegF8RC1_2__imm_95_0__imm_95_0, |
| Convert__Imm1_0__RegF8RC1_1__U1Imm1_2__Imm1_3, |
| Convert__Imm1_1__RegF8RC1_2__U1Imm1_3__Imm1_4, |
| Convert__U3Imm1_0__U4Imm1_1__imm_95_0, |
| Convert__U3Imm1_1__U4Imm1_2__imm_95_0, |
| Convert__U3Imm1_0__U4Imm1_1__Imm1_2, |
| Convert__U3Imm1_1__U4Imm1_2__U1Imm1_3, |
| Convert__imm_95_529__RegGPRC1_1, |
| Convert__imm_95_531__RegGPRC1_1, |
| Convert__imm_95_533__RegGPRC1_1, |
| Convert__imm_95_535__RegGPRC1_1, |
| Convert__imm_95_528__RegGPRC1_1, |
| Convert__imm_95_530__RegGPRC1_1, |
| Convert__imm_95_532__RegGPRC1_1, |
| Convert__imm_95_534__RegGPRC1_1, |
| Convert__imm_95_1019__RegGPRC1_0, |
| Convert__imm_95_8__RegG8RC1_0, |
| Convert__imm_95_8__RegGPRC1_0, |
| Convert__RegGPRC1_0__imm_95_0, |
| Convert__RegGPRC1_0__U1Imm1_1, |
| Convert__CRBitMask1_0__RegGPRC1_1, |
| Convert__imm_95_48__RegGPRC1_0, |
| Convert__imm_95_896__RegGPRC1_0, |
| Convert__imm_95_25__RegG8RC1_0, |
| Convert__imm_95_25__RegGPRC1_0, |
| Convert__imm_95_512__RegG8RC1_0, |
| Convert__imm_95_512__RegGPRC1_0, |
| Convert__RegGPRC1_1, |
| Convert__imm_95_272__RegG8RC1_1, |
| Convert__imm_95_272__RegGPRC1_1, |
| Convert__imm_95_273__RegG8RC1_1, |
| Convert__imm_95_273__RegGPRC1_1, |
| Convert__imm_95_274__RegG8RC1_1, |
| Convert__imm_95_274__RegGPRC1_1, |
| Convert__imm_95_275__RegG8RC1_1, |
| Convert__imm_95_275__RegGPRC1_1, |
| Convert__imm_95_260__RegGPRC1_1, |
| Convert__imm_95_261__RegGPRC1_1, |
| Convert__imm_95_262__RegGPRC1_1, |
| Convert__imm_95_263__RegGPRC1_1, |
| Convert__imm_95_272__RegG8RC1_0, |
| Convert__imm_95_272__RegGPRC1_0, |
| Convert__imm_95_273__RegG8RC1_0, |
| Convert__imm_95_273__RegGPRC1_0, |
| Convert__imm_95_274__RegG8RC1_0, |
| Convert__imm_95_274__RegGPRC1_0, |
| Convert__imm_95_275__RegG8RC1_0, |
| Convert__imm_95_275__RegGPRC1_0, |
| Convert__imm_95_260__RegGPRC1_0, |
| Convert__imm_95_261__RegGPRC1_0, |
| Convert__imm_95_262__RegGPRC1_0, |
| Convert__imm_95_263__RegGPRC1_0, |
| Convert__RegGPRC1_1__U4Imm1_0, |
| Convert__imm_95_26__RegG8RC1_0, |
| Convert__imm_95_26__RegGPRC1_0, |
| Convert__imm_95_27__RegG8RC1_0, |
| Convert__imm_95_27__RegGPRC1_0, |
| Convert__imm_95_990__RegGPRC1_0, |
| Convert__imm_95_991__RegGPRC1_0, |
| Convert__imm_95_988__RegGPRC1_0, |
| Convert__imm_95_284__RegG8RC1_0, |
| Convert__imm_95_284__RegGPRC1_0, |
| Convert__imm_95_989__RegGPRC1_0, |
| Convert__imm_95_285__RegG8RC1_0, |
| Convert__imm_95_285__RegGPRC1_0, |
| Convert__imm_95_986__RegGPRC1_0, |
| Convert__imm_95_13__RegG8RC1_0, |
| Convert__imm_95_13__RegGPRC1_0, |
| Convert__imm_95_3__RegG8RC1_0, |
| Convert__imm_95_3__RegGPRC1_0, |
| Convert__RegVRRC1_0__RegG8RC1_1, |
| Convert__RegVRRC1_0__RegGPRC1_1, |
| Convert__RegVRRC1_0__U16Imm1_1, |
| Convert__RegVSFRC1_0__RegG8RC1_1, |
| Convert__RegVSRC1_0__RegG8RCNoX01_1__RegG8RC1_2, |
| Convert__RegVSFRC1_0__RegGPRC1_1, |
| Convert__RegVSRC1_0__RegGPRC1_1, |
| Convert__imm_95_1__RegG8RC1_0, |
| Convert__imm_95_1__RegGPRC1_0, |
| Convert__regR0__regR0__imm_95_0, |
| Convert__regX0__regX0__imm_95_0, |
| Convert__RegGPRC1_0__RegGPRC1_1__U16Imm1_2, |
| Convert__RegGPRC1_0__ImmZero1_1__S34Imm1_2, |
| Convert__RegGPRC1_0__RegGPRC1_1__S34Imm1_2, |
| Convert__RegGPRC1_1__RegGPRC1_2__imm_95_1, |
| Convert__RegGPRC1_1__RegGPRC1_2__U1Imm1_3, |
| Convert__RegGPRC1_0__DispRI341_1__ImmZero1_2, |
| Convert__RegGPRC1_0__DispRI341_1__RegGxRCNoR01_2, |
| Convert__RegG8RC1_0__DispRI341_1__ImmZero1_2, |
| Convert__RegG8RC1_0__DispRI341_1__RegGxRCNoR01_2, |
| Convert__RegF8RC1_0__DispRI341_1__ImmZero1_2, |
| Convert__RegF8RC1_0__DispRI341_1__RegGxRCNoR01_2, |
| Convert__RegF4RC1_0__DispRI341_1__ImmZero1_2, |
| Convert__RegF4RC1_0__DispRI341_1__RegGxRCNoR01_2, |
| Convert__RegGPRC1_0__S34Imm1_1, |
| Convert__RegVFRC1_0__DispRI341_1__ImmZero1_2, |
| Convert__RegVFRC1_0__DispRI341_1__RegGxRCNoR01_2, |
| Convert__RegVSRC1_0__DispRI341_1__ImmZero1_2, |
| Convert__RegVSRC1_0__DispRI341_1__RegGxRCNoR01_2, |
| Convert__RegVSRpRC1_0__DispRI341_1__ImmZero1_2, |
| Convert__RegVSRpRC1_0__DispRI341_1__RegGxRCNoR01_2, |
| Convert__RegACCRC1_0__RegVSRC1_1__RegVSRC1_2__U4Imm1_3__U4Imm1_4__U2Imm1_5, |
| Convert__RegACCRC1_0__Tie0_1_1__RegVSRC1_1__RegVSRC1_2__U4Imm1_3__U4Imm1_4__U2Imm1_5, |
| Convert__RegACCRC1_0__RegVSRC1_1__RegVSRC1_2__U4Imm1_3__U4Imm1_4, |
| Convert__RegACCRC1_0__Tie0_1_1__RegVSRC1_1__RegVSRC1_2__U4Imm1_3__U4Imm1_4, |
| Convert__RegACCRC1_0__RegVSRpEvenRC1_1__RegVSRC1_2__U4Imm1_3__U2Imm1_4, |
| Convert__RegACCRC1_0__Tie0_1_1__RegVSRpEvenRC1_1__RegVSRC1_2__U4Imm1_3__U2Imm1_4, |
| Convert__RegACCRC1_0__RegVSRC1_1__RegVSRC1_2__U4Imm1_3__U4Imm1_4__U8Imm1_5, |
| Convert__RegACCRC1_0__Tie0_1_1__RegVSRC1_1__RegVSRC1_2__U4Imm1_3__U4Imm1_4__U8Imm1_5, |
| Convert__RegACCRC1_0__RegVSRC1_1__RegVSRC1_2__U4Imm1_3__U4Imm1_4__U4Imm1_5, |
| Convert__RegACCRC1_0__Tie0_1_1__RegVSRC1_1__RegVSRC1_2__U4Imm1_3__U4Imm1_4__U4Imm1_5, |
| Convert__imm_95_2, |
| Convert__U1Imm1_0, |
| Convert__RegG8RC1_0__RegG8RC1_1__RegGPRC1_2__U6Imm1_3, |
| Convert__RegG8RC1_1__RegG8RC1_2__RegGPRC1_3__U6Imm1_4, |
| Convert__RegG8RC1_0__Tie0_1_1__RegG8RC1_1__U6Imm1_2__U6Imm1_3, |
| Convert__RegG8RC1_1__Tie0_1_1__RegG8RC1_2__U6Imm1_3__U6Imm1_4, |
| Convert__RegG8RC1_0__RegG8RC1_1__U5Imm1_2__Imm1_3, |
| Convert__RegG8RC1_1__RegG8RC1_2__U5Imm1_3__Imm1_4, |
| Convert__RegGPRC1_0__Tie0_1_1__RegGPRC1_1__U5Imm1_2__U5Imm1_3__U5Imm1_4, |
| Convert__RegGPRC1_1__Tie0_1_1__RegGPRC1_2__U5Imm1_3__U5Imm1_4__U5Imm1_5, |
| Convert__RegGPRC1_0__RegGPRC1_1__U5Imm1_2__U5Imm1_3__U5Imm1_4, |
| Convert__RegGPRC1_1__RegGPRC1_2__U5Imm1_3__U5Imm1_4__U5Imm1_5, |
| Convert__RegGPRC1_0__RegGPRC1_1__RegGPRC1_2__U5Imm1_3__U5Imm1_4, |
| Convert__RegGPRC1_1__RegGPRC1_2__RegGPRC1_3__U5Imm1_4__U5Imm1_5, |
| Convert__RegG8RC1_0__RegG8RC1_1__RegGPRC1_2__imm_95_0, |
| Convert__RegG8RC1_1__RegG8RC1_2__RegGPRC1_3__imm_95_0, |
| Convert__RegG8RC1_0__RegG8RC1_1__U6Imm1_2__imm_95_0, |
| Convert__RegG8RC1_0__RegGPRC1_1__U6Imm1_2__imm_95_0, |
| Convert__RegG8RC1_1__RegG8RC1_2__U6Imm1_3__imm_95_0, |
| Convert__RegG8RC1_0__RegG8RC1_1__RegG8RC1_2__imm_95_0__imm_95_31, |
| Convert__RegGPRC1_0__RegGPRC1_1__RegGPRC1_2__imm_95_0__imm_95_31, |
| Convert__RegG8RC1_1__RegG8RC1_2__RegG8RC1_3__imm_95_0__imm_95_31, |
| Convert__RegGPRC1_1__RegGPRC1_2__RegGPRC1_3__imm_95_0__imm_95_31, |
| Convert__RegG8RC1_0__RegG8RC1_1__U5Imm1_2__imm_95_0__imm_95_31, |
| Convert__RegGPRC1_0__RegGPRC1_1__U5Imm1_2__imm_95_0__imm_95_31, |
| Convert__RegG8RC1_1__RegG8RC1_2__U5Imm1_3__imm_95_0__imm_95_31, |
| Convert__RegGPRC1_1__RegGPRC1_2__U5Imm1_3__imm_95_0__imm_95_31, |
| Convert__Imm1_0, |
| Convert__RegGPRC1_0__RegCRRC1_1, |
| Convert__RegGPRC1_0__RegCRBITRC1_1, |
| Convert__RegG8RC1_0__RegG8RC1_1__RegGPRC1_2, |
| Convert__RegG8RC1_1__RegG8RC1_2__RegGPRC1_3, |
| Convert__RegGPRC1_1__RegGxRCNoR01_2__RegGxRC1_3, |
| Convert__imm_95_0__RegGPRC1_0__DispRI1_1__RegGxRCNoR01_2, |
| Convert__imm_95_0__RegGPRC1_0__RegGxRCNoR01_1__RegGxRC1_2, |
| Convert__RegG8RC1_1__RegGxRCNoR01_2__RegGxRC1_3, |
| Convert__imm_95_0__RegG8RC1_0__DispRIX1_1__RegGxRCNoR01_2, |
| Convert__imm_95_0__RegG8RC1_0__RegGxRCNoR01_1__RegGxRC1_2, |
| Convert__imm_95_0__RegF8RC1_0__DispRI1_1__RegGxRCNoR01_2, |
| Convert__imm_95_0__RegF8RC1_0__RegGxRCNoR01_1__RegGxRC1_2, |
| Convert__imm_95_0__RegF4RC1_0__DispRI1_1__RegGxRCNoR01_2, |
| Convert__imm_95_0__RegF4RC1_0__RegGxRCNoR01_1__RegGxRC1_2, |
| Convert__RegG8pRC1_0__DispRIX1_1__RegGxRCNoR01_2, |
| Convert__RegG8pRC1_1__RegGxRCNoR01_2__RegGxRC1_3, |
| Convert__RegG8RC1_0__RegG8RC1_2__RegG8RC1_1, |
| Convert__RegGPRC1_0__RegGPRC1_2__RegGPRC1_1, |
| Convert__RegG8RC1_1__RegG8RC1_3__RegG8RC1_2, |
| Convert__RegGPRC1_1__RegGPRC1_3__RegGPRC1_2, |
| Convert__RegG8RC1_0__RegG8RC1_2__RegG8RC1_3__U1Imm1_1, |
| Convert__RegG8RC1_1__RegG8RC1_3__RegG8RC1_4__U1Imm1_2, |
| Convert__RegG8RC1_0__S16Imm1_1, |
| Convert__U2Imm1_0, |
| Convert__U5Imm1_1__RegGPRC1_2__RegGPRC1_3, |
| Convert__U5Imm1_1__RegGPRC1_2__U5Imm1_3, |
| Convert__U1Imm1_1, |
| Convert__U5Imm1_0__RegG8RC1_1__RegG8RC1_2, |
| Convert__imm_95_4__RegG8RC1_0__RegG8RC1_1, |
| Convert__imm_95_4__RegG8RC1_0__S16Imm1_1, |
| Convert__imm_95_12__RegG8RC1_0__RegG8RC1_1, |
| Convert__imm_95_12__RegG8RC1_0__S16Imm1_1, |
| Convert__imm_95_8__RegG8RC1_0__RegG8RC1_1, |
| Convert__imm_95_8__RegG8RC1_0__S16Imm1_1, |
| Convert__U5Imm1_0__RegG8RC1_1__S16Imm1_2, |
| Convert__imm_95_20__RegG8RC1_0__RegG8RC1_1, |
| Convert__imm_95_20__RegG8RC1_0__S16Imm1_1, |
| Convert__imm_95_5__RegG8RC1_0__RegG8RC1_1, |
| Convert__imm_95_5__RegG8RC1_0__S16Imm1_1, |
| Convert__imm_95_1__RegG8RC1_0__RegG8RC1_1, |
| Convert__imm_95_1__RegG8RC1_0__S16Imm1_1, |
| Convert__imm_95_6__RegG8RC1_0__RegG8RC1_1, |
| Convert__imm_95_6__RegG8RC1_0__S16Imm1_1, |
| Convert__imm_95_2__RegG8RC1_0__RegG8RC1_1, |
| Convert__imm_95_2__RegG8RC1_0__S16Imm1_1, |
| Convert__imm_95_16__RegG8RC1_0__RegG8RC1_1, |
| Convert__imm_95_16__RegG8RC1_0__S16Imm1_1, |
| Convert__imm_95_24__RegG8RC1_0__RegG8RC1_1, |
| Convert__imm_95_24__RegG8RC1_0__S16Imm1_1, |
| Convert__imm_95_31__RegG8RC1_0__RegG8RC1_1, |
| Convert__imm_95_31__RegG8RC1_0__S16Imm1_1, |
| Convert__regR0__RegGPRC1_0, |
| Convert__RegGPRC1_1__RegGPRC1_0, |
| Convert__RegGPRC1_0__RegGPRC1_1__Imm1_2, |
| Convert__RegGPRC1_0__RegGPRC1_1__imm_95_1, |
| Convert__imm_95_31__regR0__regR0, |
| Convert__U5Imm1_0__RegGPRC1_1__RegGPRC1_2, |
| Convert__imm_95_4__RegGPRC1_0__RegGPRC1_1, |
| Convert__imm_95_4__RegGPRC1_0__S16Imm1_1, |
| Convert__imm_95_12__RegGPRC1_0__RegGPRC1_1, |
| Convert__imm_95_12__RegGPRC1_0__S16Imm1_1, |
| Convert__imm_95_8__RegGPRC1_0__RegGPRC1_1, |
| Convert__imm_95_8__RegGPRC1_0__S16Imm1_1, |
| Convert__U5Imm1_0__RegGPRC1_1__S16Imm1_2, |
| Convert__imm_95_20__RegGPRC1_0__RegGPRC1_1, |
| Convert__imm_95_20__RegGPRC1_0__S16Imm1_1, |
| Convert__imm_95_5__RegGPRC1_0__RegGPRC1_1, |
| Convert__imm_95_5__RegGPRC1_0__S16Imm1_1, |
| Convert__imm_95_1__RegGPRC1_0__RegGPRC1_1, |
| Convert__imm_95_1__RegGPRC1_0__S16Imm1_1, |
| Convert__imm_95_6__RegGPRC1_0__RegGPRC1_1, |
| Convert__imm_95_6__RegGPRC1_0__S16Imm1_1, |
| Convert__imm_95_2__RegGPRC1_0__RegGPRC1_1, |
| Convert__imm_95_2__RegGPRC1_0__S16Imm1_1, |
| Convert__imm_95_16__RegGPRC1_0__RegGPRC1_1, |
| Convert__imm_95_16__RegGPRC1_0__S16Imm1_1, |
| Convert__imm_95_24__RegGPRC1_0__RegGPRC1_1, |
| Convert__imm_95_24__RegGPRC1_0__S16Imm1_1, |
| Convert__imm_95_31__RegGPRC1_0__RegGPRC1_1, |
| Convert__imm_95_31__RegGPRC1_0__S16Imm1_1, |
| Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2, |
| Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2__RegVRRC1_3, |
| Convert__RegVRRC1_0__U5Imm1_2__RegVRRC1_1, |
| Convert__RegVRRC1_0__RegVRRC1_1__RegGPRC1_2, |
| Convert__RegVRRC1_0__RegVRRC1_1, |
| Convert__RegCRRC1_0__RegVRRC1_1__RegVRRC1_2, |
| Convert__RegG8RC1_0__RegVRRC1_1__U1Imm1_2, |
| Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2__RegGPRC1_3, |
| Convert__RegVRRC1_0__U4Imm1_2__RegVRRC1_1, |
| Convert__RegG8RC1_0__RegG8RC1_1__RegVRRC1_2, |
| Convert__RegG8RC1_0__RegVRRC1_1__U3Imm1_2, |
| Convert__RegVRRC1_0__Tie0_1_1__RegGPRC1_1__RegGPRC1_2, |
| Convert__RegVRRC1_0__Tie0_1_1__RegGPRC1_1__RegVRRC1_2, |
| Convert__RegVRRC1_0__Tie0_1_1__U4Imm1_2__RegG8RC1_1, |
| Convert__RegVRRC1_0__Tie0_1_1__RegG8RC1_1__RegG8RC1_2, |
| Convert__RegVRRC1_0__Tie0_1_1__U4Imm1_2__RegVRRC1_1, |
| Convert__RegVRRC1_0__Tie0_1_1__U4Imm1_2__RegGPRC1_1, |
| Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_1, |
| Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2__Tie0_1_1, |
| Convert__RegVRRC1_0__RegVRRC1_1__U1Imm1_2__U4Imm1_3, |
| Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2__U3Imm1_3, |
| Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2__U4Imm1_3, |
| Convert__RegVRRC1_0__S5Imm1_1, |
| Convert__RegVSFRC1_0__RegVSFRC1_1, |
| Convert__RegVSFRC1_0__RegVSFRC1_1__RegVSFRC1_2, |
| Convert__RegVSSRC1_0__RegVSSRC1_1__RegVSSRC1_2, |
| Convert__RegVSRC1_0__RegVSFRC1_1__RegVSFRC1_2, |
| Convert__RegCRRC1_0__RegVSFRC1_1__RegVSFRC1_2, |
| Convert__RegVRRC1_0__RegVFRC1_1, |
| Convert__RegVSRC1_0__RegVSSRC1_1, |
| Convert__RegVFRC1_0__RegVRRC1_1, |
| Convert__RegVSSRC1_0__RegVSRC1_1, |
| Convert__RegVSSRC1_0__RegVSFRC1_1, |
| Convert__RegVSRC1_0__RegG8RC1_1__RegG8RC1_2, |
| Convert__RegVRRC1_0__RegVRRC1_1__RegVSFRC1_2, |
| Convert__RegVSFRC1_0__Tie0_1_1__RegVSFRC1_1__RegVSFRC1_2, |
| Convert__RegVSSRC1_0__Tie0_1_1__RegVSSRC1_1__RegVSSRC1_2, |
| Convert__RegVRRC1_0__Tie0_1_1__RegVRRC1_1__RegVRRC1_2, |
| Convert__RegVSSRC1_0__RegVSSRC1_1, |
| Convert__RegVRRC1_1__U1Imm1_0__RegVRRC1_2__U2Imm1_3, |
| Convert__RegCRRC1_0__RegVSFRC1_1, |
| Convert__RegCRRC1_0__U7Imm1_2__RegVSFRC1_1, |
| Convert__RegCRRC1_0__U7Imm1_2__RegVRRC1_1, |
| Convert__RegVSRC1_0__RegVSRC1_1, |
| Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2, |
| Convert__RegACCRC1_0__RegVSRC1_1__RegVSRC1_2, |
| Convert__RegACCRC1_0__Tie0_1_1__RegVSRC1_1__RegVSRC1_2, |
| Convert__RegVSRC1_1__RegVSRC1_2__RegVSRC1_3, |
| Convert__RegACCRC1_0__RegVSRpEvenRC1_1__RegVSRC1_2, |
| Convert__RegACCRC1_0__Tie0_1_1__RegVSRpEvenRC1_1__RegVSRC1_2, |
| Convert__RegVSRC1_0__Tie0_1_1__RegVSRC1_1__RegVSRC1_2, |
| Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_1, |
| Convert__RegCRRC1_0__RegVSRC1_1__RegVSRC1_2, |
| Convert__RegCRRC1_0__RegVSRC1_1, |
| Convert__RegVSRC1_0__U7Imm1_2__RegVSRC1_1, |
| Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2__RegVSRC1_3, |
| Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2__RegVSRC1_3__U8Imm1_4, |
| Convert__RegVSFRC1_0__RegVSRC1_1__U4Imm1_2, |
| Convert__RegVSRC1_0__RegVRRC1_1__S5Imm1_2, |
| Convert__RegVSRC1_0__Tie0_1_1__RegVSRC1_1__U4Imm1_2, |
| Convert__RegACCRC1_0__Tie0_1_1, |
| Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2__imm_95_0, |
| Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2__imm_95_3, |
| Convert__RegVSRC1_0__RegVSRC1_1__Tie0_1_1__RegVSRC1_2, |
| Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2__U2Imm1_3, |
| Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2__RegVSRC1_3__U3Imm1_4, |
| Convert__RegACCRC1_0, |
| Convert__RegVSRC1_0__RegVSFRC1_1__imm_95_0, |
| Convert__RegVSRC1_0__RegVSFRC1_1__imm_95_3, |
| Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_1__imm_95_0, |
| Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_1__imm_95_3, |
| Convert__RegVSRC1_0__Tie0_1_1__U1Imm1_1__Imm1_2, |
| Convert__RegVSRC1_0__U8Imm1_1, |
| Convert__RegVSRC1_0__Imm1_1, |
| Convert__RegVSRC1_0__RegVSRC1_1__U2Imm1_2, |
| Convert__RegVSRC1_0__RegVSFRC1_1__imm_95_2, |
| Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_1__imm_95_2, |
| CVT_NUM_SIGNATURES |
| }; |
| |
| } // end anonymous namespace |
| |
| static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][15] = { |
| // Convert__RegG8RC1_0__RegG8RC1_1__TLSReg1_2 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addTLSRegOperands, 3, CVT_Done }, |
| // Convert__RegGPRC1_0__RegGPRC1_1__RegGPRC1_2 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_Done }, |
| // Convert__RegGPRC1_1__RegGPRC1_2__RegGPRC1_3 |
| { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addRegGPRCOperands, 4, CVT_Done }, |
| // Convert__RegGPRC1_0__RegGPRC1_1__RegGPRC1_2__U2Imm1_3 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addImmOperands, 4, CVT_Done }, |
| // Convert__RegGPRC1_0__RegGPRCNoR01_1__S16Imm1_2 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCNoR0Operands, 2, CVT_95_addS16ImmOperands, 3, CVT_Done }, |
| // Convert__RegGPRC1_0__RegGPRC1_1__S16Imm1_2 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addS16ImmOperands, 3, CVT_Done }, |
| // Convert__RegGPRC1_1__RegGPRC1_2__S16Imm1_3 |
| { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addS16ImmOperands, 4, CVT_Done }, |
| // Convert__RegGPRC1_0__RegGPRCNoR01_1__S17Imm1_2 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCNoR0Operands, 2, CVT_95_addS16ImmOperands, 3, CVT_Done }, |
| // Convert__RegGPRC1_0__RegGPRC1_1 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__RegGPRC1_1__RegGPRC1_2 |
| { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_Done }, |
| // Convert__RegG8RC1_0__Imm1_1 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__RegGPRC1_1__RegGPRC1_2__U16Imm1_3 |
| { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addU16ImmOperands, 4, CVT_Done }, |
| // Convert_NoOperands |
| { CVT_Done }, |
| // Convert__DirectBr1_0 |
| { CVT_95_addBranchTargetOperands, 1, CVT_Done }, |
| // Convert__U5Imm1_0__RegCRBITRC1_1__CondBr1_2 |
| { CVT_95_addImmOperands, 1, CVT_95_addRegCRBITRCOperands, 2, CVT_95_addBranchTargetOperands, 3, CVT_Done }, |
| // Convert__U5Imm1_1__ATBitsAsHint1_0__RegCRBITRC1_2__CondBr1_3 |
| { CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 1, CVT_95_addRegCRBITRCOperands, 3, CVT_95_addBranchTargetOperands, 4, CVT_Done }, |
| // Convert__U5Imm1_0__imm_95_3__RegCRBITRC1_1__CondBr1_2 |
| { CVT_95_addImmOperands, 1, CVT_imm_95_3, 0, CVT_95_addRegCRBITRCOperands, 2, CVT_95_addBranchTargetOperands, 3, CVT_Done }, |
| // Convert__U5Imm1_0__imm_95_2__RegCRBITRC1_1__CondBr1_2 |
| { CVT_95_addImmOperands, 1, CVT_imm_95_2, 0, CVT_95_addRegCRBITRCOperands, 2, CVT_95_addBranchTargetOperands, 3, CVT_Done }, |
| // Convert__U5Imm1_0__RegCRBITRC1_1__imm_95_0 |
| { CVT_95_addImmOperands, 1, CVT_95_addRegCRBITRCOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__U5Imm1_0__RegCRBITRC1_1__Imm1_2 |
| { CVT_95_addImmOperands, 1, CVT_95_addRegCRBITRCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegVRRC1_1__RegVRRC1_2__RegVRRC1_3__U1Imm1_4 |
| { CVT_95_addRegVRRCOperands, 2, CVT_95_addRegVRRCOperands, 3, CVT_95_addRegVRRCOperands, 4, CVT_95_addImmOperands, 5, CVT_Done }, |
| // Convert__RegVRRC1_1__RegVRRC1_2__U1Imm1_3 |
| { CVT_95_addRegVRRCOperands, 2, CVT_95_addRegVRRCOperands, 3, CVT_95_addImmOperands, 4, CVT_Done }, |
| // Convert__RegVRRC1_1__RegVRRC1_2__RegVRRC1_3 |
| { CVT_95_addRegVRRCOperands, 2, CVT_95_addRegVRRCOperands, 3, CVT_95_addRegVRRCOperands, 4, CVT_Done }, |
| // Convert__RegVRRC1_1__RegVRRC1_2 |
| { CVT_95_addRegVRRCOperands, 2, CVT_95_addRegVRRCOperands, 3, CVT_Done }, |
| // Convert__CondBr1_0 |
| { CVT_95_addBranchTargetOperands, 1, CVT_Done }, |
| // Convert__imm_95_0__RegCRBITRC1_0__CondBr1_1 |
| { CVT_imm_95_0, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_0__RegCRBITRC1_0__imm_95_0 |
| { CVT_imm_95_0, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__imm_95_8__RegCRBITRC1_0__CondBr1_1 |
| { CVT_imm_95_8, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_8__RegCRBITRC1_0__imm_95_0 |
| { CVT_imm_95_8, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__imm_95_2__RegCRBITRC1_0__CondBr1_1 |
| { CVT_imm_95_2, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_2__RegCRBITRC1_0__imm_95_0 |
| { CVT_imm_95_2, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__imm_95_10__RegCRBITRC1_0__CondBr1_1 |
| { CVT_imm_95_10, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_10__RegCRBITRC1_0__imm_95_0 |
| { CVT_imm_95_10, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__imm_95_76__regCR0__CondBr1_0 |
| { CVT_imm_95_76, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done }, |
| // Convert__imm_95_76__RegCRRC1_0__CondBr1_1 |
| { CVT_imm_95_76, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_79__regCR0__CondBr1_0 |
| { CVT_imm_95_79, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done }, |
| // Convert__imm_95_79__RegCRRC1_0__CondBr1_1 |
| { CVT_imm_95_79, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_78__regCR0__CondBr1_0 |
| { CVT_imm_95_78, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done }, |
| // Convert__imm_95_78__RegCRRC1_0__CondBr1_1 |
| { CVT_imm_95_78, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_76__regCR0 |
| { CVT_imm_95_76, 0, CVT_regCR0, 0, CVT_Done }, |
| // Convert__imm_95_76__RegCRRC1_0 |
| { CVT_imm_95_76, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_79__regCR0 |
| { CVT_imm_95_79, 0, CVT_regCR0, 0, CVT_Done }, |
| // Convert__imm_95_79__RegCRRC1_0 |
| { CVT_imm_95_79, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_78__regCR0 |
| { CVT_imm_95_78, 0, CVT_regCR0, 0, CVT_Done }, |
| // Convert__imm_95_78__RegCRRC1_0 |
| { CVT_imm_95_78, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_4__RegCRBITRC1_0__CondBr1_1 |
| { CVT_imm_95_4, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_7__RegCRBITRC1_0__CondBr1_1 |
| { CVT_imm_95_7, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_6__RegCRBITRC1_0__CondBr1_1 |
| { CVT_imm_95_6, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_4__RegCRBITRC1_0__imm_95_0 |
| { CVT_imm_95_4, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__imm_95_7__RegCRBITRC1_0__imm_95_0 |
| { CVT_imm_95_7, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__imm_95_6__RegCRBITRC1_0__imm_95_0 |
| { CVT_imm_95_6, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__imm_95_4__regCR0__CondBr1_0 |
| { CVT_imm_95_4, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done }, |
| // Convert__imm_95_4__RegCRRC1_0__CondBr1_1 |
| { CVT_imm_95_4, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_7__regCR0__CondBr1_0 |
| { CVT_imm_95_7, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done }, |
| // Convert__imm_95_7__RegCRRC1_0__CondBr1_1 |
| { CVT_imm_95_7, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_6__regCR0__CondBr1_0 |
| { CVT_imm_95_6, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done }, |
| // Convert__imm_95_6__RegCRRC1_0__CondBr1_1 |
| { CVT_imm_95_6, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_4__regCR0 |
| { CVT_imm_95_4, 0, CVT_regCR0, 0, CVT_Done }, |
| // Convert__imm_95_4__RegCRRC1_0 |
| { CVT_imm_95_4, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_7__regCR0 |
| { CVT_imm_95_7, 0, CVT_regCR0, 0, CVT_Done }, |
| // Convert__imm_95_7__RegCRRC1_0 |
| { CVT_imm_95_7, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_6__regCR0 |
| { CVT_imm_95_6, 0, CVT_regCR0, 0, CVT_Done }, |
| // Convert__imm_95_6__RegCRRC1_0 |
| { CVT_imm_95_6, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_44__regCR0__CondBr1_0 |
| { CVT_imm_95_44, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done }, |
| // Convert__imm_95_44__RegCRRC1_0__CondBr1_1 |
| { CVT_imm_95_44, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_47__regCR0__CondBr1_0 |
| { CVT_imm_95_47, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done }, |
| // Convert__imm_95_47__RegCRRC1_0__CondBr1_1 |
| { CVT_imm_95_47, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_46__regCR0__CondBr1_0 |
| { CVT_imm_95_46, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done }, |
| // Convert__imm_95_46__RegCRRC1_0__CondBr1_1 |
| { CVT_imm_95_46, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_44__regCR0 |
| { CVT_imm_95_44, 0, CVT_regCR0, 0, CVT_Done }, |
| // Convert__imm_95_44__RegCRRC1_0 |
| { CVT_imm_95_44, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_47__regCR0 |
| { CVT_imm_95_47, 0, CVT_regCR0, 0, CVT_Done }, |
| // Convert__imm_95_47__RegCRRC1_0 |
| { CVT_imm_95_47, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_46__regCR0 |
| { CVT_imm_95_46, 0, CVT_regCR0, 0, CVT_Done }, |
| // Convert__imm_95_46__RegCRRC1_0 |
| { CVT_imm_95_46, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done }, |
| // Convert__DirectBr1_0__Imm1_1 |
| { CVT_95_addBranchTargetOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__imm_95_36__regCR0__CondBr1_0 |
| { CVT_imm_95_36, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done }, |
| // Convert__imm_95_36__RegCRRC1_0__CondBr1_1 |
| { CVT_imm_95_36, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_39__regCR0__CondBr1_0 |
| { CVT_imm_95_39, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done }, |
| // Convert__imm_95_39__RegCRRC1_0__CondBr1_1 |
| { CVT_imm_95_39, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_38__regCR0__CondBr1_0 |
| { CVT_imm_95_38, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done }, |
| // Convert__imm_95_38__RegCRRC1_0__CondBr1_1 |
| { CVT_imm_95_38, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_36__regCR0 |
| { CVT_imm_95_36, 0, CVT_regCR0, 0, CVT_Done }, |
| // Convert__imm_95_36__RegCRRC1_0 |
| { CVT_imm_95_36, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_39__regCR0 |
| { CVT_imm_95_39, 0, CVT_regCR0, 0, CVT_Done }, |
| // Convert__imm_95_39__RegCRRC1_0 |
| { CVT_imm_95_39, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_38__regCR0 |
| { CVT_imm_95_38, 0, CVT_regCR0, 0, CVT_Done }, |
| // Convert__imm_95_38__RegCRRC1_0 |
| { CVT_imm_95_38, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_12__regCR0__CondBr1_0 |
| { CVT_imm_95_12, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done }, |
| // Convert__imm_95_12__RegCRRC1_0__CondBr1_1 |
| { CVT_imm_95_12, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_15__regCR0__CondBr1_0 |
| { CVT_imm_95_15, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done }, |
| // Convert__imm_95_15__RegCRRC1_0__CondBr1_1 |
| { CVT_imm_95_15, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_14__regCR0__CondBr1_0 |
| { CVT_imm_95_14, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done }, |
| // Convert__imm_95_14__RegCRRC1_0__CondBr1_1 |
| { CVT_imm_95_14, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_12__regCR0 |
| { CVT_imm_95_12, 0, CVT_regCR0, 0, CVT_Done }, |
| // Convert__imm_95_12__RegCRRC1_0 |
| { CVT_imm_95_12, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_15__regCR0 |
| { CVT_imm_95_15, 0, CVT_regCR0, 0, CVT_Done }, |
| // Convert__imm_95_15__RegCRRC1_0 |
| { CVT_imm_95_15, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_14__regCR0 |
| { CVT_imm_95_14, 0, CVT_regCR0, 0, CVT_Done }, |
| // Convert__imm_95_14__RegCRRC1_0 |
| { CVT_imm_95_14, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_68__regCR0__CondBr1_0 |
| { CVT_imm_95_68, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done }, |
| // Convert__imm_95_68__RegCRRC1_0__CondBr1_1 |
| { CVT_imm_95_68, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_71__regCR0__CondBr1_0 |
| { CVT_imm_95_71, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done }, |
| // Convert__imm_95_71__RegCRRC1_0__CondBr1_1 |
| { CVT_imm_95_71, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_70__regCR0__CondBr1_0 |
| { CVT_imm_95_70, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done }, |
| // Convert__imm_95_70__RegCRRC1_0__CondBr1_1 |
| { CVT_imm_95_70, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_68__regCR0 |
| { CVT_imm_95_68, 0, CVT_regCR0, 0, CVT_Done }, |
| // Convert__imm_95_68__RegCRRC1_0 |
| { CVT_imm_95_68, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_71__regCR0 |
| { CVT_imm_95_71, 0, CVT_regCR0, 0, CVT_Done }, |
| // Convert__imm_95_71__RegCRRC1_0 |
| { CVT_imm_95_71, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_70__regCR0 |
| { CVT_imm_95_70, 0, CVT_regCR0, 0, CVT_Done }, |
| // Convert__imm_95_70__RegCRRC1_0 |
| { CVT_imm_95_70, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_100__regCR0__CondBr1_0 |
| { CVT_imm_95_100, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done }, |
| // Convert__imm_95_100__RegCRRC1_0__CondBr1_1 |
| { CVT_imm_95_100, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_103__regCR0__CondBr1_0 |
| { CVT_imm_95_103, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done }, |
| // Convert__imm_95_103__RegCRRC1_0__CondBr1_1 |
| { CVT_imm_95_103, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_102__regCR0__CondBr1_0 |
| { CVT_imm_95_102, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done }, |
| // Convert__imm_95_102__RegCRRC1_0__CondBr1_1 |
| { CVT_imm_95_102, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_100__regCR0 |
| { CVT_imm_95_100, 0, CVT_regCR0, 0, CVT_Done }, |
| // Convert__imm_95_100__RegCRRC1_0 |
| { CVT_imm_95_100, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_103__regCR0 |
| { CVT_imm_95_103, 0, CVT_regCR0, 0, CVT_Done }, |
| // Convert__imm_95_103__RegCRRC1_0 |
| { CVT_imm_95_103, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_102__regCR0 |
| { CVT_imm_95_102, 0, CVT_regCR0, 0, CVT_Done }, |
| // Convert__imm_95_102__RegCRRC1_0 |
| { CVT_imm_95_102, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done }, |
| // Convert__RegG8RC1_0__RegG8RC1_1__RegG8RC1_2 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_Done }, |
| // Convert__RegG8RC1_0__RegG8RC1_1 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done }, |
| // Convert__imm_95_108__regCR0__CondBr1_0 |
| { CVT_imm_95_108, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done }, |
| // Convert__imm_95_108__RegCRRC1_0__CondBr1_1 |
| { CVT_imm_95_108, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_111__regCR0__CondBr1_0 |
| { CVT_imm_95_111, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done }, |
| // Convert__imm_95_111__RegCRRC1_0__CondBr1_1 |
| { CVT_imm_95_111, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_110__regCR0__CondBr1_0 |
| { CVT_imm_95_110, 0, CVT_regCR0, 0, CVT_95_addBranchTargetOperands, 1, CVT_Done }, |
| // Convert__imm_95_110__RegCRRC1_0__CondBr1_1 |
| { CVT_imm_95_110, 0, CVT_95_addRegCRRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_108__regCR0 |
| { CVT_imm_95_108, 0, CVT_regCR0, 0, CVT_Done }, |
| // Convert__imm_95_108__RegCRRC1_0 |
| { CVT_imm_95_108, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_111__regCR0 |
| { CVT_imm_95_111, 0, CVT_regCR0, 0, CVT_Done }, |
| // Convert__imm_95_111__RegCRRC1_0 |
| { CVT_imm_95_111, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_110__regCR0 |
| { CVT_imm_95_110, 0, CVT_regCR0, 0, CVT_Done }, |
| // Convert__imm_95_110__RegCRRC1_0 |
| { CVT_imm_95_110, 0, CVT_95_addRegCRRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_12__RegCRBITRC1_0__CondBr1_1 |
| { CVT_imm_95_12, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_15__RegCRBITRC1_0__CondBr1_1 |
| { CVT_imm_95_15, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_14__RegCRBITRC1_0__CondBr1_1 |
| { CVT_imm_95_14, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_95_addBranchTargetOperands, 2, CVT_Done }, |
| // Convert__imm_95_12__RegCRBITRC1_0__imm_95_0 |
| { CVT_imm_95_12, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__imm_95_15__RegCRBITRC1_0__imm_95_0 |
| { CVT_imm_95_15, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__imm_95_14__RegCRBITRC1_0__imm_95_0 |
| { CVT_imm_95_14, 0, CVT_95_addRegCRBITRCOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__RegG8RC1_1__imm_95_0__U6Imm1_2 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_imm_95_0, 0, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegG8RC1_0__RegGPRC1_1__imm_95_0__U6Imm1_2 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_imm_95_0, 0, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegG8RC1_1__RegG8RC1_2__imm_95_0__U6Imm1_3 |
| { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_imm_95_0, 0, CVT_95_addImmOperands, 4, CVT_Done }, |
| // Convert__RegG8RC1_0__RegG8RC1_1__U6Imm1_2__U6Imm1_3 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done }, |
| // Convert__RegG8RC1_1__RegG8RC1_2__U6Imm1_3__U6Imm1_4 |
| { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_Done }, |
| // Convert__RegGPRC1_0__RegGPRC1_1__U5Imm1_2__U5Imm1_3 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done }, |
| // Convert__RegGPRC1_1__RegGPRC1_2__U5Imm1_3__U5Imm1_4 |
| { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_Done }, |
| // Convert__RegG8RC1_0__RegG8RC1_1__imm_95_0__U5Imm1_2__imm_95_31 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_imm_95_0, 0, CVT_95_addImmOperands, 3, CVT_imm_95_31, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__RegGPRC1_1__imm_95_0__U5Imm1_2__imm_95_31 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_imm_95_0, 0, CVT_95_addImmOperands, 3, CVT_imm_95_31, 0, CVT_Done }, |
| // Convert__RegG8RC1_1__RegG8RC1_2__imm_95_0__U5Imm1_3__imm_95_31 |
| { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_imm_95_0, 0, CVT_95_addImmOperands, 4, CVT_imm_95_31, 0, CVT_Done }, |
| // Convert__RegGPRC1_1__RegGPRC1_2__imm_95_0__U5Imm1_3__imm_95_31 |
| { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_imm_95_0, 0, CVT_95_addImmOperands, 4, CVT_imm_95_31, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__RegG8RC1_1__U6Imm1_2 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegG8RC1_1__RegG8RC1_2__U6Imm1_3 |
| { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_95_addImmOperands, 4, CVT_Done }, |
| // Convert__RegGPRC1_0__RegGPRC1_1__U5Imm1_2 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegGPRC1_1__RegGPRC1_2__U5Imm1_3 |
| { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addImmOperands, 4, CVT_Done }, |
| // Convert__RegCRRC1_0__RegGPRC1_2__RegGPRC1_3 |
| { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegGPRCOperands, 3, CVT_95_addRegGPRCOperands, 4, CVT_Done }, |
| // Convert__RegCRRC1_0__RegG8RC1_2__RegG8RC1_3 |
| { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegG8RCOperands, 3, CVT_95_addRegG8RCOperands, 4, CVT_Done }, |
| // Convert__regCR0__RegG8RC1_0__RegG8RC1_1 |
| { CVT_regCR0, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done }, |
| // Convert__RegCRRC1_0__RegG8RC1_1__RegG8RC1_2 |
| { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_Done }, |
| // Convert__regCR0__RegG8RC1_0__S16Imm1_1 |
| { CVT_regCR0, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__RegCRRC1_0__RegG8RC1_1__S16Imm1_2 |
| { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addS16ImmOperands, 3, CVT_Done }, |
| // Convert__RegCRRC1_0__RegGPRC1_2__S16Imm1_3 |
| { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegGPRCOperands, 3, CVT_95_addS16ImmOperands, 4, CVT_Done }, |
| // Convert__RegCRRC1_0__RegG8RC1_2__S16Imm1_3 |
| { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegG8RCOperands, 3, CVT_95_addS16ImmOperands, 4, CVT_Done }, |
| // Convert__regCR0__RegG8RC1_0__U16Imm1_1 |
| { CVT_regCR0, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addU16ImmOperands, 2, CVT_Done }, |
| // Convert__RegCRRC1_0__RegG8RC1_1__U16Imm1_2 |
| { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addU16ImmOperands, 3, CVT_Done }, |
| // Convert__RegCRRC1_0__RegGPRC1_2__U16Imm1_3 |
| { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegGPRCOperands, 3, CVT_95_addU16ImmOperands, 4, CVT_Done }, |
| // Convert__RegCRRC1_0__RegG8RC1_2__U16Imm1_3 |
| { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegG8RCOperands, 3, CVT_95_addU16ImmOperands, 4, CVT_Done }, |
| // Convert__regCR0__RegGPRC1_0__RegGPRC1_1 |
| { CVT_regCR0, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__RegCRRC1_0__RegGPRC1_1__RegGPRC1_2 |
| { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_Done }, |
| // Convert__regCR0__RegGPRC1_0__U16Imm1_1 |
| { CVT_regCR0, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addU16ImmOperands, 2, CVT_Done }, |
| // Convert__RegCRRC1_0__RegGPRC1_1__U16Imm1_2 |
| { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addU16ImmOperands, 3, CVT_Done }, |
| // Convert__RegCRRC1_0__U1Imm1_1__RegGPRC1_2__RegGPRC1_3 |
| { CVT_95_addRegCRRCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addRegGPRCOperands, 4, CVT_Done }, |
| // Convert__regCR0__RegGPRC1_0__S16Imm1_1 |
| { CVT_regCR0, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__RegCRRC1_0__RegGPRC1_1__S16Imm1_2 |
| { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addS16ImmOperands, 3, CVT_Done }, |
| // Convert__RegG8RC1_1__RegG8RC1_2 |
| { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_Done }, |
| // Convert__RegGPRC1_0__RegGPRC1_1__imm_95_0 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__RegCRBITRC1_0__RegCRBITRC1_1__RegCRBITRC1_2 |
| { CVT_95_addRegCRBITRCOperands, 1, CVT_95_addRegCRBITRCOperands, 2, CVT_95_addRegCRBITRCOperands, 3, CVT_Done }, |
| // Convert__RegCRBITRC1_0__RegCRBITRC1_0__RegCRBITRC1_0 |
| { CVT_95_addRegCRBITRCOperands, 1, CVT_95_addRegCRBITRCOperands, 1, CVT_95_addRegCRBITRCOperands, 1, CVT_Done }, |
| // Convert__RegCRBITRC1_0__RegCRBITRC1_1__RegCRBITRC1_1 |
| { CVT_95_addRegCRBITRCOperands, 1, CVT_95_addRegCRBITRCOperands, 2, CVT_95_addRegCRBITRCOperands, 2, CVT_Done }, |
| // Convert__RegG8RC1_0__U2Imm1_1 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__RegGxRCNoR01_0__RegGxRC1_1 |
| { CVT_95_addRegGxRCNoR0Operands, 1, CVT_95_addRegGxRCOperands, 2, CVT_Done }, |
| // Convert__U3Imm1_2__RegGxRCNoR01_0__RegGxRC1_1 |
| { CVT_95_addImmOperands, 3, CVT_95_addRegGxRCNoR0Operands, 1, CVT_95_addRegGxRCOperands, 2, CVT_Done }, |
| // Convert__U5Imm1_2__RegGxRCNoR01_0__RegGxRC1_1 |
| { CVT_95_addImmOperands, 3, CVT_95_addRegGxRCNoR0Operands, 1, CVT_95_addRegGxRCOperands, 2, CVT_Done }, |
| // Convert__RegGxRCNoR01_0__RegGxRC1_1__U5Imm1_2 |
| { CVT_95_addRegGxRCNoR0Operands, 1, CVT_95_addRegGxRCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegGxRCNoR01_1__RegGxRC1_2__U5Imm1_0 |
| { CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_95_addImmOperands, 1, CVT_Done }, |
| // Convert__regR0__regR0 |
| { CVT_regR0, 0, CVT_regR0, 0, CVT_Done }, |
| // Convert__RegG8RC1_1__RegG8RC1_2__RegG8RC1_3 |
| { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_95_addRegG8RCOperands, 4, CVT_Done }, |
| // Convert__RegDMRRC1_0__RegDMRRC1_1 |
| { CVT_95_addRegDMRRCOperands, 1, CVT_95_addRegDMRRCOperands, 2, CVT_Done }, |
| // Convert__RegDMRRC1_0 |
| { CVT_95_addRegDMRRCOperands, 1, CVT_Done }, |
| // Convert__RegDMRRC1_0__Tie0_1_1__RegDMRRC1_1 |
| { CVT_95_addRegDMRRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegDMRRCOperands, 2, CVT_Done }, |
| // Convert__RegVSRpRC1_1__RegDMRROWpRC1_0__U2Imm1_2 |
| { CVT_95_addRegVSRpRCOperands, 2, CVT_95_addRegDMRROWpRCOperands, 1, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegVSRpRC1_1__RegVSRpRC1_2__RegACCRC1_0 |
| { CVT_95_addRegVSRpRCOperands, 2, CVT_95_addRegVSRpRCOperands, 3, CVT_95_addRegACCRCOperands, 1, CVT_Done }, |
| // Convert__RegDMRROWpRC1_0__RegVSRpRC1_1__U2Imm1_2 |
| { CVT_95_addRegDMRROWpRCOperands, 1, CVT_95_addRegVSRpRCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegACCRC1_0__RegVSRpRC1_1__RegVSRpRC1_2 |
| { CVT_95_addRegACCRCOperands, 1, CVT_95_addRegVSRpRCOperands, 2, CVT_95_addRegVSRpRCOperands, 3, CVT_Done }, |
| // Convert__U5Imm1_0 |
| { CVT_95_addImmOperands, 1, CVT_Done }, |
| // Convert__U5Imm1_2__RegGPRC1_0__RegGPRC1_1 |
| { CVT_95_addImmOperands, 3, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__RegSPERC1_0__RegSPERC1_1 |
| { CVT_95_addRegSPERCOperands, 1, CVT_95_addRegSPERCOperands, 2, CVT_Done }, |
| // Convert__RegSPERC1_0__RegSPERC1_1__RegSPERC1_2 |
| { CVT_95_addRegSPERCOperands, 1, CVT_95_addRegSPERCOperands, 2, CVT_95_addRegSPERCOperands, 3, CVT_Done }, |
| // Convert__RegSPERC1_0__RegSPE4RC1_1 |
| { CVT_95_addRegSPERCOperands, 1, CVT_95_addRegSPE4RCOperands, 2, CVT_Done }, |
| // Convert__RegSPERC1_0__RegGPRC1_1 |
| { CVT_95_addRegSPERCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__RegCRRC1_0__RegSPERC1_1__RegSPERC1_2 |
| { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegSPERCOperands, 2, CVT_95_addRegSPERCOperands, 3, CVT_Done }, |
| // Convert__RegGPRC1_0__RegSPERC1_1 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegSPERCOperands, 2, CVT_Done }, |
| // Convert__RegSPE4RC1_0__RegSPE4RC1_1 |
| { CVT_95_addRegSPE4RCOperands, 1, CVT_95_addRegSPE4RCOperands, 2, CVT_Done }, |
| // Convert__RegSPE4RC1_0__RegSPE4RC1_1__RegSPE4RC1_2 |
| { CVT_95_addRegSPE4RCOperands, 1, CVT_95_addRegSPE4RCOperands, 2, CVT_95_addRegSPE4RCOperands, 3, CVT_Done }, |
| // Convert__RegSPE4RC1_0__RegSPERC1_1 |
| { CVT_95_addRegSPE4RCOperands, 1, CVT_95_addRegSPERCOperands, 2, CVT_Done }, |
| // Convert__RegSPE4RC1_0__RegGPRC1_1 |
| { CVT_95_addRegSPE4RCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__RegCRRC1_0__RegSPE4RC1_1__RegSPE4RC1_2 |
| { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegSPE4RCOperands, 2, CVT_95_addRegSPE4RCOperands, 3, CVT_Done }, |
| // Convert__RegGPRC1_0__RegSPE4RC1_1 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegSPE4RCOperands, 2, CVT_Done }, |
| // Convert__RegSPERC1_0__RegSPERC1_2__U5Imm1_1 |
| { CVT_95_addRegSPERCOperands, 1, CVT_95_addRegSPERCOperands, 3, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__RegSPERC1_0__DispSPE81_1__RegGxRCNoR01_2 |
| { CVT_95_addRegSPERCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__RegSPERC1_0__RegGxRCNoR01_1__RegGxRC1_2 |
| { CVT_95_addRegSPERCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done }, |
| // Convert__RegSPERC1_0__DispSPE21_1__RegGxRCNoR01_2 |
| { CVT_95_addRegSPERCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__RegSPERC1_0__DispSPE41_1__RegGxRCNoR01_2 |
| { CVT_95_addRegSPERCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__RegSPERC1_0__RegGPRC1_1__RegGPRC1_2 |
| { CVT_95_addRegSPERCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_Done }, |
| // Convert__RegSPERC1_0__RegSPERC1_1__U5Imm1_2 |
| { CVT_95_addRegSPERCOperands, 1, CVT_95_addRegSPERCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegSPERC1_1__RegSPERC1_2__RegSPERC1_3__imm_95_0 |
| { CVT_95_addRegSPERCOperands, 2, CVT_95_addRegSPERCOperands, 3, CVT_95_addRegSPERCOperands, 4, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__RegSPERC1_0__S5Imm1_1 |
| { CVT_95_addRegSPERCOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__RegSPERC1_0__U5Imm1_1__RegSPERC1_2 |
| { CVT_95_addRegSPERCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegSPERCOperands, 3, CVT_Done }, |
| // Convert__RegF4RC1_0__RegF4RC1_1 |
| { CVT_95_addRegF4RCOperands, 1, CVT_95_addRegF4RCOperands, 2, CVT_Done }, |
| // Convert__RegF4RC1_1__RegF4RC1_2 |
| { CVT_95_addRegF4RCOperands, 2, CVT_95_addRegF4RCOperands, 3, CVT_Done }, |
| // Convert__RegF8RC1_0__RegF8RC1_1__RegF8RC1_2 |
| { CVT_95_addRegF8RCOperands, 1, CVT_95_addRegF8RCOperands, 2, CVT_95_addRegF8RCOperands, 3, CVT_Done }, |
| // Convert__RegF8RC1_1__RegF8RC1_2__RegF8RC1_3 |
| { CVT_95_addRegF8RCOperands, 2, CVT_95_addRegF8RCOperands, 3, CVT_95_addRegF8RCOperands, 4, CVT_Done }, |
| // Convert__RegF4RC1_0__RegF4RC1_1__RegF4RC1_2 |
| { CVT_95_addRegF4RCOperands, 1, CVT_95_addRegF4RCOperands, 2, CVT_95_addRegF4RCOperands, 3, CVT_Done }, |
| // Convert__RegF4RC1_1__RegF4RC1_2__RegF4RC1_3 |
| { CVT_95_addRegF4RCOperands, 2, CVT_95_addRegF4RCOperands, 3, CVT_95_addRegF4RCOperands, 4, CVT_Done }, |
| // Convert__RegF8RC1_0__RegF8RC1_1 |
| { CVT_95_addRegF8RCOperands, 1, CVT_95_addRegF8RCOperands, 2, CVT_Done }, |
| // Convert__RegF8RC1_1__RegF8RC1_2 |
| { CVT_95_addRegF8RCOperands, 2, CVT_95_addRegF8RCOperands, 3, CVT_Done }, |
| // Convert__RegF4RC1_0__RegF8RC1_1 |
| { CVT_95_addRegF4RCOperands, 1, CVT_95_addRegF8RCOperands, 2, CVT_Done }, |
| // Convert__RegF4RC1_1__RegF8RC1_2 |
| { CVT_95_addRegF4RCOperands, 2, CVT_95_addRegF8RCOperands, 3, CVT_Done }, |
| // Convert__RegCRRC1_0__RegF4RC1_1__RegF4RC1_2 |
| { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegF4RCOperands, 2, CVT_95_addRegF4RCOperands, 3, CVT_Done }, |
| // Convert__RegF8RC1_0__RegF8RC1_1__RegF8RC1_2__RegF8RC1_3 |
| { CVT_95_addRegF8RCOperands, 1, CVT_95_addRegF8RCOperands, 2, CVT_95_addRegF8RCOperands, 3, CVT_95_addRegF8RCOperands, 4, CVT_Done }, |
| // Convert__RegF8RC1_1__RegF8RC1_2__RegF8RC1_3__RegF8RC1_4 |
| { CVT_95_addRegF8RCOperands, 2, CVT_95_addRegF8RCOperands, 3, CVT_95_addRegF8RCOperands, 4, CVT_95_addRegF8RCOperands, 5, CVT_Done }, |
| // Convert__RegF4RC1_0__RegF4RC1_1__RegF4RC1_2__RegF4RC1_3 |
| { CVT_95_addRegF4RCOperands, 1, CVT_95_addRegF4RCOperands, 2, CVT_95_addRegF4RCOperands, 3, CVT_95_addRegF4RCOperands, 4, CVT_Done }, |
| // Convert__RegF4RC1_1__RegF4RC1_2__RegF4RC1_3__RegF4RC1_4 |
| { CVT_95_addRegF4RCOperands, 2, CVT_95_addRegF4RCOperands, 3, CVT_95_addRegF4RCOperands, 4, CVT_95_addRegF4RCOperands, 5, CVT_Done }, |
| // Convert__RegF4RC1_0__RegF8RC1_1__RegF4RC1_2__RegF4RC1_3 |
| { CVT_95_addRegF4RCOperands, 1, CVT_95_addRegF8RCOperands, 2, CVT_95_addRegF4RCOperands, 3, CVT_95_addRegF4RCOperands, 4, CVT_Done }, |
| // Convert__RegF4RC1_1__RegF8RC1_2__RegF4RC1_3__RegF4RC1_4 |
| { CVT_95_addRegF4RCOperands, 2, CVT_95_addRegF8RCOperands, 3, CVT_95_addRegF4RCOperands, 4, CVT_95_addRegF4RCOperands, 5, CVT_Done }, |
| // Convert__RegCRRC1_0__RegF8RC1_1__RegF8RC1_2 |
| { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegF8RCOperands, 2, CVT_95_addRegF8RCOperands, 3, CVT_Done }, |
| // Convert__RegCRRC1_0__RegF8RC1_1 |
| { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegF8RCOperands, 2, CVT_Done }, |
| // Convert__RegGPRC1_0__DispRIHash1_1__RegGxRCNoR01_2 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__imm_95_0 |
| { CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__U4Imm1_0__RegGxRCNoR01_1__RegGxRC1_2 |
| { CVT_95_addImmOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done }, |
| // Convert__U4Imm1_1__RegGxRCNoR01_2__RegGxRC1_3 |
| { CVT_95_addImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_95_addRegGxRCOperands, 4, CVT_Done }, |
| // Convert__RegGPRC1_0__RegGPRCNoR01_1__RegGPRC1_2__RegCRBITRC1_3 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCNoR0Operands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addRegCRBITRCOperands, 4, CVT_Done }, |
| // Convert__RegG8RC1_0__RegG8RCNoX01_1__RegG8RC1_2__regCR0EQ |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCNoX0Operands, 2, CVT_95_addRegG8RCOperands, 3, CVT_regCR0EQ, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__RegGPRCNoR01_1__RegGPRC1_2__regCR0EQ |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCNoR0Operands, 2, CVT_95_addRegGPRCOperands, 3, CVT_regCR0EQ, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__RegG8RCNoX01_1__RegG8RC1_2__regCR0GT |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCNoX0Operands, 2, CVT_95_addRegG8RCOperands, 3, CVT_regCR0GT, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__RegGPRCNoR01_1__RegGPRC1_2__regCR0GT |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCNoR0Operands, 2, CVT_95_addRegGPRCOperands, 3, CVT_regCR0GT, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__RegG8RCNoX01_1__RegG8RC1_2__regCR0LT |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCNoX0Operands, 2, CVT_95_addRegG8RCOperands, 3, CVT_regCR0LT, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__RegGPRCNoR01_1__RegGPRC1_2__regCR0LT |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCNoR0Operands, 2, CVT_95_addRegGPRCOperands, 3, CVT_regCR0LT, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__DispRI1_1__RegGxRCNoR01_2 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__RegGPRC1_0__RegGxRCNoR01_1__RegGxRC1_2 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_0__DispRI1_1__RegGxRCNoR01_2 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_0, 0, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_0__RegGxRCNoR01_1__RegGxRC1_2 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_0, 0, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done }, |
| // Convert__RegG8RC1_0__RegGxRCNoR01_1__TLSReg1_2 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addTLSRegOperands, 3, CVT_Done }, |
| // Convert__RegG8RC1_0__DispRIX1_1__RegGxRCNoR01_2 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__RegG8RC1_0__RegGxRCNoR01_1__RegGxRC1_2 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done }, |
| // Convert__RegG8RC1_0__RegG8RC1_1__U5Imm1_2 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegG8RC1_0__imm_95_0__DispRIX1_1__RegGxRCNoR01_2 |
| { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_0, 0, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__RegG8RC1_0__imm_95_0__RegGxRCNoR01_1__RegGxRC1_2 |
| { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_0, 0, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done }, |
| // Convert__RegF8RC1_0__DispRI1_1__RegGxRCNoR01_2 |
| { CVT_95_addRegF8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__RegF8RC1_0__RegGxRCNoR01_1__RegGxRC1_2 |
| { CVT_95_addRegF8RCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done }, |
| // Convert__RegF8RC1_0__imm_95_0__DispRI1_1__RegGxRCNoR01_2 |
| { CVT_95_addRegF8RCOperands, 1, CVT_imm_95_0, 0, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__RegF8RC1_0__imm_95_0__RegGxRCNoR01_1__RegGxRC1_2 |
| { CVT_95_addRegF8RCOperands, 1, CVT_imm_95_0, 0, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done }, |
| // Convert__RegF4RC1_0__DispRI1_1__RegGxRCNoR01_2 |
| { CVT_95_addRegF4RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__RegF4RC1_0__imm_95_0__DispRI1_1__RegGxRCNoR01_2 |
| { CVT_95_addRegF4RCOperands, 1, CVT_imm_95_0, 0, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__RegF4RC1_0__imm_95_0__RegGxRCNoR01_1__RegGxRC1_2 |
| { CVT_95_addRegF4RCOperands, 1, CVT_imm_95_0, 0, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done }, |
| // Convert__RegF4RC1_0__RegGxRCNoR01_1__RegGxRC1_2 |
| { CVT_95_addRegF4RCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done }, |
| // Convert__RegG8RC1_0__regZERO8__S16Imm1_1 |
| { CVT_95_addRegG8RCOperands, 1, CVT_regZERO8, 0, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__RegGPRC1_0__S16Imm1_1 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__RegGPRC1_0__regZERO__S16Imm1_1 |
| { CVT_95_addRegGPRCOperands, 1, CVT_regZERO, 0, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__RegG8RC1_0__regZERO8__S17Imm1_1 |
| { CVT_95_addRegG8RCOperands, 1, CVT_regZERO8, 0, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__RegGPRC1_0__S17Imm1_1 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__RegGPRC1_0__regZERO__S17Imm1_1 |
| { CVT_95_addRegGPRCOperands, 1, CVT_regZERO, 0, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__RegG8RC1_0__imm_95_0 |
| { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__RegG8pRC1_0__DispRIX161_1__RegGxRCNoR01_2 |
| { CVT_95_addRegG8pRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__RegG8pRC1_0__RegGxRCNoR01_1__RegGxRC1_2 |
| { CVT_95_addRegG8pRCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done }, |
| // Convert__RegVRRC1_0__RegGxRCNoR01_1__RegGxRC1_2 |
| { CVT_95_addRegVRRCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done }, |
| // Convert__imm_95_1 |
| { CVT_imm_95_1, 0, CVT_Done }, |
| // Convert__RegSPE4RC1_0__DispRI1_1__RegGxRCNoR01_2 |
| { CVT_95_addRegSPE4RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__RegSPE4RC1_0__RegGxRCNoR01_1__RegGxRC1_2 |
| { CVT_95_addRegSPE4RCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done }, |
| // Convert__RegVFRC1_0__DispRIX1_1__RegGxRCNoR01_2 |
| { CVT_95_addRegVFRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__RegVSFRC1_0__RegGxRCNoR01_1__RegGxRC1_2 |
| { CVT_95_addRegVSFRCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done }, |
| // Convert__RegVSSRC1_0__RegGxRCNoR01_1__RegGxRC1_2 |
| { CVT_95_addRegVSSRCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done }, |
| // Convert__RegVSRC1_0__DispRIX161_1__RegGxRCNoR01_2 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__RegVSRC1_0__RegGxRCNoR01_1__RegGxRC1_2 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done }, |
| // Convert__RegVSRC1_0__U5Imm1_1 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__RegVSRC1_0__Imm1_1__RegG8RC1_2 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_Done }, |
| // Convert__RegVSRpRC1_0__DispRIX161_1__RegGxRCNoR01_2 |
| { CVT_95_addRegVSRpRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__RegVSRpRC1_0__Imm1_1__RegG8RC1_2 |
| { CVT_95_addRegVSRpRCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_Done }, |
| // Convert__RegVSRpRC1_0__RegGxRCNoR01_1__RegGxRC1_2 |
| { CVT_95_addRegVSRpRCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done }, |
| // Convert__RegG8RC1_0__RegG8RC1_1__RegG8RC1_2__RegG8RC1_3 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_95_addRegG8RCOperands, 4, CVT_Done }, |
| // Convert__RegGPRC1_0__RegGPRC1_1__RegGPRC1_2__RegGPRC1_3 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addRegGPRCOperands, 4, CVT_Done }, |
| // Convert__RegCRRC1_0__RegCRRC1_1 |
| { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegCRRCOperands, 2, CVT_Done }, |
| // Convert__RegCRRC1_0 |
| { CVT_95_addRegCRRCOperands, 1, CVT_Done }, |
| // Convert__RegG8RC1_0__imm_95_29 |
| { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_29, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_29 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_29, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__imm_95_280 |
| { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_280, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_280 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_280, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__U10Imm1_1__imm_95_0 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_128 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_128, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_129 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_129, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_130 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_130, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_131 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_131, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_132 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_132, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_133 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_133, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_134 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_134, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_135 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_135, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__imm_95_28 |
| { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_28, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_28 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_28, 0, CVT_Done }, |
| // Convert__RegGPRC1_0 |
| { CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__RegG8RC1_0__imm_95_9 |
| { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_9, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_9 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_9, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__imm_95_19 |
| { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_19, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_19 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_19, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_537 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_537, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_539 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_539, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_541 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_541, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_543 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_543, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_536 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_536, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_538 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_538, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_540 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_540, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_542 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_542, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_1018 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_1018, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__Imm1_1 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_981 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_981, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__imm_95_22 |
| { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_22, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_22 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_22, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__imm_95_17 |
| { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_17, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_17 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_17, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__imm_95_18 |
| { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_18, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_18 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_18, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_980 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_980, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__RegF8RC1_1 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegF8RCOperands, 2, CVT_Done }, |
| // Convert__RegGPRC1_0__RegF8RC1_1 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegF8RCOperands, 2, CVT_Done }, |
| // Convert__RegF8RC1_0 |
| { CVT_95_addRegF8RCOperands, 1, CVT_Done }, |
| // Convert__RegF8RC1_1 |
| { CVT_95_addRegF8RCOperands, 2, CVT_Done }, |
| // Convert__RegF8RC1_0__U3Imm1_1 |
| { CVT_95_addRegF8RCOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__RegF8RC1_0__U2Imm1_1 |
| { CVT_95_addRegF8RCOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_529 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_529, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_531 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_531, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_533 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_533, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_535 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_535, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_528 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_528, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_530 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_530, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_532 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_532, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_534 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_534, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_1019 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_1019, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__imm_95_8 |
| { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_8, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_8 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_8, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__CRBitMask1_1 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addCRBitMaskOperands, 2, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_48 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_48, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_896 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_896, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__imm_95_287 |
| { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_287, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_287 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_287, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__imm_95_5 |
| { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_5, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_5 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_5, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__imm_95_4 |
| { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_4, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_4 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_4, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__imm_95_25 |
| { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_25, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_25 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_25, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__imm_95_512 |
| { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_512, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_512 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_512, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__imm_95_272 |
| { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_272, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__imm_95_273 |
| { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_273, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__imm_95_274 |
| { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_274, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__imm_95_275 |
| { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_275, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_272 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_272, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_273 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_273, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_274 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_274, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_275 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_275, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_260 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_260, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_261 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_261, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_262 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_262, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_263 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_263, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__U4Imm1_1 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__RegG8RC1_0__imm_95_26 |
| { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_26, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_26 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_26, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__imm_95_27 |
| { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_27, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_27 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_27, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_990 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_990, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_991 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_991, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_268 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_268, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_988 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_988, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_989 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_989, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_269 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_269, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_986 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_986, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__imm_95_13 |
| { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_13, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_13 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_13, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__imm_95_3 |
| { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_3, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_3 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_3, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__RegVRRC1_1 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_Done }, |
| // Convert__RegGPRC1_0__RegVRRC1_1 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_Done }, |
| // Convert__RegVRRC1_0 |
| { CVT_95_addRegVRRCOperands, 1, CVT_Done }, |
| // Convert__RegG8RC1_0__RegVSFRC1_1 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegVSFRCOperands, 2, CVT_Done }, |
| // Convert__RegG8RC1_0__RegVSRC1_1 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_Done }, |
| // Convert__RegGPRC1_0__RegVSFRC1_1 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegVSFRCOperands, 2, CVT_Done }, |
| // Convert__RegG8RC1_0__imm_95_1 |
| { CVT_95_addRegG8RCOperands, 1, CVT_imm_95_1, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_1 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_1, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__RegG8RC1_1__RegG8RC1_1 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 2, CVT_Done }, |
| // Convert__RegGPRC1_0__RegGPRC1_1__RegGPRC1_1 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__RegG8RC1_1__RegG8RC1_2__RegG8RC1_2 |
| { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_95_addRegG8RCOperands, 3, CVT_Done }, |
| // Convert__RegGPRC1_1__RegGPRC1_2__RegGPRC1_2 |
| { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addRegGPRCOperands, 3, CVT_Done }, |
| // Convert__imm_95_29__RegG8RC1_0 |
| { CVT_imm_95_29, 0, CVT_95_addRegG8RCOperands, 1, CVT_Done }, |
| // Convert__imm_95_29__RegGPRC1_0 |
| { CVT_imm_95_29, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_280__RegG8RC1_0 |
| { CVT_imm_95_280, 0, CVT_95_addRegG8RCOperands, 1, CVT_Done }, |
| // Convert__imm_95_280__RegGPRC1_0 |
| { CVT_imm_95_280, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_28__RegG8RC1_0 |
| { CVT_imm_95_28, 0, CVT_95_addRegG8RCOperands, 1, CVT_Done }, |
| // Convert__imm_95_28__RegGPRC1_0 |
| { CVT_imm_95_28, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_255__RegG8RC1_0 |
| { CVT_imm_95_255, 0, CVT_95_addRegG8RCOperands, 1, CVT_Done }, |
| // Convert__imm_95_255__RegGPRC1_0 |
| { CVT_imm_95_255, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__Imm1_0__RegGPRC1_1 |
| { CVT_95_addImmOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_9__RegG8RC1_0 |
| { CVT_imm_95_9, 0, CVT_95_addRegG8RCOperands, 1, CVT_Done }, |
| // Convert__imm_95_9__RegGPRC1_0 |
| { CVT_imm_95_9, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_19__RegG8RC1_0 |
| { CVT_imm_95_19, 0, CVT_95_addRegG8RCOperands, 1, CVT_Done }, |
| // Convert__imm_95_19__RegGPRC1_0 |
| { CVT_imm_95_19, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_537__RegGPRC1_1 |
| { CVT_imm_95_537, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_539__RegGPRC1_1 |
| { CVT_imm_95_539, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_541__RegGPRC1_1 |
| { CVT_imm_95_541, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_543__RegGPRC1_1 |
| { CVT_imm_95_543, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_536__RegGPRC1_1 |
| { CVT_imm_95_536, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_538__RegGPRC1_1 |
| { CVT_imm_95_538, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_540__RegGPRC1_1 |
| { CVT_imm_95_540, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_542__RegGPRC1_1 |
| { CVT_imm_95_542, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_1018__RegGPRC1_0 |
| { CVT_imm_95_1018, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__RegGPRC1_1__Imm1_0 |
| { CVT_95_addRegGPRCOperands, 2, CVT_95_addImmOperands, 1, CVT_Done }, |
| // Convert__imm_95_981__RegGPRC1_0 |
| { CVT_imm_95_981, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_22__RegG8RC1_0 |
| { CVT_imm_95_22, 0, CVT_95_addRegG8RCOperands, 1, CVT_Done }, |
| // Convert__imm_95_22__RegGPRC1_0 |
| { CVT_imm_95_22, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_17__RegG8RC1_0 |
| { CVT_imm_95_17, 0, CVT_95_addRegG8RCOperands, 1, CVT_Done }, |
| // Convert__imm_95_17__RegGPRC1_0 |
| { CVT_imm_95_17, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_18__RegG8RC1_0 |
| { CVT_imm_95_18, 0, CVT_95_addRegG8RCOperands, 1, CVT_Done }, |
| // Convert__imm_95_18__RegGPRC1_0 |
| { CVT_imm_95_18, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_980__RegGPRC1_0 |
| { CVT_imm_95_980, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__RegF8RC1_0__RegG8RC1_1 |
| { CVT_95_addRegF8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done }, |
| // Convert__RegF8RC1_0__RegGPRC1_1 |
| { CVT_95_addRegF8RCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__Imm1_0__RegF8RC1_1__imm_95_0__imm_95_0 |
| { CVT_95_addImmOperands, 1, CVT_95_addRegF8RCOperands, 2, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__Imm1_1__RegF8RC1_2__imm_95_0__imm_95_0 |
| { CVT_95_addImmOperands, 2, CVT_95_addRegF8RCOperands, 3, CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__Imm1_0__RegF8RC1_1__U1Imm1_2__Imm1_3 |
| { CVT_95_addImmOperands, 1, CVT_95_addRegF8RCOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done }, |
| // Convert__Imm1_1__RegF8RC1_2__U1Imm1_3__Imm1_4 |
| { CVT_95_addImmOperands, 2, CVT_95_addRegF8RCOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_Done }, |
| // Convert__U3Imm1_0__U4Imm1_1__imm_95_0 |
| { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__U3Imm1_1__U4Imm1_2__imm_95_0 |
| { CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__U3Imm1_0__U4Imm1_1__Imm1_2 |
| { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__U3Imm1_1__U4Imm1_2__U1Imm1_3 |
| { CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done }, |
| // Convert__imm_95_529__RegGPRC1_1 |
| { CVT_imm_95_529, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_531__RegGPRC1_1 |
| { CVT_imm_95_531, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_533__RegGPRC1_1 |
| { CVT_imm_95_533, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_535__RegGPRC1_1 |
| { CVT_imm_95_535, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_528__RegGPRC1_1 |
| { CVT_imm_95_528, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_530__RegGPRC1_1 |
| { CVT_imm_95_530, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_532__RegGPRC1_1 |
| { CVT_imm_95_532, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_534__RegGPRC1_1 |
| { CVT_imm_95_534, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_1019__RegGPRC1_0 |
| { CVT_imm_95_1019, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_8__RegG8RC1_0 |
| { CVT_imm_95_8, 0, CVT_95_addRegG8RCOperands, 1, CVT_Done }, |
| // Convert__imm_95_8__RegGPRC1_0 |
| { CVT_imm_95_8, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__RegGPRC1_0__imm_95_0 |
| { CVT_95_addRegGPRCOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__U1Imm1_1 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__CRBitMask1_0__RegGPRC1_1 |
| { CVT_95_addCRBitMaskOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_48__RegGPRC1_0 |
| { CVT_imm_95_48, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_896__RegGPRC1_0 |
| { CVT_imm_95_896, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_25__RegG8RC1_0 |
| { CVT_imm_95_25, 0, CVT_95_addRegG8RCOperands, 1, CVT_Done }, |
| // Convert__imm_95_25__RegGPRC1_0 |
| { CVT_imm_95_25, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_512__RegG8RC1_0 |
| { CVT_imm_95_512, 0, CVT_95_addRegG8RCOperands, 1, CVT_Done }, |
| // Convert__imm_95_512__RegGPRC1_0 |
| { CVT_imm_95_512, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__RegGPRC1_1 |
| { CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_272__RegG8RC1_1 |
| { CVT_imm_95_272, 0, CVT_95_addRegG8RCOperands, 2, CVT_Done }, |
| // Convert__imm_95_272__RegGPRC1_1 |
| { CVT_imm_95_272, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_273__RegG8RC1_1 |
| { CVT_imm_95_273, 0, CVT_95_addRegG8RCOperands, 2, CVT_Done }, |
| // Convert__imm_95_273__RegGPRC1_1 |
| { CVT_imm_95_273, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_274__RegG8RC1_1 |
| { CVT_imm_95_274, 0, CVT_95_addRegG8RCOperands, 2, CVT_Done }, |
| // Convert__imm_95_274__RegGPRC1_1 |
| { CVT_imm_95_274, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_275__RegG8RC1_1 |
| { CVT_imm_95_275, 0, CVT_95_addRegG8RCOperands, 2, CVT_Done }, |
| // Convert__imm_95_275__RegGPRC1_1 |
| { CVT_imm_95_275, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_260__RegGPRC1_1 |
| { CVT_imm_95_260, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_261__RegGPRC1_1 |
| { CVT_imm_95_261, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_262__RegGPRC1_1 |
| { CVT_imm_95_262, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_263__RegGPRC1_1 |
| { CVT_imm_95_263, 0, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_272__RegG8RC1_0 |
| { CVT_imm_95_272, 0, CVT_95_addRegG8RCOperands, 1, CVT_Done }, |
| // Convert__imm_95_272__RegGPRC1_0 |
| { CVT_imm_95_272, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_273__RegG8RC1_0 |
| { CVT_imm_95_273, 0, CVT_95_addRegG8RCOperands, 1, CVT_Done }, |
| // Convert__imm_95_273__RegGPRC1_0 |
| { CVT_imm_95_273, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_274__RegG8RC1_0 |
| { CVT_imm_95_274, 0, CVT_95_addRegG8RCOperands, 1, CVT_Done }, |
| // Convert__imm_95_274__RegGPRC1_0 |
| { CVT_imm_95_274, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_275__RegG8RC1_0 |
| { CVT_imm_95_275, 0, CVT_95_addRegG8RCOperands, 1, CVT_Done }, |
| // Convert__imm_95_275__RegGPRC1_0 |
| { CVT_imm_95_275, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_260__RegGPRC1_0 |
| { CVT_imm_95_260, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_261__RegGPRC1_0 |
| { CVT_imm_95_261, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_262__RegGPRC1_0 |
| { CVT_imm_95_262, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_263__RegGPRC1_0 |
| { CVT_imm_95_263, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__RegGPRC1_1__U4Imm1_0 |
| { CVT_95_addRegGPRCOperands, 2, CVT_95_addImmOperands, 1, CVT_Done }, |
| // Convert__imm_95_26__RegG8RC1_0 |
| { CVT_imm_95_26, 0, CVT_95_addRegG8RCOperands, 1, CVT_Done }, |
| // Convert__imm_95_26__RegGPRC1_0 |
| { CVT_imm_95_26, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_27__RegG8RC1_0 |
| { CVT_imm_95_27, 0, CVT_95_addRegG8RCOperands, 1, CVT_Done }, |
| // Convert__imm_95_27__RegGPRC1_0 |
| { CVT_imm_95_27, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_990__RegGPRC1_0 |
| { CVT_imm_95_990, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_991__RegGPRC1_0 |
| { CVT_imm_95_991, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_988__RegGPRC1_0 |
| { CVT_imm_95_988, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_284__RegG8RC1_0 |
| { CVT_imm_95_284, 0, CVT_95_addRegG8RCOperands, 1, CVT_Done }, |
| // Convert__imm_95_284__RegGPRC1_0 |
| { CVT_imm_95_284, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_989__RegGPRC1_0 |
| { CVT_imm_95_989, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_285__RegG8RC1_0 |
| { CVT_imm_95_285, 0, CVT_95_addRegG8RCOperands, 1, CVT_Done }, |
| // Convert__imm_95_285__RegGPRC1_0 |
| { CVT_imm_95_285, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_986__RegGPRC1_0 |
| { CVT_imm_95_986, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_13__RegG8RC1_0 |
| { CVT_imm_95_13, 0, CVT_95_addRegG8RCOperands, 1, CVT_Done }, |
| // Convert__imm_95_13__RegGPRC1_0 |
| { CVT_imm_95_13, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__imm_95_3__RegG8RC1_0 |
| { CVT_imm_95_3, 0, CVT_95_addRegG8RCOperands, 1, CVT_Done }, |
| // Convert__imm_95_3__RegGPRC1_0 |
| { CVT_imm_95_3, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__RegVRRC1_0__RegG8RC1_1 |
| { CVT_95_addRegVRRCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done }, |
| // Convert__RegVRRC1_0__RegGPRC1_1 |
| { CVT_95_addRegVRRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__RegVRRC1_0__U16Imm1_1 |
| { CVT_95_addRegVRRCOperands, 1, CVT_95_addU16ImmOperands, 2, CVT_Done }, |
| // Convert__RegVSFRC1_0__RegG8RC1_1 |
| { CVT_95_addRegVSFRCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done }, |
| // Convert__RegVSRC1_0__RegG8RCNoX01_1__RegG8RC1_2 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegG8RCNoX0Operands, 2, CVT_95_addRegG8RCOperands, 3, CVT_Done }, |
| // Convert__RegVSFRC1_0__RegGPRC1_1 |
| { CVT_95_addRegVSFRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__RegVSRC1_0__RegGPRC1_1 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_1__RegG8RC1_0 |
| { CVT_imm_95_1, 0, CVT_95_addRegG8RCOperands, 1, CVT_Done }, |
| // Convert__imm_95_1__RegGPRC1_0 |
| { CVT_imm_95_1, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__regR0__regR0__imm_95_0 |
| { CVT_regR0, 0, CVT_regR0, 0, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__regX0__regX0__imm_95_0 |
| { CVT_regX0, 0, CVT_regX0, 0, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__RegGPRC1_1__U16Imm1_2 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addU16ImmOperands, 3, CVT_Done }, |
| // Convert__RegGPRC1_0__ImmZero1_1__S34Imm1_2 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegGPRC1_0__RegGPRC1_1__S34Imm1_2 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegGPRC1_1__RegGPRC1_2__imm_95_1 |
| { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_imm_95_1, 0, CVT_Done }, |
| // Convert__RegGPRC1_1__RegGPRC1_2__U1Imm1_3 |
| { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addImmOperands, 4, CVT_Done }, |
| // Convert__RegGPRC1_0__DispRI341_1__ImmZero1_2 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegGPRC1_0__DispRI341_1__RegGxRCNoR01_2 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__RegG8RC1_0__DispRI341_1__ImmZero1_2 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegG8RC1_0__DispRI341_1__RegGxRCNoR01_2 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__RegF8RC1_0__DispRI341_1__ImmZero1_2 |
| { CVT_95_addRegF8RCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegF8RC1_0__DispRI341_1__RegGxRCNoR01_2 |
| { CVT_95_addRegF8RCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__RegF4RC1_0__DispRI341_1__ImmZero1_2 |
| { CVT_95_addRegF4RCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegF4RC1_0__DispRI341_1__RegGxRCNoR01_2 |
| { CVT_95_addRegF4RCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__RegGPRC1_0__S34Imm1_1 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__RegVFRC1_0__DispRI341_1__ImmZero1_2 |
| { CVT_95_addRegVFRCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegVFRC1_0__DispRI341_1__RegGxRCNoR01_2 |
| { CVT_95_addRegVFRCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__RegVSRC1_0__DispRI341_1__ImmZero1_2 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegVSRC1_0__DispRI341_1__RegGxRCNoR01_2 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__RegVSRpRC1_0__DispRI341_1__ImmZero1_2 |
| { CVT_95_addRegVSRpRCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegVSRpRC1_0__DispRI341_1__RegGxRCNoR01_2 |
| { CVT_95_addRegVSRpRCOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__RegACCRC1_0__RegVSRC1_1__RegVSRC1_2__U4Imm1_3__U4Imm1_4__U2Imm1_5 |
| { CVT_95_addRegACCRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_Done }, |
| // Convert__RegACCRC1_0__Tie0_1_1__RegVSRC1_1__RegVSRC1_2__U4Imm1_3__U4Imm1_4__U2Imm1_5 |
| { CVT_95_addRegACCRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_Done }, |
| // Convert__RegACCRC1_0__RegVSRC1_1__RegVSRC1_2__U4Imm1_3__U4Imm1_4 |
| { CVT_95_addRegACCRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_Done }, |
| // Convert__RegACCRC1_0__Tie0_1_1__RegVSRC1_1__RegVSRC1_2__U4Imm1_3__U4Imm1_4 |
| { CVT_95_addRegACCRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_Done }, |
| // Convert__RegACCRC1_0__RegVSRpEvenRC1_1__RegVSRC1_2__U4Imm1_3__U2Imm1_4 |
| { CVT_95_addRegACCRCOperands, 1, CVT_95_addRegVSRpEvenRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_Done }, |
| // Convert__RegACCRC1_0__Tie0_1_1__RegVSRpEvenRC1_1__RegVSRC1_2__U4Imm1_3__U2Imm1_4 |
| { CVT_95_addRegACCRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegVSRpEvenRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_Done }, |
| // Convert__RegACCRC1_0__RegVSRC1_1__RegVSRC1_2__U4Imm1_3__U4Imm1_4__U8Imm1_5 |
| { CVT_95_addRegACCRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_Done }, |
| // Convert__RegACCRC1_0__Tie0_1_1__RegVSRC1_1__RegVSRC1_2__U4Imm1_3__U4Imm1_4__U8Imm1_5 |
| { CVT_95_addRegACCRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_Done }, |
| // Convert__RegACCRC1_0__RegVSRC1_1__RegVSRC1_2__U4Imm1_3__U4Imm1_4__U4Imm1_5 |
| { CVT_95_addRegACCRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_Done }, |
| // Convert__RegACCRC1_0__Tie0_1_1__RegVSRC1_1__RegVSRC1_2__U4Imm1_3__U4Imm1_4__U4Imm1_5 |
| { CVT_95_addRegACCRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_Done }, |
| // Convert__imm_95_2 |
| { CVT_imm_95_2, 0, CVT_Done }, |
| // Convert__U1Imm1_0 |
| { CVT_95_addImmOperands, 1, CVT_Done }, |
| // Convert__RegG8RC1_0__RegG8RC1_1__RegGPRC1_2__U6Imm1_3 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addImmOperands, 4, CVT_Done }, |
| // Convert__RegG8RC1_1__RegG8RC1_2__RegGPRC1_3__U6Imm1_4 |
| { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_95_addRegGPRCOperands, 4, CVT_95_addImmOperands, 5, CVT_Done }, |
| // Convert__RegG8RC1_0__Tie0_1_1__RegG8RC1_1__U6Imm1_2__U6Imm1_3 |
| { CVT_95_addRegG8RCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegG8RCOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done }, |
| // Convert__RegG8RC1_1__Tie0_1_1__RegG8RC1_2__U6Imm1_3__U6Imm1_4 |
| { CVT_95_addRegG8RCOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addRegG8RCOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_Done }, |
| // Convert__RegG8RC1_0__RegG8RC1_1__U5Imm1_2__Imm1_3 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done }, |
| // Convert__RegG8RC1_1__RegG8RC1_2__U5Imm1_3__Imm1_4 |
| { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_Done }, |
| // Convert__RegGPRC1_0__Tie0_1_1__RegGPRC1_1__U5Imm1_2__U5Imm1_3__U5Imm1_4 |
| { CVT_95_addRegGPRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegGPRCOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_Done }, |
| // Convert__RegGPRC1_1__Tie0_1_1__RegGPRC1_2__U5Imm1_3__U5Imm1_4__U5Imm1_5 |
| { CVT_95_addRegGPRCOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addRegGPRCOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_Done }, |
| // Convert__RegGPRC1_0__RegGPRC1_1__U5Imm1_2__U5Imm1_3__U5Imm1_4 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_Done }, |
| // Convert__RegGPRC1_1__RegGPRC1_2__U5Imm1_3__U5Imm1_4__U5Imm1_5 |
| { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_Done }, |
| // Convert__RegGPRC1_0__RegGPRC1_1__RegGPRC1_2__U5Imm1_3__U5Imm1_4 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 5, CVT_Done }, |
| // Convert__RegGPRC1_1__RegGPRC1_2__RegGPRC1_3__U5Imm1_4__U5Imm1_5 |
| { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addRegGPRCOperands, 4, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 6, CVT_Done }, |
| // Convert__RegG8RC1_0__RegG8RC1_1__RegGPRC1_2__imm_95_0 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__RegG8RC1_1__RegG8RC1_2__RegGPRC1_3__imm_95_0 |
| { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_95_addRegGPRCOperands, 4, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__RegG8RC1_1__U6Imm1_2__imm_95_0 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__RegGPRC1_1__U6Imm1_2__imm_95_0 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__RegG8RC1_1__RegG8RC1_2__U6Imm1_3__imm_95_0 |
| { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_95_addImmOperands, 4, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__RegG8RC1_1__RegG8RC1_2__imm_95_0__imm_95_31 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_imm_95_0, 0, CVT_imm_95_31, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__RegGPRC1_1__RegGPRC1_2__imm_95_0__imm_95_31 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_imm_95_0, 0, CVT_imm_95_31, 0, CVT_Done }, |
| // Convert__RegG8RC1_1__RegG8RC1_2__RegG8RC1_3__imm_95_0__imm_95_31 |
| { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_95_addRegG8RCOperands, 4, CVT_imm_95_0, 0, CVT_imm_95_31, 0, CVT_Done }, |
| // Convert__RegGPRC1_1__RegGPRC1_2__RegGPRC1_3__imm_95_0__imm_95_31 |
| { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addRegGPRCOperands, 4, CVT_imm_95_0, 0, CVT_imm_95_31, 0, CVT_Done }, |
| // Convert__RegG8RC1_0__RegG8RC1_1__U5Imm1_2__imm_95_0__imm_95_31 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_imm_95_31, 0, CVT_Done }, |
| // Convert__RegGPRC1_0__RegGPRC1_1__U5Imm1_2__imm_95_0__imm_95_31 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_imm_95_31, 0, CVT_Done }, |
| // Convert__RegG8RC1_1__RegG8RC1_2__U5Imm1_3__imm_95_0__imm_95_31 |
| { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_95_addImmOperands, 4, CVT_imm_95_0, 0, CVT_imm_95_31, 0, CVT_Done }, |
| // Convert__RegGPRC1_1__RegGPRC1_2__U5Imm1_3__imm_95_0__imm_95_31 |
| { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addImmOperands, 4, CVT_imm_95_0, 0, CVT_imm_95_31, 0, CVT_Done }, |
| // Convert__Imm1_0 |
| { CVT_95_addImmOperands, 1, CVT_Done }, |
| // Convert__RegGPRC1_0__RegCRRC1_1 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegCRRCOperands, 2, CVT_Done }, |
| // Convert__RegGPRC1_0__RegCRBITRC1_1 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegCRBITRCOperands, 2, CVT_Done }, |
| // Convert__RegG8RC1_0__RegG8RC1_1__RegGPRC1_2 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_Done }, |
| // Convert__RegG8RC1_1__RegG8RC1_2__RegGPRC1_3 |
| { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_95_addRegGPRCOperands, 4, CVT_Done }, |
| // Convert__RegGPRC1_1__RegGxRCNoR01_2__RegGxRC1_3 |
| { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_95_addRegGxRCOperands, 4, CVT_Done }, |
| // Convert__imm_95_0__RegGPRC1_0__DispRI1_1__RegGxRCNoR01_2 |
| { CVT_imm_95_0, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__imm_95_0__RegGPRC1_0__RegGxRCNoR01_1__RegGxRC1_2 |
| { CVT_imm_95_0, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done }, |
| // Convert__RegG8RC1_1__RegGxRCNoR01_2__RegGxRC1_3 |
| { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_95_addRegGxRCOperands, 4, CVT_Done }, |
| // Convert__imm_95_0__RegG8RC1_0__DispRIX1_1__RegGxRCNoR01_2 |
| { CVT_imm_95_0, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__imm_95_0__RegG8RC1_0__RegGxRCNoR01_1__RegGxRC1_2 |
| { CVT_imm_95_0, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done }, |
| // Convert__imm_95_0__RegF8RC1_0__DispRI1_1__RegGxRCNoR01_2 |
| { CVT_imm_95_0, 0, CVT_95_addRegF8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__imm_95_0__RegF8RC1_0__RegGxRCNoR01_1__RegGxRC1_2 |
| { CVT_imm_95_0, 0, CVT_95_addRegF8RCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done }, |
| // Convert__imm_95_0__RegF4RC1_0__DispRI1_1__RegGxRCNoR01_2 |
| { CVT_imm_95_0, 0, CVT_95_addRegF4RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__imm_95_0__RegF4RC1_0__RegGxRCNoR01_1__RegGxRC1_2 |
| { CVT_imm_95_0, 0, CVT_95_addRegF4RCOperands, 1, CVT_95_addRegGxRCNoR0Operands, 2, CVT_95_addRegGxRCOperands, 3, CVT_Done }, |
| // Convert__RegG8pRC1_0__DispRIX1_1__RegGxRCNoR01_2 |
| { CVT_95_addRegG8pRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_Done }, |
| // Convert__RegG8pRC1_1__RegGxRCNoR01_2__RegGxRC1_3 |
| { CVT_95_addRegG8pRCOperands, 2, CVT_95_addRegGxRCNoR0Operands, 3, CVT_95_addRegGxRCOperands, 4, CVT_Done }, |
| // Convert__RegG8RC1_0__RegG8RC1_2__RegG8RC1_1 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 3, CVT_95_addRegG8RCOperands, 2, CVT_Done }, |
| // Convert__RegGPRC1_0__RegGPRC1_2__RegGPRC1_1 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 3, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__RegG8RC1_1__RegG8RC1_3__RegG8RC1_2 |
| { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 4, CVT_95_addRegG8RCOperands, 3, CVT_Done }, |
| // Convert__RegGPRC1_1__RegGPRC1_3__RegGPRC1_2 |
| { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 4, CVT_95_addRegGPRCOperands, 3, CVT_Done }, |
| // Convert__RegG8RC1_0__RegG8RC1_2__RegG8RC1_3__U1Imm1_1 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 3, CVT_95_addRegG8RCOperands, 4, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__RegG8RC1_1__RegG8RC1_3__RegG8RC1_4__U1Imm1_2 |
| { CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 4, CVT_95_addRegG8RCOperands, 5, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegG8RC1_0__S16Imm1_1 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__U2Imm1_0 |
| { CVT_95_addImmOperands, 1, CVT_Done }, |
| // Convert__U5Imm1_1__RegGPRC1_2__RegGPRC1_3 |
| { CVT_95_addImmOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addRegGPRCOperands, 4, CVT_Done }, |
| // Convert__U5Imm1_1__RegGPRC1_2__U5Imm1_3 |
| { CVT_95_addImmOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_95_addImmOperands, 4, CVT_Done }, |
| // Convert__U1Imm1_1 |
| { CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__U5Imm1_0__RegG8RC1_1__RegG8RC1_2 |
| { CVT_95_addImmOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_Done }, |
| // Convert__imm_95_4__RegG8RC1_0__RegG8RC1_1 |
| { CVT_imm_95_4, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done }, |
| // Convert__imm_95_4__RegG8RC1_0__S16Imm1_1 |
| { CVT_imm_95_4, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__imm_95_12__RegG8RC1_0__RegG8RC1_1 |
| { CVT_imm_95_12, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done }, |
| // Convert__imm_95_12__RegG8RC1_0__S16Imm1_1 |
| { CVT_imm_95_12, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__imm_95_8__RegG8RC1_0__RegG8RC1_1 |
| { CVT_imm_95_8, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done }, |
| // Convert__imm_95_8__RegG8RC1_0__S16Imm1_1 |
| { CVT_imm_95_8, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__U5Imm1_0__RegG8RC1_1__S16Imm1_2 |
| { CVT_95_addImmOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addS16ImmOperands, 3, CVT_Done }, |
| // Convert__imm_95_20__RegG8RC1_0__RegG8RC1_1 |
| { CVT_imm_95_20, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done }, |
| // Convert__imm_95_20__RegG8RC1_0__S16Imm1_1 |
| { CVT_imm_95_20, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__imm_95_5__RegG8RC1_0__RegG8RC1_1 |
| { CVT_imm_95_5, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done }, |
| // Convert__imm_95_5__RegG8RC1_0__S16Imm1_1 |
| { CVT_imm_95_5, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__imm_95_1__RegG8RC1_0__RegG8RC1_1 |
| { CVT_imm_95_1, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done }, |
| // Convert__imm_95_1__RegG8RC1_0__S16Imm1_1 |
| { CVT_imm_95_1, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__imm_95_6__RegG8RC1_0__RegG8RC1_1 |
| { CVT_imm_95_6, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done }, |
| // Convert__imm_95_6__RegG8RC1_0__S16Imm1_1 |
| { CVT_imm_95_6, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__imm_95_2__RegG8RC1_0__RegG8RC1_1 |
| { CVT_imm_95_2, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done }, |
| // Convert__imm_95_2__RegG8RC1_0__S16Imm1_1 |
| { CVT_imm_95_2, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__imm_95_16__RegG8RC1_0__RegG8RC1_1 |
| { CVT_imm_95_16, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done }, |
| // Convert__imm_95_16__RegG8RC1_0__S16Imm1_1 |
| { CVT_imm_95_16, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__imm_95_24__RegG8RC1_0__RegG8RC1_1 |
| { CVT_imm_95_24, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done }, |
| // Convert__imm_95_24__RegG8RC1_0__S16Imm1_1 |
| { CVT_imm_95_24, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__imm_95_31__RegG8RC1_0__RegG8RC1_1 |
| { CVT_imm_95_31, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_Done }, |
| // Convert__imm_95_31__RegG8RC1_0__S16Imm1_1 |
| { CVT_imm_95_31, 0, CVT_95_addRegG8RCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__regR0__RegGPRC1_0 |
| { CVT_regR0, 0, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__RegGPRC1_1__RegGPRC1_0 |
| { CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 1, CVT_Done }, |
| // Convert__RegGPRC1_0__RegGPRC1_1__Imm1_2 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegGPRC1_0__RegGPRC1_1__imm_95_1 |
| { CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_imm_95_1, 0, CVT_Done }, |
| // Convert__imm_95_31__regR0__regR0 |
| { CVT_imm_95_31, 0, CVT_regR0, 0, CVT_regR0, 0, CVT_Done }, |
| // Convert__U5Imm1_0__RegGPRC1_1__RegGPRC1_2 |
| { CVT_95_addImmOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_Done }, |
| // Convert__imm_95_4__RegGPRC1_0__RegGPRC1_1 |
| { CVT_imm_95_4, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_4__RegGPRC1_0__S16Imm1_1 |
| { CVT_imm_95_4, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__imm_95_12__RegGPRC1_0__RegGPRC1_1 |
| { CVT_imm_95_12, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_12__RegGPRC1_0__S16Imm1_1 |
| { CVT_imm_95_12, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__imm_95_8__RegGPRC1_0__RegGPRC1_1 |
| { CVT_imm_95_8, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_8__RegGPRC1_0__S16Imm1_1 |
| { CVT_imm_95_8, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__U5Imm1_0__RegGPRC1_1__S16Imm1_2 |
| { CVT_95_addImmOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_95_addS16ImmOperands, 3, CVT_Done }, |
| // Convert__imm_95_20__RegGPRC1_0__RegGPRC1_1 |
| { CVT_imm_95_20, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_20__RegGPRC1_0__S16Imm1_1 |
| { CVT_imm_95_20, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__imm_95_5__RegGPRC1_0__RegGPRC1_1 |
| { CVT_imm_95_5, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_5__RegGPRC1_0__S16Imm1_1 |
| { CVT_imm_95_5, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__imm_95_1__RegGPRC1_0__RegGPRC1_1 |
| { CVT_imm_95_1, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_1__RegGPRC1_0__S16Imm1_1 |
| { CVT_imm_95_1, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__imm_95_6__RegGPRC1_0__RegGPRC1_1 |
| { CVT_imm_95_6, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_6__RegGPRC1_0__S16Imm1_1 |
| { CVT_imm_95_6, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__imm_95_2__RegGPRC1_0__RegGPRC1_1 |
| { CVT_imm_95_2, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_2__RegGPRC1_0__S16Imm1_1 |
| { CVT_imm_95_2, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__imm_95_16__RegGPRC1_0__RegGPRC1_1 |
| { CVT_imm_95_16, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_16__RegGPRC1_0__S16Imm1_1 |
| { CVT_imm_95_16, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__imm_95_24__RegGPRC1_0__RegGPRC1_1 |
| { CVT_imm_95_24, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_24__RegGPRC1_0__S16Imm1_1 |
| { CVT_imm_95_24, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__imm_95_31__RegGPRC1_0__RegGPRC1_1 |
| { CVT_imm_95_31, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__imm_95_31__RegGPRC1_0__S16Imm1_1 |
| { CVT_imm_95_31, 0, CVT_95_addRegGPRCOperands, 1, CVT_95_addS16ImmOperands, 2, CVT_Done }, |
| // Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2 |
| { CVT_95_addRegVRRCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_95_addRegVRRCOperands, 3, CVT_Done }, |
| // Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2__RegVRRC1_3 |
| { CVT_95_addRegVRRCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_95_addRegVRRCOperands, 3, CVT_95_addRegVRRCOperands, 4, CVT_Done }, |
| // Convert__RegVRRC1_0__U5Imm1_2__RegVRRC1_1 |
| { CVT_95_addRegVRRCOperands, 1, CVT_95_addImmOperands, 3, CVT_95_addRegVRRCOperands, 2, CVT_Done }, |
| // Convert__RegVRRC1_0__RegVRRC1_1__RegGPRC1_2 |
| { CVT_95_addRegVRRCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_Done }, |
| // Convert__RegVRRC1_0__RegVRRC1_1 |
| { CVT_95_addRegVRRCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_Done }, |
| // Convert__RegCRRC1_0__RegVRRC1_1__RegVRRC1_2 |
| { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_95_addRegVRRCOperands, 3, CVT_Done }, |
| // Convert__RegG8RC1_0__RegVRRC1_1__U1Imm1_2 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2__RegGPRC1_3 |
| { CVT_95_addRegVRRCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_95_addRegVRRCOperands, 3, CVT_95_addRegGPRCOperands, 4, CVT_Done }, |
| // Convert__RegVRRC1_0__U4Imm1_2__RegVRRC1_1 |
| { CVT_95_addRegVRRCOperands, 1, CVT_95_addImmOperands, 3, CVT_95_addRegVRRCOperands, 2, CVT_Done }, |
| // Convert__RegG8RC1_0__RegG8RC1_1__RegVRRC1_2 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addRegVRRCOperands, 3, CVT_Done }, |
| // Convert__RegG8RC1_0__RegVRRC1_1__U3Imm1_2 |
| { CVT_95_addRegG8RCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegVRRC1_0__Tie0_1_1__RegGPRC1_1__RegGPRC1_2 |
| { CVT_95_addRegVRRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegGPRCOperands, 2, CVT_95_addRegGPRCOperands, 3, CVT_Done }, |
| // Convert__RegVRRC1_0__Tie0_1_1__RegGPRC1_1__RegVRRC1_2 |
| { CVT_95_addRegVRRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegGPRCOperands, 2, CVT_95_addRegVRRCOperands, 3, CVT_Done }, |
| // Convert__RegVRRC1_0__Tie0_1_1__U4Imm1_2__RegG8RC1_1 |
| { CVT_95_addRegVRRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_95_addRegG8RCOperands, 2, CVT_Done }, |
| // Convert__RegVRRC1_0__Tie0_1_1__RegG8RC1_1__RegG8RC1_2 |
| { CVT_95_addRegVRRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_Done }, |
| // Convert__RegVRRC1_0__Tie0_1_1__U4Imm1_2__RegVRRC1_1 |
| { CVT_95_addRegVRRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_95_addRegVRRCOperands, 2, CVT_Done }, |
| // Convert__RegVRRC1_0__Tie0_1_1__U4Imm1_2__RegGPRC1_1 |
| { CVT_95_addRegVRRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 3, CVT_95_addRegGPRCOperands, 2, CVT_Done }, |
| // Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_1 |
| { CVT_95_addRegVRRCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_95_addRegVRRCOperands, 2, CVT_Done }, |
| // Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2__Tie0_1_1 |
| { CVT_95_addRegVRRCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_95_addRegVRRCOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
| // Convert__RegVRRC1_0__RegVRRC1_1__U1Imm1_2__U4Imm1_3 |
| { CVT_95_addRegVRRCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 4, CVT_Done }, |
| // Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2__U3Imm1_3 |
| { CVT_95_addRegVRRCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_95_addRegVRRCOperands, 3, CVT_95_addImmOperands, 4, CVT_Done }, |
| // Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2__U4Imm1_3 |
| { CVT_95_addRegVRRCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_95_addRegVRRCOperands, 3, CVT_95_addImmOperands, 4, CVT_Done }, |
| // Convert__RegVRRC1_0__S5Imm1_1 |
| { CVT_95_addRegVRRCOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__RegVSFRC1_0__RegVSFRC1_1 |
| { CVT_95_addRegVSFRCOperands, 1, CVT_95_addRegVSFRCOperands, 2, CVT_Done }, |
| // Convert__RegVSFRC1_0__RegVSFRC1_1__RegVSFRC1_2 |
| { CVT_95_addRegVSFRCOperands, 1, CVT_95_addRegVSFRCOperands, 2, CVT_95_addRegVSFRCOperands, 3, CVT_Done }, |
| // Convert__RegVSSRC1_0__RegVSSRC1_1__RegVSSRC1_2 |
| { CVT_95_addRegVSSRCOperands, 1, CVT_95_addRegVSSRCOperands, 2, CVT_95_addRegVSSRCOperands, 3, CVT_Done }, |
| // Convert__RegVSRC1_0__RegVSFRC1_1__RegVSFRC1_2 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSFRCOperands, 2, CVT_95_addRegVSFRCOperands, 3, CVT_Done }, |
| // Convert__RegCRRC1_0__RegVSFRC1_1__RegVSFRC1_2 |
| { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegVSFRCOperands, 2, CVT_95_addRegVSFRCOperands, 3, CVT_Done }, |
| // Convert__RegVRRC1_0__RegVFRC1_1 |
| { CVT_95_addRegVRRCOperands, 1, CVT_95_addRegVFRCOperands, 2, CVT_Done }, |
| // Convert__RegVSRC1_0__RegVSSRC1_1 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSSRCOperands, 2, CVT_Done }, |
| // Convert__RegVFRC1_0__RegVRRC1_1 |
| { CVT_95_addRegVFRCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_Done }, |
| // Convert__RegVSSRC1_0__RegVSRC1_1 |
| { CVT_95_addRegVSSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_Done }, |
| // Convert__RegVSSRC1_0__RegVSFRC1_1 |
| { CVT_95_addRegVSSRCOperands, 1, CVT_95_addRegVSFRCOperands, 2, CVT_Done }, |
| // Convert__RegVSRC1_0__RegG8RC1_1__RegG8RC1_2 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegG8RCOperands, 2, CVT_95_addRegG8RCOperands, 3, CVT_Done }, |
| // Convert__RegVRRC1_0__RegVRRC1_1__RegVSFRC1_2 |
| { CVT_95_addRegVRRCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_95_addRegVSFRCOperands, 3, CVT_Done }, |
| // Convert__RegVSFRC1_0__Tie0_1_1__RegVSFRC1_1__RegVSFRC1_2 |
| { CVT_95_addRegVSFRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegVSFRCOperands, 2, CVT_95_addRegVSFRCOperands, 3, CVT_Done }, |
| // Convert__RegVSSRC1_0__Tie0_1_1__RegVSSRC1_1__RegVSSRC1_2 |
| { CVT_95_addRegVSSRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegVSSRCOperands, 2, CVT_95_addRegVSSRCOperands, 3, CVT_Done }, |
| // Convert__RegVRRC1_0__Tie0_1_1__RegVRRC1_1__RegVRRC1_2 |
| { CVT_95_addRegVRRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegVRRCOperands, 2, CVT_95_addRegVRRCOperands, 3, CVT_Done }, |
| // Convert__RegVSSRC1_0__RegVSSRC1_1 |
| { CVT_95_addRegVSSRCOperands, 1, CVT_95_addRegVSSRCOperands, 2, CVT_Done }, |
| // Convert__RegVRRC1_1__U1Imm1_0__RegVRRC1_2__U2Imm1_3 |
| { CVT_95_addRegVRRCOperands, 2, CVT_95_addImmOperands, 1, CVT_95_addRegVRRCOperands, 3, CVT_95_addImmOperands, 4, CVT_Done }, |
| // Convert__RegCRRC1_0__RegVSFRC1_1 |
| { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegVSFRCOperands, 2, CVT_Done }, |
| // Convert__RegCRRC1_0__U7Imm1_2__RegVSFRC1_1 |
| { CVT_95_addRegCRRCOperands, 1, CVT_95_addImmOperands, 3, CVT_95_addRegVSFRCOperands, 2, CVT_Done }, |
| // Convert__RegCRRC1_0__U7Imm1_2__RegVRRC1_1 |
| { CVT_95_addRegCRRCOperands, 1, CVT_95_addImmOperands, 3, CVT_95_addRegVRRCOperands, 2, CVT_Done }, |
| // Convert__RegVSRC1_0__RegVSRC1_1 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_Done }, |
| // Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_Done }, |
| // Convert__RegACCRC1_0__RegVSRC1_1__RegVSRC1_2 |
| { CVT_95_addRegACCRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_Done }, |
| // Convert__RegACCRC1_0__Tie0_1_1__RegVSRC1_1__RegVSRC1_2 |
| { CVT_95_addRegACCRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_Done }, |
| // Convert__RegVSRC1_1__RegVSRC1_2__RegVSRC1_3 |
| { CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_95_addRegVSRCOperands, 4, CVT_Done }, |
| // Convert__RegACCRC1_0__RegVSRpEvenRC1_1__RegVSRC1_2 |
| { CVT_95_addRegACCRCOperands, 1, CVT_95_addRegVSRpEvenRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_Done }, |
| // Convert__RegACCRC1_0__Tie0_1_1__RegVSRpEvenRC1_1__RegVSRC1_2 |
| { CVT_95_addRegACCRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegVSRpEvenRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_Done }, |
| // Convert__RegVSRC1_0__Tie0_1_1__RegVSRC1_1__RegVSRC1_2 |
| { CVT_95_addRegVSRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_Done }, |
| // Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_1 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 2, CVT_Done }, |
| // Convert__RegCRRC1_0__RegVSRC1_1__RegVSRC1_2 |
| { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_Done }, |
| // Convert__RegCRRC1_0__RegVSRC1_1 |
| { CVT_95_addRegCRRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_Done }, |
| // Convert__RegVSRC1_0__U7Imm1_2__RegVSRC1_1 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addImmOperands, 3, CVT_95_addRegVSRCOperands, 2, CVT_Done }, |
| // Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2__RegVSRC1_3 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_95_addRegVSRCOperands, 4, CVT_Done }, |
| // Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2__RegVSRC1_3__U8Imm1_4 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_95_addRegVSRCOperands, 4, CVT_95_addImmOperands, 5, CVT_Done }, |
| // Convert__RegVSFRC1_0__RegVSRC1_1__U4Imm1_2 |
| { CVT_95_addRegVSFRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegVSRC1_0__RegVRRC1_1__S5Imm1_2 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVRRCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegVSRC1_0__Tie0_1_1__RegVSRC1_1__U4Imm1_2 |
| { CVT_95_addRegVSRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addRegVSRCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegACCRC1_0__Tie0_1_1 |
| { CVT_95_addRegACCRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_Done }, |
| // Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2__imm_95_0 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2__imm_95_3 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_imm_95_3, 0, CVT_Done }, |
| // Convert__RegVSRC1_0__RegVSRC1_1__Tie0_1_1__RegVSRC1_2 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addRegVSRCOperands, 3, CVT_Done }, |
| // Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2__U2Imm1_3 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_95_addImmOperands, 4, CVT_Done }, |
| // Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_2__RegVSRC1_3__U3Imm1_4 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 3, CVT_95_addRegVSRCOperands, 4, CVT_95_addImmOperands, 5, CVT_Done }, |
| // Convert__RegACCRC1_0 |
| { CVT_95_addRegACCRCOperands, 1, CVT_Done }, |
| // Convert__RegVSRC1_0__RegVSFRC1_1__imm_95_0 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSFRCOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__RegVSRC1_0__RegVSFRC1_1__imm_95_3 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSFRCOperands, 2, CVT_imm_95_3, 0, CVT_Done }, |
| // Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_1__imm_95_0 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_1__imm_95_3 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 2, CVT_imm_95_3, 0, CVT_Done }, |
| // Convert__RegVSRC1_0__Tie0_1_1__U1Imm1_1__Imm1_2 |
| { CVT_95_addRegVSRCOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegVSRC1_0__U8Imm1_1 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__RegVSRC1_0__Imm1_1 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__RegVSRC1_0__RegVSRC1_1__U2Imm1_2 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__RegVSRC1_0__RegVSFRC1_1__imm_95_2 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSFRCOperands, 2, CVT_imm_95_2, 0, CVT_Done }, |
| // Convert__RegVSRC1_0__RegVSRC1_1__RegVSRC1_1__imm_95_2 |
| { CVT_95_addRegVSRCOperands, 1, CVT_95_addRegVSRCOperands, 2, CVT_95_addRegVSRCOperands, 2, CVT_imm_95_2, 0, CVT_Done }, |
| }; |
| |
| void PPCAsmParser:: |
| convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, |
| const OperandVector &Operands) { |
| assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); |
| const uint8_t *Converter = ConversionTable[Kind]; |
| unsigned OpIdx; |
| Inst.setOpcode(Opcode); |
| for (const uint8_t *p = Converter; *p; p += 2) { |
| OpIdx = *(p + 1); |
|
