diff --git a/src/OpenGL/compiler/OutputASM.cpp b/src/OpenGL/compiler/OutputASM.cpp
index dffa148..9d0d88b 100644
--- a/src/OpenGL/compiler/OutputASM.cpp
+++ b/src/OpenGL/compiler/OutputASM.cpp
@@ -2273,7 +2273,6 @@
 		if(type.isStruct() || type.isInterfaceBlock())
 		{
 			const TFieldList& fields = type.getStruct() ? type.getStruct()->fields() : type.getInterfaceBlock()->fields();
-			int elements = 0;
 
 			for(const auto &field : fields)
 			{
@@ -2282,7 +2281,6 @@
 				if(fieldType.totalRegisterCount() <= registers)
 				{
 					registers -= fieldType.totalRegisterCount();
-					elements += fieldType.getObjectSize();
 				}
 				else   // Register within this field
 				{
diff --git a/third_party/llvm-10.0/llvm/lib/Target/ARM/ARMISelLowering.cpp b/third_party/llvm-10.0/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 66f3f41..15f4b51 100644
--- a/third_party/llvm-10.0/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/third_party/llvm-10.0/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -6530,12 +6530,10 @@
       return SDValue();
     // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
     uint64_t BitMask = 0xff;
-    uint64_t Val = 0;
     unsigned ImmMask = 1;
     Imm = 0;
     for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
       if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
-        Val |= BitMask;
         Imm |= ImmMask;
       } else if ((SplatBits & BitMask) != 0) {
         return SDValue();
diff --git a/third_party/llvm-10.0/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp b/third_party/llvm-10.0/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
index 6717d47..c586124 100644
--- a/third_party/llvm-10.0/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
+++ b/third_party/llvm-10.0/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
@@ -579,12 +579,9 @@
 }
 
 bool ARMLowOverheadLoops::ProcessLoop(MachineLoop *ML) {
-
-  bool Changed = false;
-
   // Process inner loops first.
   for (auto I = ML->begin(), E = ML->end(); I != E; ++I)
-    Changed |= ProcessLoop(*I);
+    ProcessLoop(*I);
 
   LLVM_DEBUG(dbgs() << "ARM Loops: Processing loop containing:\n";
              if (auto *Preheader = ML->getLoopPreheader())
diff --git a/third_party/llvm-10.0/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp b/third_party/llvm-10.0/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
index cdff4d3..d78dee6 100644
--- a/third_party/llvm-10.0/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
+++ b/third_party/llvm-10.0/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
@@ -289,7 +289,6 @@
   //     b MBB
   //
   bool MadeChange = true;
-  bool EverMadeChange = false;
   while (MadeChange) {
     // Iteratively expand branches until we reach a fixed point.
     MadeChange = false;
@@ -379,8 +378,6 @@
       // padding-based contributions to the block sizes.
       modifyAdjustment(Fn);
     }
-
-    EverMadeChange |= MadeChange;
   }
 
   BlockSizes.clear();
diff --git a/third_party/llvm-10.0/llvm/lib/Target/X86/X86FloatingPoint.cpp b/third_party/llvm-10.0/llvm/lib/Target/X86/X86FloatingPoint.cpp
index 13bbd6c..d9fbc1e 100644
--- a/third_party/llvm-10.0/llvm/lib/Target/X86/X86FloatingPoint.cpp
+++ b/third_party/llvm-10.0/llvm/lib/Target/X86/X86FloatingPoint.cpp
@@ -1523,7 +1523,7 @@
 
     // Scan the assembly for ST registers used, defined and clobbered. We can
     // only tell clobbers from defs by looking at the asm descriptor.
-    unsigned STUses = 0, STDefs = 0, STClobbers = 0, STDeadDefs = 0;
+    unsigned STUses = 0, STDefs = 0, STClobbers = 0;
     unsigned NumOps = 0;
     SmallSet<unsigned, 1> FRegIdx;
     unsigned RCID;
@@ -1556,8 +1556,6 @@
       case InlineAsm::Kind_RegDef:
       case InlineAsm::Kind_RegDefEarlyClobber:
         STDefs |= (1u << STReg);
-        if (MO.isDead())
-          STDeadDefs |= (1u << STReg);
         break;
       case InlineAsm::Kind_Clobber:
         STClobbers |= (1u << STReg);