Add CMP(register) and CMP(Immediate) to ARM integerated assembler.
Also cleans up comments on rotated immediate 8 constants.
BUG= https://code.google.com/p/nativeclient/issues/detail?id=4334
R=stichnot@chromium.org
Review URL: https://codereview.chromium.org/1414483008 .
diff --git a/src/DartARM32/assembler_arm.cc b/src/DartARM32/assembler_arm.cc
index cbf7a41..180a182 100644
--- a/src/DartARM32/assembler_arm.cc
+++ b/src/DartARM32/assembler_arm.cc
@@ -266,9 +266,12 @@
}
+#if 0
+// Moved to ARM32::AssemblerARM32::cmp()
void Assembler::cmp(Register rn, Operand o, Condition cond) {
EmitType01(cond, o.type(), CMP, 1, rn, R0, o);
}
+#endif
void Assembler::cmn(Register rn, Operand o, Condition cond) {
diff --git a/src/DartARM32/assembler_arm.h b/src/DartARM32/assembler_arm.h
index 822b738..ffc360b 100644
--- a/src/DartARM32/assembler_arm.h
+++ b/src/DartARM32/assembler_arm.h
@@ -132,15 +132,18 @@
return *this;
}
+#if 0
+ // Moved to encodeRotatedImm8() in IceAssemblerARM32.cpp
// Data-processing operands - Immediate.
explicit Operand(uint32_t immediate) {
ASSERT(immediate < (1 << kImmed8Bits));
type_ = 1;
encoding_ = immediate;
}
+#endif
#if 0
- // Moved to decodeOperand() in IceAssemblerARM32.cpp
+ // Moved to decodeOperand() and encodeRotatedImm8() in IceAssemblerARM32.cpp
// Data-processing operands - Rotated immediate.
Operand(uint32_t rotate, uint32_t immed8) {
ASSERT((rotate < (1 << kRotateBits)) && (immed8 < (1 << kImmed8Bits)));
@@ -174,6 +177,8 @@
static_cast<uint32_t>(rm);
}
+#if 0
+ // Already defined as ARM32::OperandARM32FlexImm::canHoldImm().
static bool CanHold(uint32_t immediate, Operand* o) {
// Avoid the more expensive test for frequent small immediate values.
if (immediate < (1 << kImmed8Bits)) {
@@ -192,6 +197,7 @@
}
return false;
}
+#endif
private:
bool is_valid() const { return (type_ == 0) || (type_ == 1); }
@@ -478,7 +484,10 @@
void teq(Register rn, Operand o, Condition cond = AL);
+#if 0
+ // Moved to ARM32::AssemblerARM32::cmp()
void cmp(Register rn, Operand o, Condition cond = AL);
+#endif
void cmn(Register rn, Operand o, Condition cond = AL);
diff --git a/src/IceAssemblerARM32.cpp b/src/IceAssemblerARM32.cpp
index 3e55799..20b8a34 100644
--- a/src/IceAssemblerARM32.cpp
+++ b/src/IceAssemblerARM32.cpp
@@ -173,9 +173,18 @@
// i.e. 0000000pu0w0nnnn0000iiiiiiiiiiii where nnnn is the base register Rn,
// p=1 if pre-indexed addressing, u=1 if offset positive, w=1 if writeback to
// Rn should be used, and iiiiiiiiiiii is the offset.
- DecodedAsImmRegOffset
+ DecodedAsImmRegOffset,
+ // Value is 32bit integer constant.
+ DecodedAsConstI32
};
+// Sets Encoding to a rotated Imm8 encoding of Value, if possible.
+inline IValueT encodeRotatedImm8(IValueT RotateAmt, IValueT Immed8) {
+ assert(RotateAmt < (1 << kRotateBits));
+ assert(Immed8 < (1 << kImmed8Bits));
+ return (RotateAmt << kRotateShift) | (Immed8 << kImmed8Shift);
+}
+
// Encodes iiiiitt0mmmm for data-processing (2nd) operands where iiiii=Imm5,
// tt=Shift, and mmmm=Rm.
IValueT encodeShiftRotateImm5(IValueT Rm, OperandARM32::ShiftKind Shift,
@@ -199,6 +208,10 @@
Value = (Rotate << kRotateShift) | (Immed8 << kImmed8Shift);
return DecodedAsRotatedImm8;
}
+ if (const auto *Const = llvm::dyn_cast<ConstantInteger32>(Opnd)) {
+ Value = Const->getValue();
+ return DecodedAsConstI32;
+ }
return CantDecode;
}
@@ -399,7 +412,7 @@
// xxx{s}<c> <Rd>, <Rn>, #<RotatedImm8>
//
// cccc0010100snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
- // s=SetFlags and iiiiiiiiiiii=Src1Value=RotatedImm8.
+ // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
if ((Rd == RegARM32::Encoded_Reg_pc && SetFlags))
// Conditions of rule violated.
return setNeedsTextFixup();
@@ -490,7 +503,7 @@
// adc{s}<c> <Rd>, <Rn>, #<RotatedImm8>
//
// cccc0010101snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
- // s=SetFlags and iiiiiiiiiiii=Src1Value=RotatedImm8.
+ // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
constexpr IValueT Adc = B2 | B0; // 0101
emitType01(Adc, OpRd, OpRn, OpSrc1, SetFlags, Cond);
}
@@ -512,7 +525,7 @@
// add{s}<c> <Rd>, sp, #<RotatedImm8>
//
// cccc0010100snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
- // s=SetFlags and iiiiiiiiiiii=Src1Value=RotatedImm8.
+ // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
constexpr IValueT Add = B2; // 0100
emitType01(Add, OpRd, OpRn, OpSrc1, SetFlags, Cond);
}
@@ -564,6 +577,52 @@
emitInst(Encoding);
}
+void AssemblerARM32::cmp(const Operand *OpRn, const Operand *OpSrc1,
+ CondARM32::Cond Cond) {
+ IValueT Rn;
+ if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
+ return setNeedsTextFixup();
+ constexpr IValueT Cmp = B3 | B1; // ie. 1010
+ constexpr bool SetFlags = true;
+ constexpr IValueT Rd = RegARM32::Encoded_Reg_r0;
+ IValueT Src1Value;
+ // TODO(kschimpf) Other possible decodings of cmp.
+ switch (decodeOperand(OpSrc1, Src1Value)) {
+ default:
+ return setNeedsTextFixup();
+ case DecodedAsRegister: {
+ // CMP (register) - ARM section A8.8.38, encoding A1:
+ // cmp<c> <Rn>, <Rm>{, <shift>}
+ //
+ // cccc00010101nnnn0000iiiiitt0mmmm where cccc=Cond, nnnn=Rn, mmmm=Rm,
+ // iiiii=Shift, and tt=ShiftKind.
+ constexpr IValueT Imm5 = 0;
+ Src1Value = encodeShiftRotateImm5(Src1Value, OperandARM32::kNoShift, Imm5);
+ emitType01(Cond, kInstTypeDataRegister, Cmp, SetFlags, Rn, Rd, Src1Value);
+ return;
+ }
+ case DecodedAsConstI32: {
+ // See if we can convert this to an CMP (immediate).
+ IValueT RotateAmt;
+ IValueT Imm8;
+ if (!OperandARM32FlexImm::canHoldImm(Src1Value, &RotateAmt, &Imm8))
+ return setNeedsTextFixup();
+ Src1Value = encodeRotatedImm8(RotateAmt, Imm8);
+ // Intentionally fall to next case!
+ }
+ case DecodedAsRotatedImm8: {
+ // CMP (immediate) - ARM section A8.8.37
+ // cmp<c: <Rn>, #<RotatedImm8>
+ //
+ // cccc00110101nnnn0000iiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
+ // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
+ emitType01(Cond, kInstTypeDataImmediate, Cmp, SetFlags, Rn, Rd, Src1Value);
+ return;
+ }
+ }
+ setNeedsTextFixup();
+}
+
void AssemblerARM32::eor(const Operand *OpRd, const Operand *OpRn,
const Operand *OpSrc1, bool SetFlags,
CondARM32::Cond Cond) {
@@ -577,7 +636,7 @@
// eor{s}<c> <Rd>, <Rn>, #RotatedImm8
//
// cccc0010001snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
- // s=SetFlags and iiiiiiiiiiii=Src1Value=RotatedImm8.
+ // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
constexpr IValueT Eor = B0; // 0001
emitType01(Eor, OpRd, OpRn, OpSrc1, SetFlags, Cond);
}
@@ -631,7 +690,8 @@
// mov{S}<c> <Rd>, #<RotatedImm8>
//
// cccc0011101s0000ddddiiiiiiiiiiii where cccc=Cond, s=SetFlags, dddd=Rd, and
- // iiiiiiiiiiii=RotatedImm8=Src. Note: We don't use movs in this assembler.
+ // iiiiiiiiiiii=Src defining RotatedImm8. Note: We don't use movs in this
+ // assembler.
constexpr bool SetFlags = false;
if ((Rd == RegARM32::Encoded_Reg_pc && SetFlags))
// Conditions of rule violated.
@@ -710,7 +770,7 @@
// sbc{s}<c> <Rd>, <Rn>, #<RotatedImm8>
//
// cccc0010110snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
- // s=SetFlags and iiiiiiiiiiii=Src1Value=RotatedImm8.
+ // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
constexpr IValueT Sbc = B2 | B1; // 0110
emitType01(Sbc, OpRd, OpRn, OpSrc1, SetFlags, Cond);
}
@@ -885,7 +945,7 @@
// sub{s}<c> sp, <Rn>, #<RotatedImm8>
//
// cccc0010010snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
- // s=SetFlags and iiiiiiiiiiii=Src1Value=RotatedImm8
+ // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8
constexpr IValueT Sub = B1; // 0010
emitType01(Sub, OpRd, OpRn, OpSrc1, SetFlags, Cond);
}
diff --git a/src/IceAssemblerARM32.h b/src/IceAssemblerARM32.h
index abf9b29..514cb78 100644
--- a/src/IceAssemblerARM32.h
+++ b/src/IceAssemblerARM32.h
@@ -150,6 +150,8 @@
void bkpt(uint16_t Imm16);
+ void cmp(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond);
+
void eor(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
bool SetFlags, CondARM32::Cond Cond);
diff --git a/src/IceInstARM32.cpp b/src/IceInstARM32.cpp
index 428b472..1697ee8 100644
--- a/src/IceInstARM32.cpp
+++ b/src/IceInstARM32.cpp
@@ -507,6 +507,19 @@
}
}
+template <InstARM32::InstKindARM32 K>
+void InstARM32CmpLike<K>::emitIAS(const Cfg *Func) const {
+ emitUsingTextFixup(Func);
+}
+
+template <> void InstARM32Cmp::emitIAS(const Cfg *Func) const {
+ assert(getSrcSize() == 2);
+ ARM32::AssemblerARM32 *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
+ Asm->cmp(getSrc(0), getSrc(1), getPredicate());
+ if (Asm->needsTextFixup())
+ emitUsingTextFixup(Func);
+}
+
InstARM32Vcmp::InstARM32Vcmp(Cfg *Func, Variable *Src0, Variable *Src1,
CondARM32::Cond Predicate)
: InstARM32Pred(Func, InstARM32::Vcmp, 2, nullptr, Predicate) {
@@ -1567,4 +1580,7 @@
template class InstARM32UnaryopGPR<InstARM32::Uxt, true>;
template class InstARM32UnaryopFP<InstARM32::Vsqrt>;
+template class InstARM32CmpLike<InstARM32::Cmp>;
+template class InstARM32CmpLike<InstARM32::Tst>;
+
} // end of namespace Ice
diff --git a/src/IceInstARM32.h b/src/IceInstARM32.h
index e7d9e4c..28317d2 100644
--- a/src/IceInstARM32.h
+++ b/src/IceInstARM32.h
@@ -717,6 +717,7 @@
return;
emitCmpLike(Opcode, this, Func);
}
+ void emitIAS(const Cfg *Func) const override;
void dump(const Cfg *Func) const override {
if (!BuildDefs::dump())
return;
diff --git a/tests_lit/assembler/arm32/branch-mult-fwd.ll b/tests_lit/assembler/arm32/branch-mult-fwd.ll
index 13a9315..19cd5e5 100644
--- a/tests_lit/assembler/arm32/branch-mult-fwd.ll
+++ b/tests_lit/assembler/arm32/branch-mult-fwd.ll
@@ -22,125 +22,133 @@
; ASM-LABEL:mult_fwd_branches:
; ASM-LABEL:.Lmult_fwd_branches$__0:
-; ASM-NEXT: sub sp, sp, #12
-; ASM-NEXT: str r0, [sp, #8]
-; ASM-NEXT: str r1, [sp, #4]
+; ASM-NEXT: sub sp, sp, #12
+; ASM-NEXT: str r0, [sp, #8]
+; ASM-NEXT: str r1, [sp, #4]
; DIS-LABEL:00000000 <mult_fwd_branches>:
-; DIS-NEXT: 0: e24dd00c
-; DIS-NEXT: 4: e58d0008
-; DIS-NEXT: 8: e58d1004
+; DIS-NEXT: 0: e24dd00c
+; DIS-NEXT: 4: e58d0008
+; DIS-NEXT: 8: e58d1004
; IASM-LABEL:mult_fwd_branches:
; IASM-LABEL:.Lmult_fwd_branches$__0:
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x4d
-; IASM-NEXT: .byte 0xe2
+; IASM-NEXT: .byte 0xc
+; IASM-NEXT: .byte 0xd0
+; IASM-NEXT: .byte 0x4d
+; IASM-NEXT: .byte 0xe2
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
+; IASM-NEXT: .byte 0x8
+; IASM-NEXT: .byte 0x0
+; IASM-NEXT: .byte 0x8d
+; IASM-NEXT: .byte 0xe5
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
+; IASM-NEXT: .byte 0x4
+; IASM-NEXT: .byte 0x10
+; IASM-NEXT: .byte 0x8d
+; IASM-NEXT: .byte 0xe5
%cmp = icmp slt i32 %a, %b
-; ASM-NEXT: ldr r0, [sp, #8]
-; ASM-NEXT: mov r1, #0
-; ASM-NEXT: ldr r2, [sp, #4]
-; ASM-NEXT: cmp r0, r2
-; ASM-NEXT: movlt r1, #1
-; ASM-NEXT: str r1, [sp]
+; ASM-NEXT: ldr r0, [sp, #8]
+; ASM-NEXT: mov r1, #0
+; ASM-NEXT: ldr r2, [sp, #4]
+; ASM-NEXT: cmp r0, r2
+; ASM-NEXT: movlt r1, #1
+; ASM-NEXT: str r1, [sp]
-; DIS-NEXT: c: e59d0008
-; DIS-NEXT: 10: e3a01000
-; DIS-NEXT: 14: e59d2004
-; DIS-NEXT: 18: e1500002
-; DIS-NEXT: 1c: b3a01001
-; DIS-NEXT: 20: e58d1000
+; DIS-NEXT: c: e59d0008
+; DIS-NEXT: 10: e3a01000
+; DIS-NEXT: 14: e59d2004
+; DIS-NEXT: 18: e1500002
+; DIS-NEXT: 1c: b3a01001
+; DIS-NEXT: 20: e58d1000
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
+; IASM-NEXT: .byte 0x8
+; IASM-NEXT: .byte 0x0
+; IASM-NEXT: .byte 0x9d
+; IASM-NEXT: .byte 0xe5
-; IASM-NEXT: mov r1, #0
+; IASM-NEXT: mov r1, #0
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
+; IASM-NEXT: .byte 0x4
+; IASM-NEXT: .byte 0x20
+; IASM-NEXT: .byte 0x9d
+; IASM-NEXT: .byte 0xe5
-; IASM-NEXT: cmp r0, r2
-; IASM-NEXT: movlt r1, #1
+; IASM-NEXT: .byte 0x2
+; IASM-NEXT: .byte 0x0
+; IASM-NEXT: .byte 0x50
+; IASM-NEXT: .byte 0xe1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
+; IASM-NEXT: movlt r1, #1
+
+; IASM-NEXT: .byte 0x0
+; IASM-NEXT: .byte 0x10
+; IASM-NEXT: .byte 0x8d
+; IASM-NEXT: .byte 0xe5
br i1 %cmp, label %then, label %else
-; ASM-NEXT: ldr r0, [sp]
-; ASM-NEXT: uxtb r0, r0
-; ASM-NEXT: cmp r0, #0
-; ASM-NEXT: bne .Lmult_fwd_branches$then
-; ASM-NEXT: b .Lmult_fwd_branches$else
+; ASM-NEXT: ldr r0, [sp]
+; ASM-NEXT: uxtb r0, r0
+; ASM-NEXT: cmp r0, #0
+; ASM-NEXT: bne .Lmult_fwd_branches$then
+; ASM-NEXT: b .Lmult_fwd_branches$else
-; DIS-NEXT: 24: e59d0000
-; DIS-NEXT: 28: e6ef0070
-; DIS-NEXT: 2c: e3500000
-; DIS-NEXT: 30: 1a000000
-; DIS-NEXT: 34: ea000000
+; DIS-NEXT: 24: e59d0000
+; DIS-NEXT: 28: e6ef0070
+; DIS-NEXT: 2c: e3500000
+; DIS-NEXT: 30: 1a000000
+; DIS-NEXT: 34: ea000000
-; IASM-NEXT: ldr r0, [sp]
-; IASM-NEXT: uxtb r0, r0
-; IASM-NEXT: cmp r0, #0
+; IASM-NEXT: ldr r0, [sp]
+; IASM-NEXT: uxtb r0, r0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1a
+; IASM-NEXT: .byte 0x0
+; IASM-NEXT: .byte 0x0
+; IASM-NEXT: .byte 0x50
+; IASM-NEXT: .byte 0xe3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xea
+; IASM-NEXT: .byte 0x0
+; IASM-NEXT: .byte 0x0
+; IASM-NEXT: .byte 0x0
+; IASM-NEXT: .byte 0x1a
+
+; IASM-NEXT: .byte 0x0
+; IASM-NEXT: .byte 0x0
+; IASM-NEXT: .byte 0x0
+; IASM-NEXT: .byte 0xea
then:
; ASM-LABEL:.Lmult_fwd_branches$then:
; IASM-LABEL:.Lmult_fwd_branches$then:
br label %end
-; ASM-NEXT: b .Lmult_fwd_branches$end
+; ASM-NEXT: b .Lmult_fwd_branches$end
-; DIS-NEXT: 38: ea000000
+; DIS-NEXT: 38: ea000000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xea
+; IASM-NEXT: .byte 0x0
+; IASM-NEXT: .byte 0x0
+; IASM-NEXT: .byte 0x0
+; IASM-NEXT: .byte 0xea
else:
; ASM-LABEL:.Lmult_fwd_branches$else:
; IASM-LABEL:.Lmult_fwd_branches$else:
br label %end
-; ASM-NEXT: b .Lmult_fwd_branches$end
+; ASM-NEXT: b .Lmult_fwd_branches$end
-; DIS-NEXT: 3c: eaffffff
+; DIS-NEXT: 3c: eaffffff
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xea
+; IASM-NEXT: .byte 0xff
+; IASM-NEXT: .byte 0xff
+; IASM-NEXT: .byte 0xff
+; IASM-NEXT: .byte 0xea
end:
@@ -149,20 +157,20 @@
ret void
-; ASM-NEXT: add sp, sp, #12
-; ASM-NEXT: bx lr
+; ASM-NEXT: add sp, sp, #12
+; ASM-NEXT: bx lr
-; DIS-NEXT: 40: e28dd00c
-; DIS-NEXT: 44: e12fff1e
+; DIS-NEXT: 40: e28dd00c
+; DIS-NEXT: 44: e12fff1e
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe2
+; IASM-NEXT: .byte 0xc
+; IASM-NEXT: .byte 0xd0
+; IASM-NEXT: .byte 0x8d
+; IASM-NEXT: .byte 0xe2
-; IASM-NEXT: .byte 0x1e
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x2f
-; IASM-NEXT: .byte 0xe1
+; IASM-NEXT: .byte 0x1e
+; IASM-NEXT: .byte 0xff
+; IASM-NEXT: .byte 0x2f
+; IASM-NEXT: .byte 0xe1
}
