diff --git a/src/IceTargetLoweringX86BaseImpl.h b/src/IceTargetLoweringX86BaseImpl.h
index 245861c..73c0075 100644
--- a/src/IceTargetLoweringX86BaseImpl.h
+++ b/src/IceTargetLoweringX86BaseImpl.h
@@ -3804,6 +3804,10 @@
   // eax, ax and al.
   if (IsCountConst && IsValConst) {
     Variable *Base = legalizeToReg(Dest);
+    // Add a FakeUse in case Base is ultimately not used, e.g. it falls back to
+    // calling memset().  Otherwise Om1 register allocation fails because this
+    // infinite-weight variable has a definition but no uses.
+    Context.insert(InstFakeUse::create(Func, Base));
 
     // 3 is the awkward size as it is too small for the vector or 32-bit
     // operations and will not work with lowerLeftOvers as there is no valid
diff --git a/tests_lit/llvm2ice_tests/nacl-mem-intrinsics.ll b/tests_lit/llvm2ice_tests/nacl-mem-intrinsics.ll
index b262f92..8656c57 100644
--- a/tests_lit/llvm2ice_tests/nacl-mem-intrinsics.ll
+++ b/tests_lit/llvm2ice_tests/nacl-mem-intrinsics.ll
@@ -101,6 +101,19 @@
 ; ARM32: uxtb
 ; ARM32: bl {{.*}} memset
 
+define void @test_memset_long_const_len_zero_val_align(i32 %iptr_dst) {
+entry:
+  %dst = inttoptr i32 %iptr_dst to i8*
+  call void @llvm.memset.p0i8.i32(i8* %dst, i8 0,
+                                  i32 4876, i32 1, i1 false)
+  ret void
+}
+; CHECK-LABEL: test_memset_long_const_len_zero_val_align
+; CHECK: call {{.*}} R_{{.*}} memset
+; ARM32-LABEL: test_memset_long_const_len_zero_val_align
+; ARM32: uxtb
+; ARM32: bl {{.*}} memset
+
 define void @test_memset_const_val(i32 %iptr_dst, i32 %len) {
 entry:
   %dst = inttoptr i32 %iptr_dst to i8*