diff --git a/tests_lit/llvm2ice_tests/64bit.pnacl.ll b/tests_lit/llvm2ice_tests/64bit.pnacl.ll
index b0110bf..88d4a3d 100644
--- a/tests_lit/llvm2ice_tests/64bit.pnacl.ll
+++ b/tests_lit/llvm2ice_tests/64bit.pnacl.ll
@@ -92,25 +92,19 @@
 ; OPTM1:      call {{.*}} R_{{.*}}    ignore64BitArgNoInline
 
 ; ARM32-LABEL: pass64BitArg
-; ARM32:      sub     sp, {{.*}} #16
 ; ARM32:      str     {{.*}}, [sp]
 ; ARM32:      movw    r2, #123
 ; ARM32:      bl      {{.*}} ignore64BitArgNoInline
-; ARM32:      add     sp, {{.*}} #16
-; ARM32:      sub     sp, {{.*}} #16
 ; ARM32:      str     {{.*}}, [sp]
 ; ARM32:      {{mov|ldr}} r0
 ; ARM32:      {{mov|ldr}} r1
 ; ARM32:      movw    r2, #123
 ; ARM32:      bl      {{.*}} ignore64BitArgNoInline
-; ARM32:      add     sp, {{.*}} #16
-; ARM32:      sub     sp, {{.*}} #16
 ; ARM32:      str     {{.*}}, [sp]
 ; ARM32:      {{mov|ldr}} r0
 ; ARM32:      {{mov|ldr}} r1
 ; ARM32:      movw    r2, #123
 ; ARM32:      bl      {{.*}} ignore64BitArgNoInline
-; ARM32:      add     sp, {{.*}} #16
 
 
 declare i32 @ignore64BitArgNoInline(i64, i32, i64)
@@ -144,7 +138,6 @@
 ; OPTM1:      call {{.*}} R_{{.*}}    ignore64BitArgNoInline
 
 ; ARM32-LABEL: pass64BitConstArg
-; ARM32:      sub     sp, {{.*}} #16
 ; ARM32:      movw    [[REG1:r.*]], {{.*}} ; 0xbeef
 ; ARM32:      movt    [[REG1]], {{.*}}     ; 0xdead
 ; ARM32:      movw    [[REG2:r.*]], {{.*}} ; 0x5678
@@ -155,7 +148,6 @@
 ; ARM32:      {{mov|ldr}} r1
 ; ARM32:      movw    r2, #123
 ; ARM32:      bl      {{.*}} ignore64BitArgNoInline
-; ARM32:      add     sp, {{.*}} #16
 
 define internal i32 @pass64BitUndefArg() {
 entry:
diff --git a/tests_lit/llvm2ice_tests/large_stack_offs.ll b/tests_lit/llvm2ice_tests/large_stack_offs.ll
index 7818336..8449df7 100644
--- a/tests_lit/llvm2ice_tests/large_stack_offs.ll
+++ b/tests_lit/llvm2ice_tests/large_stack_offs.ll
@@ -49,7 +49,7 @@
 ; ARM32-NOT: mov fp, sp
 ; ARM32: movw ip, #4{{.*}}
 ; ARM32-NEXT: sub sp, sp, ip
-; ARM32: movw ip, #4232
+; ARM32: movw ip, #4248
 ; ARM32-NEXT: add ip, sp, ip
 ; ARM32-NOT: movw ip
 ; %t2 is the result of the "or", and %t2 will be passed via r1 to the call.
@@ -61,14 +61,10 @@
 ; ARM32: str [[REG]], [ip, #-20]
 ; ARM32: b {{[a-f0-9]+}}
 ; Now skip ahead to where the call in br_1 begins, to check how %t2 is used.
-; ARM32: movw ip, #4216
+; ARM32: movw ip, #4232
 ; ARM32-NEXT: add ip, sp, ip
-; ARM32: sub sp, sp, #16
-; Now sp1 = sp0 - 16, but ip is still in terms of sp0.
-; So, sp0 + 4212 == ip - 4.
 ; ARM32: ldr r2, [ip, #-4]
 ; ARM32: bl {{.*}} dummy
-; ARM32: add sp, sp
 ; The call clobbers ip, so we need to re-create the base register.
 ; ARM32: movw ip, #4{{.*}}
 ; ARM32: b {{[a-f0-9]+}}
@@ -122,12 +118,8 @@
 ; Now skip ahead to where the call in br_1 begins, to check how %t2 is used.
 ; ARM32: movw ip, #4120
 ; ARM32-NEXT: sub ip, fp, ip
-; ARM32: sub sp, sp, #16
-; Now sp1 = sp0 - 16, but ip is still in terms of fp0.
-; So, fp0 - 4124 == ip - 4.
 ; ARM32: ldr r2, [ip, #-4]
 ; ARM32: bl {{.*}} dummy
-; ARM32: add sp, sp
 ; The call clobbers ip, so we need to re-create the base register.
 ; ARM32: movw ip, #4{{.*}}
 ; ARM32: b {{[a-f0-9]+}}