- This patch implements lowerstore for i32, i64 types for mips32 arch.

- InstMIPS32Memory class is added to represent memory related instructions(load/store). I will add remaining load/store instructions if you are okay with this patch.

- Changed uncond_br.ll test as it was failing due to hardcoded label no. expected in output.

R=jpp@chromium.org, stichnot@chromium.org

Review URL: https://codereview.chromium.org/2005823002 .

Patch from Mohit Bhakkad <mohit.bhakkad@imgtec.com>.

src/IceTargetLoweringMIPS32.h

diff --git a/src/IceTargetLoweringMIPS32.h b/src/IceTargetLoweringMIPS32.h
index aca82cd..5586004 100644
--- a/src/IceTargetLoweringMIPS32.h
+++ b/src/IceTargetLoweringMIPS32.h
@@ -117,8 +117,10 @@
   void emitVariable(const Variable *Var) const override;
 
   void emit(const ConstantInteger32 *C) const final {
-    (void)C;
-    llvm::report_fatal_error("Not yet implemented");
+    if (!BuildDefs::dump())
+      return;
+    Ostream &Str = Ctx->getStrEmit();
+    Str << C->getValue();
   }
   void emit(const ConstantInteger64 *C) const final {
     (void)C;
@@ -341,6 +343,10 @@
     Context.insert<InstMIPS32Subu>(Dest, Src0, Src1);
   }
 
+  void _sw(Variable *Value, OperandMIPS32Mem *Mem) {
+    Context.insert<InstMIPS32Sw>(Value, Mem);
+  }
+
   void _xor(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstMIPS32Xor>(Dest, Src0, Src1);
   }
@@ -440,6 +446,8 @@
                                 const SmallBitVector &ExcludeRegisters,
                                 uint64_t Salt) const override;
 
+  OperandMIPS32Mem *formMemoryOperand(Operand *Ptr, Type Ty);
+
   bool UsesFramePointer = false;
   bool NeedsStackAlignment = false;
   static SmallBitVector TypeToRegisterSet[RCMIPS32_NUM];