Fix bug in Subzero bitcode reader for insertelement instruction.
Instruction insertelement was incorrectly generating a result
corresponding to the element type, instead of the updated
vector type.
BUG= None
R=jvoung@chromium.org
Review URL: https://codereview.chromium.org/604023003
diff --git a/src/PNaClTranslator.cpp b/src/PNaClTranslator.cpp
index 35108cc..6c0ee8a 100644
--- a/src/PNaClTranslator.cpp
+++ b/src/PNaClTranslator.cpp
@@ -1608,7 +1608,7 @@
// TODO(kschimpf): Restrict index to a legal constant index (once
// constants can be defined).
CurrentNode->appendInst(Ice::InstInsertElement::create(
- Func, getNextInstVar(EltType), Vec, Elt, Index));
+ Func, getNextInstVar(VecType), Vec, Elt, Index));
break;
}
case naclbitc::FUNC_CODE_INST_CMP2: {
diff --git a/tests_lit/llvm2ice_tests/vector-ops.ll b/tests_lit/llvm2ice_tests/vector-ops.ll
index 0b09e6a..728170c 100644
--- a/tests_lit/llvm2ice_tests/vector-ops.ll
+++ b/tests_lit/llvm2ice_tests/vector-ops.ll
@@ -1,22 +1,21 @@
; This checks support for insertelement and extractelement.
-; TODO(kschimpf) Figure out why lc2i is needed.
-; RUN: %lc2i -i %s --args -O2 --verbose none \
+; RUN: %p2i -i %s --args -O2 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %lc2i -i %s --args -Om1 --verbose none \
+; RUN: %p2i -i %s --args -Om1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %lc2i -i %s --args -O2 -mattr=sse4.1 --verbose none \
+; RUN: %p2i -i %s --args -O2 -mattr=sse4.1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
; RUN: | FileCheck --check-prefix=SSE41 %s
-; RUN: %lc2i -i %s --args -Om1 -mattr=sse4.1 --verbose none \
+; RUN: %p2i -i %s --args -Om1 -mattr=sse4.1 --verbose none \
; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
; RUN: | FileCheck --check-prefix=SSE41 %s
-; RUN: %lc2i -i %s --args --verbose none | FileCheck --check-prefix=ERRORS %s
-; RUN: %lc2i -i %s --insts | %szdiff %s | FileCheck --check-prefix=DUMP %s
+; RUN: %p2i -i %s --args --verbose none | FileCheck --check-prefix=ERRORS %s
+; RUN: %p2i -i %s --insts | %szdiff %s | FileCheck --check-prefix=DUMP %s
; insertelement operations
diff --git a/tests_lit/reader_tests/insertextract.ll b/tests_lit/reader_tests/insertextract.ll
index 9dbe6aa..bc34011 100644
--- a/tests_lit/reader_tests/insertextract.ll
+++ b/tests_lit/reader_tests/insertextract.ll
@@ -100,7 +100,7 @@
; CHECK-NEXT: entry:
; CHECK-NEXT: %e = trunc i32 %pe to i1
; CHECK-NEXT: %r = insertelement <4 x i1> %v, i1 %e, i32 %i
-; CHECK-NEXT: ret i1 %r
+; CHECK-NEXT: ret <4 x i1> %r
; CHECK-NEXT: }
define <8 x i1> @InsertV8xi1(<8 x i1> %v, i32 %pe, i32 %i) {
@@ -114,7 +114,7 @@
; CHECK-NEXT: entry:
; CHECK-NEXT: %e = trunc i32 %pe to i1
; CHECK-NEXT: %r = insertelement <8 x i1> %v, i1 %e, i32 %i
-; CHECK-NEXT: ret i1 %r
+; CHECK-NEXT: ret <8 x i1> %r
; CHECK-NEXT: }
define <16 x i1> @InsertV16xi1(<16 x i1> %v, i32 %pe, i32 %i) {
@@ -128,7 +128,7 @@
; CHECK-NEXT: entry:
; CHECK-NEXT: %e = trunc i32 %pe to i1
; CHECK-NEXT: %r = insertelement <16 x i1> %v, i1 %e, i32 %i
-; CHECK-NEXT: ret i1 %r
+; CHECK-NEXT: ret <16 x i1> %r
; CHECK-NEXT: }
define <16 x i8> @InsertV16xi8(<16 x i8> %v, i32 %pe, i32 %i) {
@@ -142,7 +142,7 @@
; CHECK-NEXT: entry:
; CHECK-NEXT: %e = trunc i32 %pe to i8
; CHECK-NEXT: %r = insertelement <16 x i8> %v, i8 %e, i32 %i
-; CHECK-NEXT: ret i8 %r
+; CHECK-NEXT: ret <16 x i8> %r
; CHECK-NEXT: }
define <8 x i16> @InsertV8xi16(<8 x i16> %v, i32 %pe, i32 %i) {
@@ -156,7 +156,7 @@
; CHECK-NEXT: entry:
; CHECK-NEXT: %e = trunc i32 %pe to i16
; CHECK-NEXT: %r = insertelement <8 x i16> %v, i16 %e, i32 %i
-; CHECK-NEXT: ret i16 %r
+; CHECK-NEXT: ret <8 x i16> %r
; CHECK-NEXT: }
define <4 x i32> @InsertV4xi32(<4 x i32> %v, i32 %e, i32 %i) {
@@ -168,7 +168,7 @@
; CHECK-NEXT: define <4 x i32> @InsertV4xi32(<4 x i32> %v, i32 %e, i32 %i) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %r = insertelement <4 x i32> %v, i32 %e, i32 %i
-; CHECK-NEXT: ret i32 %r
+; CHECK-NEXT: ret <4 x i32> %r
; CHECK-NEXT: }
define <4 x float> @InsertV4xfloat(<4 x float> %v, float %e, i32 %i) {
@@ -180,5 +180,5 @@
; CHECK-NEXT: define <4 x float> @InsertV4xfloat(<4 x float> %v, float %e, i32 %i) {
; CHECK-NEXT: entry:
; CHECK-NEXT: %r = insertelement <4 x float> %v, float %e, i32 %i
-; CHECK-NEXT: ret float %r
+; CHECK-NEXT: ret <4 x float> %r
; CHECK-NEXT: }
