/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register Enum Values                                                *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM

namespace llvm {

class MCRegisterClass;
extern const MCRegisterClass X86MCRegisterClasses[];

namespace X86 {
enum {
  NoRegister,
  AH = 1,
  AL = 2,
  AX = 3,
  BH = 4,
  BL = 5,
  BP = 6,
  BPH = 7,
  BPL = 8,
  BX = 9,
  CH = 10,
  CL = 11,
  CS = 12,
  CX = 13,
  DF = 14,
  DH = 15,
  DI = 16,
  DIH = 17,
  DIL = 18,
  DL = 19,
  DS = 20,
  DX = 21,
  EAX = 22,
  EBP = 23,
  EBX = 24,
  ECX = 25,
  EDI = 26,
  EDX = 27,
  EFLAGS = 28,
  EIP = 29,
  EIZ = 30,
  ES = 31,
  ESI = 32,
  ESP = 33,
  FPCW = 34,
  FPSW = 35,
  FS = 36,
  GS = 37,
  HAX = 38,
  HBP = 39,
  HBX = 40,
  HCX = 41,
  HDI = 42,
  HDX = 43,
  HIP = 44,
  HSI = 45,
  HSP = 46,
  IP = 47,
  MXCSR = 48,
  RAX = 49,
  RBP = 50,
  RBX = 51,
  RCX = 52,
  RDI = 53,
  RDX = 54,
  RIP = 55,
  RIZ = 56,
  RSI = 57,
  RSP = 58,
  SI = 59,
  SIH = 60,
  SIL = 61,
  SP = 62,
  SPH = 63,
  SPL = 64,
  SS = 65,
  SSP = 66,
  BND0 = 67,
  BND1 = 68,
  BND2 = 69,
  BND3 = 70,
  CR0 = 71,
  CR1 = 72,
  CR2 = 73,
  CR3 = 74,
  CR4 = 75,
  CR5 = 76,
  CR6 = 77,
  CR7 = 78,
  CR8 = 79,
  CR9 = 80,
  CR10 = 81,
  CR11 = 82,
  CR12 = 83,
  CR13 = 84,
  CR14 = 85,
  CR15 = 86,
  DR0 = 87,
  DR1 = 88,
  DR2 = 89,
  DR3 = 90,
  DR4 = 91,
  DR5 = 92,
  DR6 = 93,
  DR7 = 94,
  DR8 = 95,
  DR9 = 96,
  DR10 = 97,
  DR11 = 98,
  DR12 = 99,
  DR13 = 100,
  DR14 = 101,
  DR15 = 102,
  FP0 = 103,
  FP1 = 104,
  FP2 = 105,
  FP3 = 106,
  FP4 = 107,
  FP5 = 108,
  FP6 = 109,
  FP7 = 110,
  K0 = 111,
  K1 = 112,
  K2 = 113,
  K3 = 114,
  K4 = 115,
  K5 = 116,
  K6 = 117,
  K7 = 118,
  MM0 = 119,
  MM1 = 120,
  MM2 = 121,
  MM3 = 122,
  MM4 = 123,
  MM5 = 124,
  MM6 = 125,
  MM7 = 126,
  R8 = 127,
  R9 = 128,
  R10 = 129,
  R11 = 130,
  R12 = 131,
  R13 = 132,
  R14 = 133,
  R15 = 134,
  ST0 = 135,
  ST1 = 136,
  ST2 = 137,
  ST3 = 138,
  ST4 = 139,
  ST5 = 140,
  ST6 = 141,
  ST7 = 142,
  XMM0 = 143,
  XMM1 = 144,
  XMM2 = 145,
  XMM3 = 146,
  XMM4 = 147,
  XMM5 = 148,
  XMM6 = 149,
  XMM7 = 150,
  XMM8 = 151,
  XMM9 = 152,
  XMM10 = 153,
  XMM11 = 154,
  XMM12 = 155,
  XMM13 = 156,
  XMM14 = 157,
  XMM15 = 158,
  XMM16 = 159,
  XMM17 = 160,
  XMM18 = 161,
  XMM19 = 162,
  XMM20 = 163,
  XMM21 = 164,
  XMM22 = 165,
  XMM23 = 166,
  XMM24 = 167,
  XMM25 = 168,
  XMM26 = 169,
  XMM27 = 170,
  XMM28 = 171,
  XMM29 = 172,
  XMM30 = 173,
  XMM31 = 174,
  YMM0 = 175,
  YMM1 = 176,
  YMM2 = 177,
  YMM3 = 178,
  YMM4 = 179,
  YMM5 = 180,
  YMM6 = 181,
  YMM7 = 182,
  YMM8 = 183,
  YMM9 = 184,
  YMM10 = 185,
  YMM11 = 186,
  YMM12 = 187,
  YMM13 = 188,
  YMM14 = 189,
  YMM15 = 190,
  YMM16 = 191,
  YMM17 = 192,
  YMM18 = 193,
  YMM19 = 194,
  YMM20 = 195,
  YMM21 = 196,
  YMM22 = 197,
  YMM23 = 198,
  YMM24 = 199,
  YMM25 = 200,
  YMM26 = 201,
  YMM27 = 202,
  YMM28 = 203,
  YMM29 = 204,
  YMM30 = 205,
  YMM31 = 206,
  ZMM0 = 207,
  ZMM1 = 208,
  ZMM2 = 209,
  ZMM3 = 210,
  ZMM4 = 211,
  ZMM5 = 212,
  ZMM6 = 213,
  ZMM7 = 214,
  ZMM8 = 215,
  ZMM9 = 216,
  ZMM10 = 217,
  ZMM11 = 218,
  ZMM12 = 219,
  ZMM13 = 220,
  ZMM14 = 221,
  ZMM15 = 222,
  ZMM16 = 223,
  ZMM17 = 224,
  ZMM18 = 225,
  ZMM19 = 226,
  ZMM20 = 227,
  ZMM21 = 228,
  ZMM22 = 229,
  ZMM23 = 230,
  ZMM24 = 231,
  ZMM25 = 232,
  ZMM26 = 233,
  ZMM27 = 234,
  ZMM28 = 235,
  ZMM29 = 236,
  ZMM30 = 237,
  ZMM31 = 238,
  R8B = 239,
  R9B = 240,
  R10B = 241,
  R11B = 242,
  R12B = 243,
  R13B = 244,
  R14B = 245,
  R15B = 246,
  R8BH = 247,
  R9BH = 248,
  R10BH = 249,
  R11BH = 250,
  R12BH = 251,
  R13BH = 252,
  R14BH = 253,
  R15BH = 254,
  R8D = 255,
  R9D = 256,
  R10D = 257,
  R11D = 258,
  R12D = 259,
  R13D = 260,
  R14D = 261,
  R15D = 262,
  R8W = 263,
  R9W = 264,
  R10W = 265,
  R11W = 266,
  R12W = 267,
  R13W = 268,
  R14W = 269,
  R15W = 270,
  R8WH = 271,
  R9WH = 272,
  R10WH = 273,
  R11WH = 274,
  R12WH = 275,
  R13WH = 276,
  R14WH = 277,
  R15WH = 278,
  K0_K1 = 279,
  K2_K3 = 280,
  K4_K5 = 281,
  K6_K7 = 282,
  NUM_TARGET_REGS 	// 283
};
} // end namespace X86

// Register classes

namespace X86 {
enum {
  GR8RegClassID = 0,
  GRH8RegClassID = 1,
  GR8_NOREXRegClassID = 2,
  GR8_ABCD_HRegClassID = 3,
  GR8_ABCD_LRegClassID = 4,
  GRH16RegClassID = 5,
  GR16RegClassID = 6,
  GR16_NOREXRegClassID = 7,
  VK1RegClassID = 8,
  VK16RegClassID = 9,
  VK2RegClassID = 10,
  VK4RegClassID = 11,
  VK8RegClassID = 12,
  VK16WMRegClassID = 13,
  VK1WMRegClassID = 14,
  VK2WMRegClassID = 15,
  VK4WMRegClassID = 16,
  VK8WMRegClassID = 17,
  SEGMENT_REGRegClassID = 18,
  GR16_ABCDRegClassID = 19,
  FPCCRRegClassID = 20,
  VK16PAIRRegClassID = 21,
  VK1PAIRRegClassID = 22,
  VK2PAIRRegClassID = 23,
  VK4PAIRRegClassID = 24,
  VK8PAIRRegClassID = 25,
  VK16PAIR_with_sub_mask_0_in_VK16WMRegClassID = 26,
  FR32XRegClassID = 27,
  LOW32_ADDR_ACCESS_RBPRegClassID = 28,
  LOW32_ADDR_ACCESSRegClassID = 29,
  LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID = 30,
  DEBUG_REGRegClassID = 31,
  FR32RegClassID = 32,
  GR32RegClassID = 33,
  GR32_NOSPRegClassID = 34,
  LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID = 35,
  GR32_NOREXRegClassID = 36,
  VK32RegClassID = 37,
  GR32_NOREX_NOSPRegClassID = 38,
  RFP32RegClassID = 39,
  VK32WMRegClassID = 40,
  GR32_ABCDRegClassID = 41,
  GR32_TCRegClassID = 42,
  GR32_ABCD_and_GR32_TCRegClassID = 43,
  GR32_ADRegClassID = 44,
  GR32_BPSPRegClassID = 45,
  GR32_BSIRegClassID = 46,
  GR32_CBRegClassID = 47,
  GR32_DCRegClassID = 48,
  GR32_DIBPRegClassID = 49,
  GR32_SIDIRegClassID = 50,
  LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID = 51,
  CCRRegClassID = 52,
  DFCCRRegClassID = 53,
  GR32_ABCD_and_GR32_BSIRegClassID = 54,
  GR32_AD_and_GR32_DCRegClassID = 55,
  GR32_BPSP_and_GR32_DIBPRegClassID = 56,
  GR32_BPSP_and_GR32_TCRegClassID = 57,
  GR32_BSI_and_GR32_SIDIRegClassID = 58,
  GR32_CB_and_GR32_DCRegClassID = 59,
  GR32_DIBP_and_GR32_SIDIRegClassID = 60,
  LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID = 61,
  LOW32_ADDR_ACCESS_with_sub_32bitRegClassID = 62,
  RFP64RegClassID = 63,
  FR64XRegClassID = 64,
  GR64RegClassID = 65,
  CONTROL_REGRegClassID = 66,
  FR64RegClassID = 67,
  GR64_with_sub_8bitRegClassID = 68,
  GR64_NOSPRegClassID = 69,
  GR64_TCRegClassID = 70,
  GR64_NOREXRegClassID = 71,
  GR64_TCW64RegClassID = 72,
  GR64_TC_with_sub_8bitRegClassID = 73,
  GR64_NOSP_and_GR64_TCRegClassID = 74,
  GR64_TCW64_with_sub_8bitRegClassID = 75,
  GR64_TC_and_GR64_TCW64RegClassID = 76,
  GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 77,
  VK64RegClassID = 78,
  VR64RegClassID = 79,
  GR64_NOREX_NOSPRegClassID = 80,
  GR64_NOREX_and_GR64_TCRegClassID = 81,
  GR64_NOSP_and_GR64_TCW64RegClassID = 82,
  GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID = 83,
  VK64WMRegClassID = 84,
  GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID = 85,
  GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 86,
  GR64_NOREX_NOSP_and_GR64_TCRegClassID = 87,
  GR64_NOREX_and_GR64_TCW64RegClassID = 88,
  GR64_ABCDRegClassID = 89,
  GR64_with_sub_32bit_in_GR32_TCRegClassID = 90,
  GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID = 91,
  GR64_ADRegClassID = 92,
  GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID = 93,
  GR64_with_sub_32bit_in_GR32_BPSPRegClassID = 94,
  GR64_with_sub_32bit_in_GR32_BSIRegClassID = 95,
  GR64_with_sub_32bit_in_GR32_CBRegClassID = 96,
  GR64_with_sub_32bit_in_GR32_DCRegClassID = 97,
  GR64_with_sub_32bit_in_GR32_DIBPRegClassID = 98,
  GR64_with_sub_32bit_in_GR32_SIDIRegClassID = 99,
  GR64_and_LOW32_ADDR_ACCESSRegClassID = 100,
  GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID = 101,
  GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClassID = 102,
  GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID = 103,
  GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID = 104,
  GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID = 105,
  GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClassID = 106,
  GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID = 107,
  RSTRegClassID = 108,
  RFP80RegClassID = 109,
  RFP80_7RegClassID = 110,
  VR128XRegClassID = 111,
  VR128RegClassID = 112,
  BNDRRegClassID = 113,
  VR256XRegClassID = 114,
  VR256RegClassID = 115,
  VR512RegClassID = 116,
  VR512_0_15RegClassID = 117,

  };
} // end namespace X86


// Subregister indices

namespace X86 {
enum {
  NoSubRegister,
  sub_8bit,	// 1
  sub_8bit_hi,	// 2
  sub_8bit_hi_phony,	// 3
  sub_16bit,	// 4
  sub_16bit_hi,	// 5
  sub_32bit,	// 6
  sub_mask_0,	// 7
  sub_mask_1,	// 8
  sub_xmm,	// 9
  sub_ymm,	// 10
  NUM_TARGET_SUBREGS
};
} // end namespace X86

} // end namespace llvm

#endif // GET_REGINFO_ENUM

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* MC Register Information                                                    *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC

namespace llvm {

extern const MCPhysReg X86RegDiffLists[] = {
  /* 0 */ 0, 1, 0,
  /* 3 */ 64871, 1, 1, 0,
  /* 7 */ 65255, 1, 1, 0,
  /* 11 */ 65391, 1, 1, 0,
  /* 15 */ 65466, 1, 1, 0,
  /* 19 */ 2, 1, 0,
  /* 22 */ 4, 1, 0,
  /* 25 */ 6, 1, 0,
  /* 28 */ 11, 1, 0,
  /* 31 */ 22, 1, 0,
  /* 34 */ 26, 1, 0,
  /* 37 */ 29, 1, 0,
  /* 40 */ 64847, 1, 0,
  /* 43 */ 65062, 1, 0,
  /* 46 */ 65368, 1, 0,
  /* 49 */ 65369, 1, 0,
  /* 52 */ 65370, 1, 0,
  /* 55 */ 65371, 1, 0,
  /* 58 */ 10, 3, 0,
  /* 61 */ 4, 0,
  /* 63 */ 5, 0,
  /* 65 */ 65282, 1, 7, 0,
  /* 69 */ 65417, 1, 7, 0,
  /* 73 */ 10, 3, 7, 0,
  /* 77 */ 65512, 8, 0,
  /* 80 */ 65334, 1, 11, 0,
  /* 84 */ 65340, 1, 11, 0,
  /* 88 */ 65442, 1, 11, 0,
  /* 92 */ 65448, 1, 11, 0,
  /* 96 */ 12, 0,
  /* 98 */ 65334, 1, 14, 0,
  /* 102 */ 65340, 1, 14, 0,
  /* 106 */ 65442, 1, 14, 0,
  /* 110 */ 65448, 1, 14, 0,
  /* 114 */ 21, 0,
  /* 116 */ 128, 8, 65512, 8, 24, 0,
  /* 122 */ 65534, 65507, 25, 0,
  /* 126 */ 65535, 65507, 25, 0,
  /* 130 */ 65534, 65509, 25, 0,
  /* 134 */ 65535, 65509, 25, 0,
  /* 138 */ 65523, 25, 0,
  /* 141 */ 65509, 65526, 2, 65535, 25, 0,
  /* 147 */ 65518, 26, 0,
  /* 150 */ 65521, 26, 0,
  /* 153 */ 2, 6, 27, 0,
  /* 157 */ 6, 6, 27, 0,
  /* 161 */ 65534, 10, 27, 0,
  /* 165 */ 65535, 10, 27, 0,
  /* 169 */ 2, 12, 27, 0,
  /* 173 */ 3, 12, 27, 0,
  /* 177 */ 4, 15, 27, 0,
  /* 181 */ 5, 15, 27, 0,
  /* 185 */ 65534, 17, 27, 0,
  /* 189 */ 65535, 17, 27, 0,
  /* 193 */ 1, 19, 27, 0,
  /* 197 */ 2, 19, 27, 0,
  /* 201 */ 65520, 27, 0,
  /* 204 */ 65509, 65530, 65534, 65532, 28, 0,
  /* 210 */ 30, 0,
  /* 212 */ 65509, 65524, 65534, 65535, 31, 0,
  /* 218 */ 32, 32, 0,
  /* 221 */ 65509, 65519, 2, 65535, 32, 0,
  /* 227 */ 65509, 65521, 65532, 65535, 36, 0,
  /* 233 */ 65509, 65517, 65535, 65535, 37, 0,
  /* 239 */ 164, 0,
  /* 241 */ 165, 0,
  /* 243 */ 166, 0,
  /* 245 */ 167, 0,
  /* 247 */ 168, 0,
  /* 249 */ 64825, 0,
  /* 251 */ 64896, 0,
  /* 253 */ 64900, 0,
  /* 255 */ 64919, 0,
  /* 257 */ 64989, 0,
  /* 259 */ 65520, 65408, 0,
  /* 262 */ 16, 65528, 65408, 0,
  /* 266 */ 24, 65528, 65408, 0,
  /* 270 */ 65427, 0,
  /* 272 */ 65429, 0,
  /* 274 */ 65461, 0,
  /* 276 */ 65493, 0,
  /* 278 */ 65504, 65504, 0,
  /* 281 */ 65509, 0,
  /* 283 */ 65511, 0,
  /* 285 */ 65513, 0,
  /* 287 */ 65511, 29, 2, 65535, 65519, 0,
  /* 293 */ 65511, 27, 2, 65535, 65521, 0,
  /* 299 */ 65525, 0,
  /* 301 */ 65530, 0,
  /* 303 */ 65531, 0,
  /* 305 */ 65534, 65532, 0,
  /* 308 */ 65510, 18, 65533, 0,
  /* 312 */ 65534, 0,
  /* 314 */ 2, 65535, 0,
  /* 317 */ 65532, 65535, 0,
  /* 320 */ 65534, 65535, 0,
  /* 323 */ 65535, 65535, 0,
};

extern const LaneBitmask X86LaneMaskLists[] = {
  /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
  /* 2 */ LaneBitmask(0x00000002), LaneBitmask(0x00000001), LaneBitmask::getAll(),
  /* 5 */ LaneBitmask(0x00000001), LaneBitmask(0x00000004), LaneBitmask::getAll(),
  /* 8 */ LaneBitmask(0x00000002), LaneBitmask(0x00000001), LaneBitmask(0x00000008), LaneBitmask::getAll(),
  /* 12 */ LaneBitmask(0x00000001), LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask::getAll(),
  /* 16 */ LaneBitmask(0x00000007), LaneBitmask(0x00000008), LaneBitmask::getAll(),
  /* 19 */ LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask::getAll(),
  /* 22 */ LaneBitmask(0x00000040), LaneBitmask::getAll(),
};

extern const uint16_t X86SubRegIdxLists[] = {
  /* 0 */ 1, 2, 0,
  /* 3 */ 1, 3, 0,
  /* 6 */ 6, 4, 1, 2, 5, 0,
  /* 12 */ 6, 4, 1, 3, 5, 0,
  /* 18 */ 6, 4, 5, 0,
  /* 22 */ 7, 8, 0,
  /* 25 */ 10, 9, 0,
};

extern const MCRegisterInfo::SubRegCoveredBits X86SubRegIdxRanges[] = {
  { 65535, 65535 },
  { 0, 8 },	// sub_8bit
  { 8, 8 },	// sub_8bit_hi
  { 8, 8 },	// sub_8bit_hi_phony
  { 0, 16 },	// sub_16bit
  { 16, 16 },	// sub_16bit_hi
  { 0, 32 },	// sub_32bit
  { 0, 65535 },	// sub_mask_0
  { 65535, 65535 },	// sub_mask_1
  { 0, 128 },	// sub_xmm
  { 0, 256 },	// sub_ymm
};

extern const char X86RegStrings[] = {
  /* 0 */ 'X', 'M', 'M', '1', '0', 0,
  /* 6 */ 'Y', 'M', 'M', '1', '0', 0,
  /* 12 */ 'Z', 'M', 'M', '1', '0', 0,
  /* 18 */ 'C', 'R', '1', '0', 0,
  /* 23 */ 'D', 'R', '1', '0', 0,
  /* 28 */ 'X', 'M', 'M', '2', '0', 0,
  /* 34 */ 'Y', 'M', 'M', '2', '0', 0,
  /* 40 */ 'Z', 'M', 'M', '2', '0', 0,
  /* 46 */ 'X', 'M', 'M', '3', '0', 0,
  /* 52 */ 'Y', 'M', 'M', '3', '0', 0,
  /* 58 */ 'Z', 'M', 'M', '3', '0', 0,
  /* 64 */ 'B', 'N', 'D', '0', 0,
  /* 69 */ 'K', '0', 0,
  /* 72 */ 'X', 'M', 'M', '0', 0,
  /* 77 */ 'Y', 'M', 'M', '0', 0,
  /* 82 */ 'Z', 'M', 'M', '0', 0,
  /* 87 */ 'F', 'P', '0', 0,
  /* 91 */ 'C', 'R', '0', 0,
  /* 95 */ 'D', 'R', '0', 0,
  /* 99 */ 'S', 'T', '0', 0,
  /* 103 */ 'X', 'M', 'M', '1', '1', 0,
  /* 109 */ 'Y', 'M', 'M', '1', '1', 0,
  /* 115 */ 'Z', 'M', 'M', '1', '1', 0,
  /* 121 */ 'C', 'R', '1', '1', 0,
  /* 126 */ 'D', 'R', '1', '1', 0,
  /* 131 */ 'X', 'M', 'M', '2', '1', 0,
  /* 137 */ 'Y', 'M', 'M', '2', '1', 0,
  /* 143 */ 'Z', 'M', 'M', '2', '1', 0,
  /* 149 */ 'X', 'M', 'M', '3', '1', 0,
  /* 155 */ 'Y', 'M', 'M', '3', '1', 0,
  /* 161 */ 'Z', 'M', 'M', '3', '1', 0,
  /* 167 */ 'B', 'N', 'D', '1', 0,
  /* 172 */ 'K', '0', '_', 'K', '1', 0,
  /* 178 */ 'X', 'M', 'M', '1', 0,
  /* 183 */ 'Y', 'M', 'M', '1', 0,
  /* 188 */ 'Z', 'M', 'M', '1', 0,
  /* 193 */ 'F', 'P', '1', 0,
  /* 197 */ 'C', 'R', '1', 0,
  /* 201 */ 'D', 'R', '1', 0,
  /* 205 */ 'S', 'T', '1', 0,
  /* 209 */ 'X', 'M', 'M', '1', '2', 0,
  /* 215 */ 'Y', 'M', 'M', '1', '2', 0,
  /* 221 */ 'Z', 'M', 'M', '1', '2', 0,
  /* 227 */ 'C', 'R', '1', '2', 0,
  /* 232 */ 'D', 'R', '1', '2', 0,
  /* 237 */ 'X', 'M', 'M', '2', '2', 0,
  /* 243 */ 'Y', 'M', 'M', '2', '2', 0,
  /* 249 */ 'Z', 'M', 'M', '2', '2', 0,
  /* 255 */ 'B', 'N', 'D', '2', 0,
  /* 260 */ 'K', '2', 0,
  /* 263 */ 'X', 'M', 'M', '2', 0,
  /* 268 */ 'Y', 'M', 'M', '2', 0,
  /* 273 */ 'Z', 'M', 'M', '2', 0,
  /* 278 */ 'F', 'P', '2', 0,
  /* 282 */ 'C', 'R', '2', 0,
  /* 286 */ 'D', 'R', '2', 0,
  /* 290 */ 'S', 'T', '2', 0,
  /* 294 */ 'X', 'M', 'M', '1', '3', 0,
  /* 300 */ 'Y', 'M', 'M', '1', '3', 0,
  /* 306 */ 'Z', 'M', 'M', '1', '3', 0,
  /* 312 */ 'C', 'R', '1', '3', 0,
  /* 317 */ 'D', 'R', '1', '3', 0,
  /* 322 */ 'X', 'M', 'M', '2', '3', 0,
  /* 328 */ 'Y', 'M', 'M', '2', '3', 0,
  /* 334 */ 'Z', 'M', 'M', '2', '3', 0,
  /* 340 */ 'B', 'N', 'D', '3', 0,
  /* 345 */ 'K', '2', '_', 'K', '3', 0,
  /* 351 */ 'X', 'M', 'M', '3', 0,
  /* 356 */ 'Y', 'M', 'M', '3', 0,
  /* 361 */ 'Z', 'M', 'M', '3', 0,
  /* 366 */ 'F', 'P', '3', 0,
  /* 370 */ 'C', 'R', '3', 0,
  /* 374 */ 'D', 'R', '3', 0,
  /* 378 */ 'S', 'T', '3', 0,
  /* 382 */ 'X', 'M', 'M', '1', '4', 0,
  /* 388 */ 'Y', 'M', 'M', '1', '4', 0,
  /* 394 */ 'Z', 'M', 'M', '1', '4', 0,
  /* 400 */ 'C', 'R', '1', '4', 0,
  /* 405 */ 'D', 'R', '1', '4', 0,
  /* 410 */ 'X', 'M', 'M', '2', '4', 0,
  /* 416 */ 'Y', 'M', 'M', '2', '4', 0,
  /* 422 */ 'Z', 'M', 'M', '2', '4', 0,
  /* 428 */ 'K', '4', 0,
  /* 431 */ 'X', 'M', 'M', '4', 0,
  /* 436 */ 'Y', 'M', 'M', '4', 0,
  /* 441 */ 'Z', 'M', 'M', '4', 0,
  /* 446 */ 'F', 'P', '4', 0,
  /* 450 */ 'C', 'R', '4', 0,
  /* 454 */ 'D', 'R', '4', 0,
  /* 458 */ 'S', 'T', '4', 0,
  /* 462 */ 'X', 'M', 'M', '1', '5', 0,
  /* 468 */ 'Y', 'M', 'M', '1', '5', 0,
  /* 474 */ 'Z', 'M', 'M', '1', '5', 0,
  /* 480 */ 'C', 'R', '1', '5', 0,
  /* 485 */ 'D', 'R', '1', '5', 0,
  /* 490 */ 'X', 'M', 'M', '2', '5', 0,
  /* 496 */ 'Y', 'M', 'M', '2', '5', 0,
  /* 502 */ 'Z', 'M', 'M', '2', '5', 0,
  /* 508 */ 'K', '4', '_', 'K', '5', 0,
  /* 514 */ 'X', 'M', 'M', '5', 0,
  /* 519 */ 'Y', 'M', 'M', '5', 0,
  /* 524 */ 'Z', 'M', 'M', '5', 0,
  /* 529 */ 'F', 'P', '5', 0,
  /* 533 */ 'C', 'R', '5', 0,
  /* 537 */ 'D', 'R', '5', 0,
  /* 541 */ 'S', 'T', '5', 0,
  /* 545 */ 'X', 'M', 'M', '1', '6', 0,
  /* 551 */ 'Y', 'M', 'M', '1', '6', 0,
  /* 557 */ 'Z', 'M', 'M', '1', '6', 0,
  /* 563 */ 'X', 'M', 'M', '2', '6', 0,
  /* 569 */ 'Y', 'M', 'M', '2', '6', 0,
  /* 575 */ 'Z', 'M', 'M', '2', '6', 0,
  /* 581 */ 'K', '6', 0,
  /* 584 */ 'X', 'M', 'M', '6', 0,
  /* 589 */ 'Y', 'M', 'M', '6', 0,
  /* 594 */ 'Z', 'M', 'M', '6', 0,
  /* 599 */ 'F', 'P', '6', 0,
  /* 603 */ 'C', 'R', '6', 0,
  /* 607 */ 'D', 'R', '6', 0,
  /* 611 */ 'S', 'T', '6', 0,
  /* 615 */ 'X', 'M', 'M', '1', '7', 0,
  /* 621 */ 'Y', 'M', 'M', '1', '7', 0,
  /* 627 */ 'Z', 'M', 'M', '1', '7', 0,
  /* 633 */ 'X', 'M', 'M', '2', '7', 0,
  /* 639 */ 'Y', 'M', 'M', '2', '7', 0,
  /* 645 */ 'Z', 'M', 'M', '2', '7', 0,
  /* 651 */ 'K', '6', '_', 'K', '7', 0,
  /* 657 */ 'X', 'M', 'M', '7', 0,
  /* 662 */ 'Y', 'M', 'M', '7', 0,
  /* 667 */ 'Z', 'M', 'M', '7', 0,
  /* 672 */ 'F', 'P', '7', 0,
  /* 676 */ 'C', 'R', '7', 0,
  /* 680 */ 'D', 'R', '7', 0,
  /* 684 */ 'S', 'T', '7', 0,
  /* 688 */ 'X', 'M', 'M', '1', '8', 0,
  /* 694 */ 'Y', 'M', 'M', '1', '8', 0,
  /* 700 */ 'Z', 'M', 'M', '1', '8', 0,
  /* 706 */ 'X', 'M', 'M', '2', '8', 0,
  /* 712 */ 'Y', 'M', 'M', '2', '8', 0,
  /* 718 */ 'Z', 'M', 'M', '2', '8', 0,
  /* 724 */ 'X', 'M', 'M', '8', 0,
  /* 729 */ 'Y', 'M', 'M', '8', 0,
  /* 734 */ 'Z', 'M', 'M', '8', 0,
  /* 739 */ 'C', 'R', '8', 0,
  /* 743 */ 'D', 'R', '8', 0,
  /* 747 */ 'X', 'M', 'M', '1', '9', 0,
  /* 753 */ 'Y', 'M', 'M', '1', '9', 0,
  /* 759 */ 'Z', 'M', 'M', '1', '9', 0,
  /* 765 */ 'X', 'M', 'M', '2', '9', 0,
  /* 771 */ 'Y', 'M', 'M', '2', '9', 0,
  /* 777 */ 'Z', 'M', 'M', '2', '9', 0,
  /* 783 */ 'X', 'M', 'M', '9', 0,
  /* 788 */ 'Y', 'M', 'M', '9', 0,
  /* 793 */ 'Z', 'M', 'M', '9', 0,
  /* 798 */ 'C', 'R', '9', 0,
  /* 802 */ 'D', 'R', '9', 0,
  /* 806 */ 'R', '1', '0', 'B', 0,
  /* 811 */ 'R', '1', '1', 'B', 0,
  /* 816 */ 'R', '1', '2', 'B', 0,
  /* 821 */ 'R', '1', '3', 'B', 0,
  /* 826 */ 'R', '1', '4', 'B', 0,
  /* 831 */ 'R', '1', '5', 'B', 0,
  /* 836 */ 'R', '8', 'B', 0,
  /* 840 */ 'R', '9', 'B', 0,
  /* 844 */ 'R', '1', '0', 'D', 0,
  /* 849 */ 'R', '1', '1', 'D', 0,
  /* 854 */ 'R', '1', '2', 'D', 0,
  /* 859 */ 'R', '1', '3', 'D', 0,
  /* 864 */ 'R', '1', '4', 'D', 0,
  /* 869 */ 'R', '1', '5', 'D', 0,
  /* 874 */ 'R', '8', 'D', 0,
  /* 878 */ 'R', '9', 'D', 0,
  /* 882 */ 'D', 'F', 0,
  /* 885 */ 'A', 'H', 0,
  /* 888 */ 'R', '1', '0', 'B', 'H', 0,
  /* 894 */ 'R', '1', '1', 'B', 'H', 0,
  /* 900 */ 'R', '1', '2', 'B', 'H', 0,
  /* 906 */ 'R', '1', '3', 'B', 'H', 0,
  /* 912 */ 'R', '1', '4', 'B', 'H', 0,
  /* 918 */ 'R', '1', '5', 'B', 'H', 0,
  /* 924 */ 'R', '8', 'B', 'H', 0,
  /* 929 */ 'R', '9', 'B', 'H', 0,
  /* 934 */ 'C', 'H', 0,
  /* 937 */ 'D', 'H', 0,
  /* 940 */ 'D', 'I', 'H', 0,
  /* 944 */ 'S', 'I', 'H', 0,
  /* 948 */ 'B', 'P', 'H', 0,
  /* 952 */ 'S', 'P', 'H', 0,
  /* 956 */ 'R', '1', '0', 'W', 'H', 0,
  /* 962 */ 'R', '1', '1', 'W', 'H', 0,
  /* 968 */ 'R', '1', '2', 'W', 'H', 0,
  /* 974 */ 'R', '1', '3', 'W', 'H', 0,
  /* 980 */ 'R', '1', '4', 'W', 'H', 0,
  /* 986 */ 'R', '1', '5', 'W', 'H', 0,
  /* 992 */ 'R', '8', 'W', 'H', 0,
  /* 997 */ 'R', '9', 'W', 'H', 0,
  /* 1002 */ 'E', 'D', 'I', 0,
  /* 1006 */ 'H', 'D', 'I', 0,
  /* 1010 */ 'R', 'D', 'I', 0,
  /* 1014 */ 'E', 'S', 'I', 0,
  /* 1018 */ 'H', 'S', 'I', 0,
  /* 1022 */ 'R', 'S', 'I', 0,
  /* 1026 */ 'A', 'L', 0,
  /* 1029 */ 'B', 'L', 0,
  /* 1032 */ 'C', 'L', 0,
  /* 1035 */ 'D', 'L', 0,
  /* 1038 */ 'D', 'I', 'L', 0,
  /* 1042 */ 'S', 'I', 'L', 0,
  /* 1046 */ 'B', 'P', 'L', 0,
  /* 1050 */ 'S', 'P', 'L', 0,
  /* 1054 */ 'E', 'B', 'P', 0,
  /* 1058 */ 'H', 'B', 'P', 0,
  /* 1062 */ 'R', 'B', 'P', 0,
  /* 1066 */ 'E', 'I', 'P', 0,
  /* 1070 */ 'H', 'I', 'P', 0,
  /* 1074 */ 'R', 'I', 'P', 0,
  /* 1078 */ 'E', 'S', 'P', 0,
  /* 1082 */ 'H', 'S', 'P', 0,
  /* 1086 */ 'R', 'S', 'P', 0,
  /* 1090 */ 'S', 'S', 'P', 0,
  /* 1094 */ 'M', 'X', 'C', 'S', 'R', 0,
  /* 1100 */ 'C', 'S', 0,
  /* 1103 */ 'D', 'S', 0,
  /* 1106 */ 'E', 'S', 0,
  /* 1109 */ 'F', 'S', 0,
  /* 1112 */ 'E', 'F', 'L', 'A', 'G', 'S', 0,
  /* 1119 */ 'S', 'S', 0,
  /* 1122 */ 'R', '1', '0', 'W', 0,
  /* 1127 */ 'R', '1', '1', 'W', 0,
  /* 1132 */ 'R', '1', '2', 'W', 0,
  /* 1137 */ 'R', '1', '3', 'W', 0,
  /* 1142 */ 'R', '1', '4', 'W', 0,
  /* 1147 */ 'R', '1', '5', 'W', 0,
  /* 1152 */ 'R', '8', 'W', 0,
  /* 1156 */ 'R', '9', 'W', 0,
  /* 1160 */ 'F', 'P', 'C', 'W', 0,
  /* 1165 */ 'F', 'P', 'S', 'W', 0,
  /* 1170 */ 'E', 'A', 'X', 0,
  /* 1174 */ 'H', 'A', 'X', 0,
  /* 1178 */ 'R', 'A', 'X', 0,
  /* 1182 */ 'E', 'B', 'X', 0,
  /* 1186 */ 'H', 'B', 'X', 0,
  /* 1190 */ 'R', 'B', 'X', 0,
  /* 1194 */ 'E', 'C', 'X', 0,
  /* 1198 */ 'H', 'C', 'X', 0,
  /* 1202 */ 'R', 'C', 'X', 0,
  /* 1206 */ 'E', 'D', 'X', 0,
  /* 1210 */ 'H', 'D', 'X', 0,
  /* 1214 */ 'R', 'D', 'X', 0,
  /* 1218 */ 'E', 'I', 'Z', 0,
  /* 1222 */ 'R', 'I', 'Z', 0,
};

extern const MCRegisterDesc X86RegDesc[] = { // Descriptors
  { 5, 0, 0, 0, 0, 0 },
  { 885, 2, 197, 2, 5041, 0 },
  { 1026, 2, 193, 2, 5041, 0 },
  { 1171, 323, 194, 0, 0, 2 },
  { 891, 2, 181, 2, 4993, 0 },
  { 1029, 2, 177, 2, 4993, 0 },
  { 1055, 314, 186, 3, 352, 5 },
  { 948, 2, 189, 2, 1008, 0 },
  { 1046, 2, 185, 2, 976, 0 },
  { 1183, 317, 178, 0, 304, 2 },
  { 934, 2, 173, 2, 4897, 0 },
  { 1032, 2, 169, 2, 4897, 0 },
  { 1100, 2, 2, 2, 4897, 0 },
  { 1195, 320, 170, 0, 400, 2 },
  { 882, 2, 2, 2, 4849, 0 },
  { 937, 2, 157, 2, 4849, 0 },
  { 1003, 314, 162, 3, 448, 5 },
  { 940, 2, 165, 2, 1536, 0 },
  { 1038, 2, 161, 2, 4530, 0 },
  { 1035, 2, 153, 2, 4817, 0 },
  { 1103, 2, 2, 2, 4817, 0 },
  { 1207, 305, 154, 0, 928, 2 },
  { 1170, 234, 155, 7, 1764, 8 },
  { 1054, 222, 155, 13, 1476, 12 },
  { 1182, 228, 155, 7, 1700, 8 },
  { 1194, 213, 155, 7, 1412, 8 },
  { 1002, 142, 155, 13, 1109, 12 },
  { 1206, 205, 155, 7, 1168, 8 },
  { 1112, 2, 2, 2, 1824, 0 },
  { 1066, 309, 148, 19, 496, 16 },
  { 1218, 2, 2, 2, 4817, 0 },
  { 1106, 2, 2, 2, 4817, 0 },
  { 1014, 294, 124, 13, 243, 12 },
  { 1078, 288, 124, 13, 243, 12 },
  { 1160, 2, 2, 2, 4993, 0 },
  { 1165, 2, 2, 2, 4993, 0 },
  { 1109, 2, 2, 2, 4993, 0 },
  { 1116, 2, 2, 2, 4993, 0 },
  { 1174, 2, 201, 2, 4561, 0 },
  { 1058, 2, 201, 2, 4561, 0 },
  { 1186, 2, 201, 2, 4561, 0 },
  { 1198, 2, 201, 2, 4561, 0 },
  { 1006, 2, 201, 2, 4561, 0 },
  { 1210, 2, 201, 2, 4561, 0 },
  { 1070, 2, 150, 2, 4323, 0 },
  { 1018, 2, 138, 2, 4355, 0 },
  { 1082, 2, 138, 2, 4355, 0 },
  { 1067, 2, 147, 2, 4062, 0 },
  { 1094, 2, 2, 2, 4062, 0 },
  { 1178, 233, 2, 6, 1636, 8 },
  { 1062, 221, 2, 12, 1348, 12 },
  { 1190, 227, 2, 6, 1572, 8 },
  { 1202, 212, 2, 6, 1284, 8 },
  { 1010, 141, 2, 12, 1045, 12 },
  { 1214, 204, 2, 6, 1168, 8 },
  { 1074, 308, 2, 18, 496, 16 },
  { 1222, 2, 2, 2, 3792, 0 },
  { 1022, 293, 2, 12, 179, 12 },
  { 1086, 287, 2, 12, 179, 12 },
  { 1015, 314, 131, 3, 544, 5 },
  { 944, 2, 134, 2, 2480, 0 },
  { 1042, 2, 130, 2, 2368, 0 },
  { 1079, 314, 123, 3, 592, 5 },
  { 952, 2, 126, 2, 3360, 0 },
  { 1050, 2, 122, 2, 4121, 0 },
  { 1119, 2, 2, 2, 4497, 0 },
  { 1090, 2, 2, 2, 4497, 0 },
  { 64, 2, 2, 2, 4497, 0 },
  { 167, 2, 2, 2, 4497, 0 },
  { 255, 2, 2, 2, 4497, 0 },
  { 340, 2, 2, 2, 4497, 0 },
  { 91, 2, 2, 2, 4497, 0 },
  { 197, 2, 2, 2, 4497, 0 },
  { 282, 2, 2, 2, 4497, 0 },
  { 370, 2, 2, 2, 4497, 0 },
  { 450, 2, 2, 2, 4497, 0 },
  { 533, 2, 2, 2, 4497, 0 },
  { 603, 2, 2, 2, 4497, 0 },
  { 676, 2, 2, 2, 4497, 0 },
  { 739, 2, 2, 2, 4497, 0 },
  { 798, 2, 2, 2, 4497, 0 },
  { 18, 2, 2, 2, 4497, 0 },
  { 121, 2, 2, 2, 4497, 0 },
  { 227, 2, 2, 2, 4497, 0 },
  { 312, 2, 2, 2, 4497, 0 },
  { 400, 2, 2, 2, 4497, 0 },
  { 480, 2, 2, 2, 4497, 0 },
  { 95, 2, 2, 2, 4497, 0 },
  { 201, 2, 2, 2, 4497, 0 },
  { 286, 2, 2, 2, 4497, 0 },
  { 374, 2, 2, 2, 4497, 0 },
  { 454, 2, 2, 2, 4497, 0 },
  { 537, 2, 2, 2, 4497, 0 },
  { 607, 2, 2, 2, 4497, 0 },
  { 680, 2, 2, 2, 4497, 0 },
  { 743, 2, 2, 2, 4497, 0 },
  { 802, 2, 2, 2, 4497, 0 },
  { 23, 2, 2, 2, 4497, 0 },
  { 126, 2, 2, 2, 4497, 0 },
  { 232, 2, 2, 2, 4497, 0 },
  { 317, 2, 2, 2, 4497, 0 },
  { 405, 2, 2, 2, 4497, 0 },
  { 485, 2, 2, 2, 4497, 0 },
  { 87, 2, 2, 2, 4497, 0 },
  { 193, 2, 2, 2, 4497, 0 },
  { 278, 2, 2, 2, 4497, 0 },
  { 366, 2, 2, 2, 4497, 0 },
  { 446, 2, 2, 2, 4497, 0 },
  { 529, 2, 2, 2, 4497, 0 },
  { 599, 2, 2, 2, 4497, 0 },
  { 672, 2, 2, 2, 4497, 0 },
  { 69, 2, 247, 2, 4497, 0 },
  { 175, 2, 245, 2, 4497, 0 },
  { 260, 2, 245, 2, 4497, 0 },
  { 348, 2, 243, 2, 4497, 0 },
  { 428, 2, 243, 2, 4497, 0 },
  { 511, 2, 241, 2, 4497, 0 },
  { 581, 2, 241, 2, 4497, 0 },
  { 654, 2, 239, 2, 4497, 0 },
  { 73, 2, 2, 2, 4497, 0 },
  { 179, 2, 2, 2, 4497, 0 },
  { 264, 2, 2, 2, 4497, 0 },
  { 352, 2, 2, 2, 4497, 0 },
  { 432, 2, 2, 2, 4497, 0 },
  { 515, 2, 2, 2, 4497, 0 },
  { 585, 2, 2, 2, 4497, 0 },
  { 658, 2, 2, 2, 4497, 0 },
  { 740, 116, 2, 12, 115, 12 },
  { 799, 116, 2, 12, 115, 12 },
  { 19, 116, 2, 12, 115, 12 },
  { 122, 116, 2, 12, 115, 12 },
  { 228, 116, 2, 12, 115, 12 },
  { 313, 116, 2, 12, 115, 12 },
  { 401, 116, 2, 12, 115, 12 },
  { 481, 116, 2, 12, 115, 12 },
  { 99, 2, 2, 2, 4785, 0 },
  { 205, 2, 2, 2, 4785, 0 },
  { 290, 2, 2, 2, 4785, 0 },
  { 378, 2, 2, 2, 4785, 0 },
  { 458, 2, 2, 2, 4785, 0 },
  { 541, 2, 2, 2, 4785, 0 },
  { 611, 2, 2, 2, 4785, 0 },
  { 684, 2, 2, 2, 4785, 0 },
  { 72, 2, 218, 2, 4785, 0 },
  { 178, 2, 218, 2, 4785, 0 },
  { 263, 2, 218, 2, 4785, 0 },
  { 351, 2, 218, 2, 4785, 0 },
  { 431, 2, 218, 2, 4785, 0 },
  { 514, 2, 218, 2, 4785, 0 },
  { 584, 2, 218, 2, 4785, 0 },
  { 657, 2, 218, 2, 4785, 0 },
  { 724, 2, 218, 2, 4785, 0 },
  { 783, 2, 218, 2, 4785, 0 },
  { 0, 2, 218, 2, 4785, 0 },
  { 103, 2, 218, 2, 4785, 0 },
  { 209, 2, 218, 2, 4785, 0 },
  { 294, 2, 218, 2, 4785, 0 },
  { 382, 2, 218, 2, 4785, 0 },
  { 462, 2, 218, 2, 4785, 0 },
  { 545, 2, 218, 2, 4785, 0 },
  { 615, 2, 218, 2, 4785, 0 },
  { 688, 2, 218, 2, 4785, 0 },
  { 747, 2, 218, 2, 4785, 0 },
  { 28, 2, 218, 2, 4785, 0 },
  { 131, 2, 218, 2, 4785, 0 },
  { 237, 2, 218, 2, 4785, 0 },
  { 322, 2, 218, 2, 4785, 0 },
  { 410, 2, 218, 2, 4785, 0 },
  { 490, 2, 218, 2, 4785, 0 },
  { 563, 2, 218, 2, 4785, 0 },
  { 633, 2, 218, 2, 4785, 0 },
  { 706, 2, 218, 2, 4785, 0 },
  { 765, 2, 218, 2, 4785, 0 },
  { 46, 2, 218, 2, 4785, 0 },
  { 149, 2, 218, 2, 4785, 0 },
  { 77, 279, 219, 26, 4417, 22 },
  { 183, 279, 219, 26, 4417, 22 },
  { 268, 279, 219, 26, 4417, 22 },
  { 356, 279, 219, 26, 4417, 22 },
  { 436, 279, 219, 26, 4417, 22 },
  { 519, 279, 219, 26, 4417, 22 },
  { 589, 279, 219, 26, 4417, 22 },
  { 662, 279, 219, 26, 4417, 22 },
  { 729, 279, 219, 26, 4417, 22 },
  { 788, 279, 219, 26, 4417, 22 },
  { 6, 279, 219, 26, 4417, 22 },
  { 109, 279, 219, 26, 4417, 22 },
  { 215, 279, 219, 26, 4417, 22 },
  { 300, 279, 219, 26, 4417, 22 },
  { 388, 279, 219, 26, 4417, 22 },
  { 468, 279, 219, 26, 4417, 22 },
  { 551, 279, 219, 26, 4417, 22 },
  { 621, 279, 219, 26, 4417, 22 },
  { 694, 279, 219, 26, 4417, 22 },
  { 753, 279, 219, 26, 4417, 22 },
  { 34, 279, 219, 26, 4417, 22 },
  { 137, 279, 219, 26, 4417, 22 },
  { 243, 279, 219, 26, 4417, 22 },
  { 328, 279, 219, 26, 4417, 22 },
  { 416, 279, 219, 26, 4417, 22 },
  { 496, 279, 219, 26, 4417, 22 },
  { 569, 279, 219, 26, 4417, 22 },
  { 639, 279, 219, 26, 4417, 22 },
  { 712, 279, 219, 26, 4417, 22 },
  { 771, 279, 219, 26, 4417, 22 },
  { 52, 279, 219, 26, 4417, 22 },
  { 155, 279, 219, 26, 4417, 22 },
  { 82, 278, 2, 25, 4385, 22 },
  { 188, 278, 2, 25, 4385, 22 },
  { 273, 278, 2, 25, 4385, 22 },
  { 361, 278, 2, 25, 4385, 22 },
  { 441, 278, 2, 25, 4385, 22 },
  { 524, 278, 2, 25, 4385, 22 },
  { 594, 278, 2, 25, 4385, 22 },
  { 667, 278, 2, 25, 4385, 22 },
  { 734, 278, 2, 25, 4385, 22 },
  { 793, 278, 2, 25, 4385, 22 },
  { 12, 278, 2, 25, 4385, 22 },
  { 115, 278, 2, 25, 4385, 22 },
  { 221, 278, 2, 25, 4385, 22 },
  { 306, 278, 2, 25, 4385, 22 },
  { 394, 278, 2, 25, 4385, 22 },
  { 474, 278, 2, 25, 4385, 22 },
  { 557, 278, 2, 25, 4385, 22 },
  { 627, 278, 2, 25, 4385, 22 },
  { 700, 278, 2, 25, 4385, 22 },
  { 759, 278, 2, 25, 4385, 22 },
  { 40, 278, 2, 25, 4385, 22 },
  { 143, 278, 2, 25, 4385, 22 },
  { 249, 278, 2, 25, 4385, 22 },
  { 334, 278, 2, 25, 4385, 22 },
  { 422, 278, 2, 25, 4385, 22 },
  { 502, 278, 2, 25, 4385, 22 },
  { 575, 278, 2, 25, 4385, 22 },
  { 645, 278, 2, 25, 4385, 22 },
  { 718, 278, 2, 25, 4385, 22 },
  { 777, 278, 2, 25, 4385, 22 },
  { 58, 278, 2, 25, 4385, 22 },
  { 161, 278, 2, 25, 4385, 22 },
  { 836, 2, 266, 2, 4083, 0 },
  { 840, 2, 266, 2, 4083, 0 },
  { 806, 2, 266, 2, 4083, 0 },
  { 811, 2, 266, 2, 4083, 0 },
  { 816, 2, 266, 2, 4083, 0 },
  { 821, 2, 266, 2, 4083, 0 },
  { 826, 2, 266, 2, 4083, 0 },
  { 831, 2, 266, 2, 4083, 0 },
  { 924, 2, 262, 2, 4019, 0 },
  { 929, 2, 262, 2, 4019, 0 },
  { 888, 2, 262, 2, 4019, 0 },
  { 894, 2, 262, 2, 4019, 0 },
  { 900, 2, 262, 2, 4019, 0 },
  { 906, 2, 262, 2, 4019, 0 },
  { 912, 2, 262, 2, 4019, 0 },
  { 918, 2, 262, 2, 4019, 0 },
  { 874, 117, 260, 13, 51, 12 },
  { 878, 117, 260, 13, 51, 12 },
  { 844, 117, 260, 13, 51, 12 },
  { 849, 117, 260, 13, 51, 12 },
  { 854, 117, 260, 13, 51, 12 },
  { 859, 117, 260, 13, 51, 12 },
  { 864, 117, 260, 13, 51, 12 },
  { 869, 117, 260, 13, 51, 12 },
  { 1152, 77, 263, 3, 643, 5 },
  { 1156, 77, 263, 3, 643, 5 },
  { 1122, 77, 263, 3, 643, 5 },
  { 1127, 77, 263, 3, 643, 5 },
  { 1132, 77, 263, 3, 643, 5 },
  { 1137, 77, 263, 3, 643, 5 },
  { 1142, 77, 263, 3, 643, 5 },
  { 1147, 77, 263, 3, 643, 5 },
  { 992, 2, 259, 2, 3987, 0 },
  { 997, 2, 259, 2, 3987, 0 },
  { 956, 2, 259, 2, 3987, 0 },
  { 962, 2, 259, 2, 3987, 0 },
  { 968, 2, 259, 2, 3987, 0 },
  { 974, 2, 259, 2, 3987, 0 },
  { 980, 2, 259, 2, 3987, 0 },
  { 986, 2, 259, 2, 3987, 0 },
  { 172, 46, 2, 22, 690, 19 },
  { 345, 49, 2, 22, 690, 19 },
  { 508, 52, 2, 22, 690, 19 },
  { 651, 55, 2, 22, 690, 19 },
};

extern const MCPhysReg X86RegUnitRoots[][2] = {
  { X86::AH },
  { X86::AL },
  { X86::BH },
  { X86::BL },
  { X86::BPL },
  { X86::BPH },
  { X86::CH },
  { X86::CL },
  { X86::CS },
  { X86::DF },
  { X86::DH },
  { X86::DIL },
  { X86::DIH },
  { X86::DL },
  { X86::DS },
  { X86::HAX },
  { X86::HBP },
  { X86::HBX },
  { X86::HCX },
  { X86::HDI },
  { X86::HDX },
  { X86::EFLAGS },
  { X86::IP },
  { X86::HIP },
  { X86::EIZ },
  { X86::ES },
  { X86::SIL },
  { X86::SIH },
  { X86::HSI },
  { X86::SPL },
  { X86::SPH },
  { X86::HSP },
  { X86::FPCW },
  { X86::FPSW },
  { X86::FS },
  { X86::GS },
  { X86::MXCSR },
  { X86::RIZ },
  { X86::SS },
  { X86::SSP },
  { X86::BND0 },
  { X86::BND1 },
  { X86::BND2 },
  { X86::BND3 },
  { X86::CR0 },
  { X86::CR1 },
  { X86::CR2 },
  { X86::CR3 },
  { X86::CR4 },
  { X86::CR5 },
  { X86::CR6 },
  { X86::CR7 },
  { X86::CR8 },
  { X86::CR9 },
  { X86::CR10 },
  { X86::CR11 },
  { X86::CR12 },
  { X86::CR13 },
  { X86::CR14 },
  { X86::CR15 },
  { X86::DR0 },
  { X86::DR1 },
  { X86::DR2 },
  { X86::DR3 },
  { X86::DR4 },
  { X86::DR5 },
  { X86::DR6 },
  { X86::DR7 },
  { X86::DR8 },
  { X86::DR9 },
  { X86::DR10 },
  { X86::DR11 },
  { X86::DR12 },
  { X86::DR13 },
  { X86::DR14 },
  { X86::DR15 },
  { X86::FP0 },
  { X86::FP1 },
  { X86::FP2 },
  { X86::FP3 },
  { X86::FP4 },
  { X86::FP5 },
  { X86::FP6 },
  { X86::FP7 },
  { X86::K0 },
  { X86::K1 },
  { X86::K2 },
  { X86::K3 },
  { X86::K4 },
  { X86::K5 },
  { X86::K6 },
  { X86::K7 },
  { X86::MM0 },
  { X86::MM1 },
  { X86::MM2 },
  { X86::MM3 },
  { X86::MM4 },
  { X86::MM5 },
  { X86::MM6 },
  { X86::MM7 },
  { X86::R8B },
  { X86::R8BH },
  { X86::R8WH },
  { X86::R9B },
  { X86::R9BH },
  { X86::R9WH },
  { X86::R10B },
  { X86::R10BH },
  { X86::R10WH },
  { X86::R11B },
  { X86::R11BH },
  { X86::R11WH },
  { X86::R12B },
  { X86::R12BH },
  { X86::R12WH },
  { X86::R13B },
  { X86::R13BH },
  { X86::R13WH },
  { X86::R14B },
  { X86::R14BH },
  { X86::R14WH },
  { X86::R15B },
  { X86::R15BH },
  { X86::R15WH },
  { X86::ST0 },
  { X86::ST1 },
  { X86::ST2 },
  { X86::ST3 },
  { X86::ST4 },
  { X86::ST5 },
  { X86::ST6 },
  { X86::ST7 },
  { X86::XMM0 },
  { X86::XMM1 },
  { X86::XMM2 },
  { X86::XMM3 },
  { X86::XMM4 },
  { X86::XMM5 },
  { X86::XMM6 },
  { X86::XMM7 },
  { X86::XMM8 },
  { X86::XMM9 },
  { X86::XMM10 },
  { X86::XMM11 },
  { X86::XMM12 },
  { X86::XMM13 },
  { X86::XMM14 },
  { X86::XMM15 },
  { X86::XMM16 },
  { X86::XMM17 },
  { X86::XMM18 },
  { X86::XMM19 },
  { X86::XMM20 },
  { X86::XMM21 },
  { X86::XMM22 },
  { X86::XMM23 },
  { X86::XMM24 },
  { X86::XMM25 },
  { X86::XMM26 },
  { X86::XMM27 },
  { X86::XMM28 },
  { X86::XMM29 },
  { X86::XMM30 },
  { X86::XMM31 },
};

namespace {     // Register classes...
  // GR8 Register Class...
  const MCPhysReg GR8[] = {
    X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B, 
  };

  // GR8 Bit set.
  const uint8_t GR8Bits[] = {
    0x36, 0x8d, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x20, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
  };

  // GRH8 Register Class...
  const MCPhysReg GRH8[] = {
    X86::SIH, X86::DIH, X86::BPH, X86::SPH, X86::R8BH, X86::R9BH, X86::R10BH, X86::R11BH, X86::R12BH, X86::R13BH, X86::R14BH, X86::R15BH, 
  };

  // GRH8 Bit set.
  const uint8_t GRH8Bits[] = {
    0x80, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
  };

  // GR8_NOREX Register Class...
  const MCPhysReg GR8_NOREX[] = {
    X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, 
  };

  // GR8_NOREX Bit set.
  const uint8_t GR8_NOREXBits[] = {
    0x36, 0x8c, 0x08, 
  };

  // GR8_ABCD_H Register Class...
  const MCPhysReg GR8_ABCD_H[] = {
    X86::AH, X86::CH, X86::DH, X86::BH, 
  };

  // GR8_ABCD_H Bit set.
  const uint8_t GR8_ABCD_HBits[] = {
    0x12, 0x84, 
  };

  // GR8_ABCD_L Register Class...
  const MCPhysReg GR8_ABCD_L[] = {
    X86::AL, X86::CL, X86::DL, X86::BL, 
  };

  // GR8_ABCD_L Bit set.
  const uint8_t GR8_ABCD_LBits[] = {
    0x24, 0x08, 0x08, 
  };

  // GRH16 Register Class...
  const MCPhysReg GRH16[] = {
    X86::HAX, X86::HCX, X86::HDX, X86::HSI, X86::HDI, X86::HBX, X86::HBP, X86::HSP, X86::HIP, X86::R8WH, X86::R9WH, X86::R10WH, X86::R11WH, X86::R12WH, X86::R13WH, X86::R14WH, X86::R15WH, 
  };

  // GRH16 Bit set.
  const uint8_t GRH16Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0xc0, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
  };

  // GR16 Register Class...
  const MCPhysReg GR16[] = {
    X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R14W, X86::R15W, X86::R12W, X86::R13W, 
  };

  // GR16 Bit set.
  const uint8_t GR16Bits[] = {
    0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
  };

  // GR16_NOREX Register Class...
  const MCPhysReg GR16_NOREX[] = {
    X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, 
  };

  // GR16_NOREX Bit set.
  const uint8_t GR16_NOREXBits[] = {
    0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x48, 
  };

  // VK1 Register Class...
  const MCPhysReg VK1[] = {
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
  };

  // VK1 Bit set.
  const uint8_t VK1Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
  };

  // VK16 Register Class...
  const MCPhysReg VK16[] = {
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
  };

  // VK16 Bit set.
  const uint8_t VK16Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
  };

  // VK2 Register Class...
  const MCPhysReg VK2[] = {
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
  };

  // VK2 Bit set.
  const uint8_t VK2Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
  };

  // VK4 Register Class...
  const MCPhysReg VK4[] = {
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
  };

  // VK4 Bit set.
  const uint8_t VK4Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
  };

  // VK8 Register Class...
  const MCPhysReg VK8[] = {
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
  };

  // VK8 Bit set.
  const uint8_t VK8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
  };

  // VK16WM Register Class...
  const MCPhysReg VK16WM[] = {
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
  };

  // VK16WM Bit set.
  const uint8_t VK16WMBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 
  };

  // VK1WM Register Class...
  const MCPhysReg VK1WM[] = {
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
  };

  // VK1WM Bit set.
  const uint8_t VK1WMBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 
  };

  // VK2WM Register Class...
  const MCPhysReg VK2WM[] = {
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
  };

  // VK2WM Bit set.
  const uint8_t VK2WMBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 
  };

  // VK4WM Register Class...
  const MCPhysReg VK4WM[] = {
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
  };

  // VK4WM Bit set.
  const uint8_t VK4WMBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 
  };

  // VK8WM Register Class...
  const MCPhysReg VK8WM[] = {
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
  };

  // VK8WM Bit set.
  const uint8_t VK8WMBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 
  };

  // SEGMENT_REG Register Class...
  const MCPhysReg SEGMENT_REG[] = {
    X86::CS, X86::DS, X86::SS, X86::ES, X86::FS, X86::GS, 
  };

  // SEGMENT_REG Bit set.
  const uint8_t SEGMENT_REGBits[] = {
    0x00, 0x10, 0x10, 0x80, 0x30, 0x00, 0x00, 0x00, 0x02, 
  };

  // GR16_ABCD Register Class...
  const MCPhysReg GR16_ABCD[] = {
    X86::AX, X86::CX, X86::DX, X86::BX, 
  };

  // GR16_ABCD Bit set.
  const uint8_t GR16_ABCDBits[] = {
    0x08, 0x22, 0x20, 
  };

  // FPCCR Register Class...
  const MCPhysReg FPCCR[] = {
    X86::FPSW, 
  };

  // FPCCR Bit set.
  const uint8_t FPCCRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x08, 
  };

  // VK16PAIR Register Class...
  const MCPhysReg VK16PAIR[] = {
    X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7, 
  };

  // VK16PAIR Bit set.
  const uint8_t VK16PAIRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 
  };

  // VK1PAIR Register Class...
  const MCPhysReg VK1PAIR[] = {
    X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7, 
  };

  // VK1PAIR Bit set.
  const uint8_t VK1PAIRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 
  };

  // VK2PAIR Register Class...
  const MCPhysReg VK2PAIR[] = {
    X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7, 
  };

  // VK2PAIR Bit set.
  const uint8_t VK2PAIRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 
  };

  // VK4PAIR Register Class...
  const MCPhysReg VK4PAIR[] = {
    X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7, 
  };

  // VK4PAIR Bit set.
  const uint8_t VK4PAIRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 
  };

  // VK8PAIR Register Class...
  const MCPhysReg VK8PAIR[] = {
    X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7, 
  };

  // VK8PAIR Bit set.
  const uint8_t VK8PAIRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 
  };

  // VK16PAIR_with_sub_mask_0_in_VK16WM Register Class...
  const MCPhysReg VK16PAIR_with_sub_mask_0_in_VK16WM[] = {
    X86::K2_K3, X86::K4_K5, X86::K6_K7, 
  };

  // VK16PAIR_with_sub_mask_0_in_VK16WM Bit set.
  const uint8_t VK16PAIR_with_sub_mask_0_in_VK16WMBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 
  };

  // FR32X Register Class...
  const MCPhysReg FR32X[] = {
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, 
  };

  // FR32X Bit set.
  const uint8_t FR32XBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 
  };

  // LOW32_ADDR_ACCESS_RBP Register Class...
  const MCPhysReg LOW32_ADDR_ACCESS_RBP[] = {
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RIP, X86::RBP, 
  };

  // LOW32_ADDR_ACCESS_RBP Bit set.
  const uint8_t LOW32_ADDR_ACCESS_RBPBits[] = {
    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
  };

  // LOW32_ADDR_ACCESS Register Class...
  const MCPhysReg LOW32_ADDR_ACCESS[] = {
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RIP, 
  };

  // LOW32_ADDR_ACCESS Bit set.
  const uint8_t LOW32_ADDR_ACCESSBits[] = {
    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
  };

  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Register Class...
  const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit[] = {
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RBP, 
  };

  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit Bit set.
  const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits[] = {
    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
  };

  // DEBUG_REG Register Class...
  const MCPhysReg DEBUG_REG[] = {
    X86::DR0, X86::DR1, X86::DR2, X86::DR3, X86::DR4, X86::DR5, X86::DR6, X86::DR7, X86::DR8, X86::DR9, X86::DR10, X86::DR11, X86::DR12, X86::DR13, X86::DR14, X86::DR15, 
  };

  // DEBUG_REG Bit set.
  const uint8_t DEBUG_REGBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 
  };

  // FR32 Register Class...
  const MCPhysReg FR32[] = {
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 
  };

  // FR32 Bit set.
  const uint8_t FR32Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 
  };

  // GR32 Register Class...
  const MCPhysReg GR32[] = {
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, 
  };

  // GR32 Bit set.
  const uint8_t GR32Bits[] = {
    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
  };

  // GR32_NOSP Register Class...
  const MCPhysReg GR32_NOSP[] = {
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, 
  };

  // GR32_NOSP Bit set.
  const uint8_t GR32_NOSPBits[] = {
    0x00, 0x00, 0xc0, 0x0f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
  };

  // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Register Class...
  const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX[] = {
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::RBP, 
  };

  // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Bit set.
  const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits[] = {
    0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x04, 
  };

  // GR32_NOREX Register Class...
  const MCPhysReg GR32_NOREX[] = {
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, 
  };

  // GR32_NOREX Bit set.
  const uint8_t GR32_NOREXBits[] = {
    0x00, 0x00, 0xc0, 0x0f, 0x03, 
  };

  // VK32 Register Class...
  const MCPhysReg VK32[] = {
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
  };

  // VK32 Bit set.
  const uint8_t VK32Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
  };

  // GR32_NOREX_NOSP Register Class...
  const MCPhysReg GR32_NOREX_NOSP[] = {
    X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 
  };

  // GR32_NOREX_NOSP Bit set.
  const uint8_t GR32_NOREX_NOSPBits[] = {
    0x00, 0x00, 0xc0, 0x0f, 0x01, 
  };

  // RFP32 Register Class...
  const MCPhysReg RFP32[] = {
    X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 
  };

  // RFP32 Bit set.
  const uint8_t RFP32Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 
  };

  // VK32WM Register Class...
  const MCPhysReg VK32WM[] = {
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
  };

  // VK32WM Bit set.
  const uint8_t VK32WMBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 
  };

  // GR32_ABCD Register Class...
  const MCPhysReg GR32_ABCD[] = {
    X86::EAX, X86::ECX, X86::EDX, X86::EBX, 
  };

  // GR32_ABCD Bit set.
  const uint8_t GR32_ABCDBits[] = {
    0x00, 0x00, 0x40, 0x0b, 
  };

  // GR32_TC Register Class...
  const MCPhysReg GR32_TC[] = {
    X86::EAX, X86::ECX, X86::EDX, X86::ESP, 
  };

  // GR32_TC Bit set.
  const uint8_t GR32_TCBits[] = {
    0x00, 0x00, 0x40, 0x0a, 0x02, 
  };

  // GR32_ABCD_and_GR32_TC Register Class...
  const MCPhysReg GR32_ABCD_and_GR32_TC[] = {
    X86::EAX, X86::ECX, X86::EDX, 
  };

  // GR32_ABCD_and_GR32_TC Bit set.
  const uint8_t GR32_ABCD_and_GR32_TCBits[] = {
    0x00, 0x00, 0x40, 0x0a, 
  };

  // GR32_AD Register Class...
  const MCPhysReg GR32_AD[] = {
    X86::EAX, X86::EDX, 
  };

  // GR32_AD Bit set.
  const uint8_t GR32_ADBits[] = {
    0x00, 0x00, 0x40, 0x08, 
  };

  // GR32_BPSP Register Class...
  const MCPhysReg GR32_BPSP[] = {
    X86::EBP, X86::ESP, 
  };

  // GR32_BPSP Bit set.
  const uint8_t GR32_BPSPBits[] = {
    0x00, 0x00, 0x80, 0x00, 0x02, 
  };

  // GR32_BSI Register Class...
  const MCPhysReg GR32_BSI[] = {
    X86::EBX, X86::ESI, 
  };

  // GR32_BSI Bit set.
  const uint8_t GR32_BSIBits[] = {
    0x00, 0x00, 0x00, 0x01, 0x01, 
  };

  // GR32_CB Register Class...
  const MCPhysReg GR32_CB[] = {
    X86::ECX, X86::EBX, 
  };

  // GR32_CB Bit set.
  const uint8_t GR32_CBBits[] = {
    0x00, 0x00, 0x00, 0x03, 
  };

  // GR32_DC Register Class...
  const MCPhysReg GR32_DC[] = {
    X86::EDX, X86::ECX, 
  };

  // GR32_DC Bit set.
  const uint8_t GR32_DCBits[] = {
    0x00, 0x00, 0x00, 0x0a, 
  };

  // GR32_DIBP Register Class...
  const MCPhysReg GR32_DIBP[] = {
    X86::EDI, X86::EBP, 
  };

  // GR32_DIBP Bit set.
  const uint8_t GR32_DIBPBits[] = {
    0x00, 0x00, 0x80, 0x04, 
  };

  // GR32_SIDI Register Class...
  const MCPhysReg GR32_SIDI[] = {
    X86::ESI, X86::EDI, 
  };

  // GR32_SIDI Bit set.
  const uint8_t GR32_SIDIBits[] = {
    0x00, 0x00, 0x00, 0x04, 0x01, 
  };

  // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Register Class...
  const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_32bit[] = {
    X86::RIP, X86::RBP, 
  };

  // LOW32_ADDR_ACCESS_RBP_with_sub_32bit Bit set.
  const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 
  };

  // CCR Register Class...
  const MCPhysReg CCR[] = {
    X86::EFLAGS, 
  };

  // CCR Bit set.
  const uint8_t CCRBits[] = {
    0x00, 0x00, 0x00, 0x10, 
  };

  // DFCCR Register Class...
  const MCPhysReg DFCCR[] = {
    X86::DF, 
  };

  // DFCCR Bit set.
  const uint8_t DFCCRBits[] = {
    0x00, 0x40, 
  };

  // GR32_ABCD_and_GR32_BSI Register Class...
  const MCPhysReg GR32_ABCD_and_GR32_BSI[] = {
    X86::EBX, 
  };

  // GR32_ABCD_and_GR32_BSI Bit set.
  const uint8_t GR32_ABCD_and_GR32_BSIBits[] = {
    0x00, 0x00, 0x00, 0x01, 
  };

  // GR32_AD_and_GR32_DC Register Class...
  const MCPhysReg GR32_AD_and_GR32_DC[] = {
    X86::EDX, 
  };

  // GR32_AD_and_GR32_DC Bit set.
  const uint8_t GR32_AD_and_GR32_DCBits[] = {
    0x00, 0x00, 0x00, 0x08, 
  };

  // GR32_BPSP_and_GR32_DIBP Register Class...
  const MCPhysReg GR32_BPSP_and_GR32_DIBP[] = {
    X86::EBP, 
  };

  // GR32_BPSP_and_GR32_DIBP Bit set.
  const uint8_t GR32_BPSP_and_GR32_DIBPBits[] = {
    0x00, 0x00, 0x80, 
  };

  // GR32_BPSP_and_GR32_TC Register Class...
  const MCPhysReg GR32_BPSP_and_GR32_TC[] = {
    X86::ESP, 
  };

  // GR32_BPSP_and_GR32_TC Bit set.
  const uint8_t GR32_BPSP_and_GR32_TCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x02, 
  };

  // GR32_BSI_and_GR32_SIDI Register Class...
  const MCPhysReg GR32_BSI_and_GR32_SIDI[] = {
    X86::ESI, 
  };

  // GR32_BSI_and_GR32_SIDI Bit set.
  const uint8_t GR32_BSI_and_GR32_SIDIBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x01, 
  };

  // GR32_CB_and_GR32_DC Register Class...
  const MCPhysReg GR32_CB_and_GR32_DC[] = {
    X86::ECX, 
  };

  // GR32_CB_and_GR32_DC Bit set.
  const uint8_t GR32_CB_and_GR32_DCBits[] = {
    0x00, 0x00, 0x00, 0x02, 
  };

  // GR32_DIBP_and_GR32_SIDI Register Class...
  const MCPhysReg GR32_DIBP_and_GR32_SIDI[] = {
    X86::EDI, 
  };

  // GR32_DIBP_and_GR32_SIDI Bit set.
  const uint8_t GR32_DIBP_and_GR32_SIDIBits[] = {
    0x00, 0x00, 0x00, 0x04, 
  };

  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Register Class...
  const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit[] = {
    X86::RBP, 
  };

  // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Bit set.
  const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 
  };

  // LOW32_ADDR_ACCESS_with_sub_32bit Register Class...
  const MCPhysReg LOW32_ADDR_ACCESS_with_sub_32bit[] = {
    X86::RIP, 
  };

  // LOW32_ADDR_ACCESS_with_sub_32bit Bit set.
  const uint8_t LOW32_ADDR_ACCESS_with_sub_32bitBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 
  };

  // RFP64 Register Class...
  const MCPhysReg RFP64[] = {
    X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 
  };

  // RFP64 Bit set.
  const uint8_t RFP64Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 
  };

  // FR64X Register Class...
  const MCPhysReg FR64X[] = {
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, 
  };

  // FR64X Bit set.
  const uint8_t FR64XBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 
  };

  // GR64 Register Class...
  const MCPhysReg GR64[] = {
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, X86::RIP, 
  };

  // GR64 Bit set.
  const uint8_t GR64Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
  };

  // CONTROL_REG Register Class...
  const MCPhysReg CONTROL_REG[] = {
    X86::CR0, X86::CR1, X86::CR2, X86::CR3, X86::CR4, X86::CR5, X86::CR6, X86::CR7, X86::CR8, X86::CR9, X86::CR10, X86::CR11, X86::CR12, X86::CR13, X86::CR14, X86::CR15, 
  };

  // CONTROL_REG Bit set.
  const uint8_t CONTROL_REGBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 
  };

  // FR64 Register Class...
  const MCPhysReg FR64[] = {
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 
  };

  // FR64 Bit set.
  const uint8_t FR64Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 
  };

  // GR64_with_sub_8bit Register Class...
  const MCPhysReg GR64_with_sub_8bit[] = {
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, 
  };

  // GR64_with_sub_8bit Bit set.
  const uint8_t GR64_with_sub_8bitBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
  };

  // GR64_NOSP Register Class...
  const MCPhysReg GR64_NOSP[] = {
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, 
  };

  // GR64_NOSP Bit set.
  const uint8_t GR64_NOSPBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
  };

  // GR64_TC Register Class...
  const MCPhysReg GR64_TC[] = {
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP, 
  };

  // GR64_TC Bit set.
  const uint8_t GR64_TCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf2, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05, 
  };

  // GR64_NOREX Register Class...
  const MCPhysReg GR64_NOREX[] = {
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, X86::RIP, 
  };

  // GR64_NOREX Bit set.
  const uint8_t GR64_NOREXBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x06, 
  };

  // GR64_TCW64 Register Class...
  const MCPhysReg GR64_TCW64[] = {
    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RIP, X86::RSP, 
  };

  // GR64_TCW64 Bit set.
  const uint8_t GR64_TCW64Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd2, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 
  };

  // GR64_TC_with_sub_8bit Register Class...
  const MCPhysReg GR64_TC_with_sub_8bit[] = {
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RSP, 
  };

  // GR64_TC_with_sub_8bit Bit set.
  const uint8_t GR64_TC_with_sub_8bitBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x72, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05, 
  };

  // GR64_NOSP_and_GR64_TC Register Class...
  const MCPhysReg GR64_NOSP_and_GR64_TC[] = {
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, 
  };

  // GR64_NOSP_and_GR64_TC Bit set.
  const uint8_t GR64_NOSP_and_GR64_TCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x72, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05, 
  };

  // GR64_TCW64_with_sub_8bit Register Class...
  const MCPhysReg GR64_TCW64_with_sub_8bit[] = {
    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RSP, 
  };

  // GR64_TCW64_with_sub_8bit Bit set.
  const uint8_t GR64_TCW64_with_sub_8bitBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x52, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 
  };

  // GR64_TC_and_GR64_TCW64 Register Class...
  const MCPhysReg GR64_TC_and_GR64_TCW64[] = {
    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP, 
  };

  // GR64_TC_and_GR64_TCW64 Bit set.
  const uint8_t GR64_TC_and_GR64_TCW64Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd2, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05, 
  };

  // GR64_with_sub_16bit_in_GR16_NOREX Register Class...
  const MCPhysReg GR64_with_sub_16bit_in_GR16_NOREX[] = {
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, 
  };

  // GR64_with_sub_16bit_in_GR16_NOREX Bit set.
  const uint8_t GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 0x06, 
  };

  // VK64 Register Class...
  const MCPhysReg VK64[] = {
    X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
  };

  // VK64 Bit set.
  const uint8_t VK64Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
  };

  // VR64 Register Class...
  const MCPhysReg VR64[] = {
    X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7, 
  };

  // VR64 Bit set.
  const uint8_t VR64Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
  };

  // GR64_NOREX_NOSP Register Class...
  const MCPhysReg GR64_NOREX_NOSP[] = {
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, 
  };

  // GR64_NOREX_NOSP Bit set.
  const uint8_t GR64_NOREX_NOSPBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7e, 0x02, 
  };

  // GR64_NOREX_and_GR64_TC Register Class...
  const MCPhysReg GR64_NOREX_and_GR64_TC[] = {
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP, X86::RIP, 
  };

  // GR64_NOREX_and_GR64_TC Bit set.
  const uint8_t GR64_NOREX_and_GR64_TCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf2, 0x06, 
  };

  // GR64_NOSP_and_GR64_TCW64 Register Class...
  const MCPhysReg GR64_NOSP_and_GR64_TCW64[] = {
    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, 
  };

  // GR64_NOSP_and_GR64_TCW64 Bit set.
  const uint8_t GR64_NOSP_and_GR64_TCW64Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 
  };

  // GR64_TCW64_and_GR64_TC_with_sub_8bit Register Class...
  const MCPhysReg GR64_TCW64_and_GR64_TC_with_sub_8bit[] = {
    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RSP, 
  };

  // GR64_TCW64_and_GR64_TC_with_sub_8bit Bit set.
  const uint8_t GR64_TCW64_and_GR64_TC_with_sub_8bitBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x52, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05, 
  };

  // VK64WM Register Class...
  const MCPhysReg VK64WM[] = {
    X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 
  };

  // VK64WM Bit set.
  const uint8_t VK64WMBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 
  };

  // GR64_TC_and_GR64_NOSP_and_GR64_TCW64 Register Class...
  const MCPhysReg GR64_TC_and_GR64_NOSP_and_GR64_TCW64[] = {
    X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, 
  };

  // GR64_TC_and_GR64_NOSP_and_GR64_TCW64 Bit set.
  const uint8_t GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x05, 
  };

  // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX Register Class...
  const MCPhysReg GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX[] = {
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP, 
  };

  // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX Bit set.
  const uint8_t GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x72, 0x06, 
  };

  // GR64_NOREX_NOSP_and_GR64_TC Register Class...
  const MCPhysReg GR64_NOREX_NOSP_and_GR64_TC[] = {
    X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, 
  };

  // GR64_NOREX_NOSP_and_GR64_TC Bit set.
  const uint8_t GR64_NOREX_NOSP_and_GR64_TCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x72, 0x02, 
  };

  // GR64_NOREX_and_GR64_TCW64 Register Class...
  const MCPhysReg GR64_NOREX_and_GR64_TCW64[] = {
    X86::RAX, X86::RCX, X86::RDX, X86::RSP, X86::RIP, 
  };

  // GR64_NOREX_and_GR64_TCW64 Bit set.
  const uint8_t GR64_NOREX_and_GR64_TCW64Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd2, 0x04, 
  };

  // GR64_ABCD Register Class...
  const MCPhysReg GR64_ABCD[] = {
    X86::RAX, X86::RCX, X86::RDX, X86::RBX, 
  };

  // GR64_ABCD Bit set.
  const uint8_t GR64_ABCDBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5a, 
  };

  // GR64_with_sub_32bit_in_GR32_TC Register Class...
  const MCPhysReg GR64_with_sub_32bit_in_GR32_TC[] = {
    X86::RAX, X86::RCX, X86::RDX, X86::RSP, 
  };

  // GR64_with_sub_32bit_in_GR32_TC Bit set.
  const uint8_t GR64_with_sub_32bit_in_GR32_TCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x52, 0x04, 
  };

  // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC Register Class...
  const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC[] = {
    X86::RAX, X86::RCX, X86::RDX, 
  };

  // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC Bit set.
  const uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x52, 
  };

  // GR64_AD Register Class...
  const MCPhysReg GR64_AD[] = {
    X86::RAX, X86::RDX, 
  };

  // GR64_AD Bit set.
  const uint8_t GR64_ADBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 
  };

  // GR64_and_LOW32_ADDR_ACCESS_RBP Register Class...
  const MCPhysReg GR64_and_LOW32_ADDR_ACCESS_RBP[] = {
    X86::RBP, X86::RIP, 
  };

  // GR64_and_LOW32_ADDR_ACCESS_RBP Bit set.
  const uint8_t GR64_and_LOW32_ADDR_ACCESS_RBPBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 
  };

  // GR64_with_sub_32bit_in_GR32_BPSP Register Class...
  const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP[] = {
    X86::RBP, X86::RSP, 
  };

  // GR64_with_sub_32bit_in_GR32_BPSP Bit set.
  const uint8_t GR64_with_sub_32bit_in_GR32_BPSPBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x04, 
  };

  // GR64_with_sub_32bit_in_GR32_BSI Register Class...
  const MCPhysReg GR64_with_sub_32bit_in_GR32_BSI[] = {
    X86::RSI, X86::RBX, 
  };

  // GR64_with_sub_32bit_in_GR32_BSI Bit set.
  const uint8_t GR64_with_sub_32bit_in_GR32_BSIBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x02, 
  };

  // GR64_with_sub_32bit_in_GR32_CB Register Class...
  const MCPhysReg GR64_with_sub_32bit_in_GR32_CB[] = {
    X86::RCX, X86::RBX, 
  };

  // GR64_with_sub_32bit_in_GR32_CB Bit set.
  const uint8_t GR64_with_sub_32bit_in_GR32_CBBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 
  };

  // GR64_with_sub_32bit_in_GR32_DC Register Class...
  const MCPhysReg GR64_with_sub_32bit_in_GR32_DC[] = {
    X86::RCX, X86::RDX, 
  };

  // GR64_with_sub_32bit_in_GR32_DC Bit set.
  const uint8_t GR64_with_sub_32bit_in_GR32_DCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 
  };

  // GR64_with_sub_32bit_in_GR32_DIBP Register Class...
  const MCPhysReg GR64_with_sub_32bit_in_GR32_DIBP[] = {
    X86::RDI, X86::RBP, 
  };

  // GR64_with_sub_32bit_in_GR32_DIBP Bit set.
  const uint8_t GR64_with_sub_32bit_in_GR32_DIBPBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24, 
  };

  // GR64_with_sub_32bit_in_GR32_SIDI Register Class...
  const MCPhysReg GR64_with_sub_32bit_in_GR32_SIDI[] = {
    X86::RSI, X86::RDI, 
  };

  // GR64_with_sub_32bit_in_GR32_SIDI Bit set.
  const uint8_t GR64_with_sub_32bit_in_GR32_SIDIBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x02, 
  };

  // GR64_and_LOW32_ADDR_ACCESS Register Class...
  const MCPhysReg GR64_and_LOW32_ADDR_ACCESS[] = {
    X86::RIP, 
  };

  // GR64_and_LOW32_ADDR_ACCESS Bit set.
  const uint8_t GR64_and_LOW32_ADDR_ACCESSBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 
  };

  // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI Register Class...
  const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI[] = {
    X86::RBX, 
  };

  // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI Bit set.
  const uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 
  };

  // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC Register Class...
  const MCPhysReg GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC[] = {
    X86::RDX, 
  };

  // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC Bit set.
  const uint8_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 
  };

  // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP Register Class...
  const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP[] = {
    X86::RBP, 
  };

  // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP Bit set.
  const uint8_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 
  };

  // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC Register Class...
  const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC[] = {
    X86::RSP, 
  };

  // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC Bit set.
  const uint8_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 
  };

  // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI Register Class...
  const MCPhysReg GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI[] = {
    X86::RSI, 
  };

  // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI Bit set.
  const uint8_t GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 
  };

  // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC Register Class...
  const MCPhysReg GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC[] = {
    X86::RCX, 
  };

  // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC Bit set.
  const uint8_t GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 
  };

  // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI Register Class...
  const MCPhysReg GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI[] = {
    X86::RDI, 
  };

  // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI Bit set.
  const uint8_t GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 
  };

  // RST Register Class...
  const MCPhysReg RST[] = {
    X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7, 
  };

  // RST Bit set.
  const uint8_t RSTBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
  };

  // RFP80 Register Class...
  const MCPhysReg RFP80[] = {
    X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6, 
  };

  // RFP80 Bit set.
  const uint8_t RFP80Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 
  };

  // RFP80_7 Register Class...
  const MCPhysReg RFP80_7[] = {
    X86::FP7, 
  };

  // RFP80_7 Bit set.
  const uint8_t RFP80_7Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 
  };

  // VR128X Register Class...
  const MCPhysReg VR128X[] = {
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31, 
  };

  // VR128X Bit set.
  const uint8_t VR128XBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 
  };

  // VR128 Register Class...
  const MCPhysReg VR128[] = {
    X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 
  };

  // VR128 Bit set.
  const uint8_t VR128Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 
  };

  // BNDR Register Class...
  const MCPhysReg BNDR[] = {
    X86::BND0, X86::BND1, X86::BND2, X86::BND3, 
  };

  // BNDR Bit set.
  const uint8_t BNDRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 
  };

  // VR256X Register Class...
  const MCPhysReg VR256X[] = {
    X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM16, X86::YMM17, X86::YMM18, X86::YMM19, X86::YMM20, X86::YMM21, X86::YMM22, X86::YMM23, X86::YMM24, X86::YMM25, X86::YMM26, X86::YMM27, X86::YMM28, X86::YMM29, X86::YMM30, X86::YMM31, 
  };

  // VR256X Bit set.
  const uint8_t VR256XBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 
  };

  // VR256 Register Class...
  const MCPhysReg VR256[] = {
    X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 
  };

  // VR256 Bit set.
  const uint8_t VR256Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 
  };

  // VR512 Register Class...
  const MCPhysReg VR512[] = {
    X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, 
  };

  // VR512 Bit set.
  const uint8_t VR512Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f, 
  };

  // VR512_0_15 Register Class...
  const MCPhysReg VR512_0_15[] = {
    X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, 
  };

  // VR512_0_15 Bit set.
  const uint8_t VR512_0_15Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 
  };

} // end anonymous namespace

extern const char X86RegClassStrings[] = {
  /* 0 */ 'R', 'F', 'P', '8', '0', 0,
  /* 6 */ 'V', 'K', '1', 0,
  /* 10 */ 'V', 'R', '5', '1', '2', 0,
  /* 16 */ 'V', 'K', '3', '2', 0,
  /* 21 */ 'R', 'F', 'P', '3', '2', 0,
  /* 27 */ 'F', 'R', '3', '2', 0,
  /* 32 */ 'G', 'R', '3', '2', 0,
  /* 37 */ 'V', 'K', '2', 0,
  /* 41 */ 'V', 'K', '6', '4', 0,
  /* 46 */ 'R', 'F', 'P', '6', '4', 0,
  /* 52 */ 'F', 'R', '6', '4', 0,
  /* 57 */ 'G', 'R', '6', '4', 0,
  /* 62 */ 'V', 'R', '6', '4', 0,
  /* 67 */ 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', 0,
  /* 90 */ 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'N', 'O', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', 0,
  /* 127 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', 0,
  /* 153 */ 'V', 'K', '4', 0,
  /* 157 */ 'V', 'R', '5', '1', '2', '_', '0', '_', '1', '5', 0,
  /* 168 */ 'G', 'R', 'H', '1', '6', 0,
  /* 174 */ 'V', 'K', '1', '6', 0,
  /* 179 */ 'G', 'R', '1', '6', 0,
  /* 184 */ 'V', 'R', '2', '5', '6', 0,
  /* 190 */ 'R', 'F', 'P', '8', '0', '_', '7', 0,
  /* 198 */ 'V', 'R', '1', '2', '8', 0,
  /* 204 */ 'G', 'R', 'H', '8', 0,
  /* 209 */ 'V', 'K', '8', 0,
  /* 213 */ 'G', 'R', '8', 0,
  /* 217 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'C', 'B', 0,
  /* 248 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'C', 'B', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'D', 'C', 0,
  /* 291 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'A', 'D', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'D', 'C', 0,
  /* 334 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'D', 'C', 0,
  /* 365 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'A', 'B', 'C', 'D', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'T', 'C', 0,
  /* 410 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'P', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'T', 'C', 0,
  /* 455 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'T', 'C', 0,
  /* 486 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 0,
  /* 508 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'N', 'O', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 0,
  /* 536 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 0,
  /* 559 */ 'G', 'R', '3', '2', '_', 'A', 'D', 0,
  /* 567 */ 'G', 'R', '6', '4', '_', 'A', 'D', 0,
  /* 575 */ 'G', 'R', '3', '2', '_', 'A', 'B', 'C', 'D', 0,
  /* 585 */ 'G', 'R', '6', '4', '_', 'A', 'B', 'C', 'D', 0,
  /* 595 */ 'G', 'R', '1', '6', '_', 'A', 'B', 'C', 'D', 0,
  /* 605 */ 'D', 'E', 'B', 'U', 'G', '_', 'R', 'E', 'G', 0,
  /* 615 */ 'C', 'O', 'N', 'T', 'R', 'O', 'L', '_', 'R', 'E', 'G', 0,
  /* 627 */ 'S', 'E', 'G', 'M', 'E', 'N', 'T', '_', 'R', 'E', 'G', 0,
  /* 639 */ 'G', 'R', '8', '_', 'A', 'B', 'C', 'D', '_', 'H', 0,
  /* 650 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'S', 'I', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'S', 'I', 'D', 'I', 0,
  /* 696 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'D', 'I', 'B', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'S', 'I', 'D', 'I', 0,
  /* 743 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'S', 'I', 'D', 'I', 0,
  /* 776 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'A', 'B', 'C', 'D', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'B', 'S', 'I', 0,
  /* 822 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'S', 'I', 0,
  /* 854 */ 'G', 'R', '8', '_', 'A', 'B', 'C', 'D', '_', 'L', 0,
  /* 865 */ 'V', 'K', '1', 'W', 'M', 0,
  /* 871 */ 'V', 'K', '3', '2', 'W', 'M', 0,
  /* 878 */ 'V', 'K', '2', 'W', 'M', 0,
  /* 884 */ 'V', 'K', '6', '4', 'W', 'M', 0,
  /* 891 */ 'V', 'K', '4', 'W', 'M', 0,
  /* 897 */ 'V', 'K', '1', '6', 'P', 'A', 'I', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'm', 'a', 's', 'k', '_', '0', '_', 'i', 'n', '_', 'V', 'K', '1', '6', 'W', 'M', 0,
  /* 932 */ 'V', 'K', '8', 'W', 'M', 0,
  /* 938 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'P', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'D', 'I', 'B', 'P', 0,
  /* 985 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'D', 'I', 'B', 'P', 0,
  /* 1018 */ 'G', 'R', '6', '4', '_', 'a', 'n', 'd', '_', 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', 0,
  /* 1049 */ 'G', 'R', '3', '2', '_', 'N', 'O', 'S', 'P', 0,
  /* 1059 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'S', 'P', 0,
  /* 1069 */ 'G', 'R', '3', '2', '_', 'N', 'O', 'R', 'E', 'X', '_', 'N', 'O', 'S', 'P', 0,
  /* 1085 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'N', 'O', 'S', 'P', 0,
  /* 1101 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'P', 'S', 'P', 0,
  /* 1134 */ 'D', 'F', 'C', 'C', 'R', 0,
  /* 1140 */ 'F', 'P', 'C', 'C', 'R', 0,
  /* 1146 */ 'B', 'N', 'D', 'R', 0,
  /* 1151 */ 'V', 'K', '1', 'P', 'A', 'I', 'R', 0,
  /* 1159 */ 'V', 'K', '2', 'P', 'A', 'I', 'R', 0,
  /* 1167 */ 'V', 'K', '4', 'P', 'A', 'I', 'R', 0,
  /* 1175 */ 'V', 'K', '1', '6', 'P', 'A', 'I', 'R', 0,
  /* 1184 */ 'V', 'K', '8', 'P', 'A', 'I', 'R', 0,
  /* 1192 */ 'G', 'R', '6', '4', '_', 'a', 'n', 'd', '_', 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', 0,
  /* 1219 */ 'R', 'S', 'T', 0,
  /* 1223 */ 'F', 'R', '3', '2', 'X', 0,
  /* 1229 */ 'F', 'R', '6', '4', 'X', 0,
  /* 1235 */ 'V', 'R', '2', '5', '6', 'X', 0,
  /* 1242 */ 'V', 'R', '1', '2', '8', 'X', 0,
  /* 1249 */ 'G', 'R', '3', '2', '_', 'N', 'O', 'R', 'E', 'X', 0,
  /* 1260 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', 0,
  /* 1271 */ 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '1', '6', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '1', '6', '_', 'N', 'O', 'R', 'E', 'X', 0,
  /* 1317 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '1', '6', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '1', '6', '_', 'N', 'O', 'R', 'E', 'X', 0,
  /* 1368 */ 'G', 'R', '8', '_', 'N', 'O', 'R', 'E', 'X', 0,
  /* 1378 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', 0,
  /* 1415 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', 0,
  /* 1448 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', 0,
  /* 1499 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0,
  /* 1518 */ 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0,
  /* 1543 */ 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0,
  /* 1580 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0,
};

extern const MCRegisterClass X86MCRegisterClasses[] = {
  { GR8, GR8Bits, 213, 20, sizeof(GR8Bits), X86::GR8RegClassID, 1, true },
  { GRH8, GRH8Bits, 204, 12, sizeof(GRH8Bits), X86::GRH8RegClassID, 1, false },
  { GR8_NOREX, GR8_NOREXBits, 1368, 8, sizeof(GR8_NOREXBits), X86::GR8_NOREXRegClassID, 1, true },
  { GR8_ABCD_H, GR8_ABCD_HBits, 639, 4, sizeof(GR8_ABCD_HBits), X86::GR8_ABCD_HRegClassID, 1, true },
  { GR8_ABCD_L, GR8_ABCD_LBits, 854, 4, sizeof(GR8_ABCD_LBits), X86::GR8_ABCD_LRegClassID, 1, true },
  { GRH16, GRH16Bits, 168, 17, sizeof(GRH16Bits), X86::GRH16RegClassID, 1, false },
  { GR16, GR16Bits, 179, 16, sizeof(GR16Bits), X86::GR16RegClassID, 1, true },
  { GR16_NOREX, GR16_NOREXBits, 1306, 8, sizeof(GR16_NOREXBits), X86::GR16_NOREXRegClassID, 1, true },
  { VK1, VK1Bits, 6, 8, sizeof(VK1Bits), X86::VK1RegClassID, 1, true },
  { VK16, VK16Bits, 174, 8, sizeof(VK16Bits), X86::VK16RegClassID, 1, true },
  { VK2, VK2Bits, 37, 8, sizeof(VK2Bits), X86::VK2RegClassID, 1, true },
  { VK4, VK4Bits, 153, 8, sizeof(VK4Bits), X86::VK4RegClassID, 1, true },
  { VK8, VK8Bits, 209, 8, sizeof(VK8Bits), X86::VK8RegClassID, 1, true },
  { VK16WM, VK16WMBits, 925, 7, sizeof(VK16WMBits), X86::VK16WMRegClassID, 1, true },
  { VK1WM, VK1WMBits, 865, 7, sizeof(VK1WMBits), X86::VK1WMRegClassID, 1, true },
  { VK2WM, VK2WMBits, 878, 7, sizeof(VK2WMBits), X86::VK2WMRegClassID, 1, true },
  { VK4WM, VK4WMBits, 891, 7, sizeof(VK4WMBits), X86::VK4WMRegClassID, 1, true },
  { VK8WM, VK8WMBits, 932, 7, sizeof(VK8WMBits), X86::VK8WMRegClassID, 1, true },
  { SEGMENT_REG, SEGMENT_REGBits, 627, 6, sizeof(SEGMENT_REGBits), X86::SEGMENT_REGRegClassID, 1, true },
  { GR16_ABCD, GR16_ABCDBits, 595, 4, sizeof(GR16_ABCDBits), X86::GR16_ABCDRegClassID, 1, true },
  { FPCCR, FPCCRBits, 1140, 1, sizeof(FPCCRBits), X86::FPCCRRegClassID, -1, false },
  { VK16PAIR, VK16PAIRBits, 1175, 4, sizeof(VK16PAIRBits), X86::VK16PAIRRegClassID, 1, true },
  { VK1PAIR, VK1PAIRBits, 1151, 4, sizeof(VK1PAIRBits), X86::VK1PAIRRegClassID, 1, true },
  { VK2PAIR, VK2PAIRBits, 1159, 4, sizeof(VK2PAIRBits), X86::VK2PAIRRegClassID, 1, true },
  { VK4PAIR, VK4PAIRBits, 1167, 4, sizeof(VK4PAIRBits), X86::VK4PAIRRegClassID, 1, true },
  { VK8PAIR, VK8PAIRBits, 1184, 4, sizeof(VK8PAIRBits), X86::VK8PAIRRegClassID, 1, true },
  { VK16PAIR_with_sub_mask_0_in_VK16WM, VK16PAIR_with_sub_mask_0_in_VK16WMBits, 897, 3, sizeof(VK16PAIR_with_sub_mask_0_in_VK16WMBits), X86::VK16PAIR_with_sub_mask_0_in_VK16WMRegClassID, 1, true },
  { FR32X, FR32XBits, 1223, 32, sizeof(FR32XBits), X86::FR32XRegClassID, 1, true },
  { LOW32_ADDR_ACCESS_RBP, LOW32_ADDR_ACCESS_RBPBits, 1027, 18, sizeof(LOW32_ADDR_ACCESS_RBPBits), X86::LOW32_ADDR_ACCESS_RBPRegClassID, 1, true },
  { LOW32_ADDR_ACCESS, LOW32_ADDR_ACCESSBits, 1201, 17, sizeof(LOW32_ADDR_ACCESSBits), X86::LOW32_ADDR_ACCESSRegClassID, 1, true },
  { LOW32_ADDR_ACCESS_RBP_with_sub_8bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits, 1580, 17, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 1, true },
  { DEBUG_REG, DEBUG_REGBits, 605, 16, sizeof(DEBUG_REGBits), X86::DEBUG_REGRegClassID, 1, true },
  { FR32, FR32Bits, 27, 16, sizeof(FR32Bits), X86::FR32RegClassID, 1, true },
  { GR32, GR32Bits, 32, 16, sizeof(GR32Bits), X86::GR32RegClassID, 1, true },
  { GR32_NOSP, GR32_NOSPBits, 1049, 15, sizeof(GR32_NOSPBits), X86::GR32_NOSPRegClassID, 1, true },
  { LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX, LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits, 1317, 9, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, 1, true },
  { GR32_NOREX, GR32_NOREXBits, 1249, 8, sizeof(GR32_NOREXBits), X86::GR32_NOREXRegClassID, 1, true },
  { VK32, VK32Bits, 16, 8, sizeof(VK32Bits), X86::VK32RegClassID, 1, true },
  { GR32_NOREX_NOSP, GR32_NOREX_NOSPBits, 1069, 7, sizeof(GR32_NOREX_NOSPBits), X86::GR32_NOREX_NOSPRegClassID, 1, true },
  { RFP32, RFP32Bits, 21, 7, sizeof(RFP32Bits), X86::RFP32RegClassID, 1, true },
  { VK32WM, VK32WMBits, 871, 7, sizeof(VK32WMBits), X86::VK32WMRegClassID, 1, true },
  { GR32_ABCD, GR32_ABCDBits, 575, 4, sizeof(GR32_ABCDBits), X86::GR32_ABCDRegClassID, 1, true },
  { GR32_TC, GR32_TCBits, 402, 4, sizeof(GR32_TCBits), X86::GR32_TCRegClassID, 1, true },
  { GR32_ABCD_and_GR32_TC, GR32_ABCD_and_GR32_TCBits, 388, 3, sizeof(GR32_ABCD_and_GR32_TCBits), X86::GR32_ABCD_and_GR32_TCRegClassID, 1, true },
  { GR32_AD, GR32_ADBits, 559, 2, sizeof(GR32_ADBits), X86::GR32_ADRegClassID, 1, true },
  { GR32_BPSP, GR32_BPSPBits, 1124, 2, sizeof(GR32_BPSPBits), X86::GR32_BPSPRegClassID, 1, true },
  { GR32_BSI, GR32_BSIBits, 813, 2, sizeof(GR32_BSIBits), X86::GR32_BSIRegClassID, 1, true },
  { GR32_CB, GR32_CBBits, 240, 2, sizeof(GR32_CBBits), X86::GR32_CBRegClassID, 1, true },
  { GR32_DC, GR32_DCBits, 283, 2, sizeof(GR32_DCBits), X86::GR32_DCRegClassID, 1, true },
  { GR32_DIBP, GR32_DIBPBits, 975, 2, sizeof(GR32_DIBPBits), X86::GR32_DIBPRegClassID, 1, true },
  { GR32_SIDI, GR32_SIDIBits, 686, 2, sizeof(GR32_SIDIBits), X86::GR32_SIDIRegClassID, 1, true },
  { LOW32_ADDR_ACCESS_RBP_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits, 1378, 2, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID, 1, true },
  { CCR, CCRBits, 1136, 1, sizeof(CCRBits), X86::CCRRegClassID, -1, false },
  { DFCCR, DFCCRBits, 1134, 1, sizeof(DFCCRBits), X86::DFCCRRegClassID, -1, false },
  { GR32_ABCD_and_GR32_BSI, GR32_ABCD_and_GR32_BSIBits, 799, 1, sizeof(GR32_ABCD_and_GR32_BSIBits), X86::GR32_ABCD_and_GR32_BSIRegClassID, 1, true },
  { GR32_AD_and_GR32_DC, GR32_AD_and_GR32_DCBits, 314, 1, sizeof(GR32_AD_and_GR32_DCBits), X86::GR32_AD_and_GR32_DCRegClassID, 1, true },
  { GR32_BPSP_and_GR32_DIBP, GR32_BPSP_and_GR32_DIBPBits, 961, 1, sizeof(GR32_BPSP_and_GR32_DIBPBits), X86::GR32_BPSP_and_GR32_DIBPRegClassID, 1, true },
  { GR32_BPSP_and_GR32_TC, GR32_BPSP_and_GR32_TCBits, 433, 1, sizeof(GR32_BPSP_and_GR32_TCBits), X86::GR32_BPSP_and_GR32_TCRegClassID, 1, true },
  { GR32_BSI_and_GR32_SIDI, GR32_BSI_and_GR32_SIDIBits, 673, 1, sizeof(GR32_BSI_and_GR32_SIDIBits), X86::GR32_BSI_and_GR32_SIDIRegClassID, 1, true },
  { GR32_CB_and_GR32_DC, GR32_CB_and_GR32_DCBits, 271, 1, sizeof(GR32_CB_and_GR32_DCBits), X86::GR32_CB_and_GR32_DCRegClassID, 1, true },
  { GR32_DIBP_and_GR32_SIDI, GR32_DIBP_and_GR32_SIDIBits, 719, 1, sizeof(GR32_DIBP_and_GR32_SIDIBits), X86::GR32_DIBP_and_GR32_SIDIRegClassID, 1, true },
  { LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits, 1448, 1, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID, 1, true },
  { LOW32_ADDR_ACCESS_with_sub_32bit, LOW32_ADDR_ACCESS_with_sub_32bitBits, 1415, 1, sizeof(LOW32_ADDR_ACCESS_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClassID, 1, true },
  { RFP64, RFP64Bits, 46, 7, sizeof(RFP64Bits), X86::RFP64RegClassID, 1, true },
  { FR64X, FR64XBits, 1229, 32, sizeof(FR64XBits), X86::FR64XRegClassID, 1, true },
  { GR64, GR64Bits, 57, 17, sizeof(GR64Bits), X86::GR64RegClassID, 1, true },
  { CONTROL_REG, CONTROL_REGBits, 615, 16, sizeof(CONTROL_REGBits), X86::CONTROL_REGRegClassID, 1, true },
  { FR64, FR64Bits, 52, 16, sizeof(FR64Bits), X86::FR64RegClassID, 1, true },
  { GR64_with_sub_8bit, GR64_with_sub_8bitBits, 1499, 16, sizeof(GR64_with_sub_8bitBits), X86::GR64_with_sub_8bitRegClassID, 1, true },
  { GR64_NOSP, GR64_NOSPBits, 1059, 15, sizeof(GR64_NOSPBits), X86::GR64_NOSPRegClassID, 1, true },
  { GR64_TC, GR64_TCBits, 500, 10, sizeof(GR64_TCBits), X86::GR64_TCRegClassID, 1, true },
  { GR64_NOREX, GR64_NOREXBits, 1260, 9, sizeof(GR64_NOREXBits), X86::GR64_NOREXRegClassID, 1, true },
  { GR64_TCW64, GR64_TCW64Bits, 79, 9, sizeof(GR64_TCW64Bits), X86::GR64_TCW64RegClassID, 1, true },
  { GR64_TC_with_sub_8bit, GR64_TC_with_sub_8bitBits, 1558, 9, sizeof(GR64_TC_with_sub_8bitBits), X86::GR64_TC_with_sub_8bitRegClassID, 1, true },
  { GR64_NOSP_and_GR64_TC, GR64_NOSP_and_GR64_TCBits, 486, 8, sizeof(GR64_NOSP_and_GR64_TCBits), X86::GR64_NOSP_and_GR64_TCRegClassID, 1, true },
  { GR64_TCW64_with_sub_8bit, GR64_TCW64_with_sub_8bitBits, 1518, 8, sizeof(GR64_TCW64_with_sub_8bitBits), X86::GR64_TCW64_with_sub_8bitRegClassID, 1, true },
  { GR64_TC_and_GR64_TCW64, GR64_TC_and_GR64_TCW64Bits, 67, 8, sizeof(GR64_TC_and_GR64_TCW64Bits), X86::GR64_TC_and_GR64_TCW64RegClassID, 1, true },
  { GR64_with_sub_16bit_in_GR16_NOREX, GR64_with_sub_16bit_in_GR16_NOREXBits, 1283, 8, sizeof(GR64_with_sub_16bit_in_GR16_NOREXBits), X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, 1, true },
  { VK64, VK64Bits, 41, 8, sizeof(VK64Bits), X86::VK64RegClassID, 1, true },
  { VR64, VR64Bits, 62, 8, sizeof(VR64Bits), X86::VR64RegClassID, 1, true },
  { GR64_NOREX_NOSP, GR64_NOREX_NOSPBits, 1085, 7, sizeof(GR64_NOREX_NOSPBits), X86::GR64_NOREX_NOSPRegClassID, 1, true },
  { GR64_NOREX_and_GR64_TC, GR64_NOREX_and_GR64_TCBits, 536, 7, sizeof(GR64_NOREX_and_GR64_TCBits), X86::GR64_NOREX_and_GR64_TCRegClassID, 1, true },
  { GR64_NOSP_and_GR64_TCW64, GR64_NOSP_and_GR64_TCW64Bits, 102, 7, sizeof(GR64_NOSP_and_GR64_TCW64Bits), X86::GR64_NOSP_and_GR64_TCW64RegClassID, 1, true },
  { GR64_TCW64_and_GR64_TC_with_sub_8bit, GR64_TCW64_and_GR64_TC_with_sub_8bitBits, 1543, 7, sizeof(GR64_TCW64_and_GR64_TC_with_sub_8bitBits), X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, 1, true },
  { VK64WM, VK64WMBits, 884, 7, sizeof(VK64WMBits), X86::VK64WMRegClassID, 1, true },
  { GR64_TC_and_GR64_NOSP_and_GR64_TCW64, GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits, 90, 6, sizeof(GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits), X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID, 1, true },
  { GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX, GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits, 1271, 6, sizeof(GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits), X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, 1, true },
  { GR64_NOREX_NOSP_and_GR64_TC, GR64_NOREX_NOSP_and_GR64_TCBits, 508, 5, sizeof(GR64_NOREX_NOSP_and_GR64_TCBits), X86::GR64_NOREX_NOSP_and_GR64_TCRegClassID, 1, true },
  { GR64_NOREX_and_GR64_TCW64, GR64_NOREX_and_GR64_TCW64Bits, 127, 5, sizeof(GR64_NOREX_and_GR64_TCW64Bits), X86::GR64_NOREX_and_GR64_TCW64RegClassID, 1, true },
  { GR64_ABCD, GR64_ABCDBits, 585, 4, sizeof(GR64_ABCDBits), X86::GR64_ABCDRegClassID, 1, true },
  { GR64_with_sub_32bit_in_GR32_TC, GR64_with_sub_32bit_in_GR32_TCBits, 455, 4, sizeof(GR64_with_sub_32bit_in_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_TCRegClassID, 1, true },
  { GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC, GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits, 365, 3, sizeof(GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID, 1, true },
  { GR64_AD, GR64_ADBits, 567, 2, sizeof(GR64_ADBits), X86::GR64_ADRegClassID, 1, true },
  { GR64_and_LOW32_ADDR_ACCESS_RBP, GR64_and_LOW32_ADDR_ACCESS_RBPBits, 1018, 2, sizeof(GR64_and_LOW32_ADDR_ACCESS_RBPBits), X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID, 1, true },
  { GR64_with_sub_32bit_in_GR32_BPSP, GR64_with_sub_32bit_in_GR32_BPSPBits, 1101, 2, sizeof(GR64_with_sub_32bit_in_GR32_BPSPBits), X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID, 1, true },
  { GR64_with_sub_32bit_in_GR32_BSI, GR64_with_sub_32bit_in_GR32_BSIBits, 822, 2, sizeof(GR64_with_sub_32bit_in_GR32_BSIBits), X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID, 1, true },
  { GR64_with_sub_32bit_in_GR32_CB, GR64_with_sub_32bit_in_GR32_CBBits, 217, 2, sizeof(GR64_with_sub_32bit_in_GR32_CBBits), X86::GR64_with_sub_32bit_in_GR32_CBRegClassID, 1, true },
  { GR64_with_sub_32bit_in_GR32_DC, GR64_with_sub_32bit_in_GR32_DCBits, 334, 2, sizeof(GR64_with_sub_32bit_in_GR32_DCBits), X86::GR64_with_sub_32bit_in_GR32_DCRegClassID, 1, true },
  { GR64_with_sub_32bit_in_GR32_DIBP, GR64_with_sub_32bit_in_GR32_DIBPBits, 985, 2, sizeof(GR64_with_sub_32bit_in_GR32_DIBPBits), X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID, 1, true },
  { GR64_with_sub_32bit_in_GR32_SIDI, GR64_with_sub_32bit_in_GR32_SIDIBits, 743, 2, sizeof(GR64_with_sub_32bit_in_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID, 1, true },
  { GR64_and_LOW32_ADDR_ACCESS, GR64_and_LOW32_ADDR_ACCESSBits, 1192, 1, sizeof(GR64_and_LOW32_ADDR_ACCESSBits), X86::GR64_and_LOW32_ADDR_ACCESSRegClassID, 1, true },
  { GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI, GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits, 776, 1, sizeof(GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits), X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID, 1, true },
  { GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC, GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCBits, 291, 1, sizeof(GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCBits), X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClassID, 1, true },
  { GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP, GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits, 938, 1, sizeof(GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits), X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID, 1, true },
  { GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC, GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits, 410, 1, sizeof(GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID, 1, true },
  { GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI, GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits, 650, 1, sizeof(GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID, 1, true },
  { GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC, GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCBits, 248, 1, sizeof(GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCBits), X86::GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClassID, 1, true },
  { GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI, GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits, 696, 1, sizeof(GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID, 1, true },
  { RST, RSTBits, 1219, 8, sizeof(RSTBits), X86::RSTRegClassID, 1, false },
  { RFP80, RFP80Bits, 0, 7, sizeof(RFP80Bits), X86::RFP80RegClassID, 1, true },
  { RFP80_7, RFP80_7Bits, 190, 1, sizeof(RFP80_7Bits), X86::RFP80_7RegClassID, 1, false },
  { VR128X, VR128XBits, 1242, 32, sizeof(VR128XBits), X86::VR128XRegClassID, 1, true },
  { VR128, VR128Bits, 198, 16, sizeof(VR128Bits), X86::VR128RegClassID, 1, true },
  { BNDR, BNDRBits, 1146, 4, sizeof(BNDRBits), X86::BNDRRegClassID, 1, true },
  { VR256X, VR256XBits, 1235, 32, sizeof(VR256XBits), X86::VR256XRegClassID, 1, true },
  { VR256, VR256Bits, 184, 16, sizeof(VR256Bits), X86::VR256RegClassID, 1, true },
  { VR512, VR512Bits, 10, 32, sizeof(VR512Bits), X86::VR512RegClassID, 1, true },
  { VR512_0_15, VR512_0_15Bits, 157, 16, sizeof(VR512_0_15Bits), X86::VR512_0_15RegClassID, 1, true },
};

// X86 Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[] = {
  { 0U, X86::RAX },
  { 1U, X86::RDX },
  { 2U, X86::RCX },
  { 3U, X86::RBX },
  { 4U, X86::RSI },
  { 5U, X86::RDI },
  { 6U, X86::RBP },
  { 7U, X86::RSP },
  { 8U, X86::R8 },
  { 9U, X86::R9 },
  { 10U, X86::R10 },
  { 11U, X86::R11 },
  { 12U, X86::R12 },
  { 13U, X86::R13 },
  { 14U, X86::R14 },
  { 15U, X86::R15 },
  { 16U, X86::RIP },
  { 17U, X86::XMM0 },
  { 18U, X86::XMM1 },
  { 19U, X86::XMM2 },
  { 20U, X86::XMM3 },
  { 21U, X86::XMM4 },
  { 22U, X86::XMM5 },
  { 23U, X86::XMM6 },
  { 24U, X86::XMM7 },
  { 25U, X86::XMM8 },
  { 26U, X86::XMM9 },
  { 27U, X86::XMM10 },
  { 28U, X86::XMM11 },
  { 29U, X86::XMM12 },
  { 30U, X86::XMM13 },
  { 31U, X86::XMM14 },
  { 32U, X86::XMM15 },
  { 33U, X86::ST0 },
  { 34U, X86::ST1 },
  { 35U, X86::ST2 },
  { 36U, X86::ST3 },
  { 37U, X86::ST4 },
  { 38U, X86::ST5 },
  { 39U, X86::ST6 },
  { 40U, X86::ST7 },
  { 41U, X86::MM0 },
  { 42U, X86::MM1 },
  { 43U, X86::MM2 },
  { 44U, X86::MM3 },
  { 45U, X86::MM4 },
  { 46U, X86::MM5 },
  { 47U, X86::MM6 },
  { 48U, X86::MM7 },
  { 67U, X86::XMM16 },
  { 68U, X86::XMM17 },
  { 69U, X86::XMM18 },
  { 70U, X86::XMM19 },
  { 71U, X86::XMM20 },
  { 72U, X86::XMM21 },
  { 73U, X86::XMM22 },
  { 74U, X86::XMM23 },
  { 75U, X86::XMM24 },
  { 76U, X86::XMM25 },
  { 77U, X86::XMM26 },
  { 78U, X86::XMM27 },
  { 79U, X86::XMM28 },
  { 80U, X86::XMM29 },
  { 81U, X86::XMM30 },
  { 82U, X86::XMM31 },
  { 118U, X86::K0 },
  { 119U, X86::K1 },
  { 120U, X86::K2 },
  { 121U, X86::K3 },
  { 122U, X86::K4 },
  { 123U, X86::K5 },
  { 124U, X86::K6 },
  { 125U, X86::K7 },
};
extern const unsigned X86DwarfFlavour0Dwarf2LSize = array_lengthof(X86DwarfFlavour0Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[] = {
  { 0U, X86::EAX },
  { 1U, X86::ECX },
  { 2U, X86::EDX },
  { 3U, X86::EBX },
  { 4U, X86::EBP },
  { 5U, X86::ESP },
  { 6U, X86::ESI },
  { 7U, X86::EDI },
  { 8U, X86::EIP },
  { 12U, X86::ST0 },
  { 13U, X86::ST1 },
  { 14U, X86::ST2 },
  { 15U, X86::ST3 },
  { 16U, X86::ST4 },
  { 17U, X86::ST5 },
  { 18U, X86::ST6 },
  { 19U, X86::ST7 },
  { 21U, X86::XMM0 },
  { 22U, X86::XMM1 },
  { 23U, X86::XMM2 },
  { 24U, X86::XMM3 },
  { 25U, X86::XMM4 },
  { 26U, X86::XMM5 },
  { 27U, X86::XMM6 },
  { 28U, X86::XMM7 },
  { 29U, X86::MM0 },
  { 30U, X86::MM1 },
  { 31U, X86::MM2 },
  { 32U, X86::MM3 },
  { 33U, X86::MM4 },
  { 34U, X86::MM5 },
  { 35U, X86::MM6 },
  { 36U, X86::MM7 },
  { 93U, X86::K0 },
  { 94U, X86::K1 },
  { 95U, X86::K2 },
  { 96U, X86::K3 },
  { 97U, X86::K4 },
  { 98U, X86::K5 },
  { 99U, X86::K6 },
  { 100U, X86::K7 },
};
extern const unsigned X86DwarfFlavour1Dwarf2LSize = array_lengthof(X86DwarfFlavour1Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[] = {
  { 0U, X86::EAX },
  { 1U, X86::ECX },
  { 2U, X86::EDX },
  { 3U, X86::EBX },
  { 4U, X86::ESP },
  { 5U, X86::EBP },
  { 6U, X86::ESI },
  { 7U, X86::EDI },
  { 8U, X86::EIP },
  { 11U, X86::ST0 },
  { 12U, X86::ST1 },
  { 13U, X86::ST2 },
  { 14U, X86::ST3 },
  { 15U, X86::ST4 },
  { 16U, X86::ST5 },
  { 17U, X86::ST6 },
  { 18U, X86::ST7 },
  { 21U, X86::XMM0 },
  { 22U, X86::XMM1 },
  { 23U, X86::XMM2 },
  { 24U, X86::XMM3 },
  { 25U, X86::XMM4 },
  { 26U, X86::XMM5 },
  { 27U, X86::XMM6 },
  { 28U, X86::XMM7 },
  { 29U, X86::MM0 },
  { 30U, X86::MM1 },
  { 31U, X86::MM2 },
  { 32U, X86::MM3 },
  { 33U, X86::MM4 },
  { 34U, X86::MM5 },
  { 35U, X86::MM6 },
  { 36U, X86::MM7 },
  { 93U, X86::K0 },
  { 94U, X86::K1 },
  { 95U, X86::K2 },
  { 96U, X86::K3 },
  { 97U, X86::K4 },
  { 98U, X86::K5 },
  { 99U, X86::K6 },
  { 100U, X86::K7 },
};
extern const unsigned X86DwarfFlavour2Dwarf2LSize = array_lengthof(X86DwarfFlavour2Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[] = {
  { 0U, X86::RAX },
  { 1U, X86::RDX },
  { 2U, X86::RCX },
  { 3U, X86::RBX },
  { 4U, X86::RSI },
  { 5U, X86::RDI },
  { 6U, X86::RBP },
  { 7U, X86::RSP },
  { 8U, X86::R8 },
  { 9U, X86::R9 },
  { 10U, X86::R10 },
  { 11U, X86::R11 },
  { 12U, X86::R12 },
  { 13U, X86::R13 },
  { 14U, X86::R14 },
  { 15U, X86::R15 },
  { 16U, X86::RIP },
  { 17U, X86::XMM0 },
  { 18U, X86::XMM1 },
  { 19U, X86::XMM2 },
  { 20U, X86::XMM3 },
  { 21U, X86::XMM4 },
  { 22U, X86::XMM5 },
  { 23U, X86::XMM6 },
  { 24U, X86::XMM7 },
  { 25U, X86::XMM8 },
  { 26U, X86::XMM9 },
  { 27U, X86::XMM10 },
  { 28U, X86::XMM11 },
  { 29U, X86::XMM12 },
  { 30U, X86::XMM13 },
  { 31U, X86::XMM14 },
  { 32U, X86::XMM15 },
  { 33U, X86::ST0 },
  { 34U, X86::ST1 },
  { 35U, X86::ST2 },
  { 36U, X86::ST3 },
  { 37U, X86::ST4 },
  { 38U, X86::ST5 },
  { 39U, X86::ST6 },
  { 40U, X86::ST7 },
  { 41U, X86::MM0 },
  { 42U, X86::MM1 },
  { 43U, X86::MM2 },
  { 44U, X86::MM3 },
  { 45U, X86::MM4 },
  { 46U, X86::MM5 },
  { 47U, X86::MM6 },
  { 48U, X86::MM7 },
  { 67U, X86::XMM16 },
  { 68U, X86::XMM17 },
  { 69U, X86::XMM18 },
  { 70U, X86::XMM19 },
  { 71U, X86::XMM20 },
  { 72U, X86::XMM21 },
  { 73U, X86::XMM22 },
  { 74U, X86::XMM23 },
  { 75U, X86::XMM24 },
  { 76U, X86::XMM25 },
  { 77U, X86::XMM26 },
  { 78U, X86::XMM27 },
  { 79U, X86::XMM28 },
  { 80U, X86::XMM29 },
  { 81U, X86::XMM30 },
  { 82U, X86::XMM31 },
  { 118U, X86::K0 },
  { 119U, X86::K1 },
  { 120U, X86::K2 },
  { 121U, X86::K3 },
  { 122U, X86::K4 },
  { 123U, X86::K5 },
  { 124U, X86::K6 },
  { 125U, X86::K7 },
};
extern const unsigned X86EHFlavour0Dwarf2LSize = array_lengthof(X86EHFlavour0Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[] = {
  { 0U, X86::EAX },
  { 1U, X86::ECX },
  { 2U, X86::EDX },
  { 3U, X86::EBX },
  { 4U, X86::EBP },
  { 5U, X86::ESP },
  { 6U, X86::ESI },
  { 7U, X86::EDI },
  { 8U, X86::EIP },
  { 12U, X86::ST0 },
  { 13U, X86::ST1 },
  { 14U, X86::ST2 },
  { 15U, X86::ST3 },
  { 16U, X86::ST4 },
  { 17U, X86::ST5 },
  { 18U, X86::ST6 },
  { 19U, X86::ST7 },
  { 21U, X86::XMM0 },
  { 22U, X86::XMM1 },
  { 23U, X86::XMM2 },
  { 24U, X86::XMM3 },
  { 25U, X86::XMM4 },
  { 26U, X86::XMM5 },
  { 27U, X86::XMM6 },
  { 28U, X86::XMM7 },
  { 29U, X86::MM0 },
  { 30U, X86::MM1 },
  { 31U, X86::MM2 },
  { 32U, X86::MM3 },
  { 33U, X86::MM4 },
  { 34U, X86::MM5 },
  { 35U, X86::MM6 },
  { 36U, X86::MM7 },
  { 93U, X86::K0 },
  { 94U, X86::K1 },
  { 95U, X86::K2 },
  { 96U, X86::K3 },
  { 97U, X86::K4 },
  { 98U, X86::K5 },
  { 99U, X86::K6 },
  { 100U, X86::K7 },
};
extern const unsigned X86EHFlavour1Dwarf2LSize = array_lengthof(X86EHFlavour1Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[] = {
  { 0U, X86::EAX },
  { 1U, X86::ECX },
  { 2U, X86::EDX },
  { 3U, X86::EBX },
  { 4U, X86::ESP },
  { 5U, X86::EBP },
  { 6U, X86::ESI },
  { 7U, X86::EDI },
  { 8U, X86::EIP },
  { 11U, X86::ST0 },
  { 12U, X86::ST1 },
  { 13U, X86::ST2 },
  { 14U, X86::ST3 },
  { 15U, X86::ST4 },
  { 16U, X86::ST5 },
  { 17U, X86::ST6 },
  { 18U, X86::ST7 },
  { 21U, X86::XMM0 },
  { 22U, X86::XMM1 },
  { 23U, X86::XMM2 },
  { 24U, X86::XMM3 },
  { 25U, X86::XMM4 },
  { 26U, X86::XMM5 },
  { 27U, X86::XMM6 },
  { 28U, X86::XMM7 },
  { 29U, X86::MM0 },
  { 30U, X86::MM1 },
  { 31U, X86::MM2 },
  { 32U, X86::MM3 },
  { 33U, X86::MM4 },
  { 34U, X86::MM5 },
  { 35U, X86::MM6 },
  { 36U, X86::MM7 },
  { 93U, X86::K0 },
  { 94U, X86::K1 },
  { 95U, X86::K2 },
  { 96U, X86::K3 },
  { 97U, X86::K4 },
  { 98U, X86::K5 },
  { 99U, X86::K6 },
  { 100U, X86::K7 },
};
extern const unsigned X86EHFlavour2Dwarf2LSize = array_lengthof(X86EHFlavour2Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[] = {
  { X86::EAX, -2U },
  { X86::EBP, -2U },
  { X86::EBX, -2U },
  { X86::ECX, -2U },
  { X86::EDI, -2U },
  { X86::EDX, -2U },
  { X86::EIP, -2U },
  { X86::ESI, -2U },
  { X86::ESP, -2U },
  { X86::RAX, 0U },
  { X86::RBP, 6U },
  { X86::RBX, 3U },
  { X86::RCX, 2U },
  { X86::RDI, 5U },
  { X86::RDX, 1U },
  { X86::RIP, 16U },
  { X86::RSI, 4U },
  { X86::RSP, 7U },
  { X86::K0, 118U },
  { X86::K1, 119U },
  { X86::K2, 120U },
  { X86::K3, 121U },
  { X86::K4, 122U },
  { X86::K5, 123U },
  { X86::K6, 124U },
  { X86::K7, 125U },
  { X86::MM0, 41U },
  { X86::MM1, 42U },
  { X86::MM2, 43U },
  { X86::MM3, 44U },
  { X86::MM4, 45U },
  { X86::MM5, 46U },
  { X86::MM6, 47U },
  { X86::MM7, 48U },
  { X86::R8, 8U },
  { X86::R9, 9U },
  { X86::R10, 10U },
  { X86::R11, 11U },
  { X86::R12, 12U },
  { X86::R13, 13U },
  { X86::R14, 14U },
  { X86::R15, 15U },
  { X86::ST0, 33U },
  { X86::ST1, 34U },
  { X86::ST2, 35U },
  { X86::ST3, 36U },
  { X86::ST4, 37U },
  { X86::ST5, 38U },
  { X86::ST6, 39U },
  { X86::ST7, 40U },
  { X86::XMM0, 17U },
  { X86::XMM1, 18U },
  { X86::XMM2, 19U },
  { X86::XMM3, 20U },
  { X86::XMM4, 21U },
  { X86::XMM5, 22U },
  { X86::XMM6, 23U },
  { X86::XMM7, 24U },
  { X86::XMM8, 25U },
  { X86::XMM9, 26U },
  { X86::XMM10, 27U },
  { X86::XMM11, 28U },
  { X86::XMM12, 29U },
  { X86::XMM13, 30U },
  { X86::XMM14, 31U },
  { X86::XMM15, 32U },
  { X86::XMM16, 67U },
  { X86::XMM17, 68U },
  { X86::XMM18, 69U },
  { X86::XMM19, 70U },
  { X86::XMM20, 71U },
  { X86::XMM21, 72U },
  { X86::XMM22, 73U },
  { X86::XMM23, 74U },
  { X86::XMM24, 75U },
  { X86::XMM25, 76U },
  { X86::XMM26, 77U },
  { X86::XMM27, 78U },
  { X86::XMM28, 79U },
  { X86::XMM29, 80U },
  { X86::XMM30, 81U },
  { X86::XMM31, 82U },
  { X86::YMM0, 17U },
  { X86::YMM1, 18U },
  { X86::YMM2, 19U },
  { X86::YMM3, 20U },
  { X86::YMM4, 21U },
  { X86::YMM5, 22U },
  { X86::YMM6, 23U },
  { X86::YMM7, 24U },
  { X86::YMM8, 25U },
  { X86::YMM9, 26U },
  { X86::YMM10, 27U },
  { X86::YMM11, 28U },
  { X86::YMM12, 29U },
  { X86::YMM13, 30U },
  { X86::YMM14, 31U },
  { X86::YMM15, 32U },
  { X86::YMM16, 67U },
  { X86::YMM17, 68U },
  { X86::YMM18, 69U },
  { X86::YMM19, 70U },
  { X86::YMM20, 71U },
  { X86::YMM21, 72U },
  { X86::YMM22, 73U },
  { X86::YMM23, 74U },
  { X86::YMM24, 75U },
  { X86::YMM25, 76U },
  { X86::YMM26, 77U },
  { X86::YMM27, 78U },
  { X86::YMM28, 79U },
  { X86::YMM29, 80U },
  { X86::YMM30, 81U },
  { X86::YMM31, 82U },
  { X86::ZMM0, 17U },
  { X86::ZMM1, 18U },
  { X86::ZMM2, 19U },
  { X86::ZMM3, 20U },
  { X86::ZMM4, 21U },
  { X86::ZMM5, 22U },
  { X86::ZMM6, 23U },
  { X86::ZMM7, 24U },
  { X86::ZMM8, 25U },
  { X86::ZMM9, 26U },
  { X86::ZMM10, 27U },
  { X86::ZMM11, 28U },
  { X86::ZMM12, 29U },
  { X86::ZMM13, 30U },
  { X86::ZMM14, 31U },
  { X86::ZMM15, 32U },
  { X86::ZMM16, 67U },
  { X86::ZMM17, 68U },
  { X86::ZMM18, 69U },
  { X86::ZMM19, 70U },
  { X86::ZMM20, 71U },
  { X86::ZMM21, 72U },
  { X86::ZMM22, 73U },
  { X86::ZMM23, 74U },
  { X86::ZMM24, 75U },
  { X86::ZMM25, 76U },
  { X86::ZMM26, 77U },
  { X86::ZMM27, 78U },
  { X86::ZMM28, 79U },
  { X86::ZMM29, 80U },
  { X86::ZMM30, 81U },
  { X86::ZMM31, 82U },
};
extern const unsigned X86DwarfFlavour0L2DwarfSize = array_lengthof(X86DwarfFlavour0L2Dwarf);

extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[] = {
  { X86::EAX, 0U },
  { X86::EBP, 4U },
  { X86::EBX, 3U },
  { X86::ECX, 1U },
  { X86::EDI, 7U },
  { X86::EDX, 2U },
  { X86::EIP, 8U },
  { X86::ESI, 6U },
  { X86::ESP, 5U },
  { X86::RAX, -2U },
  { X86::RBP, -2U },
  { X86::RBX, -2U },
  { X86::RCX, -2U },
  { X86::RDI, -2U },
  { X86::RDX, -2U },
  { X86::RIP, -2U },
  { X86::RSI, -2U },
  { X86::RSP, -2U },
  { X86::K0, 93U },
  { X86::K1, 94U },
  { X86::K2, 95U },
  { X86::K3, 96U },
  { X86::K4, 97U },
  { X86::K5, 98U },
  { X86::K6, 99U },
  { X86::K7, 100U },
  { X86::MM0, 29U },
  { X86::MM1, 30U },
  { X86::MM2, 31U },
  { X86::MM3, 32U },
  { X86::MM4, 33U },
  { X86::MM5, 34U },
  { X86::MM6, 35U },
  { X86::MM7, 36U },
  { X86::R8, -2U },
  { X86::R9, -2U },
  { X86::R10, -2U },
  { X86::R11, -2U },
  { X86::R12, -2U },
  { X86::R13, -2U },
  { X86::R14, -2U },
  { X86::R15, -2U },
  { X86::ST0, 12U },
  { X86::ST1, 13U },
  { X86::ST2, 14U },
  { X86::ST3, 15U },
  { X86::ST4, 16U },
  { X86::ST5, 17U },
  { X86::ST6, 18U },
  { X86::ST7, 19U },
  { X86::XMM0, 21U },
  { X86::XMM1, 22U },
  { X86::XMM2, 23U },
  { X86::XMM3, 24U },
  { X86::XMM4, 25U },
  { X86::XMM5, 26U },
  { X86::XMM6, 27U },
  { X86::XMM7, 28U },
  { X86::XMM8, -2U },
  { X86::XMM9, -2U },
  { X86::XMM10, -2U },
  { X86::XMM11, -2U },
  { X86::XMM12, -2U },
  { X86::XMM13, -2U },
  { X86::XMM14, -2U },
  { X86::XMM15, -2U },
  { X86::XMM16, -2U },
  { X86::XMM17, -2U },
  { X86::XMM18, -2U },
  { X86::XMM19, -2U },
  { X86::XMM20, -2U },
  { X86::XMM21, -2U },
  { X86::XMM22, -2U },
  { X86::XMM23, -2U },
  { X86::XMM24, -2U },
  { X86::XMM25, -2U },
  { X86::XMM26, -2U },
  { X86::XMM27, -2U },
  { X86::XMM28, -2U },
  { X86::XMM29, -2U },
  { X86::XMM30, -2U },
  { X86::XMM31, -2U },
  { X86::YMM0, 21U },
  { X86::YMM1, 22U },
  { X86::YMM2, 23U },
  { X86::YMM3, 24U },
  { X86::YMM4, 25U },
  { X86::YMM5, 26U },
  { X86::YMM6, 27U },
  { X86::YMM7, 28U },
  { X86::YMM8, -2U },
  { X86::YMM9, -2U },
  { X86::YMM10, -2U },
  { X86::YMM11, -2U },
  { X86::YMM12, -2U },
  { X86::YMM13, -2U },
  { X86::YMM14, -2U },
  { X86::YMM15, -2U },
  { X86::YMM16, -2U },
  { X86::YMM17, -2U },
  { X86::YMM18, -2U },
  { X86::YMM19, -2U },
  { X86::YMM20, -2U },
  { X86::YMM21, -2U },
  { X86::YMM22, -2U },
  { X86::YMM23, -2U },
  { X86::YMM24, -2U },
  { X86::YMM25, -2U },
  { X86::YMM26, -2U },
  { X86::YMM27, -2U },
  { X86::YMM28, -2U },
  { X86::YMM29, -2U },
  { X86::YMM30, -2U },
  { X86::YMM31, -2U },
  { X86::ZMM0, 21U },
  { X86::ZMM1, 22U },
  { X86::ZMM2, 23U },
  { X86::ZMM3, 24U },
  { X86::ZMM4, 25U },
  { X86::ZMM5, 26U },
  { X86::ZMM6, 27U },
  { X86::ZMM7, 28U },
  { X86::ZMM8, -2U },
  { X86::ZMM9, -2U },
  { X86::ZMM10, -2U },
  { X86::ZMM11, -2U },
  { X86::ZMM12, -2U },
  { X86::ZMM13, -2U },
  { X86::ZMM14, -2U },
  { X86::ZMM15, -2U },
  { X86::ZMM16, -2U },
  { X86::ZMM17, -2U },
  { X86::ZMM18, -2U },
  { X86::ZMM19, -2U },
  { X86::ZMM20, -2U },
  { X86::ZMM21, -2U },
  { X86::ZMM22, -2U },
  { X86::ZMM23, -2U },
  { X86::ZMM24, -2U },
  { X86::ZMM25, -2U },
  { X86::ZMM26, -2U },
  { X86::ZMM27, -2U },
  { X86::ZMM28, -2U },
  { X86::ZMM29, -2U },
  { X86::ZMM30, -2U },
  { X86::ZMM31, -2U },
};
extern const unsigned X86DwarfFlavour1L2DwarfSize = array_lengthof(X86DwarfFlavour1L2Dwarf);

extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[] = {
  { X86::EAX, 0U },
  { X86::EBP, 5U },
  { X86::EBX, 3U },
  { X86::ECX, 1U },
  { X86::EDI, 7U },
  { X86::EDX, 2U },
  { X86::EIP, 8U },
  { X86::ESI, 6U },
  { X86::ESP, 4U },
  { X86::RAX, -2U },
  { X86::RBP, -2U },
  { X86::RBX, -2U },
  { X86::RCX, -2U },
  { X86::RDI, -2U },
  { X86::RDX, -2U },
  { X86::RIP, -2U },
  { X86::RSI, -2U },
  { X86::RSP, -2U },
  { X86::K0, 93U },
  { X86::K1, 94U },
  { X86::K2, 95U },
  { X86::K3, 96U },
  { X86::K4, 97U },
  { X86::K5, 98U },
  { X86::K6, 99U },
  { X86::K7, 100U },
  { X86::MM0, 29U },
  { X86::MM1, 30U },
  { X86::MM2, 31U },
  { X86::MM3, 32U },
  { X86::MM4, 33U },
  { X86::MM5, 34U },
  { X86::MM6, 35U },
  { X86::MM7, 36U },
  { X86::R8, -2U },
  { X86::R9, -2U },
  { X86::R10, -2U },
  { X86::R11, -2U },
  { X86::R12, -2U },
  { X86::R13, -2U },
  { X86::R14, -2U },
  { X86::R15, -2U },
  { X86::ST0, 11U },
  { X86::ST1, 12U },
  { X86::ST2, 13U },
  { X86::ST3, 14U },
  { X86::ST4, 15U },
  { X86::ST5, 16U },
  { X86::ST6, 17U },
  { X86::ST7, 18U },
  { X86::XMM0, 21U },
  { X86::XMM1, 22U },
  { X86::XMM2, 23U },
  { X86::XMM3, 24U },
  { X86::XMM4, 25U },
  { X86::XMM5, 26U },
  { X86::XMM6, 27U },
  { X86::XMM7, 28U },
  { X86::XMM8, -2U },
  { X86::XMM9, -2U },
  { X86::XMM10, -2U },
  { X86::XMM11, -2U },
  { X86::XMM12, -2U },
  { X86::XMM13, -2U },
  { X86::XMM14, -2U },
  { X86::XMM15, -2U },
  { X86::XMM16, -2U },
  { X86::XMM17, -2U },
  { X86::XMM18, -2U },
  { X86::XMM19, -2U },
  { X86::XMM20, -2U },
  { X86::XMM21, -2U },
  { X86::XMM22, -2U },
  { X86::XMM23, -2U },
  { X86::XMM24, -2U },
  { X86::XMM25, -2U },
  { X86::XMM26, -2U },
  { X86::XMM27, -2U },
  { X86::XMM28, -2U },
  { X86::XMM29, -2U },
  { X86::XMM30, -2U },
  { X86::XMM31, -2U },
  { X86::YMM0, 21U },
  { X86::YMM1, 22U },
  { X86::YMM2, 23U },
  { X86::YMM3, 24U },
  { X86::YMM4, 25U },
  { X86::YMM5, 26U },
  { X86::YMM6, 27U },
  { X86::YMM7, 28U },
  { X86::YMM8, -2U },
  { X86::YMM9, -2U },
  { X86::YMM10, -2U },
  { X86::YMM11, -2U },
  { X86::YMM12, -2U },
  { X86::YMM13, -2U },
  { X86::YMM14, -2U },
  { X86::YMM15, -2U },
  { X86::YMM16, -2U },
  { X86::YMM17, -2U },
  { X86::YMM18, -2U },
  { X86::YMM19, -2U },
  { X86::YMM20, -2U },
  { X86::YMM21, -2U },
  { X86::YMM22, -2U },
  { X86::YMM23, -2U },
  { X86::YMM24, -2U },
  { X86::YMM25, -2U },
  { X86::YMM26, -2U },
  { X86::YMM27, -2U },
  { X86::YMM28, -2U },
  { X86::YMM29, -2U },
  { X86::YMM30, -2U },
  { X86::YMM31, -2U },
  { X86::ZMM0, 21U },
  { X86::ZMM1, 22U },
  { X86::ZMM2, 23U },
  { X86::ZMM3, 24U },
  { X86::ZMM4, 25U },
  { X86::ZMM5, 26U },
  { X86::ZMM6, 27U },
  { X86::ZMM7, 28U },
  { X86::ZMM8, -2U },
  { X86::ZMM9, -2U },
  { X86::ZMM10, -2U },
  { X86::ZMM11, -2U },
  { X86::ZMM12, -2U },
  { X86::ZMM13, -2U },
  { X86::ZMM14, -2U },
  { X86::ZMM15, -2U },
  { X86::ZMM16, -2U },
  { X86::ZMM17, -2U },
  { X86::ZMM18, -2U },
  { X86::ZMM19, -2U },
  { X86::ZMM20, -2U },
  { X86::ZMM21, -2U },
  { X86::ZMM22, -2U },
  { X86::ZMM23, -2U },
  { X86::ZMM24, -2U },
  { X86::ZMM25, -2U },
  { X86::ZMM26, -2U },
  { X86::ZMM27, -2U },
  { X86::ZMM28, -2U },
  { X86::ZMM29, -2U },
  { X86::ZMM30, -2U },
  { X86::ZMM31, -2U },
};
extern const unsigned X86DwarfFlavour2L2DwarfSize = array_lengthof(X86DwarfFlavour2L2Dwarf);

extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[] = {
  { X86::EAX, -2U },
  { X86::EBP, -2U },
  { X86::EBX, -2U },
  { X86::ECX, -2U },
  { X86::EDI, -2U },
  { X86::EDX, -2U },
  { X86::EIP, -2U },
  { X86::ESI, -2U },
  { X86::ESP, -2U },
  { X86::RAX, 0U },
  { X86::RBP, 6U },
  { X86::RBX, 3U },
  { X86::RCX, 2U },
  { X86::RDI, 5U },
  { X86::RDX, 1U },
  { X86::RIP, 16U },
  { X86::RSI, 4U },
  { X86::RSP, 7U },
  { X86::K0, 118U },
  { X86::K1, 119U },
  { X86::K2, 120U },
  { X86::K3, 121U },
  { X86::K4, 122U },
  { X86::K5, 123U },
  { X86::K6, 124U },
  { X86::K7, 125U },
  { X86::MM0, 41U },
  { X86::MM1, 42U },
  { X86::MM2, 43U },
  { X86::MM3, 44U },
  { X86::MM4, 45U },
  { X86::MM5, 46U },
  { X86::MM6, 47U },
  { X86::MM7, 48U },
  { X86::R8, 8U },
  { X86::R9, 9U },
  { X86::R10, 10U },
  { X86::R11, 11U },
  { X86::R12, 12U },
  { X86::R13, 13U },
  { X86::R14, 14U },
  { X86::R15, 15U },
  { X86::ST0, 33U },
  { X86::ST1, 34U },
  { X86::ST2, 35U },
  { X86::ST3, 36U },
  { X86::ST4, 37U },
  { X86::ST5, 38U },
  { X86::ST6, 39U },
  { X86::ST7, 40U },
  { X86::XMM0, 17U },
  { X86::XMM1, 18U },
  { X86::XMM2, 19U },
  { X86::XMM3, 20U },
  { X86::XMM4, 21U },
  { X86::XMM5, 22U },
  { X86::XMM6, 23U },
  { X86::XMM7, 24U },
  { X86::XMM8, 25U },
  { X86::XMM9, 26U },
  { X86::XMM10, 27U },
  { X86::XMM11, 28U },
  { X86::XMM12, 29U },
  { X86::XMM13, 30U },
  { X86::XMM14, 31U },
  { X86::XMM15, 32U },
  { X86::XMM16, 67U },
  { X86::XMM17, 68U },
  { X86::XMM18, 69U },
  { X86::XMM19, 70U },
  { X86::XMM20, 71U },
  { X86::XMM21, 72U },
  { X86::XMM22, 73U },
  { X86::XMM23, 74U },
  { X86::XMM24, 75U },
  { X86::XMM25, 76U },
  { X86::XMM26, 77U },
  { X86::XMM27, 78U },
  { X86::XMM28, 79U },
  { X86::XMM29, 80U },
  { X86::XMM30, 81U },
  { X86::XMM31, 82U },
  { X86::YMM0, 17U },
  { X86::YMM1, 18U },
  { X86::YMM2, 19U },
  { X86::YMM3, 20U },
  { X86::YMM4, 21U },
  { X86::YMM5, 22U },
  { X86::YMM6, 23U },
  { X86::YMM7, 24U },
  { X86::YMM8, 25U },
  { X86::YMM9, 26U },
  { X86::YMM10, 27U },
  { X86::YMM11, 28U },
  { X86::YMM12, 29U },
  { X86::YMM13, 30U },
  { X86::YMM14, 31U },
  { X86::YMM15, 32U },
  { X86::YMM16, 67U },
  { X86::YMM17, 68U },
  { X86::YMM18, 69U },
  { X86::YMM19, 70U },
  { X86::YMM20, 71U },
  { X86::YMM21, 72U },
  { X86::YMM22, 73U },
  { X86::YMM23, 74U },
  { X86::YMM24, 75U },
  { X86::YMM25, 76U },
  { X86::YMM26, 77U },
  { X86::YMM27, 78U },
  { X86::YMM28, 79U },
  { X86::YMM29, 80U },
  { X86::YMM30, 81U },
  { X86::YMM31, 82U },
  { X86::ZMM0, 17U },
  { X86::ZMM1, 18U },
  { X86::ZMM2, 19U },
  { X86::ZMM3, 20U },
  { X86::ZMM4, 21U },
  { X86::ZMM5, 22U },
  { X86::ZMM6, 23U },
  { X86::ZMM7, 24U },
  { X86::ZMM8, 25U },
  { X86::ZMM9, 26U },
  { X86::ZMM10, 27U },
  { X86::ZMM11, 28U },
  { X86::ZMM12, 29U },
  { X86::ZMM13, 30U },
  { X86::ZMM14, 31U },
  { X86::ZMM15, 32U },
  { X86::ZMM16, 67U },
  { X86::ZMM17, 68U },
  { X86::ZMM18, 69U },
  { X86::ZMM19, 70U },
  { X86::ZMM20, 71U },
  { X86::ZMM21, 72U },
  { X86::ZMM22, 73U },
  { X86::ZMM23, 74U },
  { X86::ZMM24, 75U },
  { X86::ZMM25, 76U },
  { X86::ZMM26, 77U },
  { X86::ZMM27, 78U },
  { X86::ZMM28, 79U },
  { X86::ZMM29, 80U },
  { X86::ZMM30, 81U },
  { X86::ZMM31, 82U },
};
extern const unsigned X86EHFlavour0L2DwarfSize = array_lengthof(X86EHFlavour0L2Dwarf);

extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[] = {
  { X86::EAX, 0U },
  { X86::EBP, 4U },
  { X86::EBX, 3U },
  { X86::ECX, 1U },
  { X86::EDI, 7U },
  { X86::EDX, 2U },
  { X86::EIP, 8U },
  { X86::ESI, 6U },
  { X86::ESP, 5U },
  { X86::RAX, -2U },
  { X86::RBP, -2U },
  { X86::RBX, -2U },
  { X86::RCX, -2U },
  { X86::RDI, -2U },
  { X86::RDX, -2U },
  { X86::RIP, -2U },
  { X86::RSI, -2U },
  { X86::RSP, -2U },
  { X86::K0, 93U },
  { X86::K1, 94U },
  { X86::K2, 95U },
  { X86::K3, 96U },
  { X86::K4, 97U },
  { X86::K5, 98U },
  { X86::K6, 99U },
  { X86::K7, 100U },
  { X86::MM0, 29U },
  { X86::MM1, 30U },
  { X86::MM2, 31U },
  { X86::MM3, 32U },
  { X86::MM4, 33U },
  { X86::MM5, 34U },
  { X86::MM6, 35U },
  { X86::MM7, 36U },
  { X86::R8, -2U },
  { X86::R9, -2U },
  { X86::R10, -2U },
  { X86::R11, -2U },
  { X86::R12, -2U },
  { X86::R13, -2U },
  { X86::R14, -2U },
  { X86::R15, -2U },
  { X86::ST0, 12U },
  { X86::ST1, 13U },
  { X86::ST2, 14U },
  { X86::ST3, 15U },
  { X86::ST4, 16U },
  { X86::ST5, 17U },
  { X86::ST6, 18U },
  { X86::ST7, 19U },
  { X86::XMM0, 21U },
  { X86::XMM1, 22U },
  { X86::XMM2, 23U },
  { X86::XMM3, 24U },
  { X86::XMM4, 25U },
  { X86::XMM5, 26U },
  { X86::XMM6, 27U },
  { X86::XMM7, 28U },
  { X86::XMM8, -2U },
  { X86::XMM9, -2U },
  { X86::XMM10, -2U },
  { X86::XMM11, -2U },
  { X86::XMM12, -2U },
  { X86::XMM13, -2U },
  { X86::XMM14, -2U },
  { X86::XMM15, -2U },
  { X86::XMM16, -2U },
  { X86::XMM17, -2U },
  { X86::XMM18, -2U },
  { X86::XMM19, -2U },
  { X86::XMM20, -2U },
  { X86::XMM21, -2U },
  { X86::XMM22, -2U },
  { X86::XMM23, -2U },
  { X86::XMM24, -2U },
  { X86::XMM25, -2U },
  { X86::XMM26, -2U },
  { X86::XMM27, -2U },
  { X86::XMM28, -2U },
  { X86::XMM29, -2U },
  { X86::XMM30, -2U },
  { X86::XMM31, -2U },
  { X86::YMM0, 21U },
  { X86::YMM1, 22U },
  { X86::YMM2, 23U },
  { X86::YMM3, 24U },
  { X86::YMM4, 25U },
  { X86::YMM5, 26U },
  { X86::YMM6, 27U },
  { X86::YMM7, 28U },
  { X86::YMM8, -2U },
  { X86::YMM9, -2U },
  { X86::YMM10, -2U },
  { X86::YMM11, -2U },
  { X86::YMM12, -2U },
  { X86::YMM13, -2U },
  { X86::YMM14, -2U },
  { X86::YMM15, -2U },
  { X86::YMM16, -2U },
  { X86::YMM17, -2U },
  { X86::YMM18, -2U },
  { X86::YMM19, -2U },
  { X86::YMM20, -2U },
  { X86::YMM21, -2U },
  { X86::YMM22, -2U },
  { X86::YMM23, -2U },
  { X86::YMM24, -2U },
  { X86::YMM25, -2U },
  { X86::YMM26, -2U },
  { X86::YMM27, -2U },
  { X86::YMM28, -2U },
  { X86::YMM29, -2U },
  { X86::YMM30, -2U },
  { X86::YMM31, -2U },
  { X86::ZMM0, 21U },
  { X86::ZMM1, 22U },
  { X86::ZMM2, 23U },
  { X86::ZMM3, 24U },
  { X86::ZMM4, 25U },
  { X86::ZMM5, 26U },
  { X86::ZMM6, 27U },
  { X86::ZMM7, 28U },
  { X86::ZMM8, -2U },
  { X86::ZMM9, -2U },
  { X86::ZMM10, -2U },
  { X86::ZMM11, -2U },
  { X86::ZMM12, -2U },
  { X86::ZMM13, -2U },
  { X86::ZMM14, -2U },
  { X86::ZMM15, -2U },
  { X86::ZMM16, -2U },
  { X86::ZMM17, -2U },
  { X86::ZMM18, -2U },
  { X86::ZMM19, -2U },
  { X86::ZMM20, -2U },
  { X86::ZMM21, -2U },
  { X86::ZMM22, -2U },
  { X86::ZMM23, -2U },
  { X86::ZMM24, -2U },
  { X86::ZMM25, -2U },
  { X86::ZMM26, -2U },
  { X86::ZMM27, -2U },
  { X86::ZMM28, -2U },
  { X86::ZMM29, -2U },
  { X86::ZMM30, -2U },
  { X86::ZMM31, -2U },
};
extern const unsigned X86EHFlavour1L2DwarfSize = array_lengthof(X86EHFlavour1L2Dwarf);

extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[] = {
  { X86::EAX, 0U },
  { X86::EBP, 5U },
  { X86::EBX, 3U },
  { X86::ECX, 1U },
  { X86::EDI, 7U },
  { X86::EDX, 2U },
  { X86::EIP, 8U },
  { X86::ESI, 6U },
  { X86::ESP, 4U },
  { X86::RAX, -2U },
  { X86::RBP, -2U },
  { X86::RBX, -2U },
  { X86::RCX, -2U },
  { X86::RDI, -2U },
  { X86::RDX, -2U },
  { X86::RIP, -2U },
  { X86::RSI, -2U },
  { X86::RSP, -2U },
  { X86::K0, 93U },
  { X86::K1, 94U },
  { X86::K2, 95U },
  { X86::K3, 96U },
  { X86::K4, 97U },
  { X86::K5, 98U },
  { X86::K6, 99U },
  { X86::K7, 100U },
  { X86::MM0, 29U },
  { X86::MM1, 30U },
  { X86::MM2, 31U },
  { X86::MM3, 32U },
  { X86::MM4, 33U },
  { X86::MM5, 34U },
  { X86::MM6, 35U },
  { X86::MM7, 36U },
  { X86::R8, -2U },
  { X86::R9, -2U },
  { X86::R10, -2U },
  { X86::R11, -2U },
  { X86::R12, -2U },
  { X86::R13, -2U },
  { X86::R14, -2U },
  { X86::R15, -2U },
  { X86::ST0, 11U },
  { X86::ST1, 12U },
  { X86::ST2, 13U },
  { X86::ST3, 14U },
  { X86::ST4, 15U },
  { X86::ST5, 16U },
  { X86::ST6, 17U },
  { X86::ST7, 18U },
  { X86::XMM0, 21U },
  { X86::XMM1, 22U },
  { X86::XMM2, 23U },
  { X86::XMM3, 24U },
  { X86::XMM4, 25U },
  { X86::XMM5, 26U },
  { X86::XMM6, 27U },
  { X86::XMM7, 28U },
  { X86::XMM8, -2U },
  { X86::XMM9, -2U },
  { X86::XMM10, -2U },
  { X86::XMM11, -2U },
  { X86::XMM12, -2U },
  { X86::XMM13, -2U },
  { X86::XMM14, -2U },
  { X86::XMM15, -2U },
  { X86::XMM16, -2U },
  { X86::XMM17, -2U },
  { X86::XMM18, -2U },
  { X86::XMM19, -2U },
  { X86::XMM20, -2U },
  { X86::XMM21, -2U },
  { X86::XMM22, -2U },
  { X86::XMM23, -2U },
  { X86::XMM24, -2U },
  { X86::XMM25, -2U },
  { X86::XMM26, -2U },
  { X86::XMM27, -2U },
  { X86::XMM28, -2U },
  { X86::XMM29, -2U },
  { X86::XMM30, -2U },
  { X86::XMM31, -2U },
  { X86::YMM0, 21U },
  { X86::YMM1, 22U },
  { X86::YMM2, 23U },
  { X86::YMM3, 24U },
  { X86::YMM4, 25U },
  { X86::YMM5, 26U },
  { X86::YMM6, 27U },
  { X86::YMM7, 28U },
  { X86::YMM8, -2U },
  { X86::YMM9, -2U },
  { X86::YMM10, -2U },
  { X86::YMM11, -2U },
  { X86::YMM12, -2U },
  { X86::YMM13, -2U },
  { X86::YMM14, -2U },
  { X86::YMM15, -2U },
  { X86::YMM16, -2U },
  { X86::YMM17, -2U },
  { X86::YMM18, -2U },
  { X86::YMM19, -2U },
  { X86::YMM20, -2U },
  { X86::YMM21, -2U },
  { X86::YMM22, -2U },
  { X86::YMM23, -2U },
  { X86::YMM24, -2U },
  { X86::YMM25, -2U },
  { X86::YMM26, -2U },
  { X86::YMM27, -2U },
  { X86::YMM28, -2U },
  { X86::YMM29, -2U },
  { X86::YMM30, -2U },
  { X86::YMM31, -2U },
  { X86::ZMM0, 21U },
  { X86::ZMM1, 22U },
  { X86::ZMM2, 23U },
  { X86::ZMM3, 24U },
  { X86::ZMM4, 25U },
  { X86::ZMM5, 26U },
  { X86::ZMM6, 27U },
  { X86::ZMM7, 28U },
  { X86::ZMM8, -2U },
  { X86::ZMM9, -2U },
  { X86::ZMM10, -2U },
  { X86::ZMM11, -2U },
  { X86::ZMM12, -2U },
  { X86::ZMM13, -2U },
  { X86::ZMM14, -2U },
  { X86::ZMM15, -2U },
  { X86::ZMM16, -2U },
  { X86::ZMM17, -2U },
  { X86::ZMM18, -2U },
  { X86::ZMM19, -2U },
  { X86::ZMM20, -2U },
  { X86::ZMM21, -2U },
  { X86::ZMM22, -2U },
  { X86::ZMM23, -2U },
  { X86::ZMM24, -2U },
  { X86::ZMM25, -2U },
  { X86::ZMM26, -2U },
  { X86::ZMM27, -2U },
  { X86::ZMM28, -2U },
  { X86::ZMM29, -2U },
  { X86::ZMM30, -2U },
  { X86::ZMM31, -2U },
};
extern const unsigned X86EHFlavour2L2DwarfSize = array_lengthof(X86EHFlavour2L2Dwarf);

extern const uint16_t X86RegEncodingTable[] = {
  0,
  4,
  0,
  0,
  7,
  3,
  5,
  65535,
  5,
  3,
  5,
  1,
  1,
  1,
  0,
  6,
  7,
  65535,
  7,
  2,
  3,
  2,
  0,
  5,
  3,
  1,
  7,
  2,
  0,
  0,
  4,
  0,
  6,
  4,
  0,
  0,
  4,
  5,
  65535,
  65535,
  65535,
  65535,
  65535,
  65535,
  65535,
  65535,
  65535,
  0,
  0,
  0,
  5,
  3,
  1,
  7,
  2,
  0,
  4,
  6,
  4,
  6,
  65535,
  6,
  4,
  65535,
  4,
  2,
  0,
  0,
  1,
  2,
  3,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  65535,
  65535,
  65535,
  65535,
  65535,
  65535,
  65535,
  65535,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  65535,
  65535,
  65535,
  65535,
  65535,
  65535,
  65535,
  65535,
  0,
  2,
  4,
  6,
};
static inline void InitX86MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
  RI->InitMCRegisterInfo(X86RegDesc, 283, RA, PC, X86MCRegisterClasses, 118, X86RegUnitRoots, 164, X86RegDiffLists, X86LaneMaskLists, X86RegStrings, X86RegClassStrings, X86SubRegIdxLists, 11,
X86SubRegIdxRanges, X86RegEncodingTable);

  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour0Dwarf2L, X86DwarfFlavour0Dwarf2LSize, false);
    break;
  case 1:
    RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour1Dwarf2L, X86DwarfFlavour1Dwarf2LSize, false);
    break;
  case 2:
    RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour2Dwarf2L, X86DwarfFlavour2Dwarf2LSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapDwarfRegsToLLVMRegs(X86EHFlavour0Dwarf2L, X86EHFlavour0Dwarf2LSize, true);
    break;
  case 1:
    RI->mapDwarfRegsToLLVMRegs(X86EHFlavour1Dwarf2L, X86EHFlavour1Dwarf2LSize, true);
    break;
  case 2:
    RI->mapDwarfRegsToLLVMRegs(X86EHFlavour2Dwarf2L, X86EHFlavour2Dwarf2LSize, true);
    break;
  }
  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour0L2Dwarf, X86DwarfFlavour0L2DwarfSize, false);
    break;
  case 1:
    RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour1L2Dwarf, X86DwarfFlavour1L2DwarfSize, false);
    break;
  case 2:
    RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour2L2Dwarf, X86DwarfFlavour2L2DwarfSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapLLVMRegsToDwarfRegs(X86EHFlavour0L2Dwarf, X86EHFlavour0L2DwarfSize, true);
    break;
  case 1:
    RI->mapLLVMRegsToDwarfRegs(X86EHFlavour1L2Dwarf, X86EHFlavour1L2DwarfSize, true);
    break;
  case 2:
    RI->mapLLVMRegsToDwarfRegs(X86EHFlavour2L2Dwarf, X86EHFlavour2L2DwarfSize, true);
    break;
  }
}

} // end namespace llvm

#endif // GET_REGINFO_MC_DESC

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Register Information Header Fragment                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_HEADER
#undef GET_REGINFO_HEADER

#include "llvm/CodeGen/TargetRegisterInfo.h"

namespace llvm {

class X86FrameLowering;

struct X86GenRegisterInfo : public TargetRegisterInfo {
  explicit X86GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
      unsigned PC = 0, unsigned HwMode = 0);
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
  unsigned getNumRegPressureSets() const override;
  const char *getRegPressureSetName(unsigned Idx) const override;
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
  ArrayRef<const char *> getRegMaskNames() const override;
  ArrayRef<const uint32_t *> getRegMasks() const override;
  /// Devirtualized TargetFrameLowering.
  static const X86FrameLowering *getFrameLowering(
      const MachineFunction &MF);
};

namespace X86 { // Register classes
  extern const TargetRegisterClass GR8RegClass;
  extern const TargetRegisterClass GRH8RegClass;
  extern const TargetRegisterClass GR8_NOREXRegClass;
  extern const TargetRegisterClass GR8_ABCD_HRegClass;
  extern const TargetRegisterClass GR8_ABCD_LRegClass;
  extern const TargetRegisterClass GRH16RegClass;
  extern const TargetRegisterClass GR16RegClass;
  extern const TargetRegisterClass GR16_NOREXRegClass;
  extern const TargetRegisterClass VK1RegClass;
  extern const TargetRegisterClass VK16RegClass;
  extern const TargetRegisterClass VK2RegClass;
  extern const TargetRegisterClass VK4RegClass;
  extern const TargetRegisterClass VK8RegClass;
  extern const TargetRegisterClass VK16WMRegClass;
  extern const TargetRegisterClass VK1WMRegClass;
  extern const TargetRegisterClass VK2WMRegClass;
  extern const TargetRegisterClass VK4WMRegClass;
  extern const TargetRegisterClass VK8WMRegClass;
  extern const TargetRegisterClass SEGMENT_REGRegClass;
  extern const TargetRegisterClass GR16_ABCDRegClass;
  extern const TargetRegisterClass FPCCRRegClass;
  extern const TargetRegisterClass VK16PAIRRegClass;
  extern const TargetRegisterClass VK1PAIRRegClass;
  extern const TargetRegisterClass VK2PAIRRegClass;
  extern const TargetRegisterClass VK4PAIRRegClass;
  extern const TargetRegisterClass VK8PAIRRegClass;
  extern const TargetRegisterClass VK16PAIR_with_sub_mask_0_in_VK16WMRegClass;
  extern const TargetRegisterClass FR32XRegClass;
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBPRegClass;
  extern const TargetRegisterClass LOW32_ADDR_ACCESSRegClass;
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass;
  extern const TargetRegisterClass DEBUG_REGRegClass;
  extern const TargetRegisterClass FR32RegClass;
  extern const TargetRegisterClass GR32RegClass;
  extern const TargetRegisterClass GR32_NOSPRegClass;
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass;
  extern const TargetRegisterClass GR32_NOREXRegClass;
  extern const TargetRegisterClass VK32RegClass;
  extern const TargetRegisterClass GR32_NOREX_NOSPRegClass;
  extern const TargetRegisterClass RFP32RegClass;
  extern const TargetRegisterClass VK32WMRegClass;
  extern const TargetRegisterClass GR32_ABCDRegClass;
  extern const TargetRegisterClass GR32_TCRegClass;
  extern const TargetRegisterClass GR32_ABCD_and_GR32_TCRegClass;
  extern const TargetRegisterClass GR32_ADRegClass;
  extern const TargetRegisterClass GR32_BPSPRegClass;
  extern const TargetRegisterClass GR32_BSIRegClass;
  extern const TargetRegisterClass GR32_CBRegClass;
  extern const TargetRegisterClass GR32_DCRegClass;
  extern const TargetRegisterClass GR32_DIBPRegClass;
  extern const TargetRegisterClass GR32_SIDIRegClass;
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass;
  extern const TargetRegisterClass CCRRegClass;
  extern const TargetRegisterClass DFCCRRegClass;
  extern const TargetRegisterClass GR32_ABCD_and_GR32_BSIRegClass;
  extern const TargetRegisterClass GR32_AD_and_GR32_DCRegClass;
  extern const TargetRegisterClass GR32_BPSP_and_GR32_DIBPRegClass;
  extern const TargetRegisterClass GR32_BPSP_and_GR32_TCRegClass;
  extern const TargetRegisterClass GR32_BSI_and_GR32_SIDIRegClass;
  extern const TargetRegisterClass GR32_CB_and_GR32_DCRegClass;
  extern const TargetRegisterClass GR32_DIBP_and_GR32_SIDIRegClass;
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass;
  extern const TargetRegisterClass LOW32_ADDR_ACCESS_with_sub_32bitRegClass;
  extern const TargetRegisterClass RFP64RegClass;
  extern const TargetRegisterClass FR64XRegClass;
  extern const TargetRegisterClass GR64RegClass;
  extern const TargetRegisterClass CONTROL_REGRegClass;
  extern const TargetRegisterClass FR64RegClass;
  extern const TargetRegisterClass GR64_with_sub_8bitRegClass;
  extern const TargetRegisterClass GR64_NOSPRegClass;
  extern const TargetRegisterClass GR64_TCRegClass;
  extern const TargetRegisterClass GR64_NOREXRegClass;
  extern const TargetRegisterClass GR64_TCW64RegClass;
  extern const TargetRegisterClass GR64_TC_with_sub_8bitRegClass;
  extern const TargetRegisterClass GR64_NOSP_and_GR64_TCRegClass;
  extern const TargetRegisterClass GR64_TCW64_with_sub_8bitRegClass;
  extern const TargetRegisterClass GR64_TC_and_GR64_TCW64RegClass;
  extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREXRegClass;
  extern const TargetRegisterClass VK64RegClass;
  extern const TargetRegisterClass VR64RegClass;
  extern const TargetRegisterClass GR64_NOREX_NOSPRegClass;
  extern const TargetRegisterClass GR64_NOREX_and_GR64_TCRegClass;
  extern const TargetRegisterClass GR64_NOSP_and_GR64_TCW64RegClass;
  extern const TargetRegisterClass GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass;
  extern const TargetRegisterClass VK64WMRegClass;
  extern const TargetRegisterClass GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass;
  extern const TargetRegisterClass GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass;
  extern const TargetRegisterClass GR64_NOREX_NOSP_and_GR64_TCRegClass;
  extern const TargetRegisterClass GR64_NOREX_and_GR64_TCW64RegClass;
  extern const TargetRegisterClass GR64_ABCDRegClass;
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_TCRegClass;
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass;
  extern const TargetRegisterClass GR64_ADRegClass;
  extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESS_RBPRegClass;
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSPRegClass;
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSIRegClass;
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CBRegClass;
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DCRegClass;
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBPRegClass;
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_SIDIRegClass;
  extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESSRegClass;
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass;
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClass;
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass;
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass;
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass;
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClass;
  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass;
  extern const TargetRegisterClass RSTRegClass;
  extern const TargetRegisterClass RFP80RegClass;
  extern const TargetRegisterClass RFP80_7RegClass;
  extern const TargetRegisterClass VR128XRegClass;
  extern const TargetRegisterClass VR128RegClass;
  extern const TargetRegisterClass BNDRRegClass;
  extern const TargetRegisterClass VR256XRegClass;
  extern const TargetRegisterClass VR256RegClass;
  extern const TargetRegisterClass VR512RegClass;
  extern const TargetRegisterClass VR512_0_15RegClass;
} // end namespace X86

} // end namespace llvm

#endif // GET_REGINFO_HEADER

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register and Register Classes Information                           *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_TARGET_DESC
#undef GET_REGINFO_TARGET_DESC

namespace llvm {

extern const MCRegisterClass X86MCRegisterClasses[];

static const MVT::SimpleValueType VTLists[] = {
  /* 0 */ MVT::i8, MVT::Other,
  /* 2 */ MVT::i16, MVT::Other,
  /* 4 */ MVT::i32, MVT::Other,
  /* 6 */ MVT::i64, MVT::Other,
  /* 8 */ MVT::f80, MVT::f64, MVT::f32, MVT::Other,
  /* 12 */ MVT::f64, MVT::Other,
  /* 14 */ MVT::f80, MVT::Other,
  /* 16 */ MVT::v4f32, MVT::v2f64, MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::f128, MVT::Other,
  /* 24 */ MVT::v1i1, MVT::Other,
  /* 26 */ MVT::v2i1, MVT::Other,
  /* 28 */ MVT::v4i1, MVT::Other,
  /* 30 */ MVT::v8i1, MVT::Other,
  /* 32 */ MVT::v16i1, MVT::Other,
  /* 34 */ MVT::v32i1, MVT::Other,
  /* 36 */ MVT::v64i1, MVT::Other,
  /* 38 */ MVT::v2i64, MVT::Other,
  /* 40 */ MVT::v8f32, MVT::v4f64, MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::Other,
  /* 47 */ MVT::v16f32, MVT::v8f64, MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, MVT::Other,
  /* 54 */ MVT::x86mmx, MVT::Other,
  /* 56 */ MVT::Untyped, MVT::Other,
};

static const char *const SubRegIndexNameTable[] = { "sub_8bit", "sub_8bit_hi", "sub_8bit_hi_phony", "sub_16bit", "sub_16bit_hi", "sub_32bit", "sub_mask_0", "sub_mask_1", "sub_xmm", "sub_ymm", "" };


static const LaneBitmask SubRegIndexLaneMaskTable[] = {
  LaneBitmask::getAll(),
  LaneBitmask(0x00000001), // sub_8bit
  LaneBitmask(0x00000002), // sub_8bit_hi
  LaneBitmask(0x00000004), // sub_8bit_hi_phony
  LaneBitmask(0x00000007), // sub_16bit
  LaneBitmask(0x00000008), // sub_16bit_hi
  LaneBitmask(0x0000000F), // sub_32bit
  LaneBitmask(0x00000010), // sub_mask_0
  LaneBitmask(0x00000020), // sub_mask_1
  LaneBitmask(0x00000040), // sub_xmm
  LaneBitmask(0x00000040), // sub_ymm
 };


static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
  // Mode = 0 (Default)
  { 8, 8, 8, VTLists+0 },    // GR8
  { 8, 8, 8, VTLists+0 },    // GRH8
  { 8, 8, 8, VTLists+0 },    // GR8_NOREX
  { 8, 8, 8, VTLists+0 },    // GR8_ABCD_H
  { 8, 8, 8, VTLists+0 },    // GR8_ABCD_L
  { 16, 16, 16, VTLists+2 },    // GRH16
  { 16, 16, 16, VTLists+2 },    // GR16
  { 16, 16, 16, VTLists+2 },    // GR16_NOREX
  { 16, 16, 16, VTLists+24 },    // VK1
  { 16, 16, 16, VTLists+32 },    // VK16
  { 16, 16, 16, VTLists+26 },    // VK2
  { 16, 16, 16, VTLists+28 },    // VK4
  { 16, 16, 16, VTLists+30 },    // VK8
  { 16, 16, 16, VTLists+32 },    // VK16WM
  { 16, 16, 16, VTLists+24 },    // VK1WM
  { 16, 16, 16, VTLists+26 },    // VK2WM
  { 16, 16, 16, VTLists+28 },    // VK4WM
  { 16, 16, 16, VTLists+30 },    // VK8WM
  { 16, 16, 16, VTLists+2 },    // SEGMENT_REG
  { 16, 16, 16, VTLists+2 },    // GR16_ABCD
  { 16, 16, 16, VTLists+2 },    // FPCCR
  { 32, 32, 16, VTLists+56 },    // VK16PAIR
  { 32, 32, 16, VTLists+56 },    // VK1PAIR
  { 32, 32, 16, VTLists+56 },    // VK2PAIR
  { 32, 32, 16, VTLists+56 },    // VK4PAIR
  { 32, 32, 16, VTLists+56 },    // VK8PAIR
  { 32, 32, 16, VTLists+56 },    // VK16PAIR_with_sub_mask_0_in_VK16WM
  { 32, 32, 32, VTLists+10 },    // FR32X
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
  { 32, 32, 32, VTLists+4 },    // DEBUG_REG
  { 32, 32, 32, VTLists+10 },    // FR32
  { 32, 32, 32, VTLists+4 },    // GR32
  { 32, 32, 32, VTLists+4 },    // GR32_NOSP
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
  { 32, 32, 32, VTLists+4 },    // GR32_NOREX
  { 32, 32, 32, VTLists+34 },    // VK32
  { 32, 32, 32, VTLists+4 },    // GR32_NOREX_NOSP
  { 32, 32, 32, VTLists+10 },    // RFP32
  { 32, 32, 32, VTLists+34 },    // VK32WM
  { 32, 32, 32, VTLists+4 },    // GR32_ABCD
  { 32, 32, 32, VTLists+4 },    // GR32_TC
  { 32, 32, 32, VTLists+4 },    // GR32_ABCD_and_GR32_TC
  { 32, 32, 32, VTLists+4 },    // GR32_AD
  { 32, 32, 32, VTLists+4 },    // GR32_BPSP
  { 32, 32, 32, VTLists+4 },    // GR32_BSI
  { 32, 32, 32, VTLists+4 },    // GR32_CB
  { 32, 32, 32, VTLists+4 },    // GR32_DC
  { 32, 32, 32, VTLists+4 },    // GR32_DIBP
  { 32, 32, 32, VTLists+4 },    // GR32_SIDI
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
  { 32, 32, 32, VTLists+4 },    // CCR
  { 32, 32, 32, VTLists+4 },    // DFCCR
  { 32, 32, 32, VTLists+4 },    // GR32_ABCD_and_GR32_BSI
  { 32, 32, 32, VTLists+4 },    // GR32_AD_and_GR32_DC
  { 32, 32, 32, VTLists+4 },    // GR32_BPSP_and_GR32_DIBP
  { 32, 32, 32, VTLists+4 },    // GR32_BPSP_and_GR32_TC
  { 32, 32, 32, VTLists+4 },    // GR32_BSI_and_GR32_SIDI
  { 32, 32, 32, VTLists+4 },    // GR32_CB_and_GR32_DC
  { 32, 32, 32, VTLists+4 },    // GR32_DIBP_and_GR32_SIDI
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
  { 32, 32, 32, VTLists+4 },    // LOW32_ADDR_ACCESS_with_sub_32bit
  { 64, 64, 32, VTLists+12 },    // RFP64
  { 64, 64, 64, VTLists+12 },    // FR64X
  { 64, 64, 64, VTLists+6 },    // GR64
  { 64, 64, 64, VTLists+6 },    // CONTROL_REG
  { 64, 64, 64, VTLists+12 },    // FR64
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_8bit
  { 64, 64, 64, VTLists+6 },    // GR64_NOSP
  { 64, 64, 64, VTLists+6 },    // GR64_TC
  { 64, 64, 64, VTLists+6 },    // GR64_NOREX
  { 64, 64, 64, VTLists+6 },    // GR64_TCW64
  { 64, 64, 64, VTLists+6 },    // GR64_TC_with_sub_8bit
  { 64, 64, 64, VTLists+6 },    // GR64_NOSP_and_GR64_TC
  { 64, 64, 64, VTLists+6 },    // GR64_TCW64_with_sub_8bit
  { 64, 64, 64, VTLists+6 },    // GR64_TC_and_GR64_TCW64
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_16bit_in_GR16_NOREX
  { 64, 64, 64, VTLists+36 },    // VK64
  { 64, 64, 64, VTLists+54 },    // VR64
  { 64, 64, 64, VTLists+6 },    // GR64_NOREX_NOSP
  { 64, 64, 64, VTLists+6 },    // GR64_NOREX_and_GR64_TC
  { 64, 64, 64, VTLists+6 },    // GR64_NOSP_and_GR64_TCW64
  { 64, 64, 64, VTLists+6 },    // GR64_TCW64_and_GR64_TC_with_sub_8bit
  { 64, 64, 64, VTLists+36 },    // VK64WM
  { 64, 64, 64, VTLists+6 },    // GR64_TC_and_GR64_NOSP_and_GR64_TCW64
  { 64, 64, 64, VTLists+6 },    // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
  { 64, 64, 64, VTLists+6 },    // GR64_NOREX_NOSP_and_GR64_TC
  { 64, 64, 64, VTLists+6 },    // GR64_NOREX_and_GR64_TCW64
  { 64, 64, 64, VTLists+6 },    // GR64_ABCD
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_TC
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
  { 64, 64, 64, VTLists+6 },    // GR64_AD
  { 64, 64, 64, VTLists+6 },    // GR64_and_LOW32_ADDR_ACCESS_RBP
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_BPSP
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_BSI
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_CB
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_DC
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_DIBP
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_SIDI
  { 64, 64, 64, VTLists+6 },    // GR64_and_LOW32_ADDR_ACCESS
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
  { 64, 64, 64, VTLists+6 },    // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
  { 80, 80, 32, VTLists+8 },    // RST
  { 80, 80, 32, VTLists+14 },    // RFP80
  { 80, 80, 32, VTLists+14 },    // RFP80_7
  { 128, 128, 128, VTLists+16 },    // VR128X
  { 128, 128, 128, VTLists+16 },    // VR128
  { 128, 128, 128, VTLists+38 },    // BNDR
  { 256, 256, 256, VTLists+40 },    // VR256X
  { 256, 256, 256, VTLists+40 },    // VR256
  { 512, 512, 512, VTLists+47 },    // VR512
  { 512, 512, 512, VTLists+47 },    // VR512_0_15
};

static const TargetRegisterClass *const NullRegClasses[] = { nullptr };

static const uint32_t GR8SubClassMask[] = {
  0x0000001d, 0x00000000, 0x00000000, 0x00000000, 
  0x400800c0, 0x3fc7fe5e, 0xdeed2e30, 0x00000fef, // sub_8bit
  0x00080000, 0x08c19a00, 0x1a000000, 0x00000463, // sub_8bit_hi
};

static const uint32_t GRH8SubClassMask[] = {
  0x00000002, 0x00000000, 0x00000000, 0x00000000, 
};

static const uint32_t GR8_NOREXSubClassMask[] = {
  0x0000001c, 0x00000000, 0x00000000, 0x00000000, 
  0x00080000, 0x08c19a00, 0x1a000000, 0x00000463, // sub_8bit
  0x00080000, 0x08c19a00, 0x1a000000, 0x00000463, // sub_8bit_hi
};

static const uint32_t GR8_ABCD_HSubClassMask[] = {
  0x00000008, 0x00000000, 0x00000000, 0x00000000, 
  0x00080000, 0x08c19a00, 0x1a000000, 0x00000463, // sub_8bit_hi
};

static const uint32_t GR8_ABCD_LSubClassMask[] = {
  0x00000010, 0x00000000, 0x00000000, 0x00000000, 
  0x00080000, 0x08c19a00, 0x1a000000, 0x00000463, // sub_8bit
};

static const uint32_t GRH16SubClassMask[] = {
  0x00000020, 0x00000000, 0x00000000, 0x00000000, 
};

static const uint32_t GR16SubClassMask[] = {
  0x000800c0, 0x00000000, 0x00000000, 0x00000000, 
  0x40000000, 0x3fc7fe5e, 0xdeed2e30, 0x00000fef, // sub_16bit
};

static const uint32_t GR16_NOREXSubClassMask[] = {
  0x00080080, 0x00000000, 0x00000000, 0x00000000, 
  0x00000000, 0x3fc7fe58, 0xdec12000, 0x00000fef, // sub_16bit
};

static const uint32_t VK1SubClassMask[] = {
  0x0003ff00, 0x00000120, 0x00104000, 0x00000000, 
  0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
  0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};

static const uint32_t VK16SubClassMask[] = {
  0x0003ff00, 0x00000120, 0x00104000, 0x00000000, 
  0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
  0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};

static const uint32_t VK2SubClassMask[] = {
  0x0003ff00, 0x00000120, 0x00104000, 0x00000000, 
  0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
  0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};

static const uint32_t VK4SubClassMask[] = {
  0x0003ff00, 0x00000120, 0x00104000, 0x00000000, 
  0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
  0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};

static const uint32_t VK8SubClassMask[] = {
  0x0003ff00, 0x00000120, 0x00104000, 0x00000000, 
  0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
  0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};

static const uint32_t VK16WMSubClassMask[] = {
  0x0003e000, 0x00000100, 0x00100000, 0x00000000, 
  0x04000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
  0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};

static const uint32_t VK1WMSubClassMask[] = {
  0x0003e000, 0x00000100, 0x00100000, 0x00000000, 
  0x04000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
  0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};

static const uint32_t VK2WMSubClassMask[] = {
  0x0003e000, 0x00000100, 0x00100000, 0x00000000, 
  0x04000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
  0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};

static const uint32_t VK4WMSubClassMask[] = {
  0x0003e000, 0x00000100, 0x00100000, 0x00000000, 
  0x04000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
  0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};

static const uint32_t VK8WMSubClassMask[] = {
  0x0003e000, 0x00000100, 0x00100000, 0x00000000, 
  0x04000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
  0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};

static const uint32_t SEGMENT_REGSubClassMask[] = {
  0x00040000, 0x00000000, 0x00000000, 0x00000000, 
};

static const uint32_t GR16_ABCDSubClassMask[] = {
  0x00080000, 0x00000000, 0x00000000, 0x00000000, 
  0x00000000, 0x08c19a00, 0x1a000000, 0x00000463, // sub_16bit
};

static const uint32_t FPCCRSubClassMask[] = {
  0x00100000, 0x00000000, 0x00000000, 0x00000000, 
};

static const uint32_t VK16PAIRSubClassMask[] = {
  0x07e00000, 0x00000000, 0x00000000, 0x00000000, 
};

static const uint32_t VK1PAIRSubClassMask[] = {
  0x07e00000, 0x00000000, 0x00000000, 0x00000000, 
};

static const uint32_t VK2PAIRSubClassMask[] = {
  0x07e00000, 0x00000000, 0x00000000, 0x00000000, 
};

static const uint32_t VK4PAIRSubClassMask[] = {
  0x07e00000, 0x00000000, 0x00000000, 0x00000000, 
};

static const uint32_t VK8PAIRSubClassMask[] = {
  0x07e00000, 0x00000000, 0x00000000, 0x00000000, 
};

static const uint32_t VK16PAIR_with_sub_mask_0_in_VK16WMSubClassMask[] = {
  0x04000000, 0x00000000, 0x00000000, 0x00000000, 
};

static const uint32_t FR32XSubClassMask[] = {
  0x08000000, 0x00000001, 0x00000009, 0x00018000, 
  0x00000000, 0x00000000, 0x00000000, 0x003c0000, // sub_xmm
};

static const uint32_t LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
  0x70000000, 0x7fcffe5e, 0x20000000, 0x00000090, 
  0x00000000, 0x20000000, 0xdeed2e30, 0x00000fef, // sub_32bit
};

static const uint32_t LOW32_ADDR_ACCESSSubClassMask[] = {
  0x20000000, 0x5fc7fe56, 0x00000000, 0x00000010, 
  0x00000000, 0x20000000, 0xdeed2e30, 0x00000fef, // sub_32bit
};

static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitSubClassMask[] = {
  0x40000000, 0x3fc7fe5e, 0x00000000, 0x00000080, 
  0x00000000, 0x20000000, 0xdeed2e30, 0x00000fef, // sub_32bit
};

static const uint32_t DEBUG_REGSubClassMask[] = {
  0x80000000, 0x00000000, 0x00000000, 0x00000000, 
};

static const uint32_t FR32SubClassMask[] = {
  0x00000000, 0x00000001, 0x00000008, 0x00010000, 
  0x00000000, 0x00000000, 0x00000000, 0x00280000, // sub_xmm
};

static const uint32_t GR32SubClassMask[] = {
  0x00000000, 0x1fc7fe56, 0x00000000, 0x00000000, 
  0x00000000, 0x20000000, 0xdeed2e30, 0x00000fef, // sub_32bit
};

static const uint32_t GR32_NOSPSubClassMask[] = {
  0x00000000, 0x1dc7da44, 0x00000000, 0x00000000, 
  0x00000000, 0x20000000, 0x9aa50420, 0x00000eef, // sub_32bit
};

static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
  0x00000000, 0x3fc7fe58, 0x00000000, 0x00000080, 
  0x00000000, 0x20000000, 0xdec12000, 0x00000fef, // sub_32bit
};

static const uint32_t GR32_NOREXSubClassMask[] = {
  0x00000000, 0x1fc7fe50, 0x00000000, 0x00000000, 
  0x00000000, 0x20000000, 0xdec12000, 0x00000fef, // sub_32bit
};

static const uint32_t VK32SubClassMask[] = {
  0x00000000, 0x00000120, 0x00104000, 0x00000000, 
  0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
  0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};

static const uint32_t GR32_NOREX_NOSPSubClassMask[] = {
  0x00000000, 0x1dc7da40, 0x00000000, 0x00000000, 
  0x00000000, 0x20000000, 0x9a810000, 0x00000eef, // sub_32bit
};

static const uint32_t RFP32SubClassMask[] = {
  0x00000000, 0x80000080, 0x00000000, 0x00002000, 
};

static const uint32_t VK32WMSubClassMask[] = {
  0x00000000, 0x00000100, 0x00100000, 0x00000000, 
  0x04000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
  0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};

static const uint32_t GR32_ABCDSubClassMask[] = {
  0x00000000, 0x08c19a00, 0x00000000, 0x00000000, 
  0x00000000, 0x00000000, 0x1a000000, 0x00000463, // sub_32bit
};

static const uint32_t GR32_TCSubClassMask[] = {
  0x00000000, 0x0a811c00, 0x00000000, 0x00000000, 
  0x00000000, 0x00000000, 0x1c000000, 0x00000542, // sub_32bit
};

static const uint32_t GR32_ABCD_and_GR32_TCSubClassMask[] = {
  0x00000000, 0x08811800, 0x00000000, 0x00000000, 
  0x00000000, 0x00000000, 0x18000000, 0x00000442, // sub_32bit
};

static const uint32_t GR32_ADSubClassMask[] = {
  0x00000000, 0x00801000, 0x00000000, 0x00000000, 
  0x00000000, 0x00000000, 0x10000000, 0x00000040, // sub_32bit
};

static const uint32_t GR32_BPSPSubClassMask[] = {
  0x00000000, 0x03002000, 0x00000000, 0x00000000, 
  0x00000000, 0x20000000, 0x40000000, 0x00000180, // sub_32bit
};

static const uint32_t GR32_BSISubClassMask[] = {
  0x00000000, 0x04404000, 0x00000000, 0x00000000, 
  0x00000000, 0x00000000, 0x80000000, 0x00000220, // sub_32bit
};

static const uint32_t GR32_CBSubClassMask[] = {
  0x00000000, 0x08408000, 0x00000000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x00000421, // sub_32bit
};

static const uint32_t GR32_DCSubClassMask[] = {
  0x00000000, 0x08810000, 0x00000000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x00000442, // sub_32bit
};

static const uint32_t GR32_DIBPSubClassMask[] = {
  0x00000000, 0x11020000, 0x00000000, 0x00000000, 
  0x00000000, 0x20000000, 0x00000000, 0x00000884, // sub_32bit
};

static const uint32_t GR32_SIDISubClassMask[] = {
  0x00000000, 0x14040000, 0x00000000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x00000a08, // sub_32bit
};

static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitSubClassMask[] = {
  0x00000000, 0x60080000, 0x20000000, 0x00000090, 
};

static const uint32_t CCRSubClassMask[] = {
  0x00000000, 0x00100000, 0x00000000, 0x00000000, 
};

static const uint32_t DFCCRSubClassMask[] = {
  0x00000000, 0x00200000, 0x00000000, 0x00000000, 
};

static const uint32_t GR32_ABCD_and_GR32_BSISubClassMask[] = {
  0x00000000, 0x00400000, 0x00000000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x00000020, // sub_32bit
};

static const uint32_t GR32_AD_and_GR32_DCSubClassMask[] = {
  0x00000000, 0x00800000, 0x00000000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x00000040, // sub_32bit
};

static const uint32_t GR32_BPSP_and_GR32_DIBPSubClassMask[] = {
  0x00000000, 0x01000000, 0x00000000, 0x00000000, 
  0x00000000, 0x20000000, 0x00000000, 0x00000080, // sub_32bit
};

static const uint32_t GR32_BPSP_and_GR32_TCSubClassMask[] = {
  0x00000000, 0x02000000, 0x00000000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x00000100, // sub_32bit
};

static const uint32_t GR32_BSI_and_GR32_SIDISubClassMask[] = {
  0x00000000, 0x04000000, 0x00000000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x00000200, // sub_32bit
};

static const uint32_t GR32_CB_and_GR32_DCSubClassMask[] = {
  0x00000000, 0x08000000, 0x00000000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x00000400, // sub_32bit
};

static const uint32_t GR32_DIBP_and_GR32_SIDISubClassMask[] = {
  0x00000000, 0x10000000, 0x00000000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000000, 0x00000800, // sub_32bit
};

static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSubClassMask[] = {
  0x00000000, 0x20000000, 0x00000000, 0x00000080, 
};

static const uint32_t LOW32_ADDR_ACCESS_with_sub_32bitSubClassMask[] = {
  0x00000000, 0x40000000, 0x00000000, 0x00000010, 
};

static const uint32_t RFP64SubClassMask[] = {
  0x00000000, 0x80000000, 0x00000000, 0x00002000, 
};

static const uint32_t FR64XSubClassMask[] = {
  0x00000000, 0x00000000, 0x00000009, 0x00018000, 
  0x00000000, 0x00000000, 0x00000000, 0x003c0000, // sub_xmm
};

static const uint32_t GR64SubClassMask[] = {
  0x00000000, 0x00000000, 0xffef3ff2, 0x00000fff, 
};

static const uint32_t CONTROL_REGSubClassMask[] = {
  0x00000000, 0x00000000, 0x00000004, 0x00000000, 
};

static const uint32_t FR64SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000008, 0x00010000, 
  0x00000000, 0x00000000, 0x00000000, 0x00280000, // sub_xmm
};

static const uint32_t GR64_with_sub_8bitSubClassMask[] = {
  0x00000000, 0x00000000, 0xdeed2e30, 0x00000fef, 
};

static const uint32_t GR64_NOSPSubClassMask[] = {
  0x00000000, 0x00000000, 0x9aa50420, 0x00000eef, 
};

static const uint32_t GR64_TCSubClassMask[] = {
  0x00000000, 0x00000000, 0x1dea1640, 0x00000f5a, 
};

static const uint32_t GR64_NOREXSubClassMask[] = {
  0x00000000, 0x00000000, 0xffc32080, 0x00000fff, 
};

static const uint32_t GR64_TCW64SubClassMask[] = {
  0x00000000, 0x00000000, 0x1d2c1900, 0x00000552, 
};

static const uint32_t GR64_TC_with_sub_8bitSubClassMask[] = {
  0x00000000, 0x00000000, 0x1ce80600, 0x00000f4a, 
};

static const uint32_t GR64_NOSP_and_GR64_TCSubClassMask[] = {
  0x00000000, 0x00000000, 0x18a00400, 0x00000e4a, 
};

static const uint32_t GR64_TCW64_with_sub_8bitSubClassMask[] = {
  0x00000000, 0x00000000, 0x1c2c0800, 0x00000542, 
};

static const uint32_t GR64_TC_and_GR64_TCW64SubClassMask[] = {
  0x00000000, 0x00000000, 0x1d281000, 0x00000552, 
};

static const uint32_t GR64_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
  0x00000000, 0x00000000, 0xdec12000, 0x00000fef, 
};

static const uint32_t VK64SubClassMask[] = {
  0x00000000, 0x00000000, 0x00104000, 0x00000000, 
  0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
  0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};

static const uint32_t VR64SubClassMask[] = {
  0x00000000, 0x00000000, 0x00008000, 0x00000000, 
};

static const uint32_t GR64_NOREX_NOSPSubClassMask[] = {
  0x00000000, 0x00000000, 0x9a810000, 0x00000eef, 
};

static const uint32_t GR64_NOREX_and_GR64_TCSubClassMask[] = {
  0x00000000, 0x00000000, 0x1dc20000, 0x00000f5a, 
};

static const uint32_t GR64_NOSP_and_GR64_TCW64SubClassMask[] = {
  0x00000000, 0x00000000, 0x18240000, 0x00000442, 
};

static const uint32_t GR64_TCW64_and_GR64_TC_with_sub_8bitSubClassMask[] = {
  0x00000000, 0x00000000, 0x1c280000, 0x00000542, 
};

static const uint32_t VK64WMSubClassMask[] = {
  0x00000000, 0x00000000, 0x00100000, 0x00000000, 
  0x04000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
  0x07e00000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};

static const uint32_t GR64_TC_and_GR64_NOSP_and_GR64_TCW64SubClassMask[] = {
  0x00000000, 0x00000000, 0x18200000, 0x00000442, 
};

static const uint32_t GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
  0x00000000, 0x00000000, 0x1cc00000, 0x00000f4a, 
};

static const uint32_t GR64_NOREX_NOSP_and_GR64_TCSubClassMask[] = {
  0x00000000, 0x00000000, 0x18800000, 0x00000e4a, 
};

static const uint32_t GR64_NOREX_and_GR64_TCW64SubClassMask[] = {
  0x00000000, 0x00000000, 0x1d000000, 0x00000552, 
};

static const uint32_t GR64_ABCDSubClassMask[] = {
  0x00000000, 0x00000000, 0x1a000000, 0x00000463, 
};

static const uint32_t GR64_with_sub_32bit_in_GR32_TCSubClassMask[] = {
  0x00000000, 0x00000000, 0x1c000000, 0x00000542, 
};

static const uint32_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSubClassMask[] = {
  0x00000000, 0x00000000, 0x18000000, 0x00000442, 
};

static const uint32_t GR64_ADSubClassMask[] = {
  0x00000000, 0x00000000, 0x10000000, 0x00000040, 
};

static const uint32_t GR64_and_LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
  0x00000000, 0x00000000, 0x20000000, 0x00000090, 
};

static const uint32_t GR64_with_sub_32bit_in_GR32_BPSPSubClassMask[] = {
  0x00000000, 0x00000000, 0x40000000, 0x00000180, 
};

static const uint32_t GR64_with_sub_32bit_in_GR32_BSISubClassMask[] = {
  0x00000000, 0x00000000, 0x80000000, 0x00000220, 
};

static const uint32_t GR64_with_sub_32bit_in_GR32_CBSubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x00000421, 
};

static const uint32_t GR64_with_sub_32bit_in_GR32_DCSubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x00000442, 
};

static const uint32_t GR64_with_sub_32bit_in_GR32_DIBPSubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x00000884, 
};

static const uint32_t GR64_with_sub_32bit_in_GR32_SIDISubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x00000a08, 
};

static const uint32_t GR64_and_LOW32_ADDR_ACCESSSubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x00000010, 
};

static const uint32_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x00000020, 
};

static const uint32_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCSubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x00000040, 
};

static const uint32_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x00000080, 
};

static const uint32_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x00000100, 
};

static const uint32_t GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x00000200, 
};

static const uint32_t GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCSubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x00000400, 
};

static const uint32_t GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x00000800, 
};

static const uint32_t RSTSubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x00001000, 
};

static const uint32_t RFP80SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x00002000, 
};

static const uint32_t RFP80_7SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x00004000, 
};

static const uint32_t VR128XSubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x00018000, 
  0x00000000, 0x00000000, 0x00000000, 0x003c0000, // sub_xmm
};

static const uint32_t VR128SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x00010000, 
  0x00000000, 0x00000000, 0x00000000, 0x00280000, // sub_xmm
};

static const uint32_t BNDRSubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x00020000, 
};

static const uint32_t VR256XSubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x000c0000, 
  0x00000000, 0x00000000, 0x00000000, 0x00300000, // sub_ymm
};

static const uint32_t VR256SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x00080000, 
  0x00000000, 0x00000000, 0x00000000, 0x00200000, // sub_ymm
};

static const uint32_t VR512SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x00300000, 
};

static const uint32_t VR512_0_15SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000000, 0x00200000, 
};

static const uint16_t SuperRegIdxSeqs[] = {
  /* 0 */ 1, 0,
  /* 2 */ 1, 2, 0,
  /* 5 */ 4, 0,
  /* 7 */ 6, 0,
  /* 9 */ 7, 8, 0,
  /* 12 */ 9, 0,
  /* 14 */ 10, 0,
};

static const TargetRegisterClass *const GR8_NOREXSuperclasses[] = {
  &X86::GR8RegClass,
  nullptr
};

static const TargetRegisterClass *const GR8_ABCD_HSuperclasses[] = {
  &X86::GR8RegClass,
  &X86::GR8_NOREXRegClass,
  nullptr
};

static const TargetRegisterClass *const GR8_ABCD_LSuperclasses[] = {
  &X86::GR8RegClass,
  &X86::GR8_NOREXRegClass,
  nullptr
};

static const TargetRegisterClass *const GR16_NOREXSuperclasses[] = {
  &X86::GR16RegClass,
  nullptr
};

static const TargetRegisterClass *const VK1Superclasses[] = {
  &X86::VK16RegClass,
  &X86::VK2RegClass,
  &X86::VK4RegClass,
  &X86::VK8RegClass,
  nullptr
};

static const TargetRegisterClass *const VK16Superclasses[] = {
  &X86::VK1RegClass,
  &X86::VK2RegClass,
  &X86::VK4RegClass,
  &X86::VK8RegClass,
  nullptr
};

static const TargetRegisterClass *const VK2Superclasses[] = {
  &X86::VK1RegClass,
  &X86::VK16RegClass,
  &X86::VK4RegClass,
  &X86::VK8RegClass,
  nullptr
};

static const TargetRegisterClass *const VK4Superclasses[] = {
  &X86::VK1RegClass,
  &X86::VK16RegClass,
  &X86::VK2RegClass,
  &X86::VK8RegClass,
  nullptr
};

static const TargetRegisterClass *const VK8Superclasses[] = {
  &X86::VK1RegClass,
  &X86::VK16RegClass,
  &X86::VK2RegClass,
  &X86::VK4RegClass,
  nullptr
};

static const TargetRegisterClass *const VK16WMSuperclasses[] = {
  &X86::VK1RegClass,
  &X86::VK16RegClass,
  &X86::VK2RegClass,
  &X86::VK4RegClass,
  &X86::VK8RegClass,
  &X86::VK1WMRegClass,
  &X86::VK2WMRegClass,
  &X86::VK4WMRegClass,
  &X86::VK8WMRegClass,
  nullptr
};

static const TargetRegisterClass *const VK1WMSuperclasses[] = {
  &X86::VK1RegClass,
  &X86::VK16RegClass,
  &X86::VK2RegClass,
  &X86::VK4RegClass,
  &X86::VK8RegClass,
  &X86::VK16WMRegClass,
  &X86::VK2WMRegClass,
  &X86::VK4WMRegClass,
  &X86::VK8WMRegClass,
  nullptr
};

static const TargetRegisterClass *const VK2WMSuperclasses[] = {
  &X86::VK1RegClass,
  &X86::VK16RegClass,
  &X86::VK2RegClass,
  &X86::VK4RegClass,
  &X86::VK8RegClass,
  &X86::VK16WMRegClass,
  &X86::VK1WMRegClass,
  &X86::VK4WMRegClass,
  &X86::VK8WMRegClass,
  nullptr
};

static const TargetRegisterClass *const VK4WMSuperclasses[] = {
  &X86::VK1RegClass,
  &X86::VK16RegClass,
  &X86::VK2RegClass,
  &X86::VK4RegClass,
  &X86::VK8RegClass,
  &X86::VK16WMRegClass,
  &X86::VK1WMRegClass,
  &X86::VK2WMRegClass,
  &X86::VK8WMRegClass,
  nullptr
};

static const TargetRegisterClass *const VK8WMSuperclasses[] = {
  &X86::VK1RegClass,
  &X86::VK16RegClass,
  &X86::VK2RegClass,
  &X86::VK4RegClass,
  &X86::VK8RegClass,
  &X86::VK16WMRegClass,
  &X86::VK1WMRegClass,
  &X86::VK2WMRegClass,
  &X86::VK4WMRegClass,
  nullptr
};

static const TargetRegisterClass *const GR16_ABCDSuperclasses[] = {
  &X86::GR16RegClass,
  &X86::GR16_NOREXRegClass,
  nullptr
};

static const TargetRegisterClass *const VK16PAIRSuperclasses[] = {
  &X86::VK1PAIRRegClass,
  &X86::VK2PAIRRegClass,
  &X86::VK4PAIRRegClass,
  &X86::VK8PAIRRegClass,
  nullptr
};

static const TargetRegisterClass *const VK1PAIRSuperclasses[] = {
  &X86::VK16PAIRRegClass,
  &X86::VK2PAIRRegClass,
  &X86::VK4PAIRRegClass,
  &X86::VK8PAIRRegClass,
  nullptr
};

static const TargetRegisterClass *const VK2PAIRSuperclasses[] = {
  &X86::VK16PAIRRegClass,
  &X86::VK1PAIRRegClass,
  &X86::VK4PAIRRegClass,
  &X86::VK8PAIRRegClass,
  nullptr
};

static const TargetRegisterClass *const VK4PAIRSuperclasses[] = {
  &X86::VK16PAIRRegClass,
  &X86::VK1PAIRRegClass,
  &X86::VK2PAIRRegClass,
  &X86::VK8PAIRRegClass,
  nullptr
};

static const TargetRegisterClass *const VK8PAIRSuperclasses[] = {
  &X86::VK16PAIRRegClass,
  &X86::VK1PAIRRegClass,
  &X86::VK2PAIRRegClass,
  &X86::VK4PAIRRegClass,
  nullptr
};

static const TargetRegisterClass *const VK16PAIR_with_sub_mask_0_in_VK16WMSuperclasses[] = {
  &X86::VK16PAIRRegClass,
  &X86::VK1PAIRRegClass,
  &X86::VK2PAIRRegClass,
  &X86::VK4PAIRRegClass,
  &X86::VK8PAIRRegClass,
  nullptr
};

static const TargetRegisterClass *const LOW32_ADDR_ACCESSSuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  nullptr
};

static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_8bitSuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  nullptr
};

static const TargetRegisterClass *const FR32Superclasses[] = {
  &X86::FR32XRegClass,
  nullptr
};

static const TargetRegisterClass *const GR32Superclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESSRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
  nullptr
};

static const TargetRegisterClass *const GR32_NOSPSuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESSRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
  &X86::GR32RegClass,
  nullptr
};

static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
  nullptr
};

static const TargetRegisterClass *const GR32_NOREXSuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESSRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
  &X86::GR32RegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
  nullptr
};

static const TargetRegisterClass *const VK32Superclasses[] = {
  &X86::VK1RegClass,
  &X86::VK16RegClass,
  &X86::VK2RegClass,
  &X86::VK4RegClass,
  &X86::VK8RegClass,
  nullptr
};

static const TargetRegisterClass *const GR32_NOREX_NOSPSuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESSRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
  &X86::GR32RegClass,
  &X86::GR32_NOSPRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR32_NOREXRegClass,
  nullptr
};

static const TargetRegisterClass *const VK32WMSuperclasses[] = {
  &X86::VK1RegClass,
  &X86::VK16RegClass,
  &X86::VK2RegClass,
  &X86::VK4RegClass,
  &X86::VK8RegClass,
  &X86::VK16WMRegClass,
  &X86::VK1WMRegClass,
  &X86::VK2WMRegClass,
  &X86::VK4WMRegClass,
  &X86::VK8WMRegClass,
  &X86::VK32RegClass,
  nullptr
};

static const TargetRegisterClass *const GR32_ABCDSuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESSRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
  &X86::GR32RegClass,
  &X86::GR32_NOSPRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR32_NOREXRegClass,
  &X86::GR32_NOREX_NOSPRegClass,
  nullptr
};

static const TargetRegisterClass *const GR32_TCSuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESSRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
  &X86::GR32RegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR32_NOREXRegClass,
  nullptr
};

static const TargetRegisterClass *const GR32_ABCD_and_GR32_TCSuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESSRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
  &X86::GR32RegClass,
  &X86::GR32_NOSPRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR32_NOREXRegClass,
  &X86::GR32_NOREX_NOSPRegClass,
  &X86::GR32_ABCDRegClass,
  &X86::GR32_TCRegClass,
  nullptr
};

static const TargetRegisterClass *const GR32_ADSuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESSRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
  &X86::GR32RegClass,
  &X86::GR32_NOSPRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR32_NOREXRegClass,
  &X86::GR32_NOREX_NOSPRegClass,
  &X86::GR32_ABCDRegClass,
  &X86::GR32_TCRegClass,
  &X86::GR32_ABCD_and_GR32_TCRegClass,
  nullptr
};

static const TargetRegisterClass *const GR32_BPSPSuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESSRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
  &X86::GR32RegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR32_NOREXRegClass,
  nullptr
};

static const TargetRegisterClass *const GR32_BSISuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESSRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
  &X86::GR32RegClass,
  &X86::GR32_NOSPRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR32_NOREXRegClass,
  &X86::GR32_NOREX_NOSPRegClass,
  nullptr
};

static const TargetRegisterClass *const GR32_CBSuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESSRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
  &X86::GR32RegClass,
  &X86::GR32_NOSPRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR32_NOREXRegClass,
  &X86::GR32_NOREX_NOSPRegClass,
  &X86::GR32_ABCDRegClass,
  nullptr
};

static const TargetRegisterClass *const GR32_DCSuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESSRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
  &X86::GR32RegClass,
  &X86::GR32_NOSPRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR32_NOREXRegClass,
  &X86::GR32_NOREX_NOSPRegClass,
  &X86::GR32_ABCDRegClass,
  &X86::GR32_TCRegClass,
  &X86::GR32_ABCD_and_GR32_TCRegClass,
  nullptr
};

static const TargetRegisterClass *const GR32_DIBPSuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESSRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
  &X86::GR32RegClass,
  &X86::GR32_NOSPRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR32_NOREXRegClass,
  &X86::GR32_NOREX_NOSPRegClass,
  nullptr
};

static const TargetRegisterClass *const GR32_SIDISuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESSRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
  &X86::GR32RegClass,
  &X86::GR32_NOSPRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR32_NOREXRegClass,
  &X86::GR32_NOREX_NOSPRegClass,
  nullptr
};

static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_32bitSuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  nullptr
};

static const TargetRegisterClass *const GR32_ABCD_and_GR32_BSISuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESSRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
  &X86::GR32RegClass,
  &X86::GR32_NOSPRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR32_NOREXRegClass,
  &X86::GR32_NOREX_NOSPRegClass,
  &X86::GR32_ABCDRegClass,
  &X86::GR32_BSIRegClass,
  &X86::GR32_CBRegClass,
  nullptr
};

static const TargetRegisterClass *const GR32_AD_and_GR32_DCSuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESSRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
  &X86::GR32RegClass,
  &X86::GR32_NOSPRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR32_NOREXRegClass,
  &X86::GR32_NOREX_NOSPRegClass,
  &X86::GR32_ABCDRegClass,
  &X86::GR32_TCRegClass,
  &X86::GR32_ABCD_and_GR32_TCRegClass,
  &X86::GR32_ADRegClass,
  &X86::GR32_DCRegClass,
  nullptr
};

static const TargetRegisterClass *const GR32_BPSP_and_GR32_DIBPSuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESSRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
  &X86::GR32RegClass,
  &X86::GR32_NOSPRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR32_NOREXRegClass,
  &X86::GR32_NOREX_NOSPRegClass,
  &X86::GR32_BPSPRegClass,
  &X86::GR32_DIBPRegClass,
  nullptr
};

static const TargetRegisterClass *const GR32_BPSP_and_GR32_TCSuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESSRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
  &X86::GR32RegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR32_NOREXRegClass,
  &X86::GR32_TCRegClass,
  &X86::GR32_BPSPRegClass,
  nullptr
};

static const TargetRegisterClass *const GR32_BSI_and_GR32_SIDISuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESSRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
  &X86::GR32RegClass,
  &X86::GR32_NOSPRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR32_NOREXRegClass,
  &X86::GR32_NOREX_NOSPRegClass,
  &X86::GR32_BSIRegClass,
  &X86::GR32_SIDIRegClass,
  nullptr
};

static const TargetRegisterClass *const GR32_CB_and_GR32_DCSuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESSRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
  &X86::GR32RegClass,
  &X86::GR32_NOSPRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR32_NOREXRegClass,
  &X86::GR32_NOREX_NOSPRegClass,
  &X86::GR32_ABCDRegClass,
  &X86::GR32_TCRegClass,
  &X86::GR32_ABCD_and_GR32_TCRegClass,
  &X86::GR32_CBRegClass,
  &X86::GR32_DCRegClass,
  nullptr
};

static const TargetRegisterClass *const GR32_DIBP_and_GR32_SIDISuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESSRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
  &X86::GR32RegClass,
  &X86::GR32_NOSPRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR32_NOREXRegClass,
  &X86::GR32_NOREX_NOSPRegClass,
  &X86::GR32_DIBPRegClass,
  &X86::GR32_SIDIRegClass,
  nullptr
};

static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
  nullptr
};

static const TargetRegisterClass *const LOW32_ADDR_ACCESS_with_sub_32bitSuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESSRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
  nullptr
};

static const TargetRegisterClass *const RFP64Superclasses[] = {
  &X86::RFP32RegClass,
  nullptr
};

static const TargetRegisterClass *const FR64XSuperclasses[] = {
  &X86::FR32XRegClass,
  nullptr
};

static const TargetRegisterClass *const FR64Superclasses[] = {
  &X86::FR32XRegClass,
  &X86::FR32RegClass,
  &X86::FR64XRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_with_sub_8bitSuperclasses[] = {
  &X86::GR64RegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_NOSPSuperclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_TCSuperclasses[] = {
  &X86::GR64RegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_NOREXSuperclasses[] = {
  &X86::GR64RegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_TCW64Superclasses[] = {
  &X86::GR64RegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_TC_with_sub_8bitSuperclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_TCRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_NOSP_and_GR64_TCSuperclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_NOSPRegClass,
  &X86::GR64_TCRegClass,
  &X86::GR64_TC_with_sub_8bitRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_TCW64_with_sub_8bitSuperclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_TCW64RegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_TC_and_GR64_TCW64Superclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_TCRegClass,
  &X86::GR64_TCW64RegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_NOREXRegClass,
  nullptr
};

static const TargetRegisterClass *const VK64Superclasses[] = {
  &X86::VK1RegClass,
  &X86::VK16RegClass,
  &X86::VK2RegClass,
  &X86::VK4RegClass,
  &X86::VK8RegClass,
  &X86::VK32RegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_NOREX_NOSPSuperclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_NOSPRegClass,
  &X86::GR64_NOREXRegClass,
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_NOREX_and_GR64_TCSuperclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_TCRegClass,
  &X86::GR64_NOREXRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_NOSP_and_GR64_TCW64Superclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_NOSPRegClass,
  &X86::GR64_TCW64RegClass,
  &X86::GR64_TCW64_with_sub_8bitRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_TCW64_and_GR64_TC_with_sub_8bitSuperclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_TCRegClass,
  &X86::GR64_TCW64RegClass,
  &X86::GR64_TC_with_sub_8bitRegClass,
  &X86::GR64_TCW64_with_sub_8bitRegClass,
  &X86::GR64_TC_and_GR64_TCW64RegClass,
  nullptr
};

static const TargetRegisterClass *const VK64WMSuperclasses[] = {
  &X86::VK1RegClass,
  &X86::VK16RegClass,
  &X86::VK2RegClass,
  &X86::VK4RegClass,
  &X86::VK8RegClass,
  &X86::VK16WMRegClass,
  &X86::VK1WMRegClass,
  &X86::VK2WMRegClass,
  &X86::VK4WMRegClass,
  &X86::VK8WMRegClass,
  &X86::VK32RegClass,
  &X86::VK32WMRegClass,
  &X86::VK64RegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_TC_and_GR64_NOSP_and_GR64_TCW64Superclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_NOSPRegClass,
  &X86::GR64_TCRegClass,
  &X86::GR64_TCW64RegClass,
  &X86::GR64_TC_with_sub_8bitRegClass,
  &X86::GR64_NOSP_and_GR64_TCRegClass,
  &X86::GR64_TCW64_with_sub_8bitRegClass,
  &X86::GR64_TC_and_GR64_TCW64RegClass,
  &X86::GR64_NOSP_and_GR64_TCW64RegClass,
  &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_TCRegClass,
  &X86::GR64_NOREXRegClass,
  &X86::GR64_TC_with_sub_8bitRegClass,
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_and_GR64_TCRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_NOREX_NOSP_and_GR64_TCSuperclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_NOSPRegClass,
  &X86::GR64_TCRegClass,
  &X86::GR64_NOREXRegClass,
  &X86::GR64_TC_with_sub_8bitRegClass,
  &X86::GR64_NOSP_and_GR64_TCRegClass,
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_NOSPRegClass,
  &X86::GR64_NOREX_and_GR64_TCRegClass,
  &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_NOREX_and_GR64_TCW64Superclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_TCRegClass,
  &X86::GR64_NOREXRegClass,
  &X86::GR64_TCW64RegClass,
  &X86::GR64_TC_and_GR64_TCW64RegClass,
  &X86::GR64_NOREX_and_GR64_TCRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_ABCDSuperclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_NOSPRegClass,
  &X86::GR64_NOREXRegClass,
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_NOSPRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_TCSuperclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_TCRegClass,
  &X86::GR64_NOREXRegClass,
  &X86::GR64_TCW64RegClass,
  &X86::GR64_TC_with_sub_8bitRegClass,
  &X86::GR64_TCW64_with_sub_8bitRegClass,
  &X86::GR64_TC_and_GR64_TCW64RegClass,
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_and_GR64_TCRegClass,
  &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
  &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_and_GR64_TCW64RegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSuperclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_NOSPRegClass,
  &X86::GR64_TCRegClass,
  &X86::GR64_NOREXRegClass,
  &X86::GR64_TCW64RegClass,
  &X86::GR64_TC_with_sub_8bitRegClass,
  &X86::GR64_NOSP_and_GR64_TCRegClass,
  &X86::GR64_TCW64_with_sub_8bitRegClass,
  &X86::GR64_TC_and_GR64_TCW64RegClass,
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_NOSPRegClass,
  &X86::GR64_NOREX_and_GR64_TCRegClass,
  &X86::GR64_NOSP_and_GR64_TCW64RegClass,
  &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
  &X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass,
  &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_NOSP_and_GR64_TCRegClass,
  &X86::GR64_NOREX_and_GR64_TCW64RegClass,
  &X86::GR64_ABCDRegClass,
  &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_ADSuperclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_NOSPRegClass,
  &X86::GR64_TCRegClass,
  &X86::GR64_NOREXRegClass,
  &X86::GR64_TCW64RegClass,
  &X86::GR64_TC_with_sub_8bitRegClass,
  &X86::GR64_NOSP_and_GR64_TCRegClass,
  &X86::GR64_TCW64_with_sub_8bitRegClass,
  &X86::GR64_TC_and_GR64_TCW64RegClass,
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_NOSPRegClass,
  &X86::GR64_NOREX_and_GR64_TCRegClass,
  &X86::GR64_NOSP_and_GR64_TCW64RegClass,
  &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
  &X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass,
  &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_NOSP_and_GR64_TCRegClass,
  &X86::GR64_NOREX_and_GR64_TCW64RegClass,
  &X86::GR64_ABCDRegClass,
  &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
  &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_and_LOW32_ADDR_ACCESS_RBPSuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
  &X86::GR64RegClass,
  &X86::GR64_NOREXRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BPSPSuperclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_NOREXRegClass,
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BSISuperclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_NOSPRegClass,
  &X86::GR64_NOREXRegClass,
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_NOSPRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_CBSuperclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_NOSPRegClass,
  &X86::GR64_NOREXRegClass,
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_NOSPRegClass,
  &X86::GR64_ABCDRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_DCSuperclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_NOSPRegClass,
  &X86::GR64_TCRegClass,
  &X86::GR64_NOREXRegClass,
  &X86::GR64_TCW64RegClass,
  &X86::GR64_TC_with_sub_8bitRegClass,
  &X86::GR64_NOSP_and_GR64_TCRegClass,
  &X86::GR64_TCW64_with_sub_8bitRegClass,
  &X86::GR64_TC_and_GR64_TCW64RegClass,
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_NOSPRegClass,
  &X86::GR64_NOREX_and_GR64_TCRegClass,
  &X86::GR64_NOSP_and_GR64_TCW64RegClass,
  &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
  &X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass,
  &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_NOSP_and_GR64_TCRegClass,
  &X86::GR64_NOREX_and_GR64_TCW64RegClass,
  &X86::GR64_ABCDRegClass,
  &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
  &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_DIBPSuperclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_NOSPRegClass,
  &X86::GR64_NOREXRegClass,
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_NOSPRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_SIDISuperclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_NOSPRegClass,
  &X86::GR64_TCRegClass,
  &X86::GR64_NOREXRegClass,
  &X86::GR64_TC_with_sub_8bitRegClass,
  &X86::GR64_NOSP_and_GR64_TCRegClass,
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_NOSPRegClass,
  &X86::GR64_NOREX_and_GR64_TCRegClass,
  &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_NOSP_and_GR64_TCRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_and_LOW32_ADDR_ACCESSSuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESSRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
  &X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClass,
  &X86::GR64RegClass,
  &X86::GR64_TCRegClass,
  &X86::GR64_NOREXRegClass,
  &X86::GR64_TCW64RegClass,
  &X86::GR64_TC_and_GR64_TCW64RegClass,
  &X86::GR64_NOREX_and_GR64_TCRegClass,
  &X86::GR64_NOREX_and_GR64_TCW64RegClass,
  &X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISuperclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_NOSPRegClass,
  &X86::GR64_NOREXRegClass,
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_NOSPRegClass,
  &X86::GR64_ABCDRegClass,
  &X86::GR64_with_sub_32bit_in_GR32_BSIRegClass,
  &X86::GR64_with_sub_32bit_in_GR32_CBRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCSuperclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_NOSPRegClass,
  &X86::GR64_TCRegClass,
  &X86::GR64_NOREXRegClass,
  &X86::GR64_TCW64RegClass,
  &X86::GR64_TC_with_sub_8bitRegClass,
  &X86::GR64_NOSP_and_GR64_TCRegClass,
  &X86::GR64_TCW64_with_sub_8bitRegClass,
  &X86::GR64_TC_and_GR64_TCW64RegClass,
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_NOSPRegClass,
  &X86::GR64_NOREX_and_GR64_TCRegClass,
  &X86::GR64_NOSP_and_GR64_TCW64RegClass,
  &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
  &X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass,
  &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_NOSP_and_GR64_TCRegClass,
  &X86::GR64_NOREX_and_GR64_TCW64RegClass,
  &X86::GR64_ABCDRegClass,
  &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
  &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass,
  &X86::GR64_ADRegClass,
  &X86::GR64_with_sub_32bit_in_GR32_DCRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSuperclasses[] = {
  &X86::LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
  &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass,
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_NOSPRegClass,
  &X86::GR64_NOREXRegClass,
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_NOSPRegClass,
  &X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClass,
  &X86::GR64_with_sub_32bit_in_GR32_BPSPRegClass,
  &X86::GR64_with_sub_32bit_in_GR32_DIBPRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSuperclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_TCRegClass,
  &X86::GR64_NOREXRegClass,
  &X86::GR64_TCW64RegClass,
  &X86::GR64_TC_with_sub_8bitRegClass,
  &X86::GR64_TCW64_with_sub_8bitRegClass,
  &X86::GR64_TC_and_GR64_TCW64RegClass,
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_and_GR64_TCRegClass,
  &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
  &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_and_GR64_TCW64RegClass,
  &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
  &X86::GR64_with_sub_32bit_in_GR32_BPSPRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISuperclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_NOSPRegClass,
  &X86::GR64_TCRegClass,
  &X86::GR64_NOREXRegClass,
  &X86::GR64_TC_with_sub_8bitRegClass,
  &X86::GR64_NOSP_and_GR64_TCRegClass,
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_NOSPRegClass,
  &X86::GR64_NOREX_and_GR64_TCRegClass,
  &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_NOSP_and_GR64_TCRegClass,
  &X86::GR64_with_sub_32bit_in_GR32_BSIRegClass,
  &X86::GR64_with_sub_32bit_in_GR32_SIDIRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCSuperclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_NOSPRegClass,
  &X86::GR64_TCRegClass,
  &X86::GR64_NOREXRegClass,
  &X86::GR64_TCW64RegClass,
  &X86::GR64_TC_with_sub_8bitRegClass,
  &X86::GR64_NOSP_and_GR64_TCRegClass,
  &X86::GR64_TCW64_with_sub_8bitRegClass,
  &X86::GR64_TC_and_GR64_TCW64RegClass,
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_NOSPRegClass,
  &X86::GR64_NOREX_and_GR64_TCRegClass,
  &X86::GR64_NOSP_and_GR64_TCW64RegClass,
  &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
  &X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass,
  &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_NOSP_and_GR64_TCRegClass,
  &X86::GR64_NOREX_and_GR64_TCW64RegClass,
  &X86::GR64_ABCDRegClass,
  &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
  &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass,
  &X86::GR64_with_sub_32bit_in_GR32_CBRegClass,
  &X86::GR64_with_sub_32bit_in_GR32_DCRegClass,
  nullptr
};

static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISuperclasses[] = {
  &X86::GR64RegClass,
  &X86::GR64_with_sub_8bitRegClass,
  &X86::GR64_NOSPRegClass,
  &X86::GR64_TCRegClass,
  &X86::GR64_NOREXRegClass,
  &X86::GR64_TC_with_sub_8bitRegClass,
  &X86::GR64_NOSP_and_GR64_TCRegClass,
  &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_NOSPRegClass,
  &X86::GR64_NOREX_and_GR64_TCRegClass,
  &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
  &X86::GR64_NOREX_NOSP_and_GR64_TCRegClass,
  &X86::GR64_with_sub_32bit_in_GR32_DIBPRegClass,
  &X86::GR64_with_sub_32bit_in_GR32_SIDIRegClass,
  nullptr
};

static const TargetRegisterClass *const RFP80Superclasses[] = {
  &X86::RFP32RegClass,
  &X86::RFP64RegClass,
  nullptr
};

static const TargetRegisterClass *const VR128XSuperclasses[] = {
  &X86::FR32XRegClass,
  &X86::FR64XRegClass,
  nullptr
};

static const TargetRegisterClass *const VR128Superclasses[] = {
  &X86::FR32XRegClass,
  &X86::FR32RegClass,
  &X86::FR64XRegClass,
  &X86::FR64RegClass,
  &X86::VR128XRegClass,
  nullptr
};

static const TargetRegisterClass *const VR256Superclasses[] = {
  &X86::VR256XRegClass,
  nullptr
};

static const TargetRegisterClass *const VR512_0_15Superclasses[] = {
  &X86::VR512RegClass,
  nullptr
};


static inline unsigned GR8AltOrderSelect(const MachineFunction &MF) {
    return MF.getSubtarget<X86Subtarget>().is64Bit();
  }

static ArrayRef<MCPhysReg> GR8GetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B };
  const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8RegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1)
  };
  const unsigned Select = GR8AltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned GR8_NOREXAltOrderSelect(const MachineFunction &MF) {
    return MF.getSubtarget<X86Subtarget>().is64Bit();
  }

static ArrayRef<MCPhysReg> GR8_NOREXGetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL };
  const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8_NOREXRegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    makeArrayRef(MCR.begin(), MCR.getNumRegs()),
    makeArrayRef(AltOrder1)
  };
  const unsigned Select = GR8_NOREXAltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

namespace X86 {   // Register class instances
  extern const TargetRegisterClass GR8RegClass = {
    &X86MCRegisterClasses[GR8RegClassID],
    GR8SubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    GR8GetRawAllocationOrder
  };

  extern const TargetRegisterClass GRH8RegClass = {
    &X86MCRegisterClasses[GRH8RegClassID],
    GRH8SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GR8_NOREXRegClass = {
    &X86MCRegisterClasses[GR8_NOREXRegClassID],
    GR8_NOREXSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR8_NOREXSuperclasses,
    GR8_NOREXGetRawAllocationOrder
  };

  extern const TargetRegisterClass GR8_ABCD_HRegClass = {
    &X86MCRegisterClasses[GR8_ABCD_HRegClassID],
    GR8_ABCD_HSubClassMask,
    SuperRegIdxSeqs + 3,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR8_ABCD_HSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR8_ABCD_LRegClass = {
    &X86MCRegisterClasses[GR8_ABCD_LRegClassID],
    GR8_ABCD_LSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR8_ABCD_LSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GRH16RegClass = {
    &X86MCRegisterClasses[GRH16RegClassID],
    GRH16SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GR16RegClass = {
    &X86MCRegisterClasses[GR16RegClassID],
    GR16SubClassMask,
    SuperRegIdxSeqs + 5,
    LaneBitmask(0x00000003),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GR16_NOREXRegClass = {
    &X86MCRegisterClasses[GR16_NOREXRegClassID],
    GR16_NOREXSubClassMask,
    SuperRegIdxSeqs + 5,
    LaneBitmask(0x00000003),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GR16_NOREXSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass VK1RegClass = {
    &X86MCRegisterClasses[VK1RegClassID],
    VK1SubClassMask,
    SuperRegIdxSeqs + 9,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VK1Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VK16RegClass = {
    &X86MCRegisterClasses[VK16RegClassID],
    VK16SubClassMask,
    SuperRegIdxSeqs + 9,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VK16Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VK2RegClass = {
    &X86MCRegisterClasses[VK2RegClassID],
    VK2SubClassMask,
    SuperRegIdxSeqs + 9,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VK2Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VK4RegClass = {
    &X86MCRegisterClasses[VK4RegClassID],
    VK4SubClassMask,
    SuperRegIdxSeqs + 9,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VK4Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VK8RegClass = {
    &X86MCRegisterClasses[VK8RegClassID],
    VK8SubClassMask,
    SuperRegIdxSeqs + 9,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VK8Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VK16WMRegClass = {
    &X86MCRegisterClasses[VK16WMRegClassID],
    VK16WMSubClassMask,
    SuperRegIdxSeqs + 9,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VK16WMSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass VK1WMRegClass = {
    &X86MCRegisterClasses[VK1WMRegClassID],
    VK1WMSubClassMask,
    SuperRegIdxSeqs + 9,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VK1WMSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass VK2WMRegClass = {
    &X86MCRegisterClasses[VK2WMRegClassID],
    VK2WMSubClassMask,
    SuperRegIdxSeqs + 9,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VK2WMSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass VK4WMRegClass = {
    &X86MCRegisterClasses[VK4WMRegClassID],
    VK4WMSubClassMask,
    SuperRegIdxSeqs + 9,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VK4WMSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass VK8WMRegClass = {
    &X86MCRegisterClasses[VK8WMRegClassID],
    VK8WMSubClassMask,
    SuperRegIdxSeqs + 9,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VK8WMSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass SEGMENT_REGRegClass = {
    &X86MCRegisterClasses[SEGMENT_REGRegClassID],
    SEGMENT_REGSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GR16_ABCDRegClass = {
    &X86MCRegisterClasses[GR16_ABCDRegClassID],
    GR16_ABCDSubClassMask,
    SuperRegIdxSeqs + 5,
    LaneBitmask(0x00000003),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GR16_ABCDSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass FPCCRRegClass = {
    &X86MCRegisterClasses[FPCCRRegClassID],
    FPCCRSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VK16PAIRRegClass = {
    &X86MCRegisterClasses[VK16PAIRRegClassID],
    VK16PAIRSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000030),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VK16PAIRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass VK1PAIRRegClass = {
    &X86MCRegisterClasses[VK1PAIRRegClassID],
    VK1PAIRSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000030),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VK1PAIRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass VK2PAIRRegClass = {
    &X86MCRegisterClasses[VK2PAIRRegClassID],
    VK2PAIRSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000030),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VK2PAIRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass VK4PAIRRegClass = {
    &X86MCRegisterClasses[VK4PAIRRegClassID],
    VK4PAIRSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000030),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VK4PAIRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass VK8PAIRRegClass = {
    &X86MCRegisterClasses[VK8PAIRRegClassID],
    VK8PAIRSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000030),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VK8PAIRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass VK16PAIR_with_sub_mask_0_in_VK16WMRegClass = {
    &X86MCRegisterClasses[VK16PAIR_with_sub_mask_0_in_VK16WMRegClassID],
    VK16PAIR_with_sub_mask_0_in_VK16WMSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000030),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VK16PAIR_with_sub_mask_0_in_VK16WMSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass FR32XRegClass = {
    &X86MCRegisterClasses[FR32XRegClassID],
    FR32XSubClassMask,
    SuperRegIdxSeqs + 12,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBPRegClass = {
    &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBPRegClassID],
    LOW32_ADDR_ACCESS_RBPSubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass LOW32_ADDR_ACCESSRegClass = {
    &X86MCRegisterClasses[LOW32_ADDR_ACCESSRegClassID],
    LOW32_ADDR_ACCESSSubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    LOW32_ADDR_ACCESSSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass = {
    &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID],
    LOW32_ADDR_ACCESS_RBP_with_sub_8bitSubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    LOW32_ADDR_ACCESS_RBP_with_sub_8bitSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass DEBUG_REGRegClass = {
    &X86MCRegisterClasses[DEBUG_REGRegClassID],
    DEBUG_REGSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass FR32RegClass = {
    &X86MCRegisterClasses[FR32RegClassID],
    FR32SubClassMask,
    SuperRegIdxSeqs + 12,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    FR32Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GR32RegClass = {
    &X86MCRegisterClasses[GR32RegClassID],
    GR32SubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x00000007),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GR32Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GR32_NOSPRegClass = {
    &X86MCRegisterClasses[GR32_NOSPRegClassID],
    GR32_NOSPSubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x00000007),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GR32_NOSPSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass = {
    &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID],
    LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR32_NOREXRegClass = {
    &X86MCRegisterClasses[GR32_NOREXRegClassID],
    GR32_NOREXSubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x00000007),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GR32_NOREXSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass VK32RegClass = {
    &X86MCRegisterClasses[VK32RegClassID],
    VK32SubClassMask,
    SuperRegIdxSeqs + 9,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VK32Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GR32_NOREX_NOSPRegClass = {
    &X86MCRegisterClasses[GR32_NOREX_NOSPRegClassID],
    GR32_NOREX_NOSPSubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x00000007),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GR32_NOREX_NOSPSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass RFP32RegClass = {
    &X86MCRegisterClasses[RFP32RegClassID],
    RFP32SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VK32WMRegClass = {
    &X86MCRegisterClasses[VK32WMRegClassID],
    VK32WMSubClassMask,
    SuperRegIdxSeqs + 9,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VK32WMSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR32_ABCDRegClass = {
    &X86MCRegisterClasses[GR32_ABCDRegClassID],
    GR32_ABCDSubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x00000007),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GR32_ABCDSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR32_TCRegClass = {
    &X86MCRegisterClasses[GR32_TCRegClassID],
    GR32_TCSubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x00000007),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GR32_TCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR32_ABCD_and_GR32_TCRegClass = {
    &X86MCRegisterClasses[GR32_ABCD_and_GR32_TCRegClassID],
    GR32_ABCD_and_GR32_TCSubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x00000007),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GR32_ABCD_and_GR32_TCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR32_ADRegClass = {
    &X86MCRegisterClasses[GR32_ADRegClassID],
    GR32_ADSubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x00000007),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GR32_ADSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR32_BPSPRegClass = {
    &X86MCRegisterClasses[GR32_BPSPRegClassID],
    GR32_BPSPSubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x00000007),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GR32_BPSPSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR32_BSIRegClass = {
    &X86MCRegisterClasses[GR32_BSIRegClassID],
    GR32_BSISubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x00000007),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GR32_BSISuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR32_CBRegClass = {
    &X86MCRegisterClasses[GR32_CBRegClassID],
    GR32_CBSubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x00000007),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GR32_CBSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR32_DCRegClass = {
    &X86MCRegisterClasses[GR32_DCRegClassID],
    GR32_DCSubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x00000007),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GR32_DCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR32_DIBPRegClass = {
    &X86MCRegisterClasses[GR32_DIBPRegClassID],
    GR32_DIBPSubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x00000007),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GR32_DIBPSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR32_SIDIRegClass = {
    &X86MCRegisterClasses[GR32_SIDIRegClassID],
    GR32_SIDISubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x00000007),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GR32_SIDISuperclasses,
    nullptr
  };

  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass = {
    &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID],
    LOW32_ADDR_ACCESS_RBP_with_sub_32bitSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    LOW32_ADDR_ACCESS_RBP_with_sub_32bitSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass CCRRegClass = {
    &X86MCRegisterClasses[CCRRegClassID],
    CCRSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass DFCCRRegClass = {
    &X86MCRegisterClasses[DFCCRRegClassID],
    DFCCRSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GR32_ABCD_and_GR32_BSIRegClass = {
    &X86MCRegisterClasses[GR32_ABCD_and_GR32_BSIRegClassID],
    GR32_ABCD_and_GR32_BSISubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x00000007),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GR32_ABCD_and_GR32_BSISuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR32_AD_and_GR32_DCRegClass = {
    &X86MCRegisterClasses[GR32_AD_and_GR32_DCRegClassID],
    GR32_AD_and_GR32_DCSubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x00000007),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GR32_AD_and_GR32_DCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR32_BPSP_and_GR32_DIBPRegClass = {
    &X86MCRegisterClasses[GR32_BPSP_and_GR32_DIBPRegClassID],
    GR32_BPSP_and_GR32_DIBPSubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x00000007),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GR32_BPSP_and_GR32_DIBPSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR32_BPSP_and_GR32_TCRegClass = {
    &X86MCRegisterClasses[GR32_BPSP_and_GR32_TCRegClassID],
    GR32_BPSP_and_GR32_TCSubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x00000007),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GR32_BPSP_and_GR32_TCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR32_BSI_and_GR32_SIDIRegClass = {
    &X86MCRegisterClasses[GR32_BSI_and_GR32_SIDIRegClassID],
    GR32_BSI_and_GR32_SIDISubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x00000007),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GR32_BSI_and_GR32_SIDISuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR32_CB_and_GR32_DCRegClass = {
    &X86MCRegisterClasses[GR32_CB_and_GR32_DCRegClassID],
    GR32_CB_and_GR32_DCSubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x00000007),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GR32_CB_and_GR32_DCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR32_DIBP_and_GR32_SIDIRegClass = {
    &X86MCRegisterClasses[GR32_DIBP_and_GR32_SIDIRegClassID],
    GR32_DIBP_and_GR32_SIDISubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x00000007),
    0,
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GR32_DIBP_and_GR32_SIDISuperclasses,
    nullptr
  };

  extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass = {
    &X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID],
    LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass LOW32_ADDR_ACCESS_with_sub_32bitRegClass = {
    &X86MCRegisterClasses[LOW32_ADDR_ACCESS_with_sub_32bitRegClassID],
    LOW32_ADDR_ACCESS_with_sub_32bitSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    LOW32_ADDR_ACCESS_with_sub_32bitSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass RFP64RegClass = {
    &X86MCRegisterClasses[RFP64RegClassID],
    RFP64SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    RFP64Superclasses,
    nullptr
  };

  extern const TargetRegisterClass FR64XRegClass = {
    &X86MCRegisterClasses[FR64XRegClassID],
    FR64XSubClassMask,
    SuperRegIdxSeqs + 12,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    FR64XSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64RegClass = {
    &X86MCRegisterClasses[GR64RegClassID],
    GR64SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass CONTROL_REGRegClass = {
    &X86MCRegisterClasses[CONTROL_REGRegClassID],
    CONTROL_REGSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass FR64RegClass = {
    &X86MCRegisterClasses[FR64RegClassID],
    FR64SubClassMask,
    SuperRegIdxSeqs + 12,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    FR64Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_with_sub_8bitRegClass = {
    &X86MCRegisterClasses[GR64_with_sub_8bitRegClassID],
    GR64_with_sub_8bitSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_with_sub_8bitSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_NOSPRegClass = {
    &X86MCRegisterClasses[GR64_NOSPRegClassID],
    GR64_NOSPSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_NOSPSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_TCRegClass = {
    &X86MCRegisterClasses[GR64_TCRegClassID],
    GR64_TCSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_TCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_NOREXRegClass = {
    &X86MCRegisterClasses[GR64_NOREXRegClassID],
    GR64_NOREXSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_NOREXSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_TCW64RegClass = {
    &X86MCRegisterClasses[GR64_TCW64RegClassID],
    GR64_TCW64SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_TCW64Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_TC_with_sub_8bitRegClass = {
    &X86MCRegisterClasses[GR64_TC_with_sub_8bitRegClassID],
    GR64_TC_with_sub_8bitSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_TC_with_sub_8bitSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_NOSP_and_GR64_TCRegClass = {
    &X86MCRegisterClasses[GR64_NOSP_and_GR64_TCRegClassID],
    GR64_NOSP_and_GR64_TCSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_NOSP_and_GR64_TCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_TCW64_with_sub_8bitRegClass = {
    &X86MCRegisterClasses[GR64_TCW64_with_sub_8bitRegClassID],
    GR64_TCW64_with_sub_8bitSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_TCW64_with_sub_8bitSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_TC_and_GR64_TCW64RegClass = {
    &X86MCRegisterClasses[GR64_TC_and_GR64_TCW64RegClassID],
    GR64_TC_and_GR64_TCW64SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_TC_and_GR64_TCW64Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREXRegClass = {
    &X86MCRegisterClasses[GR64_with_sub_16bit_in_GR16_NOREXRegClassID],
    GR64_with_sub_16bit_in_GR16_NOREXSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_with_sub_16bit_in_GR16_NOREXSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass VK64RegClass = {
    &X86MCRegisterClasses[VK64RegClassID],
    VK64SubClassMask,
    SuperRegIdxSeqs + 9,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VK64Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VR64RegClass = {
    &X86MCRegisterClasses[VR64RegClassID],
    VR64SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_NOREX_NOSPRegClass = {
    &X86MCRegisterClasses[GR64_NOREX_NOSPRegClassID],
    GR64_NOREX_NOSPSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_NOREX_NOSPSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_NOREX_and_GR64_TCRegClass = {
    &X86MCRegisterClasses[GR64_NOREX_and_GR64_TCRegClassID],
    GR64_NOREX_and_GR64_TCSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_NOREX_and_GR64_TCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_NOSP_and_GR64_TCW64RegClass = {
    &X86MCRegisterClasses[GR64_NOSP_and_GR64_TCW64RegClassID],
    GR64_NOSP_and_GR64_TCW64SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_NOSP_and_GR64_TCW64Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass = {
    &X86MCRegisterClasses[GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID],
    GR64_TCW64_and_GR64_TC_with_sub_8bitSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_TCW64_and_GR64_TC_with_sub_8bitSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass VK64WMRegClass = {
    &X86MCRegisterClasses[VK64WMRegClassID],
    VK64WMSubClassMask,
    SuperRegIdxSeqs + 9,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VK64WMSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass = {
    &X86MCRegisterClasses[GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID],
    GR64_TC_and_GR64_NOSP_and_GR64_TCW64SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_TC_and_GR64_NOSP_and_GR64_TCW64Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass = {
    &X86MCRegisterClasses[GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID],
    GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_NOREX_NOSP_and_GR64_TCRegClass = {
    &X86MCRegisterClasses[GR64_NOREX_NOSP_and_GR64_TCRegClassID],
    GR64_NOREX_NOSP_and_GR64_TCSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_NOREX_NOSP_and_GR64_TCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_NOREX_and_GR64_TCW64RegClass = {
    &X86MCRegisterClasses[GR64_NOREX_and_GR64_TCW64RegClassID],
    GR64_NOREX_and_GR64_TCW64SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_NOREX_and_GR64_TCW64Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_ABCDRegClass = {
    &X86MCRegisterClasses[GR64_ABCDRegClassID],
    GR64_ABCDSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_ABCDSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_TCRegClass = {
    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_TCRegClassID],
    GR64_with_sub_32bit_in_GR32_TCSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_with_sub_32bit_in_GR32_TCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass = {
    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID],
    GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_ADRegClass = {
    &X86MCRegisterClasses[GR64_ADRegClassID],
    GR64_ADSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_ADSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESS_RBPRegClass = {
    &X86MCRegisterClasses[GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID],
    GR64_and_LOW32_ADDR_ACCESS_RBPSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_and_LOW32_ADDR_ACCESS_RBPSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSPRegClass = {
    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSPRegClassID],
    GR64_with_sub_32bit_in_GR32_BPSPSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_with_sub_32bit_in_GR32_BPSPSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSIRegClass = {
    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BSIRegClassID],
    GR64_with_sub_32bit_in_GR32_BSISubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_with_sub_32bit_in_GR32_BSISuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CBRegClass = {
    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_CBRegClassID],
    GR64_with_sub_32bit_in_GR32_CBSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_with_sub_32bit_in_GR32_CBSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DCRegClass = {
    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_DCRegClassID],
    GR64_with_sub_32bit_in_GR32_DCSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_with_sub_32bit_in_GR32_DCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBPRegClass = {
    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_DIBPRegClassID],
    GR64_with_sub_32bit_in_GR32_DIBPSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_with_sub_32bit_in_GR32_DIBPSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_SIDIRegClass = {
    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_SIDIRegClassID],
    GR64_with_sub_32bit_in_GR32_SIDISubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_with_sub_32bit_in_GR32_SIDISuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESSRegClass = {
    &X86MCRegisterClasses[GR64_and_LOW32_ADDR_ACCESSRegClassID],
    GR64_and_LOW32_ADDR_ACCESSSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_and_LOW32_ADDR_ACCESSSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass = {
    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID],
    GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClass = {
    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClassID],
    GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass = {
    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID],
    GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass = {
    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID],
    GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass = {
    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID],
    GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClass = {
    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClassID],
    GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass = {
    &X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID],
    GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000F),
    0,
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISuperclasses,
    nullptr
  };

  extern const TargetRegisterClass RSTRegClass = {
    &X86MCRegisterClasses[RSTRegClassID],
    RSTSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass RFP80RegClass = {
    &X86MCRegisterClasses[RFP80RegClassID],
    RFP80SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    RFP80Superclasses,
    nullptr
  };

  extern const TargetRegisterClass RFP80_7RegClass = {
    &X86MCRegisterClasses[RFP80_7RegClassID],
    RFP80_7SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VR128XRegClass = {
    &X86MCRegisterClasses[VR128XRegClassID],
    VR128XSubClassMask,
    SuperRegIdxSeqs + 12,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VR128XSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass VR128RegClass = {
    &X86MCRegisterClasses[VR128RegClassID],
    VR128SubClassMask,
    SuperRegIdxSeqs + 12,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VR128Superclasses,
    nullptr
  };

  extern const TargetRegisterClass BNDRRegClass = {
    &X86MCRegisterClasses[BNDRRegClassID],
    BNDRSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000001),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VR256XRegClass = {
    &X86MCRegisterClasses[VR256XRegClassID],
    VR256XSubClassMask,
    SuperRegIdxSeqs + 14,
    LaneBitmask(0x00000040),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VR256RegClass = {
    &X86MCRegisterClasses[VR256RegClassID],
    VR256SubClassMask,
    SuperRegIdxSeqs + 14,
    LaneBitmask(0x00000040),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VR256Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VR512RegClass = {
    &X86MCRegisterClasses[VR512RegClassID],
    VR512SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000040),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VR512_0_15RegClass = {
    &X86MCRegisterClasses[VR512_0_15RegClassID],
    VR512_0_15SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000040),
    0,
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VR512_0_15Superclasses,
    nullptr
  };

} // end namespace X86

namespace {
  const TargetRegisterClass* const RegisterClasses[] = {
    &X86::GR8RegClass,
    &X86::GRH8RegClass,
    &X86::GR8_NOREXRegClass,
    &X86::GR8_ABCD_HRegClass,
    &X86::GR8_ABCD_LRegClass,
    &X86::GRH16RegClass,
    &X86::GR16RegClass,
    &X86::GR16_NOREXRegClass,
    &X86::VK1RegClass,
    &X86::VK16RegClass,
    &X86::VK2RegClass,
    &X86::VK4RegClass,
    &X86::VK8RegClass,
    &X86::VK16WMRegClass,
    &X86::VK1WMRegClass,
    &X86::VK2WMRegClass,
    &X86::VK4WMRegClass,
    &X86::VK8WMRegClass,
    &X86::SEGMENT_REGRegClass,
    &X86::GR16_ABCDRegClass,
    &X86::FPCCRRegClass,
    &X86::VK16PAIRRegClass,
    &X86::VK1PAIRRegClass,
    &X86::VK2PAIRRegClass,
    &X86::VK4PAIRRegClass,
    &X86::VK8PAIRRegClass,
    &X86::VK16PAIR_with_sub_mask_0_in_VK16WMRegClass,
    &X86::FR32XRegClass,
    &X86::LOW32_ADDR_ACCESS_RBPRegClass,
    &X86::LOW32_ADDR_ACCESSRegClass,
    &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
    &X86::DEBUG_REGRegClass,
    &X86::FR32RegClass,
    &X86::GR32RegClass,
    &X86::GR32_NOSPRegClass,
    &X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
    &X86::GR32_NOREXRegClass,
    &X86::VK32RegClass,
    &X86::GR32_NOREX_NOSPRegClass,
    &X86::RFP32RegClass,
    &X86::VK32WMRegClass,
    &X86::GR32_ABCDRegClass,
    &X86::GR32_TCRegClass,
    &X86::GR32_ABCD_and_GR32_TCRegClass,
    &X86::GR32_ADRegClass,
    &X86::GR32_BPSPRegClass,
    &X86::GR32_BSIRegClass,
    &X86::GR32_CBRegClass,
    &X86::GR32_DCRegClass,
    &X86::GR32_DIBPRegClass,
    &X86::GR32_SIDIRegClass,
    &X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
    &X86::CCRRegClass,
    &X86::DFCCRRegClass,
    &X86::GR32_ABCD_and_GR32_BSIRegClass,
    &X86::GR32_AD_and_GR32_DCRegClass,
    &X86::GR32_BPSP_and_GR32_DIBPRegClass,
    &X86::GR32_BPSP_and_GR32_TCRegClass,
    &X86::GR32_BSI_and_GR32_SIDIRegClass,
    &X86::GR32_CB_and_GR32_DCRegClass,
    &X86::GR32_DIBP_and_GR32_SIDIRegClass,
    &X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass,
    &X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClass,
    &X86::RFP64RegClass,
    &X86::FR64XRegClass,
    &X86::GR64RegClass,
    &X86::CONTROL_REGRegClass,
    &X86::FR64RegClass,
    &X86::GR64_with_sub_8bitRegClass,
    &X86::GR64_NOSPRegClass,
    &X86::GR64_TCRegClass,
    &X86::GR64_NOREXRegClass,
    &X86::GR64_TCW64RegClass,
    &X86::GR64_TC_with_sub_8bitRegClass,
    &X86::GR64_NOSP_and_GR64_TCRegClass,
    &X86::GR64_TCW64_with_sub_8bitRegClass,
    &X86::GR64_TC_and_GR64_TCW64RegClass,
    &X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
    &X86::VK64RegClass,
    &X86::VR64RegClass,
    &X86::GR64_NOREX_NOSPRegClass,
    &X86::GR64_NOREX_and_GR64_TCRegClass,
    &X86::GR64_NOSP_and_GR64_TCW64RegClass,
    &X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
    &X86::VK64WMRegClass,
    &X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass,
    &X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
    &X86::GR64_NOREX_NOSP_and_GR64_TCRegClass,
    &X86::GR64_NOREX_and_GR64_TCW64RegClass,
    &X86::GR64_ABCDRegClass,
    &X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
    &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass,
    &X86::GR64_ADRegClass,
    &X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClass,
    &X86::GR64_with_sub_32bit_in_GR32_BPSPRegClass,
    &X86::GR64_with_sub_32bit_in_GR32_BSIRegClass,
    &X86::GR64_with_sub_32bit_in_GR32_CBRegClass,
    &X86::GR64_with_sub_32bit_in_GR32_DCRegClass,
    &X86::GR64_with_sub_32bit_in_GR32_DIBPRegClass,
    &X86::GR64_with_sub_32bit_in_GR32_SIDIRegClass,
    &X86::GR64_and_LOW32_ADDR_ACCESSRegClass,
    &X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass,
    &X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClass,
    &X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass,
    &X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass,
    &X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass,
    &X86::GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClass,
    &X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass,
    &X86::RSTRegClass,
    &X86::RFP80RegClass,
    &X86::RFP80_7RegClass,
    &X86::VR128XRegClass,
    &X86::VR128RegClass,
    &X86::BNDRRegClass,
    &X86::VR256XRegClass,
    &X86::VR256RegClass,
    &X86::VR512RegClass,
    &X86::VR512_0_15RegClass,
  };
} // end anonymous namespace

static const TargetRegisterInfoDesc X86RegInfoDesc[] = { // Extra Descriptors
  { 0, false },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, false },
  { 1, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, false },
  { 0, true },
  { 0, true },
  { 0, false },
  { 1, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, false },
  { 0, false },
  { 0, true },
  { 0, true },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 1, true },
  { 0, false },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, false },
  { 1, true },
  { 0, true },
  { 0, false },
  { 1, true },
  { 0, true },
  { 0, false },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, false },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 1, true },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, false },
  { 0, true },
  { 0, true },
  { 0, true },
  { 0, true },
};
unsigned X86GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
  static const uint8_t Rows[1][10] = {
    { X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
  };

  --IdxA; assert(IdxA < 10);
  --IdxB; assert(IdxB < 10);
  return Rows[0][IdxB];
}

  struct MaskRolOp {
    LaneBitmask Mask;
    uint8_t  RotateLeft;
  };
  static const MaskRolOp LaneMaskComposeSequences[] = {
    { LaneBitmask(0xFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
    { LaneBitmask(0xFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
    { LaneBitmask(0xFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 4
    { LaneBitmask(0xFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 6
    { LaneBitmask(0xFFFFFFFF),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 8
    { LaneBitmask(0xFFFFFFFF),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 10
    { LaneBitmask(0xFFFFFFFF),  6 }, { LaneBitmask::getNone(), 0 }  // Sequence 12
  };
  static const MaskRolOp *const CompositeSequences[] = {
    &LaneMaskComposeSequences[0], // to sub_8bit
    &LaneMaskComposeSequences[2], // to sub_8bit_hi
    &LaneMaskComposeSequences[4], // to sub_8bit_hi_phony
    &LaneMaskComposeSequences[0], // to sub_16bit
    &LaneMaskComposeSequences[6], // to sub_16bit_hi
    &LaneMaskComposeSequences[0], // to sub_32bit
    &LaneMaskComposeSequences[8], // to sub_mask_0
    &LaneMaskComposeSequences[10], // to sub_mask_1
    &LaneMaskComposeSequences[12], // to sub_xmm
    &LaneMaskComposeSequences[0] // to sub_ymm
  };

LaneBitmask X86GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
  --IdxA; assert(IdxA < 10 && "Subregister index out of bounds");
  LaneBitmask Result;
  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
    if (unsigned S = Ops->RotateLeft)
      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
    else
      Result |= LaneBitmask(M);
  }
  return Result;
}

LaneBitmask X86GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
  LaneMask &= getSubRegIndexLaneMask(IdxA);
  --IdxA; assert(IdxA < 10 && "Subregister index out of bounds");
  LaneBitmask Result;
  for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
    LaneBitmask::Type M = LaneMask.getAsInteger();
    if (unsigned S = Ops->RotateLeft)
      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
    else
      Result |= LaneBitmask(M);
  }
  return Result;
}

const TargetRegisterClass *X86GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
  static const uint8_t Table[118][10] = {
    {	// GR8
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GRH8
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR8_NOREX
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR8_ABCD_H
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR8_ABCD_L
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GRH16
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR16
      7,	// sub_8bit -> GR16
      20,	// sub_8bit_hi -> GR16_ABCD
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR16_NOREX
      8,	// sub_8bit -> GR16_NOREX
      20,	// sub_8bit_hi -> GR16_ABCD
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// VK1
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// VK16
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// VK2
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// VK4
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// VK8
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// VK16WM
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// VK1WM
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// VK2WM
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// VK4WM
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// VK8WM
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// SEGMENT_REG
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR16_ABCD
      20,	// sub_8bit -> GR16_ABCD
      20,	// sub_8bit_hi -> GR16_ABCD
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// FPCCR
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// VK16PAIR
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      22,	// sub_mask_0 -> VK16PAIR
      22,	// sub_mask_1 -> VK16PAIR
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// VK1PAIR
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      23,	// sub_mask_0 -> VK1PAIR
      23,	// sub_mask_1 -> VK1PAIR
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// VK2PAIR
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      24,	// sub_mask_0 -> VK2PAIR
      24,	// sub_mask_1 -> VK2PAIR
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// VK4PAIR
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      25,	// sub_mask_0 -> VK4PAIR
      25,	// sub_mask_1 -> VK4PAIR
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// VK8PAIR
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      26,	// sub_mask_0 -> VK8PAIR
      26,	// sub_mask_1 -> VK8PAIR
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// VK16PAIR_with_sub_mask_0_in_VK16WM
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      27,	// sub_mask_0 -> VK16PAIR_with_sub_mask_0_in_VK16WM
      27,	// sub_mask_1 -> VK16PAIR_with_sub_mask_0_in_VK16WM
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// FR32X
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// LOW32_ADDR_ACCESS_RBP
      31,	// sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
      42,	// sub_8bit_hi -> GR32_ABCD
      0,	// sub_8bit_hi_phony
      29,	// sub_16bit -> LOW32_ADDR_ACCESS_RBP
      0,	// sub_16bit_hi
      52,	// sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// LOW32_ADDR_ACCESS
      34,	// sub_8bit -> GR32
      42,	// sub_8bit_hi -> GR32_ABCD
      0,	// sub_8bit_hi_phony
      30,	// sub_16bit -> LOW32_ADDR_ACCESS
      0,	// sub_16bit_hi
      63,	// sub_32bit -> LOW32_ADDR_ACCESS_with_sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit
      31,	// sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
      42,	// sub_8bit_hi -> GR32_ABCD
      0,	// sub_8bit_hi_phony
      31,	// sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
      0,	// sub_16bit_hi
      62,	// sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// DEBUG_REG
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// FR32
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR32
      34,	// sub_8bit -> GR32
      42,	// sub_8bit_hi -> GR32_ABCD
      0,	// sub_8bit_hi_phony
      34,	// sub_16bit -> GR32
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR32_NOSP
      35,	// sub_8bit -> GR32_NOSP
      42,	// sub_8bit_hi -> GR32_ABCD
      0,	// sub_8bit_hi_phony
      35,	// sub_16bit -> GR32_NOSP
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
      36,	// sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
      42,	// sub_8bit_hi -> GR32_ABCD
      0,	// sub_8bit_hi_phony
      36,	// sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
      0,	// sub_16bit_hi
      62,	// sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR32_NOREX
      37,	// sub_8bit -> GR32_NOREX
      42,	// sub_8bit_hi -> GR32_ABCD
      0,	// sub_8bit_hi_phony
      37,	// sub_16bit -> GR32_NOREX
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// VK32
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR32_NOREX_NOSP
      39,	// sub_8bit -> GR32_NOREX_NOSP
      42,	// sub_8bit_hi -> GR32_ABCD
      0,	// sub_8bit_hi_phony
      39,	// sub_16bit -> GR32_NOREX_NOSP
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// RFP32
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// VK32WM
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR32_ABCD
      42,	// sub_8bit -> GR32_ABCD
      42,	// sub_8bit_hi -> GR32_ABCD
      0,	// sub_8bit_hi_phony
      42,	// sub_16bit -> GR32_ABCD
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR32_TC
      43,	// sub_8bit -> GR32_TC
      44,	// sub_8bit_hi -> GR32_ABCD_and_GR32_TC
      0,	// sub_8bit_hi_phony
      43,	// sub_16bit -> GR32_TC
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR32_ABCD_and_GR32_TC
      44,	// sub_8bit -> GR32_ABCD_and_GR32_TC
      44,	// sub_8bit_hi -> GR32_ABCD_and_GR32_TC
      0,	// sub_8bit_hi_phony
      44,	// sub_16bit -> GR32_ABCD_and_GR32_TC
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR32_AD
      45,	// sub_8bit -> GR32_AD
      45,	// sub_8bit_hi -> GR32_AD
      0,	// sub_8bit_hi_phony
      45,	// sub_16bit -> GR32_AD
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR32_BPSP
      46,	// sub_8bit -> GR32_BPSP
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      46,	// sub_16bit -> GR32_BPSP
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR32_BSI
      47,	// sub_8bit -> GR32_BSI
      55,	// sub_8bit_hi -> GR32_ABCD_and_GR32_BSI
      0,	// sub_8bit_hi_phony
      47,	// sub_16bit -> GR32_BSI
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR32_CB
      48,	// sub_8bit -> GR32_CB
      48,	// sub_8bit_hi -> GR32_CB
      0,	// sub_8bit_hi_phony
      48,	// sub_16bit -> GR32_CB
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR32_DC
      49,	// sub_8bit -> GR32_DC
      49,	// sub_8bit_hi -> GR32_DC
      0,	// sub_8bit_hi_phony
      49,	// sub_16bit -> GR32_DC
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR32_DIBP
      50,	// sub_8bit -> GR32_DIBP
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      50,	// sub_16bit -> GR32_DIBP
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR32_SIDI
      51,	// sub_8bit -> GR32_SIDI
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      51,	// sub_16bit -> GR32_SIDI
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// LOW32_ADDR_ACCESS_RBP_with_sub_32bit
      62,	// sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      52,	// sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
      0,	// sub_16bit_hi
      52,	// sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// CCR
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// DFCCR
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR32_ABCD_and_GR32_BSI
      55,	// sub_8bit -> GR32_ABCD_and_GR32_BSI
      55,	// sub_8bit_hi -> GR32_ABCD_and_GR32_BSI
      0,	// sub_8bit_hi_phony
      55,	// sub_16bit -> GR32_ABCD_and_GR32_BSI
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR32_AD_and_GR32_DC
      56,	// sub_8bit -> GR32_AD_and_GR32_DC
      56,	// sub_8bit_hi -> GR32_AD_and_GR32_DC
      0,	// sub_8bit_hi_phony
      56,	// sub_16bit -> GR32_AD_and_GR32_DC
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR32_BPSP_and_GR32_DIBP
      57,	// sub_8bit -> GR32_BPSP_and_GR32_DIBP
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      57,	// sub_16bit -> GR32_BPSP_and_GR32_DIBP
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR32_BPSP_and_GR32_TC
      58,	// sub_8bit -> GR32_BPSP_and_GR32_TC
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      58,	// sub_16bit -> GR32_BPSP_and_GR32_TC
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR32_BSI_and_GR32_SIDI
      59,	// sub_8bit -> GR32_BSI_and_GR32_SIDI
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      59,	// sub_16bit -> GR32_BSI_and_GR32_SIDI
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR32_CB_and_GR32_DC
      60,	// sub_8bit -> GR32_CB_and_GR32_DC
      60,	// sub_8bit_hi -> GR32_CB_and_GR32_DC
      0,	// sub_8bit_hi_phony
      60,	// sub_16bit -> GR32_CB_and_GR32_DC
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR32_DIBP_and_GR32_SIDI
      61,	// sub_8bit -> GR32_DIBP_and_GR32_SIDI
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      61,	// sub_16bit -> GR32_DIBP_and_GR32_SIDI
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
      62,	// sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      62,	// sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
      0,	// sub_16bit_hi
      62,	// sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// LOW32_ADDR_ACCESS_with_sub_32bit
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      63,	// sub_16bit -> LOW32_ADDR_ACCESS_with_sub_32bit
      0,	// sub_16bit_hi
      63,	// sub_32bit -> LOW32_ADDR_ACCESS_with_sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// RFP64
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// FR64X
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64
      69,	// sub_8bit -> GR64_with_sub_8bit
      90,	// sub_8bit_hi -> GR64_ABCD
      0,	// sub_8bit_hi_phony
      66,	// sub_16bit -> GR64
      0,	// sub_16bit_hi
      66,	// sub_32bit -> GR64
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// CONTROL_REG
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// FR64
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_with_sub_8bit
      69,	// sub_8bit -> GR64_with_sub_8bit
      90,	// sub_8bit_hi -> GR64_ABCD
      0,	// sub_8bit_hi_phony
      69,	// sub_16bit -> GR64_with_sub_8bit
      0,	// sub_16bit_hi
      69,	// sub_32bit -> GR64_with_sub_8bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_NOSP
      70,	// sub_8bit -> GR64_NOSP
      90,	// sub_8bit_hi -> GR64_ABCD
      0,	// sub_8bit_hi_phony
      70,	// sub_16bit -> GR64_NOSP
      0,	// sub_16bit_hi
      70,	// sub_32bit -> GR64_NOSP
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_TC
      74,	// sub_8bit -> GR64_TC_with_sub_8bit
      92,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
      0,	// sub_8bit_hi_phony
      71,	// sub_16bit -> GR64_TC
      0,	// sub_16bit_hi
      71,	// sub_32bit -> GR64_TC
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_NOREX
      78,	// sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX
      90,	// sub_8bit_hi -> GR64_ABCD
      0,	// sub_8bit_hi_phony
      72,	// sub_16bit -> GR64_NOREX
      0,	// sub_16bit_hi
      72,	// sub_32bit -> GR64_NOREX
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_TCW64
      76,	// sub_8bit -> GR64_TCW64_with_sub_8bit
      92,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
      0,	// sub_8bit_hi_phony
      73,	// sub_16bit -> GR64_TCW64
      0,	// sub_16bit_hi
      73,	// sub_32bit -> GR64_TCW64
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_TC_with_sub_8bit
      74,	// sub_8bit -> GR64_TC_with_sub_8bit
      92,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
      0,	// sub_8bit_hi_phony
      74,	// sub_16bit -> GR64_TC_with_sub_8bit
      0,	// sub_16bit_hi
      74,	// sub_32bit -> GR64_TC_with_sub_8bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_NOSP_and_GR64_TC
      75,	// sub_8bit -> GR64_NOSP_and_GR64_TC
      92,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
      0,	// sub_8bit_hi_phony
      75,	// sub_16bit -> GR64_NOSP_and_GR64_TC
      0,	// sub_16bit_hi
      75,	// sub_32bit -> GR64_NOSP_and_GR64_TC
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_TCW64_with_sub_8bit
      76,	// sub_8bit -> GR64_TCW64_with_sub_8bit
      92,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
      0,	// sub_8bit_hi_phony
      76,	// sub_16bit -> GR64_TCW64_with_sub_8bit
      0,	// sub_16bit_hi
      76,	// sub_32bit -> GR64_TCW64_with_sub_8bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_TC_and_GR64_TCW64
      84,	// sub_8bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
      92,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
      0,	// sub_8bit_hi_phony
      77,	// sub_16bit -> GR64_TC_and_GR64_TCW64
      0,	// sub_16bit_hi
      77,	// sub_32bit -> GR64_TC_and_GR64_TCW64
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_with_sub_16bit_in_GR16_NOREX
      78,	// sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX
      90,	// sub_8bit_hi -> GR64_ABCD
      0,	// sub_8bit_hi_phony
      78,	// sub_16bit -> GR64_with_sub_16bit_in_GR16_NOREX
      0,	// sub_16bit_hi
      78,	// sub_32bit -> GR64_with_sub_16bit_in_GR16_NOREX
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// VK64
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// VR64
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_NOREX_NOSP
      81,	// sub_8bit -> GR64_NOREX_NOSP
      90,	// sub_8bit_hi -> GR64_ABCD
      0,	// sub_8bit_hi_phony
      81,	// sub_16bit -> GR64_NOREX_NOSP
      0,	// sub_16bit_hi
      81,	// sub_32bit -> GR64_NOREX_NOSP
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_NOREX_and_GR64_TC
      87,	// sub_8bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
      92,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
      0,	// sub_8bit_hi_phony
      82,	// sub_16bit -> GR64_NOREX_and_GR64_TC
      0,	// sub_16bit_hi
      82,	// sub_32bit -> GR64_NOREX_and_GR64_TC
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_NOSP_and_GR64_TCW64
      83,	// sub_8bit -> GR64_NOSP_and_GR64_TCW64
      92,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
      0,	// sub_8bit_hi_phony
      83,	// sub_16bit -> GR64_NOSP_and_GR64_TCW64
      0,	// sub_16bit_hi
      83,	// sub_32bit -> GR64_NOSP_and_GR64_TCW64
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_TCW64_and_GR64_TC_with_sub_8bit
      84,	// sub_8bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
      92,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
      0,	// sub_8bit_hi_phony
      84,	// sub_16bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
      0,	// sub_16bit_hi
      84,	// sub_32bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// VK64WM
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_TC_and_GR64_NOSP_and_GR64_TCW64
      86,	// sub_8bit -> GR64_TC_and_GR64_NOSP_and_GR64_TCW64
      92,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
      0,	// sub_8bit_hi_phony
      86,	// sub_16bit -> GR64_TC_and_GR64_NOSP_and_GR64_TCW64
      0,	// sub_16bit_hi
      86,	// sub_32bit -> GR64_TC_and_GR64_NOSP_and_GR64_TCW64
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
      87,	// sub_8bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
      92,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
      0,	// sub_8bit_hi_phony
      87,	// sub_16bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
      0,	// sub_16bit_hi
      87,	// sub_32bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_NOREX_NOSP_and_GR64_TC
      88,	// sub_8bit -> GR64_NOREX_NOSP_and_GR64_TC
      92,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
      0,	// sub_8bit_hi_phony
      88,	// sub_16bit -> GR64_NOREX_NOSP_and_GR64_TC
      0,	// sub_16bit_hi
      88,	// sub_32bit -> GR64_NOREX_NOSP_and_GR64_TC
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_NOREX_and_GR64_TCW64
      91,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_TC
      92,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
      0,	// sub_8bit_hi_phony
      89,	// sub_16bit -> GR64_NOREX_and_GR64_TCW64
      0,	// sub_16bit_hi
      89,	// sub_32bit -> GR64_NOREX_and_GR64_TCW64
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_ABCD
      90,	// sub_8bit -> GR64_ABCD
      90,	// sub_8bit_hi -> GR64_ABCD
      0,	// sub_8bit_hi_phony
      90,	// sub_16bit -> GR64_ABCD
      0,	// sub_16bit_hi
      90,	// sub_32bit -> GR64_ABCD
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_with_sub_32bit_in_GR32_TC
      91,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_TC
      92,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
      0,	// sub_8bit_hi_phony
      91,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_TC
      0,	// sub_16bit_hi
      91,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_TC
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
      92,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
      92,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
      0,	// sub_8bit_hi_phony
      92,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
      0,	// sub_16bit_hi
      92,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_AD
      93,	// sub_8bit -> GR64_AD
      93,	// sub_8bit_hi -> GR64_AD
      0,	// sub_8bit_hi_phony
      93,	// sub_16bit -> GR64_AD
      0,	// sub_16bit_hi
      93,	// sub_32bit -> GR64_AD
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_and_LOW32_ADDR_ACCESS_RBP
      104,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      94,	// sub_16bit -> GR64_and_LOW32_ADDR_ACCESS_RBP
      0,	// sub_16bit_hi
      94,	// sub_32bit -> GR64_and_LOW32_ADDR_ACCESS_RBP
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_with_sub_32bit_in_GR32_BPSP
      95,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      95,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP
      0,	// sub_16bit_hi
      95,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_with_sub_32bit_in_GR32_BSI
      96,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_BSI
      102,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
      0,	// sub_8bit_hi_phony
      96,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_BSI
      0,	// sub_16bit_hi
      96,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_BSI
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_with_sub_32bit_in_GR32_CB
      97,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_CB
      97,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_CB
      0,	// sub_8bit_hi_phony
      97,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_CB
      0,	// sub_16bit_hi
      97,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_CB
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_with_sub_32bit_in_GR32_DC
      98,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_DC
      98,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_DC
      0,	// sub_8bit_hi_phony
      98,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_DC
      0,	// sub_16bit_hi
      98,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_DC
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_with_sub_32bit_in_GR32_DIBP
      99,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_DIBP
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      99,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_DIBP
      0,	// sub_16bit_hi
      99,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_DIBP
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_with_sub_32bit_in_GR32_SIDI
      100,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_SIDI
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      100,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_SIDI
      0,	// sub_16bit_hi
      100,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_SIDI
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_and_LOW32_ADDR_ACCESS
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      101,	// sub_16bit -> GR64_and_LOW32_ADDR_ACCESS
      0,	// sub_16bit_hi
      101,	// sub_32bit -> GR64_and_LOW32_ADDR_ACCESS
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
      102,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
      102,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
      0,	// sub_8bit_hi_phony
      102,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
      0,	// sub_16bit_hi
      102,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
      103,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
      103,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
      0,	// sub_8bit_hi_phony
      103,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
      0,	// sub_16bit_hi
      103,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
      104,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      104,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
      0,	// sub_16bit_hi
      104,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
      105,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      105,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
      0,	// sub_16bit_hi
      105,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
      106,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      106,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
      0,	// sub_16bit_hi
      106,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
      107,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
      107,	// sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
      0,	// sub_8bit_hi_phony
      107,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
      0,	// sub_16bit_hi
      107,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
      108,	// sub_8bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      108,	// sub_16bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
      0,	// sub_16bit_hi
      108,	// sub_32bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// RST
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// RFP80
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// RFP80_7
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// VR128X
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// VR128
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// BNDR
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      0,	// sub_xmm
      0,	// sub_ymm
    },
    {	// VR256X
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      115,	// sub_xmm -> VR256X
      0,	// sub_ymm
    },
    {	// VR256
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      116,	// sub_xmm -> VR256
      0,	// sub_ymm
    },
    {	// VR512
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      117,	// sub_xmm -> VR512
      117,	// sub_ymm -> VR512
    },
    {	// VR512_0_15
      0,	// sub_8bit
      0,	// sub_8bit_hi
      0,	// sub_8bit_hi_phony
      0,	// sub_16bit
      0,	// sub_16bit_hi
      0,	// sub_32bit
      0,	// sub_mask_0
      0,	// sub_mask_1
      118,	// sub_xmm -> VR512_0_15
      118,	// sub_ymm -> VR512_0_15
    },
  };
  assert(RC && "Missing regclass");
  if (!Idx) return RC;
  --Idx;
  assert(Idx < 10 && "Bad subreg");
  unsigned TV = Table[RC->getID()][Idx];
  return TV ? getRegClass(TV - 1) : nullptr;
}

/// Get the weight in units of pressure for this register class.
const RegClassWeight &X86GenRegisterInfo::
getRegClassWeight(const TargetRegisterClass *RC) const {
  static const RegClassWeight RCWeightTable[] = {
    {1, 20},  	// GR8
    {0, 0},  	// GRH8
    {1, 8},  	// GR8_NOREX
    {1, 4},  	// GR8_ABCD_H
    {1, 4},  	// GR8_ABCD_L
    {0, 0},  	// GRH16
    {2, 32},  	// GR16
    {2, 16},  	// GR16_NOREX
    {1, 8},  	// VK1
    {1, 8},  	// VK16
    {1, 8},  	// VK2
    {1, 8},  	// VK4
    {1, 8},  	// VK8
    {1, 7},  	// VK16WM
    {1, 7},  	// VK1WM
    {1, 7},  	// VK2WM
    {1, 7},  	// VK4WM
    {1, 7},  	// VK8WM
    {1, 6},  	// SEGMENT_REG
    {2, 8},  	// GR16_ABCD
    {0, 0},  	// FPCCR
    {2, 8},  	// VK16PAIR
    {2, 8},  	// VK1PAIR
    {2, 8},  	// VK2PAIR
    {2, 8},  	// VK4PAIR
    {2, 8},  	// VK8PAIR
    {2, 6},  	// VK16PAIR_with_sub_mask_0_in_VK16WM
    {1, 32},  	// FR32X
    {2, 34},  	// LOW32_ADDR_ACCESS_RBP
    {2, 34},  	// LOW32_ADDR_ACCESS
    {2, 32},  	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit
    {1, 16},  	// DEBUG_REG
    {1, 16},  	// FR32
    {2, 32},  	// GR32
    {2, 30},  	// GR32_NOSP
    {2, 16},  	// LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
    {2, 16},  	// GR32_NOREX
    {1, 8},  	// VK32
    {2, 14},  	// GR32_NOREX_NOSP
    {1, 7},  	// RFP32
    {1, 7},  	// VK32WM
    {2, 8},  	// GR32_ABCD
    {2, 8},  	// GR32_TC
    {2, 6},  	// GR32_ABCD_and_GR32_TC
    {2, 4},  	// GR32_AD
    {2, 4},  	// GR32_BPSP
    {2, 4},  	// GR32_BSI
    {2, 4},  	// GR32_CB
    {2, 4},  	// GR32_DC
    {2, 4},  	// GR32_DIBP
    {2, 4},  	// GR32_SIDI
    {2, 4},  	// LOW32_ADDR_ACCESS_RBP_with_sub_32bit
    {0, 0},  	// CCR
    {0, 0},  	// DFCCR
    {2, 2},  	// GR32_ABCD_and_GR32_BSI
    {2, 2},  	// GR32_AD_and_GR32_DC
    {2, 2},  	// GR32_BPSP_and_GR32_DIBP
    {2, 2},  	// GR32_BPSP_and_GR32_TC
    {2, 2},  	// GR32_BSI_and_GR32_SIDI
    {2, 2},  	// GR32_CB_and_GR32_DC
    {2, 2},  	// GR32_DIBP_and_GR32_SIDI
    {2, 2},  	// LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
    {2, 2},  	// LOW32_ADDR_ACCESS_with_sub_32bit
    {1, 7},  	// RFP64
    {1, 32},  	// FR64X
    {2, 34},  	// GR64
    {1, 16},  	// CONTROL_REG
    {1, 16},  	// FR64
    {2, 32},  	// GR64_with_sub_8bit
    {2, 30},  	// GR64_NOSP
    {2, 20},  	// GR64_TC
    {2, 18},  	// GR64_NOREX
    {2, 18},  	// GR64_TCW64
    {2, 18},  	// GR64_TC_with_sub_8bit
    {2, 16},  	// GR64_NOSP_and_GR64_TC
    {2, 16},  	// GR64_TCW64_with_sub_8bit
    {2, 16},  	// GR64_TC_and_GR64_TCW64
    {2, 16},  	// GR64_with_sub_16bit_in_GR16_NOREX
    {1, 8},  	// VK64
    {1, 8},  	// VR64
    {2, 14},  	// GR64_NOREX_NOSP
    {2, 14},  	// GR64_NOREX_and_GR64_TC
    {2, 14},  	// GR64_NOSP_and_GR64_TCW64
    {2, 14},  	// GR64_TCW64_and_GR64_TC_with_sub_8bit
    {1, 7},  	// VK64WM
    {2, 12},  	// GR64_TC_and_GR64_NOSP_and_GR64_TCW64
    {2, 12},  	// GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
    {2, 10},  	// GR64_NOREX_NOSP_and_GR64_TC
    {2, 10},  	// GR64_NOREX_and_GR64_TCW64
    {2, 8},  	// GR64_ABCD
    {2, 8},  	// GR64_with_sub_32bit_in_GR32_TC
    {2, 6},  	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
    {2, 4},  	// GR64_AD
    {2, 4},  	// GR64_and_LOW32_ADDR_ACCESS_RBP
    {2, 4},  	// GR64_with_sub_32bit_in_GR32_BPSP
    {2, 4},  	// GR64_with_sub_32bit_in_GR32_BSI
    {2, 4},  	// GR64_with_sub_32bit_in_GR32_CB
    {2, 4},  	// GR64_with_sub_32bit_in_GR32_DC
    {2, 4},  	// GR64_with_sub_32bit_in_GR32_DIBP
    {2, 4},  	// GR64_with_sub_32bit_in_GR32_SIDI
    {2, 2},  	// GR64_and_LOW32_ADDR_ACCESS
    {2, 2},  	// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
    {2, 2},  	// GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
    {2, 2},  	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
    {2, 2},  	// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
    {2, 2},  	// GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
    {2, 2},  	// GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
    {2, 2},  	// GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
    {0, 0},  	// RST
    {1, 7},  	// RFP80
    {0, 0},  	// RFP80_7
    {1, 32},  	// VR128X
    {1, 16},  	// VR128
    {1, 4},  	// BNDR
    {1, 32},  	// VR256X
    {1, 16},  	// VR256
    {1, 32},  	// VR512
    {1, 16},  	// VR512_0_15
  };
  return RCWeightTable[RC->getID()];
}

/// Get the weight in units of pressure for this register unit.
unsigned X86GenRegisterInfo::
getRegUnitWeight(unsigned RegUnit) const {
  assert(RegUnit < 164 && "invalid register unit");
  // All register units have unit weight.
  return 1;
}


// Get the number of dimensions of register pressure.
unsigned X86GenRegisterInfo::getNumRegPressureSets() const {
  return 33;
}

// Get the name of this register unit pressure set.
const char *X86GenRegisterInfo::
getRegPressureSetName(unsigned Idx) const {
  static const char *const PressureNameTable[] = {
    "BNDR",
    "SEGMENT_REG",
    "GR32_BPSP",
    "LOW32_ADDR_ACCESS_with_sub_32bit",
    "GR32_BSI",
    "GR32_SIDI",
    "GR32_DIBP+GR32_SIDI",
    "GR32_DIBP+LOW32_ADDR_ACCESS_with_sub_32bit",
    "RFP32",
    "GR8_ABCD_H+GR32_BSI",
    "GR8_ABCD_L+GR32_BSI",
    "VK1",
    "VR64",
    "GR8_NOREX",
    "GR32_TC",
    "GR32_BPSP+GR32_TC",
    "DEBUG_REG",
    "FR32",
    "CONTROL_REG",
    "GR64_NOREX",
    "GR64_TCW64",
    "GR32_BPSP+GR64_TCW64",
    "GR8",
    "GR8+GR32_DIBP",
    "GR8+GR32_BSI",
    "GR64_TC+GR64_TCW64",
    "GR8+LOW32_ADDR_ACCESS_with_sub_32bit",
    "GR8+GR64_NOREX",
    "GR64_TC",
    "GR8+GR64_TCW64",
    "GR8+GR64_TC",
    "FR32X",
    "GR16",
  };
  return PressureNameTable[Idx];
}

// Get the register unit pressure limit for this dimension.
// This limit must be adjusted dynamically for reserved registers.
unsigned X86GenRegisterInfo::
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
  static const uint8_t PressureLimitTable[] = {
    4,  	// 0: BNDR
    6,  	// 1: SEGMENT_REG
    6,  	// 2: GR32_BPSP
    6,  	// 3: LOW32_ADDR_ACCESS_with_sub_32bit
    6,  	// 4: GR32_BSI
    6,  	// 5: GR32_SIDI
    6,  	// 6: GR32_DIBP+GR32_SIDI
    6,  	// 7: GR32_DIBP+LOW32_ADDR_ACCESS_with_sub_32bit
    7,  	// 8: RFP32
    7,  	// 9: GR8_ABCD_H+GR32_BSI
    7,  	// 10: GR8_ABCD_L+GR32_BSI
    8,  	// 11: VK1
    8,  	// 12: VR64
    10,  	// 13: GR8_NOREX
    12,  	// 14: GR32_TC
    12,  	// 15: GR32_BPSP+GR32_TC
    16,  	// 16: DEBUG_REG
    16,  	// 17: FR32
    16,  	// 18: CONTROL_REG
    18,  	// 19: GR64_NOREX
    20,  	// 20: GR64_TCW64
    20,  	// 21: GR32_BPSP+GR64_TCW64
    22,  	// 22: GR8
    22,  	// 23: GR8+GR32_DIBP
    22,  	// 24: GR8+GR32_BSI
    22,  	// 25: GR64_TC+GR64_TCW64
    23,  	// 26: GR8+LOW32_ADDR_ACCESS_with_sub_32bit
    26,  	// 27: GR8+GR64_NOREX
    26,  	// 28: GR64_TC
    27,  	// 29: GR8+GR64_TCW64
    28,  	// 30: GR8+GR64_TC
    32,  	// 31: FR32X
    34,  	// 32: GR16
  };
  return PressureLimitTable[Idx];
}

/// Table of pressure sets per register class or unit.
static const int RCSetsTable[] = {
  /* 0 */ 0, -1,
  /* 2 */ 1, -1,
  /* 4 */ 8, -1,
  /* 6 */ 11, -1,
  /* 8 */ 12, -1,
  /* 10 */ 16, -1,
  /* 12 */ 18, -1,
  /* 14 */ 17, 31, -1,
  /* 17 */ 19, 27, 28, 32, -1,
  /* 22 */ 2, 3, 15, 19, 21, 22, 27, 28, 32, -1,
  /* 32 */ 2, 6, 7, 19, 23, 27, 28, 32, -1,
  /* 41 */ 3, 7, 15, 19, 21, 26, 27, 28, 32, -1,
  /* 51 */ 2, 3, 6, 7, 15, 19, 21, 22, 23, 26, 27, 28, 32, -1,
  /* 65 */ 20, 21, 25, 28, 29, 32, -1,
  /* 72 */ 25, 28, 30, 32, -1,
  /* 77 */ 4, 5, 9, 10, 13, 19, 24, 27, 28, 30, 32, -1,
  /* 89 */ 19, 25, 27, 28, 30, 32, -1,
  /* 96 */ 5, 6, 19, 24, 25, 27, 28, 30, 32, -1,
  /* 106 */ 4, 5, 6, 9, 10, 13, 19, 24, 25, 27, 28, 30, 32, -1,
  /* 120 */ 2, 5, 6, 7, 19, 23, 24, 25, 27, 28, 30, 32, -1,
  /* 133 */ 22, 23, 24, 26, 27, 29, 30, 32, -1,
  /* 142 */ 20, 21, 25, 28, 29, 30, 32, -1,
  /* 150 */ 14, 15, 19, 20, 21, 25, 27, 28, 29, 30, 32, -1,
  /* 162 */ 2, 3, 14, 15, 19, 20, 21, 22, 25, 27, 28, 29, 30, 32, -1,
  /* 177 */ 4, 13, 14, 19, 20, 22, 23, 24, 26, 27, 28, 29, 30, 32, -1,
  /* 192 */ 9, 13, 14, 19, 20, 22, 23, 24, 26, 27, 28, 29, 30, 32, -1,
  /* 207 */ 4, 5, 9, 10, 13, 14, 19, 20, 22, 23, 24, 26, 27, 28, 29, 30, 32, -1,
  /* 225 */ 2, 3, 6, 7, 15, 19, 21, 22, 23, 24, 26, 27, 28, 29, 30, 32, -1,
  /* 242 */ 3, 7, 14, 15, 19, 20, 21, 25, 26, 27, 28, 29, 30, 32, -1,
  /* 257 */ 2, 5, 6, 7, 19, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32, -1,
  /* 273 */ 4, 5, 6, 9, 10, 13, 19, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32, -1,
  /* 291 */ 2, 3, 14, 15, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32, -1,
  /* 309 */ 4, 13, 14, 15, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32, -1,
  /* 327 */ 4, 9, 13, 14, 15, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32, -1,
  /* 346 */ 4, 10, 13, 14, 15, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32, -1,
};

/// Get the dimensions of register pressure impacted by this register class.
/// Returns a -1 terminated array of pressure set IDs
const int* X86GenRegisterInfo::
getRegClassPressureSets(const TargetRegisterClass *RC) const {
  static const uint16_t RCSetStartTable[] = {
    133,1,178,192,210,1,20,17,6,6,6,6,6,6,6,6,6,6,2,178,1,6,6,6,6,6,6,15,20,20,20,10,14,20,20,17,17,6,17,4,6,178,164,310,310,22,77,177,310,32,96,41,1,1,207,310,51,162,106,309,120,51,242,4,15,20,12,14,20,20,72,17,65,72,72,65,142,17,6,8,17,89,65,142,6,142,89,98,150,178,164,310,310,41,22,77,177,310,32,96,242,207,310,51,162,106,309,120,1,4,1,15,14,0,15,14,15,14,};
  return &RCSetsTable[RCSetStartTable[RC->getID()]];
}

/// Get the dimensions of register pressure impacted by this register unit.
/// Returns a -1 terminated array of pressure set IDs
const int* X86GenRegisterInfo::
getRegUnitPressureSets(unsigned RegUnit) const {
  assert(RegUnit < 164 && "invalid register unit");
  static const uint16_t RUSetStartTable[] = {
    328,347,207,207,225,1,327,346,2,1,328,257,1,347,2,1,1,1,1,1,1,1,242,1,1,2,273,1,1,291,1,1,1,1,2,2,1,1,2,1,0,0,0,0,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,4,4,4,4,4,4,4,1,6,6,6,6,6,6,6,6,8,8,8,8,8,8,8,8,296,1,1,296,1,1,296,1,1,296,1,1,133,1,1,133,1,1,133,1,1,133,1,1,1,1,1,1,1,1,1,1,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,};
  return &RCSetsTable[RUSetStartTable[RegUnit]];
}

extern const MCRegisterDesc X86RegDesc[];
extern const MCPhysReg X86RegDiffLists[];
extern const LaneBitmask X86LaneMaskLists[];
extern const char X86RegStrings[];
extern const char X86RegClassStrings[];
extern const MCPhysReg X86RegUnitRoots[][2];
extern const uint16_t X86SubRegIdxLists[];
extern const MCRegisterInfo::SubRegCoveredBits X86SubRegIdxRanges[];
extern const uint16_t X86RegEncodingTable[];
// X86 Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[];
extern const unsigned X86DwarfFlavour0Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[];
extern const unsigned X86DwarfFlavour1Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[];
extern const unsigned X86DwarfFlavour2Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[];
extern const unsigned X86EHFlavour0Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[];
extern const unsigned X86EHFlavour1Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[];
extern const unsigned X86EHFlavour2Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[];
extern const unsigned X86DwarfFlavour0L2DwarfSize;

extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[];
extern const unsigned X86DwarfFlavour1L2DwarfSize;

extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[];
extern const unsigned X86DwarfFlavour2L2DwarfSize;

extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[];
extern const unsigned X86EHFlavour0L2DwarfSize;

extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[];
extern const unsigned X86EHFlavour1L2DwarfSize;

extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[];
extern const unsigned X86EHFlavour2L2DwarfSize;

X86GenRegisterInfo::
X86GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
      unsigned PC, unsigned HwMode)
  : TargetRegisterInfo(X86RegInfoDesc, RegisterClasses, RegisterClasses+118,
             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
             LaneBitmask(0xFFFFFFB0), RegClassInfos, HwMode) {
  InitMCRegisterInfo(X86RegDesc, 283, RA, PC,
                     X86MCRegisterClasses, 118,
                     X86RegUnitRoots,
                     164,
                     X86RegDiffLists,
                     X86LaneMaskLists,
                     X86RegStrings,
                     X86RegClassStrings,
                     X86SubRegIdxLists,
                     11,
                     X86SubRegIdxRanges,
                     X86RegEncodingTable);

  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapDwarfRegsToLLVMRegs(X86DwarfFlavour0Dwarf2L, X86DwarfFlavour0Dwarf2LSize, false);
    break;
  case 1:
    mapDwarfRegsToLLVMRegs(X86DwarfFlavour1Dwarf2L, X86DwarfFlavour1Dwarf2LSize, false);
    break;
  case 2:
    mapDwarfRegsToLLVMRegs(X86DwarfFlavour2Dwarf2L, X86DwarfFlavour2Dwarf2LSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapDwarfRegsToLLVMRegs(X86EHFlavour0Dwarf2L, X86EHFlavour0Dwarf2LSize, true);
    break;
  case 1:
    mapDwarfRegsToLLVMRegs(X86EHFlavour1Dwarf2L, X86EHFlavour1Dwarf2LSize, true);
    break;
  case 2:
    mapDwarfRegsToLLVMRegs(X86EHFlavour2Dwarf2L, X86EHFlavour2Dwarf2LSize, true);
    break;
  }
  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapLLVMRegsToDwarfRegs(X86DwarfFlavour0L2Dwarf, X86DwarfFlavour0L2DwarfSize, false);
    break;
  case 1:
    mapLLVMRegsToDwarfRegs(X86DwarfFlavour1L2Dwarf, X86DwarfFlavour1L2DwarfSize, false);
    break;
  case 2:
    mapLLVMRegsToDwarfRegs(X86DwarfFlavour2L2Dwarf, X86DwarfFlavour2L2DwarfSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapLLVMRegsToDwarfRegs(X86EHFlavour0L2Dwarf, X86EHFlavour0L2DwarfSize, true);
    break;
  case 1:
    mapLLVMRegsToDwarfRegs(X86EHFlavour1L2Dwarf, X86EHFlavour1L2DwarfSize, true);
    break;
  case 2:
    mapLLVMRegsToDwarfRegs(X86EHFlavour2L2Dwarf, X86EHFlavour2L2DwarfSize, true);
    break;
  }
}

static const MCPhysReg CSR_32_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
static const uint32_t CSR_32_RegMask[] = { 0x058703f0, 0x38002581, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_32EHRet_SaveList[] = { X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
static const uint32_t CSR_32EHRet_RegMask[] = { 0x0def83fe, 0x38002dc1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_32_AllRegs_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, 0 };
static const uint32_t CSR_32_AllRegs_RegMask[] = { 0x0fefaffe, 0x38002fc1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_32_AllRegs_AVX_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, 0 };
static const uint32_t CSR_32_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0x38002fc1, 0x00000000, 0x00000000, 0x007f8000, 0x007f8000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_32_AllRegs_AVX512_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
static const uint32_t CSR_32_AllRegs_AVX512_RegMask[] = { 0x0fefaffe, 0x38002fc1, 0x00000000, 0x007f8000, 0x007f8000, 0x007f8000, 0x007f8000, 0x00000000, 0x07800000, };
static const MCPhysReg CSR_32_AllRegs_SSE_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 };
static const uint32_t CSR_32_AllRegs_SSE_RegMask[] = { 0x0fefaffe, 0x38002fc1, 0x00000000, 0x00000000, 0x007f8000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_32_RegCall_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 };
static const uint32_t CSR_32_RegCall_RegMask[] = { 0x058703f0, 0xf8006583, 0x00000001, 0x00000000, 0x00780000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_32_RegCall_NoSSE_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, 0 };
static const uint32_t CSR_32_RegCall_NoSSE_RegMask[] = { 0x058703f0, 0xf8006583, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_64_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
static const uint32_t CSR_64_RegMask[] = { 0x018003f0, 0x000c0180, 0x00000000, 0x00000000, 0x00000078, 0x00000000, 0x00000000, 0x78780000, 0x00787878, };
static const MCPhysReg CSR_64EHRet_SaveList[] = { X86::RAX, X86::RDX, X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
static const uint32_t CSR_64EHRet_RegMask[] = { 0x09e883fe, 0x004e09c0, 0x00000000, 0x00000000, 0x00000078, 0x00000000, 0x00000000, 0x78780000, 0x00787878, };
static const MCPhysReg CSR_64_AllRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::RAX, 0 };
static const uint32_t CSR_64_AllRegs_RegMask[] = { 0x0fefaffe, 0x3a7e2fc1, 0x00000000, 0x80000000, 0x7fff807f, 0x00000000, 0x00000000, 0xffff8000, 0x007fffff, };
static const MCPhysReg CSR_64_AllRegs_AVX_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
static const uint32_t CSR_64_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0x3a7e2fc1, 0x00000000, 0x80000000, 0x7fff807f, 0x7fff8000, 0x00000000, 0xffff8000, 0x007fffff, };
static const MCPhysReg CSR_64_AllRegs_AVX512_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
static const uint32_t CSR_64_AllRegs_AVX512_RegMask[] = { 0x0fefaffe, 0x3a7e2fc1, 0x00000000, 0x807f8000, 0xffff807f, 0xffffffff, 0xffffffff, 0xffffffff, 0x07ffffff, };
static const MCPhysReg CSR_64_AllRegs_NoSSE_SaveList[] = { X86::RAX, X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
static const uint32_t CSR_64_AllRegs_NoSSE_RegMask[] = { 0x0fefaffe, 0x3a7e2fc1, 0x00000000, 0x80000000, 0x0000007f, 0x00000000, 0x00000000, 0xffff8000, 0x007fffff, };
static const MCPhysReg CSR_64_CXX_TLS_Darwin_PE_SaveList[] = { X86::RBP, 0 };
static const uint32_t CSR_64_CXX_TLS_Darwin_PE_RegMask[] = { 0x008001c0, 0x00040080, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RCX, X86::RDX, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, 0 };
static const uint32_t CSR_64_CXX_TLS_Darwin_ViaCopy_RegMask[] = { 0x0b28ae30, 0x3a582b01, 0x00000000, 0x80000000, 0x0000007f, 0x00000000, 0x00000000, 0xffff8000, 0x007fffff, };
static const MCPhysReg CSR_64_HHVM_SaveList[] = { X86::R12, 0 };
static const uint32_t CSR_64_HHVM_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008, 0x00000000, 0x00000000, 0x08080000, 0x00080808, };
static const MCPhysReg CSR_64_Intel_OCL_BI_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
static const uint32_t CSR_64_Intel_OCL_BI_RegMask[] = { 0x018003f0, 0x000c0180, 0x00000000, 0x00000000, 0x7f800078, 0x00000000, 0x00000000, 0x78780000, 0x00787878, };
static const MCPhysReg CSR_64_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
static const uint32_t CSR_64_Intel_OCL_BI_AVX_RegMask[] = { 0x018003f0, 0x000c0180, 0x00000000, 0x00000000, 0x7f800078, 0x7f800000, 0x00000000, 0x78780000, 0x00787878, };
static const MCPhysReg CSR_64_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RDI, X86::RSI, X86::R14, X86::R15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
static const uint32_t CSR_64_Intel_OCL_BI_AVX512_RegMask[] = { 0x05070230, 0x3a282501, 0x00000000, 0x00780000, 0x80000060, 0x80007fff, 0x80007fff, 0x60607fff, 0x06606060, };
static const MCPhysReg CSR_64_MostRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
static const uint32_t CSR_64_MostRegs_RegMask[] = { 0x0fafaff0, 0x3a7c2f81, 0x00000000, 0x80000000, 0x7fff807f, 0x00000000, 0x00000000, 0xffff8000, 0x007fffff, };
static const MCPhysReg CSR_64_RT_AllRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::RSP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
static const uint32_t CSR_64_RT_AllRegs_RegMask[] = { 0x0fefaffe, 0xfe7e6fc3, 0x00000001, 0x80000000, 0x7fff807b, 0x00000000, 0x00000000, 0xfbfb8000, 0x007bfbfb, };
static const MCPhysReg CSR_64_RT_AllRegs_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::RSP, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
static const uint32_t CSR_64_RT_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xfe7e6fc3, 0x00000001, 0x80000000, 0x7fff807b, 0x7fff8000, 0x00000000, 0xfbfb8000, 0x007bfbfb, };
static const MCPhysReg CSR_64_RT_MostRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::RSP, 0 };
static const uint32_t CSR_64_RT_MostRegs_RegMask[] = { 0x0fefaffe, 0xfe7e6fc3, 0x00000001, 0x80000000, 0x0000007b, 0x00000000, 0x00000000, 0xfbfb8000, 0x007bfbfb, };
static const MCPhysReg CSR_64_SwiftError_SaveList[] = { X86::RBX, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
static const uint32_t CSR_64_SwiftError_RegMask[] = { 0x018003f0, 0x000c0180, 0x00000000, 0x00000000, 0x00000070, 0x00000000, 0x00000000, 0x70700000, 0x00707070, };
static const MCPhysReg CSR_64_TLS_Darwin_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RCX, X86::RDX, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, 0 };
static const uint32_t CSR_64_TLS_Darwin_RegMask[] = { 0x0ba8aff0, 0x3a5c2b81, 0x00000000, 0x80000000, 0x0000007f, 0x00000000, 0x00000000, 0xffff8000, 0x007fffff, };
static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_SysV64_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::RSP, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
static const uint32_t CSR_SysV64_RegCall_RegMask[] = { 0x018003f0, 0xc40c4182, 0x00000001, 0x00000000, 0x7f800078, 0x00000000, 0x00000000, 0x78780000, 0x00787878, };
static const MCPhysReg CSR_SysV64_RegCall_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::RSP, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
static const uint32_t CSR_SysV64_RegCall_NoSSE_RegMask[] = { 0x018003f0, 0xc40c4182, 0x00000001, 0x00000000, 0x00000078, 0x00000000, 0x00000000, 0x78780000, 0x00787878, };
static const MCPhysReg CSR_Win32_CFGuard_Check_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::ECX, 0 };
static const uint32_t CSR_Win32_CFGuard_Check_RegMask[] = { 0x07872ff0, 0xf8006783, 0x00000001, 0x00000000, 0x00780000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_Win32_CFGuard_Check_NoSSE_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::ECX, 0 };
static const uint32_t CSR_Win32_CFGuard_Check_NoSSE_RegMask[] = { 0x07872ff0, 0xf8006783, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_Win64_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
static const uint32_t CSR_Win64_RegMask[] = { 0x058703f0, 0x3a2c2581, 0x00000000, 0x00000000, 0x7fe00078, 0x00000000, 0x00000000, 0x78780000, 0x00787878, };
static const MCPhysReg CSR_Win64_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
static const uint32_t CSR_Win64_Intel_OCL_BI_AVX_RegMask[] = { 0x058703f0, 0x3a2c2581, 0x00000000, 0x00000000, 0x7fe00078, 0x7fe00000, 0x00000000, 0x78780000, 0x00787878, };
static const MCPhysReg CSR_Win64_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
static const uint32_t CSR_Win64_Intel_OCL_BI_AVX512_RegMask[] = { 0x058703f0, 0x3a2c2581, 0x00000000, 0x00780000, 0xffe00078, 0xffe0001f, 0xffe0001f, 0x7878001f, 0x06787878, };
static const MCPhysReg CSR_Win64_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
static const uint32_t CSR_Win64_NoSSE_RegMask[] = { 0x058703f0, 0x3a2c2581, 0x00000000, 0x00000000, 0x00000078, 0x00000000, 0x00000000, 0x78780000, 0x00787878, };
static const MCPhysReg CSR_Win64_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::RSP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
static const uint32_t CSR_Win64_RegCall_RegMask[] = { 0x018003f0, 0xc40c4182, 0x00000001, 0x00000000, 0x7f80007e, 0x00000000, 0x00000000, 0x7e7e0000, 0x007e7e7e, };
static const MCPhysReg CSR_Win64_RegCall_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::RSP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
static const uint32_t CSR_Win64_RegCall_NoSSE_RegMask[] = { 0x018003f0, 0xc40c4182, 0x00000001, 0x00000000, 0x0000007e, 0x00000000, 0x00000000, 0x7e7e0000, 0x007e7e7e, };
static const MCPhysReg CSR_Win64_SwiftError_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R13, X86::R14, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
static const uint32_t CSR_Win64_SwiftError_RegMask[] = { 0x058703f0, 0x3a2c2581, 0x00000000, 0x00000000, 0x7fe00070, 0x00000000, 0x00000000, 0x70700000, 0x00707070, };


ArrayRef<const uint32_t *> X86GenRegisterInfo::getRegMasks() const {
  static const uint32_t *const Masks[] = {
    CSR_32_RegMask,
    CSR_32EHRet_RegMask,
    CSR_32_AllRegs_RegMask,
    CSR_32_AllRegs_AVX_RegMask,
    CSR_32_AllRegs_AVX512_RegMask,
    CSR_32_AllRegs_SSE_RegMask,
    CSR_32_RegCall_RegMask,
    CSR_32_RegCall_NoSSE_RegMask,
    CSR_64_RegMask,
    CSR_64EHRet_RegMask,
    CSR_64_AllRegs_RegMask,
    CSR_64_AllRegs_AVX_RegMask,
    CSR_64_AllRegs_AVX512_RegMask,
    CSR_64_AllRegs_NoSSE_RegMask,
    CSR_64_CXX_TLS_Darwin_PE_RegMask,
    CSR_64_CXX_TLS_Darwin_ViaCopy_RegMask,
    CSR_64_HHVM_RegMask,
    CSR_64_Intel_OCL_BI_RegMask,
    CSR_64_Intel_OCL_BI_AVX_RegMask,
    CSR_64_Intel_OCL_BI_AVX512_RegMask,
    CSR_64_MostRegs_RegMask,
    CSR_64_RT_AllRegs_RegMask,
    CSR_64_RT_AllRegs_AVX_RegMask,
    CSR_64_RT_MostRegs_RegMask,
    CSR_64_SwiftError_RegMask,
    CSR_64_TLS_Darwin_RegMask,
    CSR_NoRegs_RegMask,
    CSR_SysV64_RegCall_RegMask,
    CSR_SysV64_RegCall_NoSSE_RegMask,
    CSR_Win32_CFGuard_Check_RegMask,
    CSR_Win32_CFGuard_Check_NoSSE_RegMask,
    CSR_Win64_RegMask,
    CSR_Win64_Intel_OCL_BI_AVX_RegMask,
    CSR_Win64_Intel_OCL_BI_AVX512_RegMask,
    CSR_Win64_NoSSE_RegMask,
    CSR_Win64_RegCall_RegMask,
    CSR_Win64_RegCall_NoSSE_RegMask,
    CSR_Win64_SwiftError_RegMask,
  };
  return makeArrayRef(Masks);
}

ArrayRef<const char *> X86GenRegisterInfo::getRegMaskNames() const {
  static const char *const Names[] = {
    "CSR_32",
    "CSR_32EHRet",
    "CSR_32_AllRegs",
    "CSR_32_AllRegs_AVX",
    "CSR_32_AllRegs_AVX512",
    "CSR_32_AllRegs_SSE",
    "CSR_32_RegCall",
    "CSR_32_RegCall_NoSSE",
    "CSR_64",
    "CSR_64EHRet",
    "CSR_64_AllRegs",
    "CSR_64_AllRegs_AVX",
    "CSR_64_AllRegs_AVX512",
    "CSR_64_AllRegs_NoSSE",
    "CSR_64_CXX_TLS_Darwin_PE",
    "CSR_64_CXX_TLS_Darwin_ViaCopy",
    "CSR_64_HHVM",
    "CSR_64_Intel_OCL_BI",
    "CSR_64_Intel_OCL_BI_AVX",
    "CSR_64_Intel_OCL_BI_AVX512",
    "CSR_64_MostRegs",
    "CSR_64_RT_AllRegs",
    "CSR_64_RT_AllRegs_AVX",
    "CSR_64_RT_MostRegs",
    "CSR_64_SwiftError",
    "CSR_64_TLS_Darwin",
    "CSR_NoRegs",
    "CSR_SysV64_RegCall",
    "CSR_SysV64_RegCall_NoSSE",
    "CSR_Win32_CFGuard_Check",
    "CSR_Win32_CFGuard_Check_NoSSE",
    "CSR_Win64",
    "CSR_Win64_Intel_OCL_BI_AVX",
    "CSR_Win64_Intel_OCL_BI_AVX512",
    "CSR_Win64_NoSSE",
    "CSR_Win64_RegCall",
    "CSR_Win64_RegCall_NoSSE",
    "CSR_Win64_SwiftError",
  };
  return makeArrayRef(Names);
}

const X86FrameLowering *
X86GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
  return static_cast<const X86FrameLowering *>(
      MF.getSubtarget().getFrameLowering());
}

} // end namespace llvm

#endif // GET_REGINFO_TARGET_DESC