)]}'
{
  "commit": "ed2c06b20a04fc07f0a54b7ce01f19c98bd5a3ab",
  "tree": "95acfc131e0648835391099e9b58f231db835238",
  "parents": [
    "7cb12682204f56e0c49f695599c434f77ed6cf29"
  ],
  "author": {
    "name": "John Porto",
    "email": "jpp@chromium.org",
    "time": "Thu Oct 01 15:27:15 2015 -0700"
  },
  "committer": {
    "name": "John Porto",
    "email": "jpp@chromium.org",
    "time": "Thu Oct 01 15:27:15 2015 -0700"
  },
  "message": "Subzero. Adds I64 register pairs for ARM32.\n\nThis is in preparation for llvm.nacl.atomic.* lowerings. atomic i64\nloads and stores require their operands to be consecutive registers\nstarting at an even register that is not r14.\n\nBUG\u003d https://code.google.com/p/nativeclient/issues/detail?id\u003d4076\nR\u003dkschimpf@google.com\n\nReview URL: https://codereview.chromium.org/1382063002 .\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "3fb6898b272776388bf37a893e26b3a7f0ca62c9",
      "old_mode": 33188,
      "old_path": "src/IceInstARM32.def",
      "new_id": "b8a9778f578b5072fd354bc92366b5c0787d703a",
      "new_mode": 33188,
      "new_path": "src/IceInstARM32.def"
    },
    {
      "type": "modify",
      "old_id": "eafed3afde27a9cfbfce75a9c5969eed959aa4c6",
      "old_mode": 33188,
      "old_path": "src/IceRegistersARM32.h",
      "new_id": "88577559968e6e56f7537e7e730a98ec401026a1",
      "new_mode": 33188,
      "new_path": "src/IceRegistersARM32.h"
    },
    {
      "type": "modify",
      "old_id": "99be924fd7c131c2f06fd205d73962d90af9a3ce",
      "old_mode": 33188,
      "old_path": "src/IceTargetLoweringARM32.cpp",
      "new_id": "d9c57c25562296a287e29b304e7884425851d341",
      "new_mode": 33188,
      "new_path": "src/IceTargetLoweringARM32.cpp"
    }
  ]
}