Add VORR instruction to the integrated ARM assembler.
Also simplify several switch statements by replacing type entries with
default.
BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334
Review URL: https://codereview.chromium.org/1661633002 .
diff --git a/src/DartARM32/assembler_arm.cc b/src/DartARM32/assembler_arm.cc
index 54bc3d8..41bc3ca 100644
--- a/src/DartARM32/assembler_arm.cc
+++ b/src/DartARM32/assembler_arm.cc
@@ -1306,11 +1306,12 @@
EmitSIMDqqq(B24 | B8 | B4, kByte, qd, qn, qm);
}
-
+#if 0
+// Moved to ARM32::AssemblerARM32::vorrq()
void Assembler::vorrq(QRegister qd, QRegister qn, QRegister qm) {
EmitSIMDqqq(B21 | B8 | B4, kByte, qd, qn, qm);
}
-
+#endif
void Assembler::vornq(QRegister qd, QRegister qn, QRegister qm) {
EmitSIMDqqq(B21 | B20 | B8 | B4, kByte, qd, qn, qm);
diff --git a/src/IceAssemblerARM32.cpp b/src/IceAssemblerARM32.cpp
index 4049920..d996a56 100644
--- a/src/IceAssemblerARM32.cpp
+++ b/src/IceAssemblerARM32.cpp
@@ -2191,13 +2191,13 @@
void AssemblerARM32::vandq(const Operand *OpQd, const Operand *OpQm,
const Operand *OpQn) {
// VAND (register) - ARM section A8.8.287, encoding A1:
- // vand.<dt> <Qd>, <Qn>, <Qm>
+ // vand <Qd>, <Qn>, <Qm>
//
// 111100100D00nnn0ddd00001N1M1mmm0 where Dddd=OpQd, Nnnn=OpQm, and Mmmm=OpQm.
- constexpr const char *Vandqi = "vandqi";
- constexpr IValueT VandqiOpcode = B8 | B4;
+ constexpr const char *Vandq = "vandq";
+ constexpr IValueT VandqOpcode = B8 | B4;
constexpr Type ElmtTy = IceType_i8;
- emitSIMDqqq(VandqiOpcode, ElmtTy, OpQd, OpQm, OpQn, Vandqi);
+ emitSIMDqqq(VandqOpcode, ElmtTy, OpQd, OpQm, OpQn, Vandq);
}
void AssemblerARM32::vcmpd(const Operand *OpDd, const Operand *OpDm,
@@ -2722,6 +2722,18 @@
emitVFPddd(Cond, VmuldOpcode, OpDd, OpDn, OpDm, Vmuld);
}
+void AssemblerARM32::vorrq(const Operand *OpQd, const Operand *OpQm,
+ const Operand *OpQn) {
+ // VORR (register) - ARM section A8.8.360, encoding A1:
+ // vorr <Qd>, <Qn>, <Qm>
+ //
+ // 111100100D10nnn0ddd00001N1M1mmm0 where Dddd=OpQd, Nnnn=OpQm, and Mmmm=OpQm.
+ constexpr const char *Vorrq = "vandq";
+ constexpr IValueT VorrqOpcode = B21 | B8 | B4;
+ constexpr Type ElmtTy = IceType_i8;
+ emitSIMDqqq(VorrqOpcode, ElmtTy, OpQd, OpQm, OpQn, Vorrq);
+}
+
void AssemblerARM32::vstrd(const Operand *OpDd, const Operand *OpAddress,
CondARM32::Cond Cond, const TargetInfo &TInfo) {
// VSTR - ARM section A8.8.413, encoding A1:
diff --git a/src/IceAssemblerARM32.h b/src/IceAssemblerARM32.h
index ee5e9c0..58d50be 100644
--- a/src/IceAssemblerARM32.h
+++ b/src/IceAssemblerARM32.h
@@ -432,6 +432,8 @@
void vmuls(const Operand *OpSd, const Operand *OpSn, const Operand *OpSm,
CondARM32::Cond Cond);
+ void vorrq(const Operand *OpQd, const Operand *OpQm, const Operand *OpQn);
+
void vpop(const Variable *OpBaseReg, SizeT NumConsecRegs,
CondARM32::Cond Cond);
diff --git a/src/IceInstARM32.cpp b/src/IceInstARM32.cpp
index 843e0f5..e0793c3 100644
--- a/src/IceInstARM32.cpp
+++ b/src/IceInstARM32.cpp
@@ -618,16 +618,7 @@
const Variable *Dest = getDest();
Type DestTy = Dest->getType();
switch (DestTy) {
- case IceType_void:
- case IceType_i1:
- case IceType_i8:
- case IceType_i16:
- case IceType_i32:
- case IceType_i64:
- case IceType_v4i1:
- case IceType_v8i1:
- case IceType_v16i1:
- case IceType_NUM:
+ default:
llvm::report_fatal_error("Vadd not defined on type " +
typeIceString(DestTy));
break;
@@ -650,7 +641,6 @@
}
template <> void InstARM32Vand::emitIAS(const Cfg *Func) const {
- // TODO(kschimpf): add support for these instructions
auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
const Variable *Dest = getDest();
switch (Dest->getType()) {
@@ -742,8 +732,21 @@
}
template <> void InstARM32Vorr::emitIAS(const Cfg *Func) const {
- // TODO(kschimpf): add support for these instructions
- emitUsingTextFixup(Func);
+ auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
+ const Variable *Dest = getDest();
+ switch (Dest->getType()) {
+ default:
+ llvm::report_fatal_error("Vorr not defined on type " +
+ typeIceString(Dest->getType()));
+ case IceType_v4i1:
+ case IceType_v8i1:
+ case IceType_v16i1:
+ case IceType_v16i8:
+ case IceType_v8i16:
+ case IceType_v4i32:
+ Asm->vorrq(Dest, getSrc(0), getSrc(1));
+ }
+ assert(!Asm->needsTextFixup());
}
template <> void InstARM32Vsub::emitIAS(const Cfg *Func) const {
@@ -751,16 +754,7 @@
const Variable *Dest = getDest();
Type DestTy = Dest->getType();
switch (DestTy) {
- case IceType_void:
- case IceType_i1:
- case IceType_i8:
- case IceType_i16:
- case IceType_i32:
- case IceType_i64:
- case IceType_v4i1:
- case IceType_v8i1:
- case IceType_v16i1:
- case IceType_NUM:
+ default:
llvm::report_fatal_error("Vsub not defined on type " +
typeIceString(DestTy));
case IceType_v16i8:
diff --git a/src/IceTargetLoweringARM32.cpp b/src/IceTargetLoweringARM32.cpp
index 7a19f11..34069eb 100644
--- a/src/IceTargetLoweringARM32.cpp
+++ b/src/IceTargetLoweringARM32.cpp
@@ -2976,6 +2976,7 @@
}
case InstArithmetic::Or: {
Variable *Src0R = Srcs.src0R(this);
+ assert(isIntegerType(DestTy));
if (isVectorType(DestTy)) {
Variable *Src1R = legalizeToReg(Src1);
_vorr(T, Src0R, Src1R);
diff --git a/tests_lit/assembler/arm32/or-vec.ll b/tests_lit/assembler/arm32/or-vec.ll
index dd9a51f..b6cf580 100644
--- a/tests_lit/assembler/arm32/or-vec.ll
+++ b/tests_lit/assembler/arm32/or-vec.ll
@@ -30,7 +30,7 @@
; ASM: vorr.i32 q0, q0, q1
; DIS: 0: f2200152
-; IASM: vorr.i32
+; IASM-NOT: vorr.i32
ret <4 x i32> %res
}
@@ -45,7 +45,7 @@
; ASM: vorr.i16 q0, q0, q1
; DIS: 10: f2200152
-; IASM: vorr.i16
+; IASM-NOT: vorr.i16
ret <8 x i16> %res
}
@@ -60,7 +60,7 @@
; ASM: vorr.i8 q0, q0, q1
; DIS: 20: f2200152
-; IASM: vorr.i8
+; IASM-NOT: vorr.i8
ret <16 x i8> %res
}
@@ -79,7 +79,7 @@
; ASM: vorr.i32 q0, q0, q1
; DIS: 30: f2200152
-; IASM: vorr.i32
+; IASM-NOT: vorr.i32
ret <4 x i1> %res
}
@@ -94,7 +94,7 @@
; ASM: vorr.i16 q0, q0, q1
; DIS: 40: f2200152
-; IASM: vorr.i16
+; IASM-NOT: vorr.i16
ret <8 x i1> %res
}
@@ -109,7 +109,7 @@
; ASM: vorr.i8 q0, q0, q1
; DIS: 50: f2200152
-; IASM: vorr.i8
+; IASM-NOT: vorr.i8
ret <16 x i1> %res
}
