Convert lit tests to check disassembled assembly.
Then when we have an integrated assembler, we can check
its disassembly and the result should be the same.
This only touches the tests that invoke llvm-mc currently.
There are other tests which check for .s file output.
There are quite a bit of quirks with llvm-objdump,
which is unfortunate:
(*) The symbolizer doesn't pick up non-section-local
function calls. Some externals were converted to be
local functions. Workaround: where it counts, I just
left a check via .s files and a new --check-prefix.
It's a little better in 3.6.
(*) The symbolizer doesn't pick up global variable names.
I just checked for the relocation addend instead.
Didn't check if it was better in 3.6, but maybe.
(*) We have a bug in bundling lock + instructions.
See
BUG=https://code.google.com/p/nativeclient/issues/detail?id=3929
(*) There's no disassembly for branch lables.
Checks of jump instructions were converted to check
for positive or negative values, depending on whether
it is a forward or backward branch.
BUG=none
R=stichnot@chromium.org
Review URL: https://codereview.chromium.org/509233002
diff --git a/tests_lit/llvm2ice_tests/64bit.pnacl.ll b/tests_lit/llvm2ice_tests/64bit.pnacl.ll
index 0989b96..58091dd 100644
--- a/tests_lit/llvm2ice_tests/64bit.pnacl.ll
+++ b/tests_lit/llvm2ice_tests/64bit.pnacl.ll
@@ -2,12 +2,19 @@
; particular the patterns for lowering i64 operations into constituent
; i32 operations on x86-32.
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck --check-prefix=OPTM1 %s
+; TODO(jvoung): fix extra "CALLTARGETS" run. The llvm-objdump symbolizer
+; doesn't know how to symbolize non-section-local functions.
+; The newer LLVM 3.6 one does work, but watch out for other bugs.
+
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | FileCheck --check-prefix=CALLTARGETS %s
+; RUN: %llvm2ice -O2 --verbose none %s \
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice -Om1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: | FileCheck --check-prefix=OPTM1 %s
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
@@ -33,50 +40,54 @@
ret i32 %add3
}
; CHECK-LABEL: pass64BitArg
+; CALLTARGETS-LABEL: pass64BitArg
; CHECK: sub esp
-; CHECK: mov dword ptr [esp+4]
+; CHECK: mov dword ptr [esp + 4]
; CHECK: mov dword ptr [esp]
-; CHECK: mov dword ptr [esp+8], 123
-; CHECK: mov dword ptr [esp+16]
-; CHECK: mov dword ptr [esp+12]
-; CHECK: call ignore64BitArgNoInline
-; CHECK sub esp
-; CHECK: mov dword ptr [esp+4]
-; CHECK: mov dword ptr [esp]
-; CHECK: mov dword ptr [esp+8], 123
-; CHECK: mov dword ptr [esp+16]
-; CHECK: mov dword ptr [esp+12]
-; CHECK: call ignore64BitArgNoInline
+; CHECK: mov dword ptr [esp + 8], 123
+; CHECK: mov dword ptr [esp + 16]
+; CHECK: mov dword ptr [esp + 12]
+; CHECK: call -4
+; CALLTARGETS: call ignore64BitArgNoInline
; CHECK: sub esp
-; CHECK: mov dword ptr [esp+4]
+; CHECK: mov dword ptr [esp + 4]
; CHECK: mov dword ptr [esp]
-; CHECK: mov dword ptr [esp+8], 123
-; CHECK: mov dword ptr [esp+16]
-; CHECK: mov dword ptr [esp+12]
-; CHECK: call ignore64BitArgNoInline
+; CHECK: mov dword ptr [esp + 8], 123
+; CHECK: mov dword ptr [esp + 16]
+; CHECK: mov dword ptr [esp + 12]
+; CHECK: call -4
+; CALLTARGETS: call ignore64BitArgNoInline
+; CHECK: sub esp
+; CHECK: mov dword ptr [esp + 4]
+; CHECK: mov dword ptr [esp]
+; CHECK: mov dword ptr [esp + 8], 123
+; CHECK: mov dword ptr [esp + 16]
+; CHECK: mov dword ptr [esp + 12]
+; CHECK: call -4
+; CALLTARGETS: call ignore64BitArgNoInline
;
; OPTM1-LABEL: pass64BitArg
; OPTM1: sub esp
-; OPTM1: mov dword ptr [esp+4]
+; OPTM1: mov dword ptr [esp + 4]
; OPTM1: mov dword ptr [esp]
-; OPTM1: mov dword ptr [esp+8], 123
-; OPTM1: mov dword ptr [esp+16]
-; OPTM1: mov dword ptr [esp+12]
-; OPTM1: call ignore64BitArgNoInline
-; OPTM1 sub esp
-; OPTM1: mov dword ptr [esp+4]
-; OPTM1: mov dword ptr [esp]
-; OPTM1: mov dword ptr [esp+8], 123
-; OPTM1: mov dword ptr [esp+16]
-; OPTM1: mov dword ptr [esp+12]
-; OPTM1: call ignore64BitArgNoInline
+; OPTM1: mov dword ptr [esp + 8], 123
+; OPTM1: mov dword ptr [esp + 16]
+; OPTM1: mov dword ptr [esp + 12]
+; OPTM1: call -4
; OPTM1: sub esp
-; OPTM1: mov dword ptr [esp+4]
+; OPTM1: mov dword ptr [esp + 4]
; OPTM1: mov dword ptr [esp]
-; OPTM1: mov dword ptr [esp+8], 123
-; OPTM1: mov dword ptr [esp+16]
-; OPTM1: mov dword ptr [esp+12]
-; OPTM1: call ignore64BitArgNoInline
+; OPTM1: mov dword ptr [esp + 8], 123
+; OPTM1: mov dword ptr [esp + 16]
+; OPTM1: mov dword ptr [esp + 12]
+; OPTM1: call -4
+; OPTM1: sub esp
+; OPTM1: mov dword ptr [esp + 4]
+; OPTM1: mov dword ptr [esp]
+; OPTM1: mov dword ptr [esp + 8], 123
+; OPTM1: mov dword ptr [esp + 16]
+; OPTM1: mov dword ptr [esp + 12]
+; OPTM1: call -4
declare i32 @ignore64BitArgNoInline(i64, i32, i64)
@@ -86,35 +97,41 @@
ret i32 %call
}
; CHECK-LABEL: pass64BitConstArg
+; CALLTARGETS-LABEL: pass64BitConstArg
; CHECK: sub esp
-; CHECK: mov dword ptr [esp+4]
+; CHECK: mov dword ptr [esp + 4]
; CHECK-NEXT: mov dword ptr [esp]
-; CHECK-NEXT: mov dword ptr [esp+8], 123
-; CHECK-NEXT: mov dword ptr [esp+16], 3735928559
-; CHECK-NEXT: mov dword ptr [esp+12], 305419896
-; CHECK-NEXT: call ignore64BitArgNoInline
+; CHECK-NEXT: mov dword ptr [esp + 8], 123
+; Bundle padding added by -triple=i686-none-nacl.
+; CHECK-NEXT: nop
+; CHECK-NEXT: mov dword ptr [esp + 16], 3735928559
+; CHECK-NEXT: mov dword ptr [esp + 12], 305419896
+; CHECK-NEXT: call -4
+; CALLTARGETS: call ignore64BitArgNoInline
;
; OPTM1-LABEL: pass64BitConstArg
; OPTM1: sub esp
-; OPTM1: mov dword ptr [esp+4]
+; OPTM1: mov dword ptr [esp + 4]
; OPTM1-NEXT: mov dword ptr [esp]
-; OPTM1-NEXT: mov dword ptr [esp+8], 123
-; OPTM1-NEXT: mov dword ptr [esp+16], 3735928559
-; OPTM1-NEXT: mov dword ptr [esp+12], 305419896
-; OPTM1-NEXT: call ignore64BitArgNoInline
+; OPTM1-NEXT: mov dword ptr [esp + 8], 123
+; Bundle padding added by -triple=i686-none-nacl.
+; OPTM1-NEXT: nop
+; OPTM1-NEXT: mov dword ptr [esp + 16], 3735928559
+; OPTM1-NEXT: mov dword ptr [esp + 12], 305419896
+; OPTM1-NEXT: call -4
define internal i64 @return64BitArg(i64 %a) {
entry:
ret i64 %a
}
; CHECK-LABEL: return64BitArg
-; CHECK: mov {{.*}}, dword ptr [esp+4]
-; CHECK: mov {{.*}}, dword ptr [esp+8]
+; CHECK: mov {{.*}}, dword ptr [esp + 4]
+; CHECK: mov {{.*}}, dword ptr [esp + 8]
; CHECK: ret
;
; OPTM1-LABEL: return64BitArg
-; OPTM1: mov {{.*}}, dword ptr [esp+4]
-; OPTM1: mov {{.*}}, dword ptr [esp+8]
+; OPTM1: mov {{.*}}, dword ptr [esp + 4]
+; OPTM1: mov {{.*}}, dword ptr [esp + 8]
; OPTM1: ret
define internal i64 @return64BitConst() {
@@ -239,11 +256,13 @@
ret i64 %div
}
; CHECK-LABEL: div64BitSigned
-; CHECK: call __divdi3
+; CALLTARGETS-LABEL: div64BitSigned
+; CHECK: call -4
+; CALLTARGETS: call __divdi3
; CHECK: ret
-;
+
; OPTM1-LABEL: div64BitSigned
-; OPTM1: call __divdi3
+; OPTM1: call -4
; OPTM1: ret
define internal i64 @div64BitSignedConst(i64 %a) {
@@ -252,15 +271,17 @@
ret i64 %div
}
; CHECK-LABEL: div64BitSignedConst
-; CHECK: mov dword ptr [esp+12], 2874
-; CHECK: mov dword ptr [esp+8], 1942892530
-; CHECK: call __divdi3
+; CALLTARGETS-LABEL: div64BitSignedConst
+; CHECK: mov dword ptr [esp + 12], 2874
+; CHECK: mov dword ptr [esp + 8], 1942892530
+; CHECK: call -4
+; CALLTARGETS: call __divdi3
; CHECK: ret
;
; OPTM1-LABEL: div64BitSignedConst
-; OPTM1: mov dword ptr [esp+12], 2874
-; OPTM1: mov dword ptr [esp+8], 1942892530
-; OPTM1: call __divdi3
+; OPTM1: mov dword ptr [esp + 12], 2874
+; OPTM1: mov dword ptr [esp + 8], 1942892530
+; OPTM1: call -4
; OPTM1: ret
define internal i64 @div64BitUnsigned(i64 %a, i64 %b) {
@@ -269,11 +290,13 @@
ret i64 %div
}
; CHECK-LABEL: div64BitUnsigned
-; CHECK: call __udivdi3
+; CALLTARGETS-LABEL: div64BitUnsigned
+; CHECK: call -4
+; CALLTARGETS: call __udivdi3
; CHECK: ret
;
; OPTM1-LABEL: div64BitUnsigned
-; OPTM1: call __udivdi3
+; OPTM1: call -4
; OPTM1: ret
define internal i64 @rem64BitSigned(i64 %a, i64 %b) {
@@ -282,11 +305,13 @@
ret i64 %rem
}
; CHECK-LABEL: rem64BitSigned
-; CHECK: call __moddi3
+; CALLTARGETS-LABEL: rem64BitSigned
+; CHECK: call -4
+; CALLTARGETS: call __moddi3
; CHECK: ret
;
; OPTM1-LABEL: rem64BitSigned
-; OPTM1: call __moddi3
+; OPTM1: call -4
; OPTM1: ret
define internal i64 @rem64BitUnsigned(i64 %a, i64 %b) {
@@ -295,11 +320,13 @@
ret i64 %rem
}
; CHECK-LABEL: rem64BitUnsigned
-; CHECK: call __umoddi3
+; CALLTARGETS-LABEL: rem64BitUnsigned
+; CHECK: call -4
+; CALLTARGETS: call __umoddi3
; CHECK: ret
;
; OPTM1-LABEL: rem64BitUnsigned
-; OPTM1: call __umoddi3
+; OPTM1: call -4
; OPTM1: ret
define internal i64 @shl64BitSigned(i64 %a, i64 %b) {
@@ -456,11 +483,11 @@
ret i32 %conv
}
; CHECK-LABEL: trunc64To32Signed
-; CHECK: mov eax, dword ptr [esp+4]
+; CHECK: mov eax, dword ptr [esp + 4]
; CHECK-NEXT: ret
;
; OPTM1-LABEL: trunc64To32Signed
-; OPTM1: mov eax, dword ptr [esp+
+; OPTM1: mov eax, dword ptr [esp +
; OPTM1: ret
define internal i32 @trunc64To16Signed(i64 %a) {
@@ -470,12 +497,12 @@
ret i32 %conv.ret_ext
}
; CHECK-LABEL: trunc64To16Signed
-; CHECK: mov eax, dword ptr [esp+4]
+; CHECK: mov eax, dword ptr [esp + 4]
; CHECK-NEXT: movsx eax, ax
; CHECK-NEXT: ret
;
; OPTM1-LABEL: trunc64To16Signed
-; OPTM1: mov eax, dword ptr [esp+
+; OPTM1: mov eax, dword ptr [esp +
; OPTM1: movsx eax,
; OPTM1: ret
@@ -486,12 +513,12 @@
ret i32 %conv.ret_ext
}
; CHECK-LABEL: trunc64To8Signed
-; CHECK: mov eax, dword ptr [esp+4]
+; CHECK: mov eax, dword ptr [esp + 4]
; CHECK-NEXT: movsx eax, al
; CHECK-NEXT: ret
;
; OPTM1-LABEL: trunc64To8Signed
-; OPTM1: mov eax, dword ptr [esp+
+; OPTM1: mov eax, dword ptr [esp +
; OPTM1: movsx eax,
; OPTM1: ret
@@ -526,11 +553,11 @@
ret i32 %conv
}
; CHECK-LABEL: trunc64To32Unsigned
-; CHECK: mov eax, dword ptr [esp+4]
+; CHECK: mov eax, dword ptr [esp + 4]
; CHECK-NEXT: ret
;
; OPTM1-LABEL: trunc64To32Unsigned
-; OPTM1: mov eax, dword ptr [esp+
+; OPTM1: mov eax, dword ptr [esp +
; OPTM1: ret
define internal i32 @trunc64To16Unsigned(i64 %a) {
@@ -540,12 +567,12 @@
ret i32 %conv.ret_ext
}
; CHECK-LABEL: trunc64To16Unsigned
-; CHECK: mov eax, dword ptr [esp+4]
+; CHECK: mov eax, dword ptr [esp + 4]
; CHECK-NEXT: movzx eax, ax
; CHECK-NEXT: ret
;
; OPTM1-LABEL: trunc64To16Unsigned
-; OPTM1: mov eax, dword ptr [esp+
+; OPTM1: mov eax, dword ptr [esp +
; OPTM1: movzx eax,
; OPTM1: ret
@@ -556,12 +583,12 @@
ret i32 %conv.ret_ext
}
; CHECK-LABEL: trunc64To8Unsigned
-; CHECK: mov eax, dword ptr [esp+4]
+; CHECK: mov eax, dword ptr [esp + 4]
; CHECK-NEXT: movzx eax, al
; CHECK-NEXT: ret
;
; OPTM1-LABEL: trunc64To8Unsigned
-; OPTM1: mov eax, dword ptr [esp+
+; OPTM1: mov eax, dword ptr [esp +
; OPTM1: movzx eax,
; OPTM1: ret
@@ -573,12 +600,12 @@
ret i32 %tobool.ret_ext
}
; CHECK-LABEL: trunc64To1
-; CHECK: mov eax, dword ptr [esp+4]
+; CHECK: mov eax, dword ptr [esp + 4]
; CHECK: and eax, 1
; CHECK-NEXT: ret
;
; OPTM1-LABEL: trunc64To1
-; OPTM1: mov eax, dword ptr [esp+
+; OPTM1: mov eax, dword ptr [esp +
; OPTM1: and eax, 1
; OPTM1: ret
@@ -1107,13 +1134,13 @@
ret i64 %v0
}
; CHECK-LABEL: load64
-; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp+4]
+; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp + 4]
; CHECK-NEXT: mov {{.*}}, dword ptr [e[[REGISTER]]]
-; CHECK-NEXT: mov {{.*}}, dword ptr [e[[REGISTER]]+4]
+; CHECK-NEXT: mov {{.*}}, dword ptr [e[[REGISTER]] + 4]
;
; OPTM1-LABEL: load64
; OPTM1: mov e{{..}}, dword ptr [e{{..}}]
-; OPTM1: mov e{{..}}, dword ptr [e{{..}}+4]
+; OPTM1: mov e{{..}}, dword ptr [e{{..}} + 4]
define internal void @store64(i32 %a, i64 %value) {
entry:
@@ -1122,12 +1149,12 @@
ret void
}
; CHECK-LABEL: store64
-; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp+4]
-; CHECK: mov dword ptr [e[[REGISTER]]+4],
+; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp + 4]
+; CHECK: mov dword ptr [e[[REGISTER]] + 4],
; CHECK: mov dword ptr [e[[REGISTER]]],
;
; OPTM1-LABEL: store64
-; OPTM1: mov dword ptr [e[[REGISTER:[a-z]+]]+4],
+; OPTM1: mov dword ptr [e[[REGISTER:[a-z]+]] + 4],
; OPTM1: mov dword ptr [e[[REGISTER]]],
define internal void @store64Const(i32 %a) {
@@ -1137,12 +1164,12 @@
ret void
}
; CHECK-LABEL: store64Const
-; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp+4]
-; CHECK: mov dword ptr [e[[REGISTER]]+4], 3735928559
+; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp + 4]
+; CHECK: mov dword ptr [e[[REGISTER]] + 4], 3735928559
; CHECK: mov dword ptr [e[[REGISTER]]], 305419896
;
; OPTM1-LABEL: store64Const
-; OPTM1: mov dword ptr [e[[REGISTER:[a-z]+]]+4], 3735928559
+; OPTM1: mov dword ptr [e[[REGISTER:[a-z]+]] + 4], 3735928559
; OPTM1: mov dword ptr [e[[REGISTER]]], 305419896
define internal i64 @select64VarVar(i64 %a, i64 %b) {
diff --git a/tests_lit/llvm2ice_tests/address-mode-opt.ll b/tests_lit/llvm2ice_tests/address-mode-opt.ll
index 3543c6d..08fd091 100644
--- a/tests_lit/llvm2ice_tests/address-mode-opt.ll
+++ b/tests_lit/llvm2ice_tests/address-mode-opt.ll
@@ -1,8 +1,8 @@
; This file checks support for address mode optimization.
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
define float @load_arg_plus_200000(float* %arg) {
@@ -13,7 +13,7 @@
%addr.load = load float* %addr.ptr, align 4
ret float %addr.load
; CHECK-LABEL: load_arg_plus_200000:
-; CHECK: movss xmm0, dword ptr [eax+200000]
+; CHECK: movss xmm0, dword ptr [eax + 200000]
}
define float @load_200000_plus_arg(float* %arg) {
@@ -24,7 +24,7 @@
%addr.load = load float* %addr.ptr, align 4
ret float %addr.load
; CHECK-LABEL: load_200000_plus_arg:
-; CHECK: movss xmm0, dword ptr [eax+200000]
+; CHECK: movss xmm0, dword ptr [eax + 200000]
}
define float @load_arg_minus_200000(float* %arg) {
@@ -35,7 +35,7 @@
%addr.load = load float* %addr.ptr, align 4
ret float %addr.load
; CHECK-LABEL: load_arg_minus_200000:
-; CHECK: movss xmm0, dword ptr [eax-200000]
+; CHECK: movss xmm0, dword ptr [eax - 200000]
}
define float @load_200000_minus_arg(float* %arg) {
@@ -58,7 +58,7 @@
%addr2.load = load float* %addr2.ptr, align 4
ret float %addr2.load
; CHECK-LABEL: address_mode_opt_chaining:
-; CHECK: movss xmm0, dword ptr [eax+8]
+; CHECK: movss xmm0, dword ptr [eax + 8]
}
; ERRORS-NOT: ICE translation error
diff --git a/tests_lit/llvm2ice_tests/alloc.ll b/tests_lit/llvm2ice_tests/alloc.ll
index af87f78..80bba30 100644
--- a/tests_lit/llvm2ice_tests/alloc.ll
+++ b/tests_lit/llvm2ice_tests/alloc.ll
@@ -1,11 +1,11 @@
; This is a basic test of the alloca instruction.
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice -Om1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
@@ -32,7 +32,7 @@
ret void
}
; CHECK-LABEL: fixed_416_align_32:
-; CHECK: and esp, 4294967264
+; CHECK: and esp, -32
; CHECK: sub esp, 416
; CHECK: sub esp, 16
; CHECK: mov dword ptr [esp], eax
@@ -59,13 +59,16 @@
ret void
}
; CHECK-LABEL: fixed_351_align_32:
-; CHECK: and esp, 4294967264
+; CHECK: and esp, -32
; CHECK: sub esp, 352
; CHECK: sub esp, 16
; CHECK: mov dword ptr [esp], eax
; CHECK: call f1
-declare void @f1(i32)
+define void @f1(i32 %ignored) {
+entry:
+ ret void
+}
define void @variable_n_align_16(i32 %n) {
entry:
@@ -75,9 +78,9 @@
ret void
}
; CHECK-LABEL: variable_n_align_16:
-; CHECK: mov eax, dword ptr [ebp+8]
+; CHECK: mov eax, dword ptr [ebp + 8]
; CHECK: add eax, 15
-; CHECK: and eax, 4294967280
+; CHECK: and eax, -16
; CHECK: sub esp, eax
; CHECK: sub esp, 16
; CHECK: mov dword ptr [esp], eax
@@ -92,16 +95,19 @@
}
; In -O2, the order of the CHECK-DAG lines in the output is switched.
; CHECK-LABEL: variable_n_align_32:
-; CHECK-DAG: and esp, 4294967264
-; CHECK-DAG: mov eax, dword ptr [ebp+8]
+; CHECK-DAG: and esp, -32
+; CHECK-DAG: mov eax, dword ptr [ebp + 8]
; CHECK: add eax, 31
-; CHECK: and eax, 4294967264
+; CHECK: and eax, -32
; CHECK: sub esp, eax
; CHECK: sub esp, 16
; CHECK: mov dword ptr [esp], eax
; CHECK: call f2
-declare void @f2(i32)
+define void @f2(i32 %ignored) {
+entry:
+ ret void
+}
; ERRORS-NOT: ICE translation error
; DUMP-NOT: SZ
diff --git a/tests_lit/llvm2ice_tests/bitcast.ll b/tests_lit/llvm2ice_tests/bitcast.ll
index 511b2d8..7d85e07 100644
--- a/tests_lit/llvm2ice_tests/bitcast.ll
+++ b/tests_lit/llvm2ice_tests/bitcast.ll
@@ -1,10 +1,11 @@
; Trivial smoke test of bitcast between integer and FP types.
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice -Om1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
@@ -43,7 +44,7 @@
ret i64 %v0
}
; CHECK-LABEL: cast_d2ll_const
-; CHECK: movsd xmm{{.*}}, {{.*}}L$double
+; CHECK: movsd xmm{{.*}}, qword ptr
; CHECK: mov edx
; CHECK: ret
diff --git a/tests_lit/llvm2ice_tests/callindirect.pnacl.ll b/tests_lit/llvm2ice_tests/callindirect.pnacl.ll
index 5ef2ab5..0636107 100644
--- a/tests_lit/llvm2ice_tests/callindirect.pnacl.ll
+++ b/tests_lit/llvm2ice_tests/callindirect.pnacl.ll
@@ -2,12 +2,13 @@
; should be to the same operand, whether it's in a register or on the
; stack.
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck --check-prefix=OPTM1 %s
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice -Om1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: | FileCheck --check-prefix=OPTM1 %s
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
diff --git a/tests_lit/llvm2ice_tests/cmp-opt.ll b/tests_lit/llvm2ice_tests/cmp-opt.ll
index 0cdf7f3..305dc10 100644
--- a/tests_lit/llvm2ice_tests/cmp-opt.ll
+++ b/tests_lit/llvm2ice_tests/cmp-opt.ll
@@ -1,11 +1,12 @@
; Simple test of non-fused compare/branch.
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck --check-prefix=OPTM1 %s
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice -Om1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: | FileCheck --check-prefix=OPTM1 %s
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
@@ -36,7 +37,7 @@
declare void @use(i32)
-; CHECK: .globl testBool
+; CHECK-LABEL: testBool
; Two bool computations
; CHECK: cmp
; CHECK: cmp
@@ -48,7 +49,7 @@
; CHECK: call
; CHECK: ret
;
-; OPTM1: .globl testBool
+; OPTM1-LABEL: testBool
; Two bool computations
; OPTM1: cmp
; OPTM1: cmp
diff --git a/tests_lit/llvm2ice_tests/convert.ll b/tests_lit/llvm2ice_tests/convert.ll
index 7a971ef..95b5e7d 100644
--- a/tests_lit/llvm2ice_tests/convert.ll
+++ b/tests_lit/llvm2ice_tests/convert.ll
@@ -1,11 +1,14 @@
; Simple test of signed and unsigned integer conversions.
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s
+; TODO(jvoung): llvm-objdump doesn't symbolize global symbols well, so we
+; have [0] == i8v, [2] == i16v, [4] == i32v, [8] == i64v, etc.
+
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice -Om1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
@@ -35,7 +38,7 @@
store i64 %v3, i64* %__7, align 1
ret void
}
-; CHECK: from_int8:
+; CHECK-LABEL: from_int8
; CHECK: mov {{.*}}, byte ptr [
; CHECK: movsx
; CHECK: mov word ptr [
@@ -43,7 +46,7 @@
; CHECK: mov dword ptr [
; CHECK: movsx
; CHECK: sar {{.*}}, 31
-; CHECK: i64v
+; CHECK: [8]
define void @from_int16() {
entry:
@@ -60,14 +63,14 @@
store i64 %v3, i64* %__7, align 1
ret void
}
-; CHECK: from_int16:
+; CHECK-LABEL: from_int16
; CHECK: mov {{.*}}, word ptr [
-; CHECK: i8v
+; CHECK: [0]
; CHECK: movsx
-; CHECK: i32v
+; CHECK: [4]
; CHECK: movsx
; CHECK: sar {{.*}}, 31
-; CHECK: i64v
+; CHECK: [8]
define void @from_int32() {
entry:
@@ -84,12 +87,12 @@
store i64 %v3, i64* %__7, align 1
ret void
}
-; CHECK: from_int32:
-; CHECK: i32v
-; CHECK: i8v
-; CHECK: i16v
+; CHECK-LABEL: from_int32
+; CHECK: [4]
+; CHECK: [0]
+; CHECK: [2]
; CHECK: sar {{.*}}, 31
-; CHECK: i64v
+; CHECK: [8]
define void @from_int64() {
entry:
@@ -106,11 +109,12 @@
store i32 %v3, i32* %__7, align 1
ret void
}
-; CHECK: from_int64:
-; CHECK: i64v
-; CHECK: i8v
-; CHECK: i16v
-; CHECK: i32v
+; CHECK-LABEL: from_int64
+; CHECK: [8]
+; CHECK: [0]
+; CHECK: [2]
+; CHECK: [4]
+
define void @from_uint8() {
entry:
@@ -127,15 +131,15 @@
store i64 %v3, i64* %__7, align 1
ret void
}
-; CHECK: from_uint8:
-; CHECK: u8v
+; CHECK-LABEL: from_uint8
+; CHECK: [16]
; CHECK: movzx
-; CHECK: i16v
+; CHECK: [2]
; CHECK: movzx
-; CHECK: i32v
+; CHECK: [4]
; CHECK: movzx
; CHECK: mov {{.*}}, 0
-; CHECK: i64v
+; CHECK: [8]
define void @from_uint16() {
entry:
@@ -152,14 +156,14 @@
store i64 %v3, i64* %__7, align 1
ret void
}
-; CHECK: from_uint16:
-; CHECK: u16v
-; CHECK: i8v
+; CHECK-LABEL: from_uint16
+; CHECK: [18]
+; CHECK: [0]
; CHECK: movzx
-; CHECK: i32v
+; CHECK: [4]
; CHECK: movzx
; CHECK: mov {{.*}}, 0
-; CHECK: i64v
+; CHECK: [8]
define void @from_uint32() {
entry:
@@ -176,12 +180,12 @@
store i64 %v3, i64* %__7, align 1
ret void
}
-; CHECK: from_uint32:
-; CHECK: u32v
-; CHECK: i8v
-; CHECK: i16v
+; CHECK-LABEL: from_uint32
+; CHECK: [20]
+; CHECK: [0]
+; CHECK: [2]
; CHECK: mov {{.*}}, 0
-; CHECK: i64v
+; CHECK: [8]
define void @from_uint64() {
entry:
@@ -198,11 +202,11 @@
store i32 %v3, i32* %__7, align 1
ret void
}
-; CHECK: from_uint64:
-; CHECK: u64v
-; CHECK: i8v
-; CHECK: i16v
-; CHECK: i32v
+; CHECK-LABEL: from_uint64
+; CHECK: [24]
+; CHECK: [0]
+; CHECK: [2]
+; CHECK: [4]
; ERRORS-NOT: ICE translation error
; DUMP-NOT: SZ
diff --git a/tests_lit/llvm2ice_tests/div_legalization.ll b/tests_lit/llvm2ice_tests/div_legalization.ll
index cce7e17..2fdb3bc 100644
--- a/tests_lit/llvm2ice_tests/div_legalization.ll
+++ b/tests_lit/llvm2ice_tests/div_legalization.ll
@@ -1,12 +1,12 @@
; This is a regression test that idiv and div operands are legalized
; (they cannot be constants and can only be reg/mem for x86).
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice -Om1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
diff --git a/tests_lit/llvm2ice_tests/fp.pnacl.ll b/tests_lit/llvm2ice_tests/fp.pnacl.ll
index bd4db77..ab2f439 100644
--- a/tests_lit/llvm2ice_tests/fp.pnacl.ll
+++ b/tests_lit/llvm2ice_tests/fp.pnacl.ll
@@ -3,12 +3,18 @@
; that should be present regardless of the optimization level, so
; there are no special OPTM1 match lines.
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s
+; TODO(jvoung): fix extra "CALLTARGETS" run. The llvm-objdump symbolizer
+; doesn't know how to symbolize non-section-local functions.
+; The newer LLVM 3.6 one does work, but watch out for other bugs.
+
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | FileCheck --check-prefix=CALLTARGETS %s
+; RUN: %llvm2ice -O2 --verbose none %s \
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice -Om1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
@@ -24,7 +30,7 @@
ret i32 %b
}
; CHECK-LABEL: doubleArgs
-; CHECK: mov eax, dword ptr [esp+12]
+; CHECK: mov eax, dword ptr [esp + 12]
; CHECK-NEXT: ret
define internal i32 @floatArgs(float %a, i32 %b, float %c) {
@@ -32,7 +38,7 @@
ret i32 %b
}
; CHECK-LABEL: floatArgs
-; CHECK: mov eax, dword ptr [esp+8]
+; CHECK: mov eax, dword ptr [esp + 8]
; CHECK-NEXT: ret
define internal i32 @passFpArgs(float %a, double %b, float %c, double %d, float %e, double %f) {
@@ -45,14 +51,17 @@
ret i32 %add3
}
; CHECK-LABEL: passFpArgs
-; CHECK: mov dword ptr [esp+4], 123
+; CHECK: mov dword ptr [esp + 4], 123
; CHECK: call ignoreFpArgsNoInline
-; CHECK: mov dword ptr [esp+4], 123
+; CHECK: mov dword ptr [esp + 4], 123
; CHECK: call ignoreFpArgsNoInline
-; CHECK: mov dword ptr [esp+4], 123
+; CHECK: mov dword ptr [esp + 4], 123
; CHECK: call ignoreFpArgsNoInline
-declare i32 @ignoreFpArgsNoInline(float, i32, double)
+define i32 @ignoreFpArgsNoInline(float %x, i32 %y, double %z) {
+entry:
+ ret i32 %y
+}
define internal i32 @passFpConstArg(float %a, double %b) {
entry:
@@ -60,7 +69,7 @@
ret i32 %call
}
; CHECK-LABEL: passFpConstArg
-; CHECK: mov dword ptr [esp+4], 123
+; CHECK: mov dword ptr [esp + 4], 123
; CHECK: call ignoreFpArgsNoInline
define internal i32 @passFp32ConstArg(float %a) {
@@ -69,11 +78,14 @@
ret i32 %call
}
; CHECK-LABEL: passFp32ConstArg
-; CHECK: mov dword ptr [esp+4], 123
-; CHECK: movss dword ptr [esp+8]
+; CHECK: mov dword ptr [esp + 4], 123
+; CHECK: movss dword ptr [esp + 8]
; CHECK: call ignoreFp32ArgsNoInline
-declare i32 @ignoreFp32ArgsNoInline(float, i32, float)
+define i32 @ignoreFp32ArgsNoInline(float %x, i32 %y, float %z) {
+entry:
+ ret i32 %y
+}
define internal float @returnFloatArg(float %a) {
entry:
@@ -181,7 +193,9 @@
ret float %div
}
; CHECK-LABEL: remFloat
-; CHECK: call fmodf
+; CALLTARGETS-LABEL: remFloat
+; CHECK: call -4
+; CALLTARGETS: call fmodf
define internal double @remDouble(double %a, double %b) {
entry:
@@ -189,7 +203,9 @@
ret double %div
}
; CHECK-LABEL: remDouble
-; CHECK: call fmod
+; CALLTARGETS-LABEL: remDouble
+; CHECK: call -4
+; CALLTARGETS: call fmod
define internal float @fptrunc(double %a) {
entry:
@@ -215,7 +231,9 @@
ret i64 %conv
}
; CHECK-LABEL: doubleToSigned64
-; CHECK: call cvtdtosi64
+; CALLTARGETS-LABEL: doubleToSigned64
+; CHECK: call -4
+; CALLTARGETS: call cvtdtosi64
define internal i64 @floatToSigned64(float %a) {
entry:
@@ -223,7 +241,9 @@
ret i64 %conv
}
; CHECK-LABEL: floatToSigned64
-; CHECK: call cvtftosi64
+; CALLTARGETS-LABEL: floatToSigned64
+; CHECK: call -4
+; CALLTARGETS: call cvtftosi64
define internal i64 @doubleToUnsigned64(double %a) {
entry:
@@ -231,7 +251,9 @@
ret i64 %conv
}
; CHECK-LABEL: doubleToUnsigned64
-; CHECK: call cvtdtoui64
+; CALLTARGETS-LABEL: doubleToUnsigned64
+; CHECK: call -4
+; CALLTARGETS: call cvtdtoui64
define internal i64 @floatToUnsigned64(float %a) {
entry:
@@ -239,7 +261,9 @@
ret i64 %conv
}
; CHECK-LABEL: floatToUnsigned64
-; CHECK: call cvtftoui64
+; CALLTARGETS-LABEL: floatToUnsigned64
+; CHECK: call -4
+; CALLTARGETS: call cvtftoui64
define internal i32 @doubleToSigned32(double %a) {
entry:
@@ -263,7 +287,9 @@
ret i32 %conv
}
; CHECK-LABEL: doubleToUnsigned32
-; CHECK: call cvtdtoui32
+; CALLTARGETS-LABEL: doubleToUnsigned32
+; CHECK: call -4
+; CALLTARGETS: call cvtdtoui32
define internal i32 @floatToUnsigned32(float %a) {
entry:
@@ -271,7 +297,10 @@
ret i32 %conv
}
; CHECK-LABEL: floatToUnsigned32
-; CHECK: call cvtftoui32
+; CALLTARGETS-LABEL: floatToUnsigned32
+; CHECK: call -4
+; CALLTARGETS: call cvtftoui32
+
define internal i32 @doubleToSigned16(double %a) {
entry:
@@ -379,7 +408,9 @@
ret double %conv
}
; CHECK-LABEL: signed64ToDouble
-; CHECK: call cvtsi64tod
+; CALLTARGETS-LABEL: signed64ToDouble
+; CHECK: call -4
+; CALLTARGETS: call cvtsi64tod
; CHECK: fstp
define internal float @signed64ToFloat(i64 %a) {
@@ -388,7 +419,9 @@
ret float %conv
}
; CHECK-LABEL: signed64ToFloat
-; CHECK: call cvtsi64tof
+; CALLTARGETS-LABEL: signed64ToFloat
+; CHECK: call -4
+; CALLTARGETS: call cvtsi64tof
; CHECK: fstp
define internal double @unsigned64ToDouble(i64 %a) {
@@ -397,7 +430,9 @@
ret double %conv
}
; CHECK-LABEL: unsigned64ToDouble
-; CHECK: call cvtui64tod
+; CALLTARGETS-LABEL: unsigned64ToDouble
+; CHECK: call -4
+; CALLTARGETS: call cvtui64tod
; CHECK: fstp
define internal float @unsigned64ToFloat(i64 %a) {
@@ -406,7 +441,9 @@
ret float %conv
}
; CHECK-LABEL: unsigned64ToFloat
-; CHECK: call cvtui64tof
+; CALLTARGETS-LABEL: unsigned64ToFloat
+; CHECK: call -4
+; CALLTARGETS: call cvtui64tof
; CHECK: fstp
define internal double @unsigned64ToDoubleConst() {
@@ -415,9 +452,11 @@
ret double %conv
}
; CHECK-LABEL: unsigned64ToDouble
-; CHECK: mov dword ptr [esp+4], 2874
+; CALLTARGETS-LABEL: unsigned64ToDouble
+; CHECK: mov dword ptr [esp + 4], 2874
; CHECK: mov dword ptr [esp], 1942892530
-; CHECK: call cvtui64tod
+; CHECK: call -4
+; CALLTARGETS: call cvtui64tod
; CHECK: fstp
define internal double @signed32ToDouble(i32 %a) {
@@ -444,7 +483,9 @@
ret double %conv
}
; CHECK-LABEL: unsigned32ToDouble
-; CHECK: call cvtui32tod
+; CALLTARGETS-LABEL: unsigned32ToDouble
+; CHECK: call -4
+; CALLTARGETS: call cvtui32tod
; CHECK: fstp
define internal float @unsigned32ToFloat(i32 %a) {
@@ -453,7 +494,9 @@
ret float %conv
}
; CHECK-LABEL: unsigned32ToFloat
-; CHECK: call cvtui32tof
+; CALLTARGETS-LABEL: unsigned32ToFloat
+; CHECK: call -4
+; CALLTARGETS: call cvtui32tof
; CHECK: fstp
define internal double @signed16ToDouble(i32 %a) {
@@ -578,15 +621,18 @@
}
; CHECK-LABEL: fcmpEq
; CHECK: ucomiss
-; CHECK: jne .
-; CHECK-NEXT: jp .
+; CHECK: jne {{[0-9]}}
+; CHECK-NEXT: jp {{[0-9]}}
; CHECK: call func
; CHECK: ucomisd
-; CHECK: jne .
-; CHECK-NEXT: jp .
+; CHECK: jne {{[0-9]}}
+; CHECK-NEXT: jp {{[0-9]}}
; CHECK: call func
-declare void @func()
+define void @func() {
+entry:
+ ret void
+}
define internal void @fcmpNe(float %a, float %b, double %c, double %d) {
entry:
@@ -610,12 +656,12 @@
}
; CHECK-LABEL: fcmpNe
; CHECK: ucomiss
-; CHECK: jne .
-; CHECK-NEXT: jp .
+; CHECK: jne {{[0-9]}}
+; CHECK-NEXT: jp {{[0-9]}}
; CHECK: call func
; CHECK: ucomisd
-; CHECK: jne .
-; CHECK-NEXT: jp .
+; CHECK: jne {{[0-9]}}
+; CHECK-NEXT: jp {{[0-9]}}
; CHECK: call func
define internal void @fcmpGt(float %a, float %b, double %c, double %d) {
@@ -640,10 +686,10 @@
}
; CHECK-LABEL: fcmpGt
; CHECK: ucomiss
-; CHECK: ja .
+; CHECK: ja {{[0-9]}}
; CHECK: call func
; CHECK: ucomisd
-; CHECK: ja .
+; CHECK: ja {{[0-9]}}
; CHECK: call func
define internal void @fcmpGe(float %a, float %b, double %c, double %d) {
@@ -668,10 +714,10 @@
}
; CHECK-LABEL: fcmpGe
; CHECK: ucomiss
-; CHECK: jb .
+; CHECK: jb {{[0-9]}}
; CHECK: call func
; CHECK: ucomisd
-; CHECK: jb .
+; CHECK: jb {{[0-9]}}
; CHECK: call func
define internal void @fcmpLt(float %a, float %b, double %c, double %d) {
@@ -696,10 +742,10 @@
}
; CHECK-LABEL: fcmpLt
; CHECK: ucomiss
-; CHECK: ja .
+; CHECK: ja {{[0-9]}}
; CHECK: call func
; CHECK: ucomisd
-; CHECK: ja .
+; CHECK: ja {{[0-9]}}
; CHECK: call func
define internal void @fcmpLe(float %a, float %b, double %c, double %d) {
@@ -724,10 +770,10 @@
}
; CHECK-LABEL: fcmpLe
; CHECK: ucomiss
-; CHECK: jb .
+; CHECK: jb {{[0-9]}}
; CHECK: call func
; CHECK: ucomisd
-; CHECK: jb .
+; CHECK: jb {{[0-9]}}
; CHECK: call func
define internal i32 @fcmpFalseFloat(float %a, float %b) {
@@ -756,8 +802,8 @@
}
; CHECK-LABEL: fcmpOeqFloat
; CHECK: ucomiss
-; CHECK: jne .
-; CHECK: jp .
+; CHECK: jne {{[0-9]}}
+; CHECK: jp {{[0-9]}}
define internal i32 @fcmpOeqDouble(double %a, double %b) {
entry:
@@ -767,8 +813,8 @@
}
; CHECK-LABEL: fcmpOeqDouble
; CHECK: ucomisd
-; CHECK: jne .
-; CHECK: jp .
+; CHECK: jne {{[0-9]}}
+; CHECK: jp {{[0-9]}}
define internal i32 @fcmpOgtFloat(float %a, float %b) {
entry:
@@ -778,7 +824,7 @@
}
; CHECK-LABEL: fcmpOgtFloat
; CHECK: ucomiss
-; CHECK: ja .
+; CHECK: ja {{[0-9]}}
define internal i32 @fcmpOgtDouble(double %a, double %b) {
entry:
@@ -788,7 +834,7 @@
}
; CHECK-LABEL: fcmpOgtDouble
; CHECK: ucomisd
-; CHECK: ja .
+; CHECK: ja {{[0-9]}}
define internal i32 @fcmpOgeFloat(float %a, float %b) {
entry:
@@ -798,7 +844,7 @@
}
; CHECK-LABEL: fcmpOgeFloat
; CHECK: ucomiss
-; CHECK: jae .
+; CHECK: jae {{[0-9]}}
define internal i32 @fcmpOgeDouble(double %a, double %b) {
entry:
@@ -808,7 +854,7 @@
}
; CHECK-LABEL: fcmpOgeDouble
; CHECK: ucomisd
-; CHECK: jae .
+; CHECK: jae {{[0-9]}}
define internal i32 @fcmpOltFloat(float %a, float %b) {
entry:
@@ -818,7 +864,7 @@
}
; CHECK-LABEL: fcmpOltFloat
; CHECK: ucomiss
-; CHECK: ja .
+; CHECK: ja {{[0-9]}}
define internal i32 @fcmpOltDouble(double %a, double %b) {
entry:
@@ -828,7 +874,7 @@
}
; CHECK-LABEL: fcmpOltDouble
; CHECK: ucomisd
-; CHECK: ja .
+; CHECK: ja {{[0-9]}}
define internal i32 @fcmpOleFloat(float %a, float %b) {
entry:
@@ -838,7 +884,7 @@
}
; CHECK-LABEL: fcmpOleFloat
; CHECK: ucomiss
-; CHECK: jae .
+; CHECK: jae {{[0-9]}}
define internal i32 @fcmpOleDouble(double %a, double %b) {
entry:
@@ -848,7 +894,7 @@
}
; CHECK-LABEL: fcmpOleDouble
; CHECK: ucomisd
-; CHECK: jae .
+; CHECK: jae {{[0-9]}}
define internal i32 @fcmpOneFloat(float %a, float %b) {
entry:
@@ -858,7 +904,7 @@
}
; CHECK-LABEL: fcmpOneFloat
; CHECK: ucomiss
-; CHECK: jne .
+; CHECK: jne {{[0-9]}}
define internal i32 @fcmpOneDouble(double %a, double %b) {
entry:
@@ -868,7 +914,7 @@
}
; CHECK-LABEL: fcmpOneDouble
; CHECK: ucomisd
-; CHECK: jne .
+; CHECK: jne {{[0-9]}}
define internal i32 @fcmpOrdFloat(float %a, float %b) {
entry:
@@ -878,7 +924,7 @@
}
; CHECK-LABEL: fcmpOrdFloat
; CHECK: ucomiss
-; CHECK: jnp .
+; CHECK: jnp {{[0-9]}}
define internal i32 @fcmpOrdDouble(double %a, double %b) {
entry:
@@ -888,7 +934,7 @@
}
; CHECK-LABEL: fcmpOrdDouble
; CHECK: ucomisd
-; CHECK: jnp .
+; CHECK: jnp {{[0-9]}}
define internal i32 @fcmpUeqFloat(float %a, float %b) {
entry:
@@ -898,7 +944,7 @@
}
; CHECK-LABEL: fcmpUeqFloat
; CHECK: ucomiss
-; CHECK: je .
+; CHECK: je {{[0-9]}}
define internal i32 @fcmpUeqDouble(double %a, double %b) {
entry:
@@ -908,7 +954,7 @@
}
; CHECK-LABEL: fcmpUeqDouble
; CHECK: ucomisd
-; CHECK: je .
+; CHECK: je {{[0-9]}}
define internal i32 @fcmpUgtFloat(float %a, float %b) {
entry:
@@ -918,7 +964,7 @@
}
; CHECK-LABEL: fcmpUgtFloat
; CHECK: ucomiss
-; CHECK: jb .
+; CHECK: jb {{[0-9]}}
define internal i32 @fcmpUgtDouble(double %a, double %b) {
entry:
@@ -928,7 +974,7 @@
}
; CHECK-LABEL: fcmpUgtDouble
; CHECK: ucomisd
-; CHECK: jb .
+; CHECK: jb {{[0-9]}}
define internal i32 @fcmpUgeFloat(float %a, float %b) {
entry:
@@ -938,7 +984,7 @@
}
; CHECK-LABEL: fcmpUgeFloat
; CHECK: ucomiss
-; CHECK: jbe .
+; CHECK: jbe {{[0-9]}}
define internal i32 @fcmpUgeDouble(double %a, double %b) {
entry:
@@ -948,7 +994,7 @@
}
; CHECK-LABEL: fcmpUgeDouble
; CHECK: ucomisd
-; CHECK: jbe .
+; CHECK: jbe {{[0-9]}}
define internal i32 @fcmpUltFloat(float %a, float %b) {
entry:
@@ -958,7 +1004,7 @@
}
; CHECK-LABEL: fcmpUltFloat
; CHECK: ucomiss
-; CHECK: jb .
+; CHECK: jb {{[0-9]}}
define internal i32 @fcmpUltDouble(double %a, double %b) {
entry:
@@ -968,7 +1014,7 @@
}
; CHECK-LABEL: fcmpUltDouble
; CHECK: ucomisd
-; CHECK: jb .
+; CHECK: jb {{[0-9]}}
define internal i32 @fcmpUleFloat(float %a, float %b) {
entry:
@@ -978,7 +1024,7 @@
}
; CHECK-LABEL: fcmpUleFloat
; CHECK: ucomiss
-; CHECK: jbe .
+; CHECK: jbe {{[0-9]}}
define internal i32 @fcmpUleDouble(double %a, double %b) {
entry:
@@ -988,7 +1034,7 @@
}
; CHECK-LABEL: fcmpUleDouble
; CHECK: ucomisd
-; CHECK: jbe .
+; CHECK: jbe {{[0-9]}}
define internal i32 @fcmpUneFloat(float %a, float %b) {
entry:
@@ -998,8 +1044,8 @@
}
; CHECK-LABEL: fcmpUneFloat
; CHECK: ucomiss
-; CHECK: jne .
-; CHECK: jp .
+; CHECK: jne {{[0-9]}}
+; CHECK: jp {{[0-9]}}
define internal i32 @fcmpUneDouble(double %a, double %b) {
entry:
@@ -1009,8 +1055,8 @@
}
; CHECK-LABEL: fcmpUneDouble
; CHECK: ucomisd
-; CHECK: jne .
-; CHECK: jp .
+; CHECK: jne {{[0-9]}}
+; CHECK: jp {{[0-9]}}
define internal i32 @fcmpUnoFloat(float %a, float %b) {
entry:
@@ -1020,7 +1066,7 @@
}
; CHECK-LABEL: fcmpUnoFloat
; CHECK: ucomiss
-; CHECK: jp .
+; CHECK: jp {{[0-9]}}
define internal i32 @fcmpUnoDouble(double %a, double %b) {
entry:
@@ -1030,7 +1076,7 @@
}
; CHECK-LABEL: fcmpUnoDouble
; CHECK: ucomisd
-; CHECK: jp .
+; CHECK: jp {{[0-9]}}
define internal i32 @fcmpTrueFloat(float %a, float %b) {
entry:
@@ -1118,7 +1164,7 @@
}
; CHECK-LABEL: selectFloatVarVar
; CHECK: ucomiss
-; CHECK: ja .
+; CHECK: ja {{[0-9]}}
; CHECK: fld
define internal double @selectDoubleVarVar(double %a, double %b) {
@@ -1129,7 +1175,7 @@
}
; CHECK-LABEL: selectDoubleVarVar
; CHECK: ucomisd
-; CHECK: ja .
+; CHECK: ja {{[0-9]}}
; CHECK: fld
; ERRORS-NOT: ICE translation error
diff --git a/tests_lit/llvm2ice_tests/fpconst.pnacl.ll b/tests_lit/llvm2ice_tests/fpconst.pnacl.ll
index cd300ec..295e2a2 100644
--- a/tests_lit/llvm2ice_tests/fpconst.pnacl.ll
+++ b/tests_lit/llvm2ice_tests/fpconst.pnacl.ll
@@ -6,12 +6,12 @@
; number in a reasonable number of digits". See
; http://llvm.org/docs/LangRef.html#simple-constants .
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -s -d -symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice -Om1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -s -d -symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
@@ -545,11 +545,15 @@
; pick one value for each type, and make sure it appears exactly once.
; Check for float 0.5
-; CHECK: .long 0x3f000000
-; CHECK-NOT: .long 0x3f000000
+; CHECK-LABEL: .rodata.cst4
+; CHECK: 0000003f
+; CHECK-NOT: 0000003f
+
; Check for double 0.5
-; CHECK: .quad 0x3fe0000000000000
-; CHECK-NOT: .quad 0x3fe0000000000000
+; CHECK-LABEL: .rodata.cst8
+; CHECK: 00000000 0000e03f
+; CHECK-NOT: 00000000 0000e03f
+; CHECK-LABEL: .shstrtab
; ERRORS-NOT: ICE translation error
; DUMP-NOT: SZ
diff --git a/tests_lit/llvm2ice_tests/nacl-atomic-cmpxchg-optimization.ll b/tests_lit/llvm2ice_tests/nacl-atomic-cmpxchg-optimization.ll
index 2051ffd..01a4571 100644
--- a/tests_lit/llvm2ice_tests/nacl-atomic-cmpxchg-optimization.ll
+++ b/tests_lit/llvm2ice_tests/nacl-atomic-cmpxchg-optimization.ll
@@ -1,11 +1,13 @@
; This tests the optimization of atomic cmpxchg w/ following cmp + branches.
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s --check-prefix=O2
-; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s --check-prefix=OM1
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d -symbolize -x86-asm-syntax=intel - \
+; RUN: | FileCheck --check-prefix=O2 %s
; RUN: %llvm2ice -Om1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d -symbolize -x86-asm-syntax=intel - \
+; RUN: | FileCheck --check-prefix=OM1 %s
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
@@ -37,23 +39,23 @@
call void @use_value(i32 %old)
ret i32 %succeeded_first_try
}
-; O2-LABEL: .Ltest_atomic_cmpxchg_loop{{.*}}loop
-; O2: lock cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
+; O2-LABEL: test_atomic_cmpxchg_loop
+; O2: lock
+; O2-NEXT: cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
; O2-NOT: cmp
; Make sure the phi assignment for succeeded_first_try is still there.
; O2: mov {{.*}}, 2
; O2-NOT: cmp
; O2: je
-; O2-LABEL: .Ltest_atomic_cmpxchg_loop{{.*}}done
; Make sure the call isn't accidentally deleted.
; O2: call
;
; Check that the unopt version does have a cmp
-; OM1-LABEL: .Ltest_atomic_cmpxchg_loop{{.*}}loop
-; OM1: lock cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
+; OM1-LABEL: test_atomic_cmpxchg_loop
+; OM1: lock
+; OM1-NEXT: cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
; OM1: cmp
; OM1: je
-; OM1-LABEL: .Ltest_atomic_cmpxchg_loop{{.*}}done
; OM1: call
; Still works if the compare operands are flipped.
@@ -72,8 +74,9 @@
done:
ret i32 %old
}
-; O2-LABEL: .Ltest_atomic_cmpxchg_loop2{{.*}}loop
-; O2: lock cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
+; O2-LABEL: test_atomic_cmpxchg_loop2
+; O2: lock
+; O2-NEXT: cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
; O2-NOT: cmp
; O2: je
@@ -94,8 +97,10 @@
done:
ret i32 %succeeded_first_try
}
-; O2-LABEL: .Ltest_atomic_cmpxchg_loop_const{{.*}}loop
-; O2: lock cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
+; O2-LABEL: test_atomic_cmpxchg_loop_const
+; O2: lock
+; Should be using NEXT: see issue 3929
+; O2: cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
; O2-NOT: cmp
; O2: je
@@ -116,8 +121,9 @@
done:
ret i32 %old
}
-; O2-LABEL: .Ltest_atomic_cmpxchg_no_opt{{.*}}loop
-; O2: lock cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
+; O2-LABEL: test_atomic_cmpxchg_no_opt
+; O2: lock
+; O2-NEXT: cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
; O2: mov {{.*}}
; O2: cmp
; O2: jg
@@ -140,8 +146,9 @@
%r = zext i1 %success to i32
ret i32 %r
}
-; O2-LABEL: .Ltest_atomic_cmpxchg_no_opt2{{.*}}loop
-; O2: lock cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
+; O2-LABEL: test_atomic_cmpxchg_no_opt2
+; O2: lock
+; O2-NEXT: cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
; O2: mov {{.*}}
; O2: cmp
; O2: je
diff --git a/tests_lit/llvm2ice_tests/nacl-atomic-fence-all.ll b/tests_lit/llvm2ice_tests/nacl-atomic-fence-all.ll
index 4b0127b..0ad2e91 100644
--- a/tests_lit/llvm2ice_tests/nacl-atomic-fence-all.ll
+++ b/tests_lit/llvm2ice_tests/nacl-atomic-fence-all.ll
@@ -3,9 +3,13 @@
; (unlike the non-"all" variety of nacl.atomic.fence, which only
; applies to atomic load/stores).
;
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d -symbolize -x86-asm-syntax=intel - | FileCheck %s
+
+; TODO(jvoung): llvm-objdump doesn't symbolize global symbols well, so we
+; have [0] == g32_a, [4] == g32_b, [8] == g32_c.
+; g32_d is also [0] because it's in the .data section instead of .bss.
declare void @llvm.nacl.atomic.fence.all()
declare i32 @llvm.nacl.atomic.load.i32(i32*, i32)
@@ -45,15 +49,15 @@
; CHECK: mov {{.*}}, esp
; CHECK: mov dword ptr {{.*}}, 999
; atomic store (w/ its own mfence)
-; CHECK: lea {{.*}}, g32_a
+; CHECK: dword ptr [0]
; The load + add are optimized into one everywhere.
; CHECK: add {{.*}}, dword ptr
; CHECK: mov dword ptr
; CHECK: mfence
-; CHECK: lea {{.*}}, g32_b
+; CHECK: dword ptr [4]
; CHECK: add {{.*}}, dword ptr
; CHECK: mov dword ptr
-; CHECK: lea {{.*}}, g32_c
+; CHECK: dword ptr [8]
; CHECK: add {{.*}}, dword ptr
; CHECK: mfence
; CHECK: mov dword ptr
@@ -88,14 +92,14 @@
; CHECK: mov {{.*}}, esp
; CHECK: mov dword ptr {{.*}}, 999
; atomic store (w/ its own mfence)
-; CHECK: lea {{.*}}, g32_a
+; CHECK: dword ptr [0]
; CHECK: add {{.*}}, dword ptr
; CHECK: mov dword ptr
; CHECK: mfence
-; CHECK: lea {{.*}}, g32_b
+; CHECK: dword ptr [4]
; CHECK: add {{.*}}, dword ptr
; CHECK: mov dword ptr
-; CHECK: lea {{.*}}, g32_c
+; CHECK: dword ptr [8]
; CHECK: mfence
; Load + add can still be optimized into one instruction
; because it is not separated by a fence.
@@ -132,11 +136,11 @@
; CHECK: mov {{.*}}, esp
; CHECK: mov dword ptr {{.*}}, 999
; atomic store (w/ its own mfence)
-; CHECK: lea {{.*}}, g32_a
+; CHECK: dword ptr [0]
; CHECK: add {{.*}}, dword ptr
; CHECK: mov dword ptr
; CHECK: mfence
-; CHECK: lea {{.*}}, g32_b
+; CHECK: dword ptr [4]
; This load + add are no longer optimized into one,
; though perhaps it should be legal as long as
; the load stays on the same side of the fence.
@@ -144,7 +148,7 @@
; CHECK: mfence
; CHECK: add {{.*}}, 1
; CHECK: mov dword ptr
-; CHECK: lea {{.*}}, g32_c
+; CHECK: dword ptr [8]
; CHECK: add {{.*}}, dword ptr
; CHECK: mov dword ptr
@@ -184,7 +188,7 @@
ret i32 %b1234
}
; CHECK-LABEL: could_have_fused_loads
-; CHECK: lea {{.*}}, g32_d
+; CHECK: dword ptr [0]
; CHECK: mov {{.*}}, byte ptr
; CHECK: mov {{.*}}, byte ptr
; CHECK: mov {{.*}}, byte ptr
@@ -208,7 +212,7 @@
ret i32 %z
}
; CHECK-LABEL: could_have_hoisted_loads
-; CHECK: lea {{.*}}, g32_d
+; CHECK: dword ptr [0]
; CHECK: je {{.*}}
; CHECK: jmp {{.*}}
; CHECK: mov {{.*}}, dword ptr
diff --git a/tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll b/tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll
index dfc86bd..a8dd9ac 100644
--- a/tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll
+++ b/tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll
@@ -1,18 +1,27 @@
; This tests each of the supported NaCl atomic instructions for every
; size allowed.
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s --check-prefix=CHECKO2
-; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %llvm2ice -O2 --verbose none %s \
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: | FileCheck --check-prefix=CHECKO2 %s
; RUN: %llvm2ice -Om1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
; RUN: | FileCheck --check-prefix=DUMP %s
+; TODO(jvoung): Uh... normally pnacl-llc is not supposed to separate the
+; lock from its instruction w/ bundle padding, but when processing .s
+; files with llvm-mc it seems be ocassionally wrong!
+; https://code.google.com/p/nativeclient/issues/detail?id=3929
+; That makes the current "lock" checks avoid using CHECK-NEXT.
+
declare i8 @llvm.nacl.atomic.load.i8(i8*, i32)
declare i16 @llvm.nacl.atomic.load.i16(i16*, i32)
declare i32 @llvm.nacl.atomic.load.i32(i32*, i32)
@@ -201,7 +210,8 @@
ret i32 %a_ext
}
; CHECK-LABEL: test_atomic_rmw_add_8
-; CHECK: lock xadd byte {{.*}}, [[REG:.*]]
+; CHECK: lock
+; CHECK-NEXT: xadd byte {{.*}}, [[REG:.*]]
; CHECK: mov {{.*}}, [[REG]]
define i32 @test_atomic_rmw_add_16(i32 %iptr, i32 %v) {
@@ -213,7 +223,9 @@
ret i32 %a_ext
}
; CHECK-LABEL: test_atomic_rmw_add_16
-; CHECK: lock xadd word {{.*}}, [[REG:.*]]
+; CHECK: lock
+; Should be using NEXT: see issue 3929
+; CHECK: xadd word {{.*}}, [[REG:.*]]
; CHECK: mov {{.*}}, [[REG]]
define i32 @test_atomic_rmw_add_32(i32 %iptr, i32 %v) {
@@ -223,7 +235,8 @@
ret i32 %a
}
; CHECK-LABEL: test_atomic_rmw_add_32
-; CHECK: lock xadd dword {{.*}}, [[REG:.*]]
+; CHECK: lock
+; CHECK-NEXT: xadd dword {{.*}}, [[REG:.*]]
; CHECK: mov {{.*}}, [[REG]]
define i64 @test_atomic_rmw_add_64(i32 %iptr, i64 %v) {
@@ -235,8 +248,7 @@
; CHECK-LABEL: test_atomic_rmw_add_64
; CHECK: push ebx
; CHECK: mov eax, dword ptr [{{.*}}]
-; CHECK: mov edx, dword ptr [{{.*}}+4]
-; CHECK: .L[[LABEL:.*]]:
+; CHECK: mov edx, dword ptr [{{.*}} + 4]
; CHECK: mov ebx, eax
; RHS of add cannot be any of the e[abcd]x regs because they are
; clobbered in the loop, and the RHS needs to be remain live.
@@ -246,12 +258,16 @@
; Ptr cannot be eax, ebx, ecx, or edx (used up for the expected and desired).
; It can be esi, edi, or ebp though, for example (so we need to be careful
; about rejecting eb* and ed*.)
-; CHECK: lock cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK: jne .L[[LABEL]]
+; CHECK: lock
+; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
+; CHECK: jne -{{[0-9]}}
; Test with some more register pressure. When we have an alloca, ebp is
; used to manage the stack frame, so it cannot be used as a register either.
-declare void @use_ptr(i32 %iptr)
+define void @use_ptr(i32 %iptr) {
+entry:
+ ret void
+}
define i64 @test_atomic_rmw_add_64_alloca(i32 %iptr, i64 %v) {
entry:
@@ -277,7 +293,8 @@
; not esp, since that's the stack pointer and mucking with it will break
; the later use_ptr function call.
; That pretty much leaves esi, or edi as the only viable registers.
-; CHECK: lock cmpxchg8b qword ptr [e{{[ds]}}i]
+; CHECK: lock
+; CHECK-NEXT: cmpxchg8b qword ptr [e{{[ds]}}i]
; CHECK: call use_ptr
define i32 @test_atomic_rmw_add_32_ignored(i32 %iptr, i32 %v) {
@@ -289,7 +306,8 @@
; Technically this could use "lock add" instead of "lock xadd", if liveness
; tells us that the destination variable is dead.
; CHECK-LABEL: test_atomic_rmw_add_32_ignored
-; CHECK: lock xadd dword {{.*}}, [[REG:.*]]
+; CHECK: lock
+; CHECK-NEXT: xadd dword {{.*}}, [[REG:.*]]
; Atomic RMW 64 needs to be expanded into its own loop.
; Make sure that works w/ non-trivial function bodies.
@@ -313,17 +331,15 @@
}
; CHECK-LABEL: test_atomic_rmw_add_64_loop
; CHECK: push ebx
-; CHECK-LABEL: .Ltest_atomic_rmw_add_64_loop{{.*}}loop
; CHECK: mov eax, dword ptr [{{.*}}]
-; CHECK: mov edx, dword ptr [{{.*}}+4]
-; CHECK: .L[[LABEL:.*]]:
+; CHECK: mov edx, dword ptr [{{.*}} + 4]
; CHECK: mov ebx, eax
; CHECK: add ebx, {{.*e.[^x]}}
; CHECK: mov ecx, edx
; CHECK: adc ecx, {{.*e.[^x]}}
-; CHECK: lock cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK: jne .L[[LABEL]]
-; CHECK-LABEL: .Ltest_atomic_rmw_add_64_loop{{.*}}done
+; CHECK: lock
+; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
+; CHECK: jne -{{[0-9]}}
;; sub
@@ -337,7 +353,9 @@
}
; CHECK-LABEL: test_atomic_rmw_sub_8
; CHECK: neg [[REG:.*]]
-; CHECK: lock xadd byte {{.*}}, [[REG]]
+; CHECK: lock
+; Should be using NEXT: see issue 3929
+; CHECK: xadd byte {{.*}}, [[REG]]
; CHECK: mov {{.*}}, [[REG]]
define i32 @test_atomic_rmw_sub_16(i32 %iptr, i32 %v) {
@@ -350,7 +368,8 @@
}
; CHECK-LABEL: test_atomic_rmw_sub_16
; CHECK: neg [[REG:.*]]
-; CHECK: lock xadd word {{.*}}, [[REG]]
+; CHECK: lock
+; CHECK-NEXT: xadd word {{.*}}, [[REG]]
; CHECK: mov {{.*}}, [[REG]]
define i32 @test_atomic_rmw_sub_32(i32 %iptr, i32 %v) {
@@ -361,7 +380,8 @@
}
; CHECK-LABEL: test_atomic_rmw_sub_32
; CHECK: neg [[REG:.*]]
-; CHECK: lock xadd dword {{.*}}, [[REG]]
+; CHECK: lock
+; CHECK-NEXT: xadd dword {{.*}}, [[REG]]
; CHECK: mov {{.*}}, [[REG]]
define i64 @test_atomic_rmw_sub_64(i32 %iptr, i64 %v) {
@@ -373,14 +393,15 @@
; CHECK-LABEL: test_atomic_rmw_sub_64
; CHECK: push ebx
; CHECK: mov eax, dword ptr [{{.*}}]
-; CHECK: mov edx, dword ptr [{{.*}}+4]
-; CHECK: .L[[LABEL:.*]]:
+; CHECK: mov edx, dword ptr [{{.*}} + 4]
; CHECK: mov ebx, eax
; CHECK: sub ebx, {{.*e.[^x]}}
; CHECK: mov ecx, edx
; CHECK: sbb ecx, {{.*e.[^x]}}
-; CHECK: lock cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK: jne .L[[LABEL]]
+; CHECK: lock
+; Should be using NEXT: see issue 3929
+; CHECK: cmpxchg8b qword ptr [e{{.[^x]}}]
+; CHECK: jne -{{[0-9]}}
define i32 @test_atomic_rmw_sub_32_ignored(i32 %iptr, i32 %v) {
@@ -392,7 +413,8 @@
; Could use "lock sub" instead of "neg; lock xadd"
; CHECK-LABEL: test_atomic_rmw_sub_32_ignored
; CHECK: neg [[REG:.*]]
-; CHECK: lock xadd dword {{.*}}, [[REG]]
+; CHECK: lock
+; CHECK-NEXT: xadd dword {{.*}}, [[REG]]
;; or
@@ -406,12 +428,12 @@
}
; CHECK-LABEL: test_atomic_rmw_or_8
; CHECK: mov al, byte ptr
-; CHECK: .L[[LABEL:.*]]:
; Dest cannot be eax here, because eax is used for the old value. Also want
; to make sure that cmpxchg's source is the same register.
; CHECK: or [[REG:[^a].]]
-; CHECK: lock cmpxchg byte ptr [e{{[^a].}}], [[REG]]
-; CHECK: jne .L[[LABEL]]
+; CHECK: lock
+; CHECK-NEXT: cmpxchg byte ptr [e{{[^a].}}], [[REG]]
+; CHECK: jne -{{[0-9]}}
define i32 @test_atomic_rmw_or_16(i32 %iptr, i32 %v) {
entry:
@@ -423,10 +445,10 @@
}
; CHECK-LABEL: test_atomic_rmw_or_16
; CHECK: mov ax, word ptr
-; CHECK: .L[[LABEL:.*]]:
; CHECK: or [[REG:[^a].]]
-; CHECK: lock cmpxchg word ptr [e{{[^a].}}], [[REG]]
-; CHECK: jne .L[[LABEL]]
+; CHECK: lock
+; CHECK-NEXT: cmpxchg word ptr [e{{[^a].}}], [[REG]]
+; CHECK: jne -{{[0-9]}}
define i32 @test_atomic_rmw_or_32(i32 %iptr, i32 %v) {
entry:
@@ -436,10 +458,10 @@
}
; CHECK-LABEL: test_atomic_rmw_or_32
; CHECK: mov eax, dword ptr
-; CHECK: .L[[LABEL:.*]]:
; CHECK: or [[REG:e[^a].]]
-; CHECK: lock cmpxchg dword ptr [e{{[^a].}}], [[REG]]
-; CHECK: jne .L[[LABEL]]
+; CHECK: lock
+; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}], [[REG]]
+; CHECK: jne -{{[0-9]}}
define i64 @test_atomic_rmw_or_64(i32 %iptr, i64 %v) {
entry:
@@ -450,14 +472,14 @@
; CHECK-LABEL: test_atomic_rmw_or_64
; CHECK: push ebx
; CHECK: mov eax, dword ptr [{{.*}}]
-; CHECK: mov edx, dword ptr [{{.*}}+4]
-; CHECK: .L[[LABEL:.*]]:
+; CHECK: mov edx, dword ptr [{{.*}} + 4]
; CHECK: mov ebx, eax
; CHECK: or ebx, {{.*e.[^x]}}
; CHECK: mov ecx, edx
; CHECK: or ecx, {{.*e.[^x]}}
-; CHECK: lock cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK: jne .L[[LABEL]]
+; CHECK: lock
+; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
+; CHECK: jne -{{[0-9]}}
define i32 @test_atomic_rmw_or_32_ignored(i32 %iptr, i32 %v) {
entry:
@@ -470,10 +492,10 @@
; Would also need a way to introduce "lock"'edness to binary
; operators without introducing overhead on the more common binary ops.
; CHECK: mov eax, dword ptr
-; CHECK: .L[[LABEL:.*]]:
; CHECK: or [[REG:e[^a].]]
-; CHECK: lock cmpxchg dword ptr [e{{[^a].}}], [[REG]]
-; CHECK: jne .L[[LABEL]]
+; CHECK: lock
+; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}], [[REG]]
+; CHECK: jne -{{[0-9]}}
;; and
@@ -487,10 +509,10 @@
}
; CHECK-LABEL: test_atomic_rmw_and_8
; CHECK: mov al, byte ptr
-; CHECK: .L[[LABEL:.*]]:
; CHECK: and [[REG:[^a].]]
-; CHECK: lock cmpxchg byte ptr [e{{[^a].}}], [[REG]]
-; CHECK: jne .L[[LABEL]]
+; CHECK: lock
+; CHECK-NEXT: cmpxchg byte ptr [e{{[^a].}}], [[REG]]
+; CHECK: jne -{{[0-9]}}
define i32 @test_atomic_rmw_and_16(i32 %iptr, i32 %v) {
entry:
@@ -502,10 +524,10 @@
}
; CHECK-LABEL: test_atomic_rmw_and_16
; CHECK: mov ax, word ptr
-; CHECK: .L[[LABEL:.*]]:
; CHECK: and
-; CHECK: lock cmpxchg word ptr [e{{[^a].}}]
-; CHECK: jne .L[[LABEL]]
+; CHECK: lock
+; CHECK-NEXT: cmpxchg word ptr [e{{[^a].}}]
+; CHECK: jne -{{[0-9]}}
define i32 @test_atomic_rmw_and_32(i32 %iptr, i32 %v) {
entry:
@@ -515,10 +537,10 @@
}
; CHECK-LABEL: test_atomic_rmw_and_32
; CHECK: mov eax, dword ptr
-; CHECK: .L[[LABEL:.*]]:
; CHECK: and
-; CHECK: lock cmpxchg dword ptr [e{{[^a].}}]
-; CHECK: jne .L[[LABEL]]
+; CHECK: lock
+; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}]
+; CHECK: jne -{{[0-9]}}
define i64 @test_atomic_rmw_and_64(i32 %iptr, i64 %v) {
entry:
@@ -529,14 +551,14 @@
; CHECK-LABEL: test_atomic_rmw_and_64
; CHECK: push ebx
; CHECK: mov eax, dword ptr [{{.*}}]
-; CHECK: mov edx, dword ptr [{{.*}}+4]
-; CHECK: .L[[LABEL:.*]]:
+; CHECK: mov edx, dword ptr [{{.*}} + 4]
; CHECK: mov ebx, eax
; CHECK: and ebx, {{.*e.[^x]}}
; CHECK: mov ecx, edx
; CHECK: and ecx, {{.*e.[^x]}}
-; CHECK: lock cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK: jne .L[[LABEL]]
+; CHECK: lock
+; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
+; CHECK: jne -{{[0-9]}}
define i32 @test_atomic_rmw_and_32_ignored(i32 %iptr, i32 %v) {
entry:
@@ -547,10 +569,11 @@
; CHECK-LABEL: test_atomic_rmw_and_32_ignored
; Could just "lock and"
; CHECK: mov eax, dword ptr
-; CHECK: .L[[LABEL:.*]]:
; CHECK: and
-; CHECK: lock cmpxchg dword ptr [e{{[^a].}}]
-; CHECK: jne .L[[LABEL]]
+; CHECK: lock
+; Should be using NEXT: see issue 3929
+; CHECK: cmpxchg dword ptr [e{{[^a].}}]
+; CHECK: jne -{{[0-9]}}
;; xor
@@ -564,10 +587,10 @@
}
; CHECK-LABEL: test_atomic_rmw_xor_8
; CHECK: mov al, byte ptr
-; CHECK: .L[[LABEL:.*]]:
; CHECK: xor [[REG:[^a].]]
-; CHECK: lock cmpxchg byte ptr [e{{[^a].}}], [[REG]]
-; CHECK: jne .L[[LABEL]]
+; CHECK: lock
+; CHECK-NEXT: cmpxchg byte ptr [e{{[^a].}}], [[REG]]
+; CHECK: jne -{{[0-9]}}
define i32 @test_atomic_rmw_xor_16(i32 %iptr, i32 %v) {
entry:
@@ -579,10 +602,10 @@
}
; CHECK-LABEL: test_atomic_rmw_xor_16
; CHECK: mov ax, word ptr
-; CHECK: .L[[LABEL:.*]]:
; CHECK: xor
-; CHECK: lock cmpxchg word ptr [e{{[^a].}}]
-; CHECK: jne .L[[LABEL]]
+; CHECK: lock
+; CHECK-NEXT: cmpxchg word ptr [e{{[^a].}}]
+; CHECK: jne -{{[0-9]}}
define i32 @test_atomic_rmw_xor_32(i32 %iptr, i32 %v) {
@@ -593,10 +616,10 @@
}
; CHECK-LABEL: test_atomic_rmw_xor_32
; CHECK: mov eax, dword ptr
-; CHECK: .L[[LABEL:.*]]:
; CHECK: xor
-; CHECK: lock cmpxchg dword ptr [e{{[^a].}}]
-; CHECK: jne .L[[LABEL]]
+; CHECK: lock
+; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}]
+; CHECK: jne -{{[0-9]}}
define i64 @test_atomic_rmw_xor_64(i32 %iptr, i64 %v) {
entry:
@@ -607,14 +630,14 @@
; CHECK-LABEL: test_atomic_rmw_xor_64
; CHECK: push ebx
; CHECK: mov eax, dword ptr [{{.*}}]
-; CHECK: mov edx, dword ptr [{{.*}}+4]
-; CHECK: .L[[LABEL:.*]]:
+; CHECK: mov edx, dword ptr [{{.*}} + 4]
; CHECK: mov ebx, eax
; CHECK: or ebx, {{.*e.[^x]}}
; CHECK: mov ecx, edx
; CHECK: or ecx, {{.*e.[^x]}}
-; CHECK: lock cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK: jne .L[[LABEL]]
+; CHECK: lock
+; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
+; CHECK: jne -{{[0-9]}}
define i32 @test_atomic_rmw_xor_32_ignored(i32 %iptr, i32 %v) {
entry:
@@ -624,10 +647,10 @@
}
; CHECK-LABEL: test_atomic_rmw_xor_32_ignored
; CHECK: mov eax, dword ptr
-; CHECK: .L[[LABEL:.*]]:
; CHECK: xor
-; CHECK: lock cmpxchg dword ptr [e{{[^a].}}]
-; CHECK: jne .L[[LABEL]]
+; CHECK: lock
+; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}]
+; CHECK: jne -{{[0-9]}}
;; exchange
@@ -674,9 +697,9 @@
; CHECK-DAG: mov eax
; CHECK-DAG: mov ecx
; CHECK-DAG: mov ebx
-; CHECK: .L[[LABEL:.*]]:
-; CHECK: lock cmpxchg8b qword ptr [{{e.[^x]}}]
-; CHECK: jne .L[[LABEL]]
+; CHECK: lock
+; CHECK-NEXT: cmpxchg8b qword ptr [{{e.[^x]}}]
+; CHECK: jne -{{[0-9]}}
define i32 @test_atomic_rmw_xchg_32_ignored(i32 %iptr, i32 %v) {
entry:
@@ -705,7 +728,8 @@
; CHECK: mov al, {{.*}}
; Need to check that eax isn't used as the address register or the desired.
; since it is already used as the *expected* register.
-; CHECK: lock cmpxchg byte ptr [e{{[^a].}}], {{[^a]}}
+; CHECK: lock
+; CHECK-NEXT: cmpxchg byte ptr [e{{[^a].}}], {{[^a]}}
define i32 @test_atomic_cmpxchg_16(i32 %iptr, i32 %expected, i32 %desired) {
entry:
@@ -719,7 +743,8 @@
}
; CHECK-LABEL: test_atomic_cmpxchg_16
; CHECK: mov ax, {{.*}}
-; CHECK: lock cmpxchg word ptr [e{{[^a].}}], {{[^a]}}
+; CHECK: lock
+; CHECK-NEXT: cmpxchg word ptr [e{{[^a].}}], {{[^a]}}
define i32 @test_atomic_cmpxchg_32(i32 %iptr, i32 %expected, i32 %desired) {
entry:
@@ -730,7 +755,8 @@
}
; CHECK-LABEL: test_atomic_cmpxchg_32
; CHECK: mov eax, {{.*}}
-; CHECK: lock cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
+; CHECK: lock
+; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
define i64 @test_atomic_cmpxchg_64(i32 %iptr, i64 %expected, i64 %desired) {
entry:
@@ -745,7 +771,9 @@
; CHECK-DAG: mov eax
; CHECK-DAG: mov ecx
; CHECK-DAG: mov ebx
-; CHECK: lock cmpxchg8b qword ptr [e{{.[^x]}}]
+; CHECK: lock
+; Should be using NEXT: see issue 3929
+; CHECK: cmpxchg8b qword ptr [e{{.[^x]}}]
; edx and eax are already the return registers, so they don't actually
; need to be reshuffled via movs. The next test stores the result
; somewhere, so in that case they do need to be mov'ed.
@@ -766,7 +794,8 @@
; CHECK-DAG: mov eax
; CHECK-DAG: mov ecx
; CHECK-DAG: mov ebx
-; CHECK: lock cmpxchg8b qword ptr [e{{.[^x]}}]
+; CHECK: lock
+; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
; CHECK: mov {{.*}}, edx
; CHECK: mov {{.*}}, eax
@@ -797,7 +826,9 @@
; not esp, since that's the stack pointer and mucking with it will break
; the later use_ptr function call.
; That pretty much leaves esi, or edi as the only viable registers.
-; CHECK: lock cmpxchg8b qword ptr [e{{[ds]}}i]
+; CHECK: lock
+; Should be using NEXT: see issue 3929
+; CHECK: cmpxchg8b qword ptr [e{{[ds]}}i]
; CHECK: call use_ptr
define i32 @test_atomic_cmpxchg_32_ignored(i32 %iptr, i32 %expected, i32 %desired) {
@@ -809,7 +840,8 @@
}
; CHECK-LABEL: test_atomic_cmpxchg_32_ignored
; CHECK: mov eax, {{.*}}
-; CHECK: lock cmpxchg dword ptr [e{{[^a].}}]
+; CHECK: lock
+; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}]
define i64 @test_atomic_cmpxchg_64_ignored(i32 %iptr, i64 %expected, i64 %desired) {
entry:
@@ -824,7 +856,9 @@
; CHECK-DAG: mov eax
; CHECK-DAG: mov ecx
; CHECK-DAG: mov ebx
-; CHECK: lock cmpxchg8b qword ptr [e{{.[^x]}}]
+; CHECK: lock
+; Should be using NEXT: see issue 3929
+; CHECK: cmpxchg8b qword ptr [e{{.[^x]}}]
;;;; Fence and is-lock-free.
diff --git a/tests_lit/llvm2ice_tests/nacl-other-intrinsics.ll b/tests_lit/llvm2ice_tests/nacl-other-intrinsics.ll
index 60652dc..3e2f9e0 100644
--- a/tests_lit/llvm2ice_tests/nacl-other-intrinsics.ll
+++ b/tests_lit/llvm2ice_tests/nacl-other-intrinsics.ll
@@ -1,25 +1,34 @@
; This tests the NaCl intrinsics not related to atomic operations.
-; RUN: %llvm2ice -O2 --verbose none -sandbox %s | FileCheck %s
-; RUN: %llvm2ice -Om1 --verbose none -sandbox %s | FileCheck %s
+; TODO(jvoung): fix extra "CALLTARGETS" run. The llvm-objdump symbolizer
+; doesn't know how to symbolize non-section-local functions.
+; The newer LLVM 3.6 one does work, but watch out for other bugs.
+
+; RUN: %llvm2ice -O2 --verbose none %s \
+; RUN: | FileCheck --check-prefix=CALLTARGETS %s
+; RUN: %llvm2ice -O2 --verbose none -sandbox %s \
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %llvm2ice -Om1 --verbose none -sandbox %s \
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; Do another run w/ O2 and a different check-prefix (otherwise O2 and Om1
; share the same "CHECK" prefix). This separate run helps check that
; some code is optimized out.
; RUN: %llvm2ice -O2 --verbose none -sandbox %s \
-; RUN: | FileCheck %s --check-prefix=CHECKO2REM
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: | FileCheck --check-prefix=CHECKO2REM %s
; Do O2 runs without -sandbox to make sure llvm.nacl.read.tp gets
; lowered to __nacl_read_tp instead of gs:[0x0].
+; We also know that because it's O2, it'll have the O2REM optimizations.
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | FileCheck --check-prefix=CHECKO2UNSANDBOXED %s
-; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | FileCheck --check-prefix=CHECKO2UNSANDBOXEDREM %s
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: | FileCheck --check-prefix=CHECKO2UNSANDBOXEDREM %s
-; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
-; RUN: %llvm2ice -Om1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
@@ -56,10 +65,10 @@
; CHECK: mov e{{.*}}, dword ptr gs:[0]
; CHECKO2REM-LABEL: test_nacl_read_tp
; CHECKO2REM: mov e{{.*}}, dword ptr gs:[0]
-; CHECKO2UNSANDBOXED-LABEL: test_nacl_read_tp
-; CHECKO2UNSANDBOXED: call __nacl_read_tp
; CHECKO2UNSANDBOXEDREM-LABEL: test_nacl_read_tp
-; CHECKO2UNSANDBOXEDREM: call __nacl_read_tp
+; CHECKO2UNSANDBOXEDREM: call -4
+; CALLTARGETS-LABEL: test_nacl_read_tp
+; CALLTARGETS: call __nacl_read_tp
define i32 @test_nacl_read_tp_more_addressing() {
entry:
@@ -81,12 +90,12 @@
; CHECKO2REM-LABEL: test_nacl_read_tp_more_addressing
; CHECKO2REM: mov e{{.*}}, dword ptr gs:[0]
; CHECKO2REM: mov e{{.*}}, dword ptr gs:[0]
-; CHECKO2UNSANDBOXED-LABEL: test_nacl_read_tp_more_addressing
-; CHECKO2UNSANDBOXED: call __nacl_read_tp
-; CHECKO2UNSANDBOXED: call __nacl_read_tp
; CHECKO2UNSANDBOXEDREM-LABEL: test_nacl_read_tp_more_addressing
-; CHECKO2UNSANDBOXEDREM: call __nacl_read_tp
-; CHECKO2UNSANDBOXEDREM: call __nacl_read_tp
+; CHECKO2UNSANDBOXEDREM: call -4
+; CHECKO2UNSANDBOXEDREM: call -4
+; CALLTARGETS-LABEL: test_nacl_read_tp_more_addressing
+; CALLTARGETS: call __nacl_read_tp
+; CALLTARGETS: call __nacl_read_tp
define i32 @test_nacl_read_tp_dead(i32 %a) {
entry:
@@ -99,7 +108,9 @@
; CHECKO2REM-LABEL: test_nacl_read_tp_dead
; CHECKO2REM-NOT: mov e{{.*}}, dword ptr gs:[0]
; CHECKO2UNSANDBOXEDREM-LABEL: test_nacl_read_tp_dead
-; CHECKO2UNSANDBOXEDREM-NOT: call __nacl_read_tp
+; CHECKO2UNSANDBOXEDREM-NOT: call -4
+; CALLTARGETS-LABEL: test_nacl_read_tp_dead
+; CALLTARGETS-NOT: call __nacl_read_tp
define void @test_memcpy(i32 %iptr_dst, i32 %iptr_src, i32 %len) {
entry:
@@ -110,7 +121,9 @@
ret void
}
; CHECK-LABEL: test_memcpy
-; CHECK: call memcpy
+; CHECK: call -4
+; CALLTARGETS-LABEL: test_memcpy
+; CALLTARGETS: call memcpy
; CHECKO2REM-LABEL: test_memcpy
; CHECKO2UNSANDBOXEDREM-LABEL: test_memcpy
@@ -125,7 +138,9 @@
ret void
}
; CHECK-LABEL: test_memcpy_const_len_align
-; CHECK: call memcpy
+; CHECK: call -4
+; CALLTARGETS-LABEL: test_memcpy_const_len_align
+; CALLTARGETS: call memcpy
define void @test_memmove(i32 %iptr_dst, i32 %iptr_src, i32 %len) {
entry:
@@ -136,7 +151,9 @@
ret void
}
; CHECK-LABEL: test_memmove
-; CHECK: call memmove
+; CHECK: call -4
+; CALLTARGETS-LABEL: test_memmove
+; CALLTARGETS: call memmove
define void @test_memmove_const_len_align(i32 %iptr_dst, i32 %iptr_src) {
entry:
@@ -147,7 +164,9 @@
ret void
}
; CHECK-LABEL: test_memmove_const_len_align
-; CHECK: call memmove
+; CHECK: call -4
+; CALLTARGETS-LABEL: test_memmove_const_len_align
+; CALLTARGETS: call memmove
define void @test_memset(i32 %iptr_dst, i32 %wide_val, i32 %len) {
entry:
@@ -159,7 +178,9 @@
}
; CHECK-LABEL: test_memset
; CHECK: movzx
-; CHECK: call memset
+; CHECK: call -4
+; CALLTARGETS-LABEL: test_memset
+; CALLTARGETS: call memset
define void @test_memset_const_len_align(i32 %iptr_dst, i32 %wide_val) {
entry:
@@ -171,7 +192,9 @@
}
; CHECK-LABEL: test_memset_const_len_align
; CHECK: movzx
-; CHECK: call memset
+; CHECK: call -4
+; CALLTARGETS-LABEL: test_memset_const_len_align
+; CALLTARGETS: call memset
define void @test_memset_const_val(i32 %iptr_dst, i32 %len) {
entry:
@@ -182,7 +205,10 @@
; CHECK-LABEL: test_memset_const_val
; Make sure the argument is legalized (can't movzx reg, 0).
; CHECK: movzx {{.*}}, {{[^0]}}
-; CHECK: call memset
+; CHECK: call -4
+; CALLTARGETS-LABEL: test_memset_const_val
+; CALLTARGETS: call memset
+
define i32 @test_setjmplongjmp(i32 %iptr_env) {
entry:
@@ -199,11 +225,14 @@
ret i32 1
}
; CHECK-LABEL: test_setjmplongjmp
-; CHECK: call setjmp
-; CHECK: call longjmp
+; CHECK: call -4
+; CHECK: call -4
; CHECKO2REM-LABEL: test_setjmplongjmp
-; CHECKO2REM: call setjmp
-; CHECKO2REM: call longjmp
+; CHECKO2REM: call -4
+; CHECKO2REM: call -4
+; CALLTARGETS-LABEL: test_setjmplongjmp
+; CALLTARGETS: call setjmp
+; CALLTARGETS: call longjmp
define i32 @test_setjmp_unused(i32 %iptr_env, i32 %i_other) {
entry:
@@ -214,7 +243,9 @@
; Don't consider setjmp side-effect free, so it's not eliminated if
; result unused.
; CHECKO2REM-LABEL: test_setjmp_unused
-; CHECKO2REM: call setjmp
+; CHECKO2REM: call -4
+; CALLTARGETS-LABEL: test_setjmp_unused
+; CALLTARGETS: call setjmp
define float @test_sqrt_float(float %x, i32 %iptr) {
entry:
@@ -222,20 +253,22 @@
%r2 = call float @llvm.sqrt.f32(float %r)
%r3 = call float @llvm.sqrt.f32(float -0.0)
%r4 = fadd float %r2, %r3
- br label %next
-
-next:
- %__6 = inttoptr i32 %iptr to float*
- %y = load float* %__6, align 4
- %r5 = call float @llvm.sqrt.f32(float %y)
- %r6 = fadd float %r4, %r5
- ret float %r6
+ ret float %r4
}
; CHECK-LABEL: test_sqrt_float
; CHECK: sqrtss xmm{{.*}}
; CHECK: sqrtss xmm{{.*}}
; CHECK: sqrtss xmm{{.*}}, dword ptr
-; CHECK-LABEL: .L{{.*}}next
+
+define float @test_sqrt_float_mergeable_load(float %x, i32 %iptr) {
+entry:
+ %__2 = inttoptr i32 %iptr to float*
+ %y = load float* %__2, align 4
+ %r5 = call float @llvm.sqrt.f32(float %y)
+ %r6 = fadd float %x, %r5
+ ret float %r6
+}
+; CHECK-LABEL: test_sqrt_float_mergeable_load
; We could fold the load and the sqrt into one operation, but the
; current folding only handles load + arithmetic op. The sqrt inst
; is considered an intrinsic call and not an arithmetic op.
@@ -247,20 +280,22 @@
%r2 = call double @llvm.sqrt.f64(double %r)
%r3 = call double @llvm.sqrt.f64(double -0.0)
%r4 = fadd double %r2, %r3
- br label %next
-
-next:
- %__6 = inttoptr i32 %iptr to double*
- %y = load double* %__6, align 8
- %r5 = call double @llvm.sqrt.f64(double %y)
- %r6 = fadd double %r4, %r5
- ret double %r6
+ ret double %r4
}
; CHECK-LABEL: test_sqrt_double
; CHECK: sqrtsd xmm{{.*}}
; CHECK: sqrtsd xmm{{.*}}
; CHECK: sqrtsd xmm{{.*}}, qword ptr
-; CHECK-LABEL: .L{{.*}}next
+
+define double @test_sqrt_double_mergeable_load(double %x, i32 %iptr) {
+entry:
+ %__2 = inttoptr i32 %iptr to double*
+ %y = load double* %__2, align 8
+ %r5 = call double @llvm.sqrt.f64(double %y)
+ %r6 = fadd double %x, %r5
+ ret double %r6
+}
+; CHECK-LABEL: test_sqrt_double_mergeable_load
; CHECK: sqrtsd xmm{{.*}}
define float @test_sqrt_ignored(float %x, double %y) {
@@ -414,7 +449,9 @@
ret i32 %r
}
; CHECK-LABEL: test_popcount_32
-; CHECK: call __popcountsi2
+; CHECK: call -4
+; CALLTARGETS-LABEL: test_popcount_32
+; CALLTARGETS: call __popcountsi2
define i64 @test_popcount_64(i64 %x) {
entry:
@@ -422,10 +459,13 @@
ret i64 %r
}
; CHECK-LABEL: test_popcount_64
-; CHECK: call __popcountdi2
+; CHECK: call -4
; __popcountdi2 only returns a 32-bit result, so clear the upper bits of
; the return value just in case.
; CHECK: mov {{.*}}, 0
+; CALLTARGETS-LABEL: test_popcount_64
+; CALLTARGETS: call __popcountdi2
+
define i32 @test_popcount_64_ret_i32(i64 %x) {
entry:
@@ -435,8 +475,10 @@
}
; If there is a trunc, then the mov {{.*}}, 0 is dead and gets optimized out.
; CHECKO2REM-LABEL: test_popcount_64_ret_i32
-; CHECKO2REM: call __popcountdi2
+; CHECKO2REM: call -4
; CHECKO2REM-NOT: mov {{.*}}, 0
+; CALLTARGETS-LABEL: test_popcount_64_ret_i32
+; CALLTARGETS: call __popcountdi2
define void @test_stacksave_noalloca() {
entry:
diff --git a/tests_lit/llvm2ice_tests/sdiv.ll b/tests_lit/llvm2ice_tests/sdiv.ll
index 9f2d94a..7486d94 100644
--- a/tests_lit/llvm2ice_tests/sdiv.ll
+++ b/tests_lit/llvm2ice_tests/sdiv.ll
@@ -1,12 +1,12 @@
; This checks the correctness of the lowering code for the small
; integer variants of sdiv and srem.
-; RUN: %llvm2ice --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice -Om1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
diff --git a/tests_lit/llvm2ice_tests/select-opt.ll b/tests_lit/llvm2ice_tests/select-opt.ll
index 83a3d42..ca91274 100644
--- a/tests_lit/llvm2ice_tests/select-opt.ll
+++ b/tests_lit/llvm2ice_tests/select-opt.ll
@@ -3,12 +3,12 @@
; regardless of the optimization level, so there are no special OPTM1
; match lines.
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice -Om1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
@@ -25,9 +25,15 @@
ret void
}
-declare void @useInt(i32)
+define void @useInt(i32 %x) {
+entry:
+ call void @useIntHelper(i32 %x)
+ ret void
+}
-; CHECK: .globl testSelect
+declare void @useIntHelper(i32)
+
+; CHECK-LABEL: testSelect
; CHECK: cmp
; CHECK: cmp
; CHECK: call useInt
diff --git a/tests_lit/llvm2ice_tests/shift.ll b/tests_lit/llvm2ice_tests/shift.ll
index d9f608d..260d685 100644
--- a/tests_lit/llvm2ice_tests/shift.ll
+++ b/tests_lit/llvm2ice_tests/shift.ll
@@ -1,12 +1,12 @@
; This is a test of C-level conversion operations that clang lowers
; into pairs of shifts.
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice -Om1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
@@ -26,7 +26,7 @@
store i32 %v1, i32* %__4, align 1
ret void
}
-; CHECK: conv1:
+; CHECK-LABEL: conv1
; CHECK: shl {{.*}}, 24
; CHECK: sar {{.*}}, 24
@@ -40,7 +40,7 @@
store i32 %v1, i32* %__4, align 1
ret void
}
-; CHECK: conv2:
+; CHECK-LABEL: conv2
; CHECK: shl {{.*}}, 16
; CHECK: sar {{.*}}, 16
diff --git a/tests_lit/llvm2ice_tests/simple-loop.ll b/tests_lit/llvm2ice_tests/simple-loop.ll
index e58eaf9..dd94a57 100644
--- a/tests_lit/llvm2ice_tests/simple-loop.ll
+++ b/tests_lit/llvm2ice_tests/simple-loop.ll
@@ -1,12 +1,13 @@
; This tests a simple loop that sums the elements of an input array.
; The O2 check patterns represent the best code currently achieved.
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck --check-prefix=OPTM1 %s
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d -symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice -Om1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d -symbolize -x86-asm-syntax=intel - \
+; RUN: | FileCheck --check-prefix=OPTM1 %s
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
@@ -34,11 +35,13 @@
ret i32 %sum.0.lcssa
}
-; CHECK: .globl simple_loop
-; CHECK: mov ecx, dword ptr [esp+{{[0-9]+}}]
+; CHECK-LABEL: simple_loop
+; CHECK: mov ecx, dword ptr [esp{{.*}}+{{.*}}{{[0-9]+}}]
; CHECK: cmp ecx, 0
-; CHECK-NEXT: jg {{.*}}for.body
-; CHECK-NEXT: jmp {{.*}}for.end
+; CHECK-NEXT: jg {{[0-9]}}
+; NaCl bundle padding
+; CHECK-NEXT: nop
+; CHECK-NEXT: jmp {{[0-9]}}
; TODO: the mov from ebx to esi seems redundant here - so this may need to be
; modified later
@@ -46,11 +49,11 @@
; CHECK: add [[IREG:[a-z]+]], 1
; CHECK-NEXT: mov [[ICMPREG:[a-z]+]], [[IREG]]
; CHECK: cmp [[ICMPREG]], ecx
-; CHECK-NEXT: jl {{.*}}for.body
+; CHECK-NEXT: jl -{{[0-9]}}
;
; There's nothing remarkable under Om1 to test for, since Om1 generates
; such atrocious code (by design).
-; OPTM1: .globl simple_loop
+; OPTM1-LABEL: simple_loop
; OPTM1: cmp {{.*}}, 0
; OPTM1: jg
; OPTM1: ret
diff --git a/tests_lit/llvm2ice_tests/undef.ll b/tests_lit/llvm2ice_tests/undef.ll
index b98946c..6b66e0a 100644
--- a/tests_lit/llvm2ice_tests/undef.ll
+++ b/tests_lit/llvm2ice_tests/undef.ll
@@ -1,17 +1,17 @@
; This test checks that undef values are represented as zero.
-; RUN: %llvm2ice --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -mattr=sse4.1 --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -mattr=sse4.1 -O2 --verbose none %s | FileCheck %s
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice -Om1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
-; RUN: %llvm2ice -mattr=sse4.1 -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
-; RUN: %llvm2ice -mattr=sse4.1 -Om1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %llvm2ice -O2 -mattr=sse4.1 --verbose none %s \
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %llvm2ice -Om1 -mattr=sse4.1 --verbose none %s \
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
@@ -20,14 +20,14 @@
define i32 @undef_i32() {
entry:
ret i32 undef
-; CHECK-LABEL: undef_i32:
+; CHECK-LABEL: undef_i32
; CHECK: mov eax, 0
}
define i64 @undef_i64() {
entry:
ret i64 undef
-; CHECK-LABEL: undef_i64:
+; CHECK-LABEL: undef_i64
; CHECK-DAG: mov eax, 0
; CHECK-DAG: mov edx, 0
; CHECK: ret
@@ -36,56 +36,56 @@
define float @undef_float() {
entry:
ret float undef
-; CHECK-LABEL: undef_float:
-; CHECK: [L$float$
+; CHECK-LABEL: undef_float
+; CHECK: fld dword ptr [0]
}
define <4 x i1> @undef_v4i1() {
entry:
ret <4 x i1> undef
-; CHECK-LABEL: undef_v4i1:
+; CHECK-LABEL: undef_v4i1
; CHECK: pxor
}
define <8 x i1> @undef_v8i1() {
entry:
ret <8 x i1> undef
-; CHECK-LABEL: undef_v8i1:
+; CHECK-LABEL: undef_v8i1
; CHECK: pxor
}
define <16 x i1> @undef_v16i1() {
entry:
ret <16 x i1> undef
-; CHECK-LABEL: undef_v16i1:
+; CHECK-LABEL: undef_v16i1
; CHECK: pxor
}
define <16 x i8> @undef_v16i8() {
entry:
ret <16 x i8> undef
-; CHECK-LABEL: undef_v16i8:
+; CHECK-LABEL: undef_v16i8
; CHECK: pxor
}
define <8 x i16> @undef_v8i16() {
entry:
ret <8 x i16> undef
-; CHECK-LABEL: undef_v8i16:
+; CHECK-LABEL: undef_v8i16
; CHECK: pxor
}
define <4 x i32> @undef_v4i32() {
entry:
ret <4 x i32> undef
-; CHECK-LABEL: undef_v4i32:
+; CHECK-LABEL: undef_v4i32
; CHECK: pxor
}
define <4 x float> @undef_v4f32() {
entry:
ret <4 x float> undef
-; CHECK-LABEL: undef_v4f32:
+; CHECK-LABEL: undef_v4f32
; CHECK: pxor
}
@@ -93,7 +93,7 @@
entry:
%val = add <4 x i32> undef, %arg
ret <4 x i32> %val
-; CHECK-LABEL: vector_arith:
+; CHECK-LABEL: vector_arith
; CHECK: pxor
}
@@ -101,7 +101,7 @@
entry:
%val = bitcast <4 x i32> undef to <4 x float>
ret <4 x float> %val
-; CHECK-LABEL: vector_bitcast:
+; CHECK-LABEL: vector_bitcast
; CHECK: pxor
}
@@ -109,7 +109,7 @@
entry:
%val = sext <4 x i1> undef to <4 x i32>
ret <4 x i32> %val
-; CHECK-LABEL: vector_sext:
+; CHECK-LABEL: vector_sext
; CHECK: pxor
}
@@ -117,7 +117,7 @@
entry:
%val = zext <4 x i1> undef to <4 x i32>
ret <4 x i32> %val
-; CHECK-LABEL: vector_zext:
+; CHECK-LABEL: vector_zext
; CHECK: pxor
}
@@ -125,7 +125,7 @@
entry:
%val = trunc <4 x i32> undef to <4 x i1>
ret <4 x i1> %val
-; CHECK-LABEL: vector_trunc:
+; CHECK-LABEL: vector_trunc
; CHECK: pxor
}
@@ -133,7 +133,7 @@
entry:
%val = icmp eq <4 x i32> undef, %arg
ret <4 x i1> %val
-; CHECK-LABEL: vector_icmp:
+; CHECK-LABEL: vector_icmp
; CHECK: pxor
}
@@ -141,7 +141,7 @@
entry:
%val = fcmp ueq <4 x float> undef, %arg
ret <4 x i1> %val
-; CHECK-LABEL: vector_fcmp:
+; CHECK-LABEL: vector_fcmp
; CHECK: pxor
}
@@ -149,7 +149,7 @@
entry:
%val = fptosi <4 x float> undef to <4 x i32>
ret <4 x i32> %val
-; CHECK-LABEL: vector_fptosi:
+; CHECK-LABEL: vector_fptosi
; CHECK: pxor
}
@@ -157,7 +157,7 @@
entry:
%val = fptoui <4 x float> undef to <4 x i32>
ret <4 x i32> %val
-; CHECK-LABEL: vector_fptoui:
+; CHECK-LABEL: vector_fptoui
; CHECK: pxor
}
@@ -165,7 +165,7 @@
entry:
%val = sitofp <4 x i32> undef to <4 x float>
ret <4 x float> %val
-; CHECK-LABEL: vector_sitofp:
+; CHECK-LABEL: vector_sitofp
; CHECK: pxor
}
@@ -173,7 +173,7 @@
entry:
%val = uitofp <4 x i32> undef to <4 x float>
ret <4 x float> %val
-; CHECK-LABEL: vector_uitofp:
+; CHECK-LABEL: vector_uitofp
; CHECK: pxor
}
@@ -181,7 +181,7 @@
entry:
%val = insertelement <4 x float> undef, float 1.0, i32 0
ret <4 x float> %val
-; CHECK-LABEL: vector_insertelement_arg1:
+; CHECK-LABEL: vector_insertelement_arg1
; CHECK: pxor
}
@@ -189,15 +189,15 @@
entry:
%val = insertelement <4 x float> %arg, float undef, i32 0
ret <4 x float> %val
-; CHECK-LABEL: vector_insertelement_arg2:
-; CHECK: [L$float$
+; CHECK-LABEL: vector_insertelement_arg2
+; CHECK: movss {{.*}}, dword ptr [0]
}
define float @vector_extractelement_v4f32_index_0() {
entry:
%val = extractelement <4 x float> undef, i32 0
ret float %val
-; CHECK-LABEL: vector_extractelement_v4f32_index_0:
+; CHECK-LABEL: vector_extractelement_v4f32_index_0
; CHECK: pxor
}
@@ -205,7 +205,7 @@
entry:
%val = extractelement <4 x float> undef, i32 1
ret float %val
-; CHECK-LABEL: vector_extractelement_v4f32_index_1:
+; CHECK-LABEL: vector_extractelement_v4f32_index_1
; CHECK: pxor
}
@@ -214,7 +214,7 @@
%val.trunc = extractelement <16 x i1> undef, i32 7
%val = sext i1 %val.trunc to i32
ret i32 %val
-; CHECK-LABEL: vector_extractelement_v16i1_index_7:
+; CHECK-LABEL: vector_extractelement_v16i1_index_7
; CHECK: pxor
}
@@ -222,7 +222,7 @@
entry:
%val = select <4 x i1> undef, <4 x i32> %a, <4 x i32> %b
ret <4 x i32> %val
-; CHECK-LABEL: vector_select_v4i32_cond:
+; CHECK-LABEL: vector_select_v4i32_cond
; CHECK: pxor
}
@@ -230,7 +230,7 @@
entry:
%val = select <4 x i1> %cond, <4 x i32> undef, <4 x i32> %b
ret <4 x i32> %val
-; CHECK-LABEL: vector_select_v4i32_arg1:
+; CHECK-LABEL: vector_select_v4i32_arg1
; CHECK: pxor
}
@@ -238,7 +238,7 @@
entry:
%val = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> undef
ret <4 x i32> %val
-; CHECK-LABEL: vector_select_v4i32_arg2:
+; CHECK-LABEL: vector_select_v4i32_arg2
; CHECK: pxor
}
@@ -246,7 +246,7 @@
entry:
%val = select <4 x i1> undef, <4 x i1> %a, <4 x i1> %b
ret <4 x i1> %val
-; CHECK-LABEL: vector_select_v4i1_cond:
+; CHECK-LABEL: vector_select_v4i1_cond
; CHECK: pxor
}
@@ -254,7 +254,7 @@
entry:
%val = select <4 x i1> %cond, <4 x i1> undef, <4 x i1> %b
ret <4 x i1> %val
-; CHECK-LABEL: vector_select_v4i1_arg1:
+; CHECK-LABEL: vector_select_v4i1_arg1
; CHECK: pxor
}
@@ -262,7 +262,7 @@
entry:
%val = select <4 x i1> %cond, <4 x i1> %a, <4 x i1> undef
ret <4 x i1> %val
-; CHECK-LABEL: vector_select_v4i1_arg2:
+; CHECK-LABEL: vector_select_v4i1_arg2
; CHECK: pxor
}
@@ -270,7 +270,7 @@
entry:
%val = select <4 x i1> undef, <4 x float> %a, <4 x float> %b
ret <4 x float> %val
-; CHECK-LABEL: vector_select_v4f32_cond:
+; CHECK-LABEL: vector_select_v4f32_cond
; CHECK: pxor
}
@@ -278,7 +278,7 @@
entry:
%val = select <4 x i1> %cond, <4 x float> undef, <4 x float> %b
ret <4 x float> %val
-; CHECK-LABEL: vector_select_v4f32_arg1:
+; CHECK-LABEL: vector_select_v4f32_arg1
; CHECK: pxor
}
@@ -286,7 +286,7 @@
entry:
%val = select <4 x i1> %cond, <4 x float> %a, <4 x float> undef
ret <4 x float> %val
-; CHECK-LABEL: vector_select_v4f32_arg2:
+; CHECK-LABEL: vector_select_v4f32_arg2
; CHECK: pxor
}
diff --git a/tests_lit/llvm2ice_tests/unreachable.ll b/tests_lit/llvm2ice_tests/unreachable.ll
index 0c5f5b2..8db1bff 100644
--- a/tests_lit/llvm2ice_tests/unreachable.ll
+++ b/tests_lit/llvm2ice_tests/unreachable.ll
@@ -1,13 +1,23 @@
; This tests the basic structure of the Unreachable instruction.
-; RUN: %llvm2ice --verbose inst %s | FileCheck %s
-; RUN: %llvm2ice --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; TODO(jvoung): fix extra "CALLTARGETS" run. The llvm-objdump symbolizer
+; doesn't know how to symbolize non-section-local functions.
+; The newer LLVM 3.6 one does work, but watch out for other bugs.
+
+; RUN: %llvm2ice -O2 --verbose none %s \
+; RUN: | FileCheck --check-prefix=CALLTARGETS %s
+; RUN: %llvm2ice -O2 --verbose none %s \
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %llvm2ice -Om1 --verbose none %s \
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
; RUN: | FileCheck --check-prefix=DUMP %s
+
define internal i32 @divide(i32 %num, i32 %den) {
entry:
%cmp = icmp ne i32 %den, 0
@@ -15,15 +25,17 @@
abort: ; preds = %entry
unreachable
-; CHECK: unreachable
return: ; preds = %entry
%div = sdiv i32 %num, %den
ret i32 %div
}
+; CHECK-LABEL: divide
+; CALLTARGETS-LABEL: divide
; CHECK: cmp
-; CHECK: call ice_unreachable
+; CHECK: call -4
+; CALLTARGETS: call ice_unreachable
; CHECK: cdq
; CHECK: idiv
; CHECK: ret
diff --git a/tests_lit/llvm2ice_tests/vector-arg.ll b/tests_lit/llvm2ice_tests/vector-arg.ll
index 1725aed..cdefd3c 100644
--- a/tests_lit/llvm2ice_tests/vector-arg.ll
+++ b/tests_lit/llvm2ice_tests/vector-arg.ll
@@ -1,12 +1,13 @@
; This file checks that Subzero generates code in accordance with the
; calling convention for vectors.
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck --check-prefix=OPTM1 %s
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice -Om1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: | FileCheck --check-prefix=OPTM1 %s
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
@@ -71,7 +72,7 @@
entry:
ret <4 x float> %arg4
; CHECK-LABEL: test_returning_arg4:
-; CHECK: movups xmm0, xmmword ptr [esp+4]
+; CHECK: movups xmm0, xmmword ptr [esp + 4]
; CHECK: ret
; OPTM1-LABEL: test_returning_arg4:
@@ -139,7 +140,7 @@
entry:
ret <4 x float> %arg4
; CHECK-LABEL: test_returning_interspersed_arg4:
-; CHECK: movups xmm0, xmmword ptr [esp+52]
+; CHECK: movups xmm0, xmmword ptr [esp + 52]
; CHECK: ret
; OPTM1-LABEL: test_returning_interspersed_arg4:
@@ -162,15 +163,15 @@
ret void
; CHECK-LABEL: test_passing_vectors:
; CHECK: sub esp, 32
-; CHECK: movups [[ARG5:.*]], xmmword ptr [esp+64]
+; CHECK: movups [[ARG5:.*]], xmmword ptr [esp + 64]
; CHECK: movups xmmword ptr [esp], [[ARG5]]
-; CHECK: movups [[ARG6:.*]], xmmword ptr [esp+48]
-; CHECK: movups xmmword ptr [esp+16], [[ARG6]]
-; CHECK: movups xmm0, xmmword ptr [esp+128]
-; CHECK: movups xmm1, xmmword ptr [esp+112]
-; CHECK: movups xmm2, xmmword ptr [esp+96]
-; CHECK: movups xmm3, xmmword ptr [esp+80]
-; CHECK: call VectorArgs
+; CHECK: movups [[ARG6:.*]], xmmword ptr [esp + 48]
+; CHECK: movups xmmword ptr [esp + 16], [[ARG6]]
+; CHECK: movups xmm0, xmmword ptr [esp + 128]
+; CHECK: movups xmm1, xmmword ptr [esp + 112]
+; CHECK: movups xmm2, xmmword ptr [esp + 96]
+; CHECK: movups xmm3, xmmword ptr [esp + 80]
+; CHECK: call -4
; CHECK-NEXT: add esp, 32
; CHECK: ret
@@ -179,12 +180,12 @@
; OPTM1: movups [[ARG5:.*]], xmmword ptr {{.*}}
; OPTM1: movups xmmword ptr [esp], [[ARG5]]
; OPTM1: movups [[ARG6:.*]], xmmword ptr {{.*}}
-; OPTM1: movups xmmword ptr [esp+16], [[ARG6]]
+; OPTM1: movups xmmword ptr [esp + 16], [[ARG6]]
; OPTM1: movups xmm0, xmmword ptr {{.*}}
; OPTM1: movups xmm1, xmmword ptr {{.*}}
; OPTM1: movups xmm2, xmmword ptr {{.*}}
; OPTM1: movups xmm3, xmmword ptr {{.*}}
-; OPTM1: call VectorArgs
+; OPTM1: call -4
; OPTM1-NEXT: add esp, 32
; OPTM1: ret
}
@@ -200,29 +201,29 @@
ret void
; CHECK-LABEL: test_passing_vectors_interspersed:
; CHECK: sub esp, 80
-; CHECK: movups [[ARG9:.*]], xmmword ptr [esp+112]
-; CHECK: movups xmmword ptr [esp+32], [[ARG9]]
-; CHECK: movups [[ARG11:.*]], xmmword ptr [esp+96]
-; CHECK: movups xmmword ptr [esp+64], [[ARG11]]
-; CHECK: movups xmm0, xmmword ptr [esp+176]
-; CHECK: movups xmm1, xmmword ptr [esp+160]
-; CHECK: movups xmm2, xmmword ptr [esp+144]
-; CHECK: movups xmm3, xmmword ptr [esp+128]
-; CHECK: call InterspersedVectorArgs
+; CHECK: movups [[ARG9:.*]], xmmword ptr [esp + 112]
+; CHECK: movups xmmword ptr [esp + 32], [[ARG9]]
+; CHECK: movups [[ARG11:.*]], xmmword ptr [esp + 96]
+; CHECK: movups xmmword ptr [esp + 64], [[ARG11]]
+; CHECK: movups xmm0, xmmword ptr [esp + 176]
+; CHECK: movups xmm1, xmmword ptr [esp + 160]
+; CHECK: movups xmm2, xmmword ptr [esp + 144]
+; CHECK: movups xmm3, xmmword ptr [esp + 128]
+; CHECK: call -4
; CHECK-NEXT: add esp, 80
; CHECK: ret
; OPTM1-LABEL: test_passing_vectors_interspersed:
; OPTM1: sub esp, 80
; OPTM1: movups [[ARG9:.*]], xmmword ptr {{.*}}
-; OPTM1: movups xmmword ptr [esp+32], [[ARG9]]
+; OPTM1: movups xmmword ptr [esp + 32], [[ARG9]]
; OPTM1: movups [[ARG11:.*]], xmmword ptr {{.*}}
-; OPTM1: movups xmmword ptr [esp+64], [[ARG11]]
+; OPTM1: movups xmmword ptr [esp + 64], [[ARG11]]
; OPTM1: movups xmm0, xmmword ptr {{.*}}
; OPTM1: movups xmm1, xmmword ptr {{.*}}
; OPTM1: movups xmm2, xmmword ptr {{.*}}
; OPTM1: movups xmm3, xmmword ptr {{.*}}
-; OPTM1: call InterspersedVectorArgs
+; OPTM1: call -4
; OPTM1-NEXT: add esp, 80
; OPTM1: ret
}
@@ -238,16 +239,16 @@
%result2 = call <4 x float> @VectorReturn(<4 x float> %result)
ret void
; CHECK-LABEL: test_receiving_vectors:
-; CHECK: call VectorReturn
+; CHECK: call -4
; CHECK-NOT: movups xmm0
-; CHECK: call VectorReturn
+; CHECK: call -4
; CHECK: ret
; OPTM1-LABEL: test_receiving_vectors:
-; OPTM1: call VectorReturn
+; OPTM1: call -4
; OPTM1: movups {{.*}}, xmm0
; OPTM1: movups xmm0, {{.*}}
-; OPTM1: call VectorReturn
+; OPTM1: call -4
; OPTM1: ret
}
diff --git a/tests_lit/llvm2ice_tests/vector-arith.ll b/tests_lit/llvm2ice_tests/vector-arith.ll
index 37038ba..72055f4 100644
--- a/tests_lit/llvm2ice_tests/vector-arith.ll
+++ b/tests_lit/llvm2ice_tests/vector-arith.ll
@@ -1,19 +1,25 @@
; This test checks support for vector arithmetic.
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -O2 -mattr=sse4.1 --verbose none %s \
-; RUN: | FileCheck %s --check-prefix=SSE41
-; RUN: %llvm2ice -Om1 -mattr=sse4.1 --verbose none %s \
-; RUN: | FileCheck %s --check-prefix=SSE41
+; TODO(jvoung): fix extra "CALLTARGETS" run. The llvm-objdump symbolizer
+; doesn't know how to symbolize non-section-local functions.
+; The newer LLVM 3.6 one does work, but watch out for other bugs.
+
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | FileCheck --check-prefix=CALLTARGETS %s
+; RUN: %llvm2ice -O2 --verbose none %s \
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice -Om1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice -O2 -mattr=sse4.1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: | FileCheck --check-prefix=SSE41 %s
; RUN: %llvm2ice -Om1 -mattr=sse4.1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: | FileCheck --check-prefix=SSE41 %s
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
@@ -56,10 +62,15 @@
%res = frem <4 x float> %arg0, %arg1
ret <4 x float> %res
; CHECK-LABEL: test_frem:
-; CHECK: fmodf
-; CHECK: fmodf
-; CHECK: fmodf
-; CHECK: fmodf
+; CALLTARGETS-LABEL: test_frem:
+; CHECK: -4
+; CHECK: -4
+; CHECK: -4
+; CHECK: -4
+; CALLTARGETS: fmodf
+; CALLTARGETS: fmodf
+; CALLTARGETS: fmodf
+; CALLTARGETS: fmodf
}
define <16 x i8> @test_add_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
diff --git a/tests_lit/llvm2ice_tests/vector-bitcast.ll b/tests_lit/llvm2ice_tests/vector-bitcast.ll
index 3da21a2..c346936 100644
--- a/tests_lit/llvm2ice_tests/vector-bitcast.ll
+++ b/tests_lit/llvm2ice_tests/vector-bitcast.ll
@@ -1,12 +1,19 @@
; This file tests bitcasts of vector type. For most operations, these
; should be lowered to a no-op on -O2.
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s --check-prefix=OPTM1
+; TODO(jvoung): fix extra "CALLTARGETS" run. The llvm-objdump symbolizer
+; doesn't know how to symbolize non-section-local functions.
+; The newer LLVM 3.6 one does work, but watch out for other bugs.
+
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | FileCheck --check-prefix=CALLTARGETS %s
+; RUN: %llvm2ice -O2 --verbose none %s \
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d -symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice -Om1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d -symbolize -x86-asm-syntax=intel - \
+; RUN: | FileCheck --check-prefix=OPTM1 %s
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
@@ -17,8 +24,7 @@
%res = bitcast <16 x i8> %arg to <16 x i8>
ret <16 x i8> %res
-; CHECK-LABEL: test_bitcast_v16i8_to_v16i8:
-; CHECK: .L{{.*}}entry:
+; CHECK-LABEL: test_bitcast_v16i8_to_v16i8
; CHECK-NEXT: ret
}
@@ -27,8 +33,7 @@
%res = bitcast <16 x i8> %arg to <8 x i16>
ret <8 x i16> %res
-; CHECK-LABEL: test_bitcast_v16i8_to_v8i16:
-; CHECK: .L{{.*}}entry:
+; CHECK-LABEL: test_bitcast_v16i8_to_v8i16
; CHECK-NEXT: ret
}
@@ -38,7 +43,6 @@
ret <4 x i32> %res
; CHECK-LABEL: test_bitcast_v16i8_to_v4i32:
-; CHECK: .L{{.*}}entry:
; CHECK-NEXT: ret
}
@@ -48,7 +52,6 @@
ret <4 x float> %res
; CHECK-LABEL: test_bitcast_v16i8_to_v4f32:
-; CHECK: .L{{.*}}entry:
; CHECK-NEXT: ret
}
@@ -58,7 +61,6 @@
ret <16 x i8> %res
; CHECK-LABEL: test_bitcast_v8i16_to_v16i8:
-; CHECK: .L{{.*}}entry:
; CHECK-NEXT: ret
}
@@ -68,7 +70,6 @@
ret <8 x i16> %res
; CHECK-LABEL: test_bitcast_v8i16_to_v8i16:
-; CHECK: .L{{.*}}entry:
; CHECK-NEXT: ret
}
@@ -78,7 +79,6 @@
ret <4 x i32> %res
; CHECK-LABEL: test_bitcast_v8i16_to_v4i32:
-; CHECK: .L{{.*}}entry:
; CHECK-NEXT: ret
}
@@ -88,7 +88,6 @@
ret <4 x float> %res
; CHECK-LABEL: test_bitcast_v8i16_to_v4f32:
-; CHECK: .L{{.*}}entry:
; CHECK-NEXT: ret
}
@@ -98,7 +97,6 @@
ret <16 x i8> %res
; CHECK-LABEL: test_bitcast_v4i32_to_v16i8:
-; CHECK: .L{{.*}}entry:
; CHECK-NEXT: ret
}
@@ -108,7 +106,6 @@
ret <8 x i16> %res
; CHECK-LABEL: test_bitcast_v4i32_to_v8i16:
-; CHECK: .L{{.*}}entry:
; CHECK-NEXT: ret
}
@@ -118,7 +115,6 @@
ret <4 x i32> %res
; CHECK-LABEL: test_bitcast_v4i32_to_v4i32:
-; CHECK: .L{{.*}}entry:
; CHECK-NEXT: ret
}
@@ -128,7 +124,6 @@
ret <4 x float> %res
; CHECK-LABEL: test_bitcast_v4i32_to_v4f32:
-; CHECK: .L{{.*}}entry:
; CHECK-NEXT: ret
}
@@ -138,7 +133,6 @@
ret <16 x i8> %res
; CHECK-LABEL: test_bitcast_v4f32_to_v16i8:
-; CHECK: .L{{.*}}entry:
; CHECK-NEXT: ret
}
@@ -148,7 +142,6 @@
ret <8 x i16> %res
; CHECK-LABEL: test_bitcast_v4f32_to_v8i16:
-; CHECK: .L{{.*}}entry:
; CHECK-NEXT: ret
}
@@ -158,7 +151,6 @@
ret <4 x i32> %res
; CHECK-LABEL: test_bitcast_v4f32_to_v4i32:
-; CHECK: .L{{.*}}entry:
; CHECK-NEXT: ret
}
@@ -168,7 +160,6 @@
ret <4 x float> %res
; CHECK-LABEL: test_bitcast_v4f32_to_v4f32:
-; CHECK: .L{{.*}}entry:
; CHECK-NEXT: ret
}
@@ -178,10 +169,12 @@
ret i8 %res
; CHECK-LABEL: test_bitcast_v8i1_to_i8:
-; CHECK: call Sz_bitcast_v8i1_to_i8
+; CALLTARGETS-LABEL: test_bitcast_v8i1_to_i8:
+; CHECK: call -4
+; CALLTARGETS: call Sz_bitcast_v8i1_to_i8
; OPTM1-LABEL: test_bitcast_v8i1_to_i8:
-; OPMT1: call Sz_bitcast_v8i1_to_i8
+; OPMT1: call -4
}
define i16 @test_bitcast_v16i1_to_i16(<16 x i1> %arg) {
@@ -190,10 +183,12 @@
ret i16 %res
; CHECK-LABEL: test_bitcast_v16i1_to_i16:
-; CHECK: call Sz_bitcast_v16i1_to_i16
+; CALLTARGETS-LABEL: test_bitcast_v16i1_to_i16:
+; CHECK: call -4
+; CALLTARGETS: call Sz_bitcast_v16i1_to_i16
; OPTM1-LABEL: test_bitcast_v16i1_to_i16:
-; OPMT1: call Sz_bitcast_v16i1_to_i16
+; OPMT1: call -4
}
define <8 x i1> @test_bitcast_i8_to_v8i1(i32 %arg) {
@@ -203,10 +198,12 @@
ret <8 x i1> %res
; CHECK-LABEL: test_bitcast_i8_to_v8i1:
-; CHECK: call Sz_bitcast_i8_to_v8i1
+; CALLTARGETS-LABEL: test_bitcast_i8_to_v8i1
+; CHECK: call -4
+; CALLTARGETS: call Sz_bitcast_i8_to_v8i1
; OPTM1-LABEL: test_bitcast_i8_to_v8i1:
-; OPTM1: call Sz_bitcast_i8_to_v8i1
+; OPTM1: call -4
}
define <16 x i1> @test_bitcast_i16_to_v16i1(i32 %arg) {
@@ -216,10 +213,12 @@
ret <16 x i1> %res
; CHECK-LABEL: test_bitcast_i16_to_v16i1:
-; CHECK: call Sz_bitcast_i16_to_v16i1
+; CALLTARGETS-LABEL: test_bitcast_i16_to_v16i1
+; CHECK: call -4
+; CALLTARGETS: call Sz_bitcast_i16_to_v16i1
; OPTM1-LABEL: test_bitcast_i16_to_v16i1:
-; OPTM1: call Sz_bitcast_i16_to_v16i1
+; OPTM1: call -4
}
; ERRORS-NOT: ICE translation error
diff --git a/tests_lit/llvm2ice_tests/vector-cast.ll b/tests_lit/llvm2ice_tests/vector-cast.ll
index c552bd5..363ab98 100644
--- a/tests_lit/llvm2ice_tests/vector-cast.ll
+++ b/tests_lit/llvm2ice_tests/vector-cast.ll
@@ -1,12 +1,18 @@
; This file tests casting / conversion operations that apply to vector types.
; bitcast operations are in vector-bitcast.ll.
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s
+; TODO(jvoung): fix extra "CALLTARGETS" run. The llvm-objdump symbolizer
+; doesn't know how to symbolize non-section-local functions.
+; The newer LLVM 3.6 one does work, but watch out for other bugs.
+
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | FileCheck --check-prefix=CALLTARGETS %s
+; RUN: %llvm2ice -O2 --verbose none %s \
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice -Om1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
@@ -141,7 +147,9 @@
ret <4 x i32> %res
; CHECK-LABEL: test_fptoui_v4f32_to_v4i32:
-; CHECK: call Sz_fptoui_v4f32
+; CHECK: call -4
+; CALLTARGETS-LABEL: test_fptoui_v4f32_to_v4i32
+; CALLTARGETS: call Sz_fptoui_v4f32
}
; [su]itofp operations
@@ -161,7 +169,9 @@
ret <4 x float> %res
; CHECK-LABEL: test_uitofp_v4i32_to_v4f32:
-; CHECK: call Sz_uitofp_v4i32
+; CHECK: call -4
+; CALLTARGETS-LABEL: test_uitofp_v4i32_to_v4f32
+; CALLTARGETS: call Sz_uitofp_v4i32
}
; ERRORS-NOT: ICE translation error
diff --git a/tests_lit/llvm2ice_tests/vector-fcmp.ll b/tests_lit/llvm2ice_tests/vector-fcmp.ll
index 270fb37..15ad180 100644
--- a/tests_lit/llvm2ice_tests/vector-fcmp.ll
+++ b/tests_lit/llvm2ice_tests/vector-fcmp.ll
@@ -1,12 +1,12 @@
; This file checks support for comparing vector values with the fcmp
; instruction.
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice -Om1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
diff --git a/tests_lit/llvm2ice_tests/vector-icmp.ll b/tests_lit/llvm2ice_tests/vector-icmp.ll
index bff8fc3..96bb0e7 100644
--- a/tests_lit/llvm2ice_tests/vector-icmp.ll
+++ b/tests_lit/llvm2ice_tests/vector-icmp.ll
@@ -1,12 +1,12 @@
; This file checks support for comparing vector values with the icmp
; instruction.
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice -Om1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
diff --git a/tests_lit/llvm2ice_tests/vector-ops.ll b/tests_lit/llvm2ice_tests/vector-ops.ll
index 48cf2cf..1866e62 100644
--- a/tests_lit/llvm2ice_tests/vector-ops.ll
+++ b/tests_lit/llvm2ice_tests/vector-ops.ll
@@ -1,19 +1,19 @@
; This checks support for insertelement and extractelement.
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -O2 -mattr=sse4.1 --verbose none %s \
-; RUN: | FileCheck %s --check-prefix=SSE41
-; RUN: %llvm2ice -Om1 -mattr=sse4.1 --verbose none %s \
-; RUN: | FileCheck %s --check-prefix=SSE41
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice -Om1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice -O2 -mattr=sse4.1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: | FileCheck --check-prefix=SSE41 %s
; RUN: %llvm2ice -Om1 -mattr=sse4.1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: | FileCheck --check-prefix=SSE41 %s
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
diff --git a/tests_lit/llvm2ice_tests/vector-select.ll b/tests_lit/llvm2ice_tests/vector-select.ll
index 4bcbbfb..da7270b 100644
--- a/tests_lit/llvm2ice_tests/vector-select.ll
+++ b/tests_lit/llvm2ice_tests/vector-select.ll
@@ -1,19 +1,19 @@
; This file tests support for the select instruction with vector valued inputs.
-; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s
-; RUN: %llvm2ice -O2 -mattr=sse4.1 --verbose none %s \
-; RUN: | FileCheck %s --check-prefix=SSE41
-; RUN: %llvm2ice -Om1 -mattr=sse4.1 --verbose none %s \
-; RUN: | FileCheck %s --check-prefix=SSE41
; RUN: %llvm2ice -O2 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice -Om1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
; RUN: %llvm2ice -O2 -mattr=sse4.1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: | FileCheck --check-prefix=SSE41 %s
; RUN: %llvm2ice -Om1 -mattr=sse4.1 --verbose none %s \
-; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj
+; RUN: | llvm-mc -triple=i686-none-nacl -x86-asm-syntax=intel -filetype=obj \
+; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: | FileCheck --check-prefix=SSE41 %s
; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
