Subzero: Use a "known" version of clang-format.
There are two problems with "make format" and "make format-diff" in
Makefile.standalone:
1. You have to make sure clang-format and clang-format-diff.py are
available in $PATH.
2. Different users may have different versions installed (even for the
same user on different machines), leading to whitespace wars. Can't we
all just get along?
Since the normal LLVM build that Subzero depends on also exposes and
builds clang-format and friends, we might as well use it. The
clang-format binary is found in $LLVM_BIN_PATH, and clang-format-diff.py
is found relative to $LLVM_SRC_PATH. As long as the user's LLVM build
is fairly up to date, whitespace wars are unlikely.
Given this, there's a much higher incentive to use "make format"
regularly instead of "make format-diff". In particular, inline comments
on variable/field declaration lists can get lined up more nicely by
looking at the entire context, rather than the small diff window.
BUG= none
R=jvoung@chromium.org
Review URL: https://codereview.chromium.org/877003003
diff --git a/src/IceCfg.h b/src/IceCfg.h
index 5f827f5..71f0a0d 100644
--- a/src/IceCfg.h
+++ b/src/IceCfg.h
@@ -95,9 +95,7 @@
const IceString &getIdentifierName(IdentifierIndexType Index) const {
return IdentifierNames[Index];
}
- enum {
- IdentifierIndexInvalid = -1
- };
+ enum { IdentifierIndexInvalid = -1 };
// Manage instruction numbering.
InstNumberT newInstNumber() { return NextInstNumber++; }
@@ -201,7 +199,7 @@
std::vector<IceString> IdentifierNames;
InstNumberT NextInstNumber;
VarList Variables;
- VarList Args; // subset of Variables, in argument order
+ VarList Args; // subset of Variables, in argument order
VarList ImplicitArgs; // subset of Variables
std::unique_ptr<ArenaAllocator<>> Allocator;
std::unique_ptr<Liveness> Live;
diff --git a/src/IceCfgNode.cpp b/src/IceCfgNode.cpp
index 7f96454..8fb06b8 100644
--- a/src/IceCfgNode.cpp
+++ b/src/IceCfgNode.cpp
@@ -820,8 +820,7 @@
for (SizeT J = 0; J < NumVars; ++J) {
const Variable *Var = Src->getVar(J);
if (Var->hasReg()) {
- if (Instr->isLastUse(Var) &&
- --LiveRegCount[Var->getRegNum()] == 0) {
+ if (Instr->isLastUse(Var) && --LiveRegCount[Var->getRegNum()] == 0) {
if (First)
Str << " \t# END=";
else
@@ -943,8 +942,9 @@
Variable *Var = Liveness->getVariable(i, this);
Str << " %" << Var->getName(Func);
if (Func->isVerbose(IceV_RegOrigins) && Var->hasReg()) {
- Str << ":" << Func->getTarget()->getRegName(Var->getRegNum(),
- Var->getType());
+ Str << ":"
+ << Func->getTarget()->getRegName(Var->getRegNum(),
+ Var->getType());
}
}
}
@@ -968,8 +968,9 @@
Variable *Var = Liveness->getVariable(i, this);
Str << " %" << Var->getName(Func);
if (Func->isVerbose(IceV_RegOrigins) && Var->hasReg()) {
- Str << ":" << Func->getTarget()->getRegName(Var->getRegNum(),
- Var->getType());
+ Str << ":"
+ << Func->getTarget()->getRegName(Var->getRegNum(),
+ Var->getType());
}
}
}
diff --git a/src/IceCfgNode.h b/src/IceCfgNode.h
index c5b9ac5..e3c3ee7 100644
--- a/src/IceCfgNode.h
+++ b/src/IceCfgNode.h
@@ -91,15 +91,15 @@
private:
CfgNode(Cfg *Func, SizeT LabelIndex);
Cfg *const Func;
- const SizeT Number; // label index
+ const SizeT Number; // label index
Cfg::IdentifierIndexType NameIndex; // index into Cfg::NodeNames table
- bool HasReturn; // does this block need an epilog?
+ bool HasReturn; // does this block need an epilog?
bool NeedsPlacement;
InstNumberT InstCountEstimate; // rough instruction count estimate
- NodeList InEdges; // in no particular order
- NodeList OutEdges; // in no particular order
- PhiList Phis; // unordered set of phi instructions
- InstList Insts; // ordered list of non-phi instructions
+ NodeList InEdges; // in no particular order
+ NodeList OutEdges; // in no particular order
+ PhiList Phis; // unordered set of phi instructions
+ InstList Insts; // ordered list of non-phi instructions
};
} // end of namespace Ice
diff --git a/src/IceConverter.cpp b/src/IceConverter.cpp
index 0bbcfb7..0be0f28 100644
--- a/src/IceConverter.cpp
+++ b/src/IceConverter.cpp
@@ -690,7 +690,7 @@
const GlobalVariable *GV = I;
Ice::GlobalDeclaration *Var = getConverter().getGlobalDeclaration(GV);
- Ice::VariableDeclaration* VarDecl = cast<Ice::VariableDeclaration>(Var);
+ Ice::VariableDeclaration *VarDecl = cast<Ice::VariableDeclaration>(Var);
VariableDeclarations.push_back(VarDecl);
if (!GV->hasInternalLinkage() && GV->hasInitializer()) {
diff --git a/src/IceDefs.h b/src/IceDefs.h
index 051edbb..55e09ac 100644
--- a/src/IceDefs.h
+++ b/src/IceDefs.h
@@ -126,9 +126,7 @@
// Use alignas(MaxCacheLineSize) to isolate variables/fields that
// might be contended while multithreading. Assumes the maximum cache
// line size is 64.
-enum {
- MaxCacheLineSize = 64
-};
+enum { MaxCacheLineSize = 64 };
// Use ICE_CACHELINE_BOUNDARY to force the next field in a declaration
// list to be aligned to the next cache line.
#define ICE_CACHELINE_BOUNDARY \
@@ -179,12 +177,7 @@
typedef std::mutex GlobalLockType;
-enum ErrorCodes {
- EC_None = 0,
- EC_Args,
- EC_Bitcode,
- EC_Translation
-};
+enum ErrorCodes { EC_None = 0, EC_Args, EC_Bitcode, EC_Translation };
// Wrapper around std::error_code for allowing multiple errors to be
// folded into one. The current implementation keeps track of the
diff --git a/src/IceELFObjectWriter.cpp b/src/IceELFObjectWriter.cpp
index f1b698b..c4ff4f0 100644
--- a/src/IceELFObjectWriter.cpp
+++ b/src/IceELFObjectWriter.cpp
@@ -34,7 +34,7 @@
#define X(tag, str, is_elf64, e_machine, e_flags) \
{ is_elf64, e_machine, e_flags } \
,
- TARGETARCH_TABLE
+ TARGETARCH_TABLE
#undef X
};
diff --git a/src/IceGlobalContext.h b/src/IceGlobalContext.h
index dfa665b..ac321e6 100644
--- a/src/IceGlobalContext.h
+++ b/src/IceGlobalContext.h
@@ -209,11 +209,7 @@
}
// These are predefined TimerStackIdT values.
- enum TimerStackKind {
- TSK_Default = 0,
- TSK_Funcs,
- TSK_Num
- };
+ enum TimerStackKind { TSK_Default = 0, TSK_Funcs, TSK_Num };
TimerStackIdT newTimerStackID(const IceString &Name);
TimerIdT getTimerID(TimerStackIdT StackID, const IceString &Name);
diff --git a/src/IceGlobalInits.cpp b/src/IceGlobalInits.cpp
index 4f209f8..c9bdf99 100644
--- a/src/IceGlobalInits.cpp
+++ b/src/IceGlobalInits.cpp
@@ -123,8 +123,9 @@
void VariableDeclaration::dump(GlobalContext *Ctx, Ostream &Stream) const {
if (!ALLOW_DUMP)
return;
- Stream << "@" << ((Ctx && !getSuppressMangling())
- ? Ctx->mangleName(Name) : Name) << " = ";
+ Stream << "@"
+ << ((Ctx && !getSuppressMangling()) ? Ctx->mangleName(Name) : Name)
+ << " = ";
::dumpLinkage(Stream, Linkage);
Stream << " " << (IsConstant ? "constant" : "global") << " ";
@@ -158,8 +159,8 @@
Stream << "[" << getNumBytes() << " x " << Ice::IceType_i8 << "]";
}
-void VariableDeclaration::DataInitializer::dump(
- GlobalContext *, Ostream &Stream) const {
+void VariableDeclaration::DataInitializer::dump(GlobalContext *,
+ Ostream &Stream) const {
if (!ALLOW_DUMP)
return;
dumpType(Stream);
@@ -176,8 +177,8 @@
Stream << "\"";
}
-void VariableDeclaration::ZeroInitializer::dump(
- GlobalContext *, Ostream &Stream) const {
+void VariableDeclaration::ZeroInitializer::dump(GlobalContext *,
+ Ostream &Stream) const {
if (!ALLOW_DUMP)
return;
dumpType(Stream);
@@ -190,8 +191,8 @@
Stream << Ice::IceType_i32;
}
-void VariableDeclaration::RelocInitializer::dump(
- GlobalContext *Ctx, Ostream &Stream) const {
+void VariableDeclaration::RelocInitializer::dump(GlobalContext *Ctx,
+ Ostream &Stream) const {
if (!ALLOW_DUMP)
return;
if (Offset != 0) {
diff --git a/src/IceGlobalInits.h b/src/IceGlobalInits.h
index 0d560a1..3478a98 100644
--- a/src/IceGlobalInits.h
+++ b/src/IceGlobalInits.h
@@ -107,9 +107,7 @@
}
void dumpType(Ostream &Stream) const final;
void dump(GlobalContext *Ctx, Ostream &Stream) const final;
- bool getSuppressMangling() const final {
- return isExternal() && IsProto;
- }
+ bool getSuppressMangling() const final { return isExternal() && IsProto; }
private:
const Ice::FuncSigType Signature;
@@ -127,6 +125,7 @@
class VariableDeclaration : public GlobalDeclaration {
VariableDeclaration(const VariableDeclaration &) = delete;
VariableDeclaration &operator=(const VariableDeclaration &) = delete;
+
public:
/// Base class for a global variable initializer.
class Initializer {
diff --git a/src/IceInst.cpp b/src/IceInst.cpp
index 86886a6..3327455 100644
--- a/src/IceInst.cpp
+++ b/src/IceInst.cpp
@@ -30,9 +30,9 @@
#define X(tag, str, commutative) \
{ str, commutative } \
,
- ICEINSTARITHMETIC_TABLE
+ ICEINSTARITHMETIC_TABLE
#undef X
- };
+};
// Using non-anonymous struct so that array_lengthof works.
const struct InstCastAttributes_ {
@@ -41,9 +41,9 @@
#define X(tag, str) \
{ str } \
,
- ICEINSTCAST_TABLE
+ ICEINSTCAST_TABLE
#undef X
- };
+};
// Using non-anonymous struct so that array_lengthof works.
const struct InstFcmpAttributes_ {
@@ -52,9 +52,9 @@
#define X(tag, str) \
{ str } \
,
- ICEINSTFCMP_TABLE
+ ICEINSTFCMP_TABLE
#undef X
- };
+};
// Using non-anonymous struct so that array_lengthof works.
const struct InstIcmpAttributes_ {
@@ -63,9 +63,9 @@
#define X(tag, str) \
{ str } \
,
- ICEINSTICMP_TABLE
+ ICEINSTICMP_TABLE
#undef X
- };
+};
} // end of anonymous namespace
diff --git a/src/IceInstX8632.cpp b/src/IceInstX8632.cpp
index 9bb136d..30edb9e 100644
--- a/src/IceInstX8632.cpp
+++ b/src/IceInstX8632.cpp
@@ -34,9 +34,9 @@
#define X(tag, encode, opp, dump, emit) \
{ CondX86::opp, dump, emit } \
,
- ICEINSTX8632BR_TABLE
+ ICEINSTX8632BR_TABLE
#undef X
- };
+};
const struct InstX8632CmppsAttributes_ {
const char *EmitString;
@@ -44,9 +44,9 @@
#define X(tag, emit) \
{ emit } \
,
- ICEINSTX8632CMPPS_TABLE
+ ICEINSTX8632CMPPS_TABLE
#undef X
- };
+};
const struct TypeX8632Attributes_ {
const char *CvtString; // i (integer), s (single FP), d (double FP)
@@ -58,9 +58,9 @@
#define X(tag, elementty, cvt, sdss, pack, width, fld) \
{ cvt, sdss, pack, width, fld } \
,
- ICETYPEX8632_TABLE
+ ICETYPEX8632_TABLE
#undef X
- };
+};
const char *InstX8632SegmentRegNames[] = {
#define X(val, name, prefix) name,
@@ -900,7 +900,8 @@
// Inplace GPR ops
template <>
const x86::AssemblerX86::GPREmitterOneOp InstX8632Bswap::Emitter = {
- &x86::AssemblerX86::bswap, nullptr /* only a reg form exists */};
+ &x86::AssemblerX86::bswap, nullptr /* only a reg form exists */
+};
template <>
const x86::AssemblerX86::GPREmitterOneOp InstX8632Neg::Emitter = {
&x86::AssemblerX86::neg, &x86::AssemblerX86::neg};
@@ -926,8 +927,7 @@
// Unary XMM ops
template <>
const x86::AssemblerX86::XmmEmitterRegOp InstX8632Sqrtss::Emitter = {
- &x86::AssemblerX86::sqrtss, &x86::AssemblerX86::sqrtss
-};
+ &x86::AssemblerX86::sqrtss, &x86::AssemblerX86::sqrtss};
// Binary GPR ops
template <>
@@ -969,76 +969,58 @@
// Binary XMM ops
template <>
const x86::AssemblerX86::XmmEmitterRegOp InstX8632Addss::Emitter = {
- &x86::AssemblerX86::addss, &x86::AssemblerX86::addss
-};
+ &x86::AssemblerX86::addss, &x86::AssemblerX86::addss};
template <>
const x86::AssemblerX86::XmmEmitterRegOp InstX8632Addps::Emitter = {
- &x86::AssemblerX86::addps, &x86::AssemblerX86::addps
-};
+ &x86::AssemblerX86::addps, &x86::AssemblerX86::addps};
template <>
const x86::AssemblerX86::XmmEmitterRegOp InstX8632Divss::Emitter = {
- &x86::AssemblerX86::divss, &x86::AssemblerX86::divss
-};
+ &x86::AssemblerX86::divss, &x86::AssemblerX86::divss};
template <>
const x86::AssemblerX86::XmmEmitterRegOp InstX8632Divps::Emitter = {
- &x86::AssemblerX86::divps, &x86::AssemblerX86::divps
-};
+ &x86::AssemblerX86::divps, &x86::AssemblerX86::divps};
template <>
const x86::AssemblerX86::XmmEmitterRegOp InstX8632Mulss::Emitter = {
- &x86::AssemblerX86::mulss, &x86::AssemblerX86::mulss
-};
+ &x86::AssemblerX86::mulss, &x86::AssemblerX86::mulss};
template <>
const x86::AssemblerX86::XmmEmitterRegOp InstX8632Mulps::Emitter = {
- &x86::AssemblerX86::mulps, &x86::AssemblerX86::mulps
-};
+ &x86::AssemblerX86::mulps, &x86::AssemblerX86::mulps};
template <>
const x86::AssemblerX86::XmmEmitterRegOp InstX8632Padd::Emitter = {
- &x86::AssemblerX86::padd, &x86::AssemblerX86::padd
-};
+ &x86::AssemblerX86::padd, &x86::AssemblerX86::padd};
template <>
const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pand::Emitter = {
- &x86::AssemblerX86::pand, &x86::AssemblerX86::pand
-};
+ &x86::AssemblerX86::pand, &x86::AssemblerX86::pand};
template <>
const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pandn::Emitter = {
- &x86::AssemblerX86::pandn, &x86::AssemblerX86::pandn
-};
+ &x86::AssemblerX86::pandn, &x86::AssemblerX86::pandn};
template <>
const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pcmpeq::Emitter = {
- &x86::AssemblerX86::pcmpeq, &x86::AssemblerX86::pcmpeq
-};
+ &x86::AssemblerX86::pcmpeq, &x86::AssemblerX86::pcmpeq};
template <>
const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pcmpgt::Emitter = {
- &x86::AssemblerX86::pcmpgt, &x86::AssemblerX86::pcmpgt
-};
+ &x86::AssemblerX86::pcmpgt, &x86::AssemblerX86::pcmpgt};
template <>
const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pmull::Emitter = {
- &x86::AssemblerX86::pmull, &x86::AssemblerX86::pmull
-};
+ &x86::AssemblerX86::pmull, &x86::AssemblerX86::pmull};
template <>
const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pmuludq::Emitter = {
- &x86::AssemblerX86::pmuludq, &x86::AssemblerX86::pmuludq
-};
+ &x86::AssemblerX86::pmuludq, &x86::AssemblerX86::pmuludq};
template <>
const x86::AssemblerX86::XmmEmitterRegOp InstX8632Por::Emitter = {
- &x86::AssemblerX86::por, &x86::AssemblerX86::por
-};
+ &x86::AssemblerX86::por, &x86::AssemblerX86::por};
template <>
const x86::AssemblerX86::XmmEmitterRegOp InstX8632Psub::Emitter = {
- &x86::AssemblerX86::psub, &x86::AssemblerX86::psub
-};
+ &x86::AssemblerX86::psub, &x86::AssemblerX86::psub};
template <>
const x86::AssemblerX86::XmmEmitterRegOp InstX8632Pxor::Emitter = {
- &x86::AssemblerX86::pxor, &x86::AssemblerX86::pxor
-};
+ &x86::AssemblerX86::pxor, &x86::AssemblerX86::pxor};
template <>
const x86::AssemblerX86::XmmEmitterRegOp InstX8632Subss::Emitter = {
- &x86::AssemblerX86::subss, &x86::AssemblerX86::subss
-};
+ &x86::AssemblerX86::subss, &x86::AssemblerX86::subss};
template <>
const x86::AssemblerX86::XmmEmitterRegOp InstX8632Subps::Emitter = {
- &x86::AssemblerX86::subps, &x86::AssemblerX86::subps
-};
+ &x86::AssemblerX86::subps, &x86::AssemblerX86::subps};
// Binary XMM Shift ops
template <>
@@ -1756,11 +1738,10 @@
const Operand *Src1 = getSrc(1);
Type Ty = Src0->getType();
static const x86::AssemblerX86::GPREmitterRegOp RegEmitter = {
- &x86::AssemblerX86::cmp, &x86::AssemblerX86::cmp, &x86::AssemblerX86::cmp
- };
+ &x86::AssemblerX86::cmp, &x86::AssemblerX86::cmp,
+ &x86::AssemblerX86::cmp};
static const x86::AssemblerX86::GPREmitterAddrOp AddrEmitter = {
- &x86::AssemblerX86::cmp, &x86::AssemblerX86::cmp
- };
+ &x86::AssemblerX86::cmp, &x86::AssemblerX86::cmp};
if (const auto SrcVar0 = llvm::dyn_cast<Variable>(Src0)) {
if (SrcVar0->hasReg()) {
emitIASRegOpTyGPR(Func, Ty, SrcVar0, Src1, RegEmitter);
@@ -1798,8 +1779,7 @@
const auto Src0Var = llvm::cast<Variable>(getSrc(0));
Type Ty = Src0Var->getType();
const static x86::AssemblerX86::XmmEmitterRegOp Emitter = {
- &x86::AssemblerX86::ucomiss, &x86::AssemblerX86::ucomiss
- };
+ &x86::AssemblerX86::ucomiss, &x86::AssemblerX86::ucomiss};
emitIASRegOpTyXMM(Func, Ty, Src0Var, getSrc(1), Emitter);
}
@@ -1851,8 +1831,7 @@
static const x86::AssemblerX86::GPREmitterRegOp RegEmitter = {
&x86::AssemblerX86::test, nullptr, &x86::AssemblerX86::test};
static const x86::AssemblerX86::GPREmitterAddrOp AddrEmitter = {
- &x86::AssemblerX86::test, &x86::AssemblerX86::test
- };
+ &x86::AssemblerX86::test, &x86::AssemblerX86::test};
if (const auto SrcVar0 = llvm::dyn_cast<Variable>(Src0)) {
if (SrcVar0->hasReg()) {
emitIASRegOpTyGPR(Func, Ty, SrcVar0, Src1, RegEmitter);
@@ -2181,9 +2160,8 @@
const Variable *Dest = getDest();
const Operand *Src = getSrc(0);
const static x86::AssemblerX86::XmmEmitterMovOps Emitter = {
- &x86::AssemblerX86::movups, &x86::AssemblerX86::movups,
- &x86::AssemblerX86::movups
- };
+ &x86::AssemblerX86::movups, &x86::AssemblerX86::movups,
+ &x86::AssemblerX86::movups};
emitIASMovlikeXMM(Func, Dest, Src, Emitter);
}
@@ -2207,8 +2185,8 @@
const Variable *Dest = getDest();
const Operand *Src = getSrc(0);
const static x86::AssemblerX86::XmmEmitterMovOps Emitter = {
- &x86::AssemblerX86::movq, &x86::AssemblerX86::movq, &x86::AssemblerX86::movq
- };
+ &x86::AssemblerX86::movq, &x86::AssemblerX86::movq,
+ &x86::AssemblerX86::movq};
emitIASMovlikeXMM(Func, Dest, Src, Emitter);
}
@@ -2432,10 +2410,10 @@
// pextrb and pextrd are SSE4.1 instructions.
assert(getSrc(0)->getType() == IceType_v8i16 ||
getSrc(0)->getType() == IceType_v8i1 ||
- static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet()
- >= TargetX8632::SSE4_1);
- Str << "\t" << Opcode
- << TypeX8632Attributes[getSrc(0)->getType()].PackString << "\t";
+ static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet() >=
+ TargetX8632::SSE4_1);
+ Str << "\t" << Opcode << TypeX8632Attributes[getSrc(0)->getType()].PackString
+ << "\t";
getSrc(1)->emit(Func);
Str << ", ";
getSrc(0)->emit(Func);
@@ -2478,10 +2456,10 @@
// pinsrb and pinsrd are SSE4.1 instructions.
assert(getDest()->getType() == IceType_v8i16 ||
getDest()->getType() == IceType_v8i1 ||
- static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet()
- >= TargetX8632::SSE4_1);
- Str << "\t" << Opcode
- << TypeX8632Attributes[getDest()->getType()].PackString << "\t";
+ static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet() >=
+ TargetX8632::SSE4_1);
+ Str << "\t" << Opcode << TypeX8632Attributes[getDest()->getType()].PackString
+ << "\t";
getSrc(2)->emit(Func);
Str << ", ";
Operand *Src1 = getSrc(1);
diff --git a/src/IceInstX8632.h b/src/IceInstX8632.h
index e63e628..7725ad7 100644
--- a/src/IceInstX8632.h
+++ b/src/IceInstX8632.h
@@ -34,11 +34,7 @@
OperandX8632 &operator=(const OperandX8632 &) = delete;
public:
- enum OperandKindX8632 {
- k__Start = Operand::kTarget,
- kMem,
- kSplit
- };
+ enum OperandKindX8632 { k__Start = Operand::kTarget, kMem, kSplit };
using Operand::dump;
void dump(const Cfg *, Ostream &Str) const override {
if (ALLOW_DUMP)
@@ -110,10 +106,7 @@
VariableSplit &operator=(const VariableSplit &) = delete;
public:
- enum Portion {
- Low,
- High
- };
+ enum Portion { Low, High };
static VariableSplit *create(Cfg *Func, Variable *Var, Portion Part) {
return new (Func->allocate<VariableSplit>()) VariableSplit(Func, Var, Part);
}
@@ -1464,8 +1457,7 @@
public:
static InstX8632Push *create(Cfg *Func, Variable *Source) {
- return new (Func->allocate<InstX8632Push>())
- InstX8632Push(Func, Source);
+ return new (Func->allocate<InstX8632Push>()) InstX8632Push(Func, Source);
}
void emit(const Cfg *Func) const override;
void emitIAS(const Cfg *Func) const override;
diff --git a/src/IceIntrinsics.cpp b/src/IceIntrinsics.cpp
index 16d07e1..29b8ad2 100644
--- a/src/IceIntrinsics.cpp
+++ b/src/IceIntrinsics.cpp
@@ -28,7 +28,8 @@
namespace {
-#define INTRIN(ID, SE, RT) { Intrinsics::ID, Intrinsics::SE, Intrinsics::RT }
+#define INTRIN(ID, SE, RT) \
+ { Intrinsics::ID, Intrinsics::SE, Intrinsics::RT }
// Build list of intrinsics with their attributes and expected prototypes.
// List is sorted alphabetically.
@@ -40,163 +41,169 @@
#define AtomicCmpxchgInit(Overload, NameSuffix) \
{ \
{ \
- INTRIN(AtomicCmpxchg, SideEffects_T, ReturnsTwice_F), \
- { Overload, IceType_i32, Overload, Overload, IceType_i32, IceType_i32 }, \
- 6 }, \
- "nacl.atomic.cmpxchg." NameSuffix \
+ INTRIN(AtomicCmpxchg, SideEffects_T, ReturnsTwice_F), {Overload, \
+ IceType_i32, \
+ Overload, \
+ Overload, \
+ IceType_i32, \
+ IceType_i32}, \
+ 6 \
+ } \
+ , "nacl.atomic.cmpxchg." NameSuffix \
}
- AtomicCmpxchgInit(IceType_i8, "i8"),
- AtomicCmpxchgInit(IceType_i16, "i16"),
- AtomicCmpxchgInit(IceType_i32, "i32"),
- AtomicCmpxchgInit(IceType_i64, "i64"),
+ AtomicCmpxchgInit(IceType_i8, "i8"),
+ AtomicCmpxchgInit(IceType_i16, "i16"),
+ AtomicCmpxchgInit(IceType_i32, "i32"),
+ AtomicCmpxchgInit(IceType_i64, "i64"),
#undef AtomicCmpxchgInit
- { { INTRIN(AtomicFence, SideEffects_T, ReturnsTwice_F),
- { IceType_void, IceType_i32 }, 2 },
- "nacl.atomic.fence" },
- { { INTRIN(AtomicFenceAll, SideEffects_T, ReturnsTwice_F),
- { IceType_void }, 1 },
- "nacl.atomic.fence.all" },
- { { INTRIN(AtomicIsLockFree, SideEffects_F, ReturnsTwice_F),
- { IceType_i1, IceType_i32, IceType_i32 }, 3 },
- "nacl.atomic.is.lock.free" },
+ {{INTRIN(AtomicFence, SideEffects_T, ReturnsTwice_F),
+ {IceType_void, IceType_i32},
+ 2},
+ "nacl.atomic.fence"},
+ {{INTRIN(AtomicFenceAll, SideEffects_T, ReturnsTwice_F),
+ {IceType_void},
+ 1},
+ "nacl.atomic.fence.all"},
+ {{INTRIN(AtomicIsLockFree, SideEffects_F, ReturnsTwice_F),
+ {IceType_i1, IceType_i32, IceType_i32},
+ 3},
+ "nacl.atomic.is.lock.free"},
#define AtomicLoadInit(Overload, NameSuffix) \
{ \
{ \
INTRIN(AtomicLoad, SideEffects_T, ReturnsTwice_F), \
- { Overload, IceType_i32, IceType_i32 }, 3 }, \
- "nacl.atomic.load." NameSuffix \
+ {Overload, IceType_i32, IceType_i32}, 3 \
+ } \
+ , "nacl.atomic.load." NameSuffix \
}
- AtomicLoadInit(IceType_i8, "i8"),
- AtomicLoadInit(IceType_i16, "i16"),
- AtomicLoadInit(IceType_i32, "i32"),
- AtomicLoadInit(IceType_i64, "i64"),
+ AtomicLoadInit(IceType_i8, "i8"),
+ AtomicLoadInit(IceType_i16, "i16"),
+ AtomicLoadInit(IceType_i32, "i32"),
+ AtomicLoadInit(IceType_i64, "i64"),
#undef AtomicLoadInit
#define AtomicRMWInit(Overload, NameSuffix) \
{ \
{ \
INTRIN(AtomicRMW, SideEffects_T, ReturnsTwice_F) \
- , { Overload, IceType_i32, IceType_i32, Overload, IceType_i32 }, 5 \
+ , {Overload, IceType_i32, IceType_i32, Overload, IceType_i32}, 5 \
} \
, "nacl.atomic.rmw." NameSuffix \
}
- AtomicRMWInit(IceType_i8, "i8"),
- AtomicRMWInit(IceType_i16, "i16"),
- AtomicRMWInit(IceType_i32, "i32"),
- AtomicRMWInit(IceType_i64, "i64"),
+ AtomicRMWInit(IceType_i8, "i8"),
+ AtomicRMWInit(IceType_i16, "i16"),
+ AtomicRMWInit(IceType_i32, "i32"),
+ AtomicRMWInit(IceType_i64, "i64"),
#undef AtomicRMWInit
#define AtomicStoreInit(Overload, NameSuffix) \
{ \
{ \
INTRIN(AtomicStore, SideEffects_T, ReturnsTwice_F) \
- , { IceType_void, Overload, IceType_i32, IceType_i32 }, 4 \
+ , {IceType_void, Overload, IceType_i32, IceType_i32}, 4 \
} \
, "nacl.atomic.store." NameSuffix \
}
- AtomicStoreInit(IceType_i8, "i8"),
- AtomicStoreInit(IceType_i16, "i16"),
- AtomicStoreInit(IceType_i32, "i32"),
- AtomicStoreInit(IceType_i64, "i64"),
+ AtomicStoreInit(IceType_i8, "i8"),
+ AtomicStoreInit(IceType_i16, "i16"),
+ AtomicStoreInit(IceType_i32, "i32"),
+ AtomicStoreInit(IceType_i64, "i64"),
#undef AtomicStoreInit
#define BswapInit(Overload, NameSuffix) \
{ \
{ \
INTRIN(Bswap, SideEffects_F, ReturnsTwice_F) \
- , { Overload, Overload }, 2 \
+ , {Overload, Overload}, 2 \
} \
, "bswap." NameSuffix \
}
- BswapInit(IceType_i16, "i16"),
- BswapInit(IceType_i32, "i32"),
- BswapInit(IceType_i64, "i64"),
+ BswapInit(IceType_i16, "i16"),
+ BswapInit(IceType_i32, "i32"),
+ BswapInit(IceType_i64, "i64"),
#undef BswapInit
#define CtlzInit(Overload, NameSuffix) \
{ \
{ \
INTRIN(Ctlz, SideEffects_F, ReturnsTwice_F) \
- , { Overload, Overload, IceType_i1 }, 3 \
+ , {Overload, Overload, IceType_i1}, 3 \
} \
, "ctlz." NameSuffix \
}
- CtlzInit(IceType_i32, "i32"),
- CtlzInit(IceType_i64, "i64"),
+ CtlzInit(IceType_i32, "i32"),
+ CtlzInit(IceType_i64, "i64"),
#undef CtlzInit
#define CtpopInit(Overload, NameSuffix) \
{ \
{ \
INTRIN(Ctpop, SideEffects_F, ReturnsTwice_F) \
- , { Overload, Overload }, 2 \
+ , {Overload, Overload}, 2 \
} \
, "ctpop." NameSuffix \
}
- CtpopInit(IceType_i32, "i32"),
- CtpopInit(IceType_i64, "i64"),
+ CtpopInit(IceType_i32, "i32"),
+ CtpopInit(IceType_i64, "i64"),
#undef CtpopInit
#define CttzInit(Overload, NameSuffix) \
{ \
{ \
INTRIN(Cttz, SideEffects_F, ReturnsTwice_F) \
- , { Overload, Overload, IceType_i1 }, 3 \
+ , {Overload, Overload, IceType_i1}, 3 \
} \
, "cttz." NameSuffix \
}
- CttzInit(IceType_i32, "i32"),
- CttzInit(IceType_i64, "i64"),
+ CttzInit(IceType_i32, "i32"),
+ CttzInit(IceType_i64, "i64"),
#undef CttzInit
- { { INTRIN(Longjmp, SideEffects_T, ReturnsTwice_F),
- { IceType_void, IceType_i32, IceType_i32 }, 3 },
- "nacl.longjmp" },
- { { INTRIN(Memcpy, SideEffects_T, ReturnsTwice_F),
- { IceType_void, IceType_i32, IceType_i32, IceType_i32, IceType_i32,
- IceType_i1},
- 6 },
- "memcpy.p0i8.p0i8.i32" },
- { { INTRIN(Memmove, SideEffects_T, ReturnsTwice_F),
- { IceType_void, IceType_i32, IceType_i32, IceType_i32, IceType_i32,
- IceType_i1 },
- 6 },
- "memmove.p0i8.p0i8.i32" },
- { { INTRIN(Memset, SideEffects_T, ReturnsTwice_F),
- { IceType_void, IceType_i32, IceType_i8, IceType_i32, IceType_i32,
- IceType_i1 },
- 6 },
- "memset.p0i8.i32" },
- { { INTRIN(NaClReadTP, SideEffects_F, ReturnsTwice_F),
- { IceType_i32 }, 1 },
- "nacl.read.tp" },
- { { INTRIN(Setjmp, SideEffects_T, ReturnsTwice_T),
- { IceType_i32, IceType_i32 }, 2 },
- "nacl.setjmp" },
+ {{INTRIN(Longjmp, SideEffects_T, ReturnsTwice_F),
+ {IceType_void, IceType_i32, IceType_i32},
+ 3},
+ "nacl.longjmp"},
+ {{INTRIN(Memcpy, SideEffects_T, ReturnsTwice_F),
+ {IceType_void, IceType_i32, IceType_i32, IceType_i32, IceType_i32,
+ IceType_i1},
+ 6},
+ "memcpy.p0i8.p0i8.i32"},
+ {{INTRIN(Memmove, SideEffects_T, ReturnsTwice_F),
+ {IceType_void, IceType_i32, IceType_i32, IceType_i32, IceType_i32,
+ IceType_i1},
+ 6},
+ "memmove.p0i8.p0i8.i32"},
+ {{INTRIN(Memset, SideEffects_T, ReturnsTwice_F),
+ {IceType_void, IceType_i32, IceType_i8, IceType_i32, IceType_i32,
+ IceType_i1},
+ 6},
+ "memset.p0i8.i32"},
+ {{INTRIN(NaClReadTP, SideEffects_F, ReturnsTwice_F), {IceType_i32}, 1},
+ "nacl.read.tp"},
+ {{INTRIN(Setjmp, SideEffects_T, ReturnsTwice_T),
+ {IceType_i32, IceType_i32},
+ 2},
+ "nacl.setjmp"},
#define SqrtInit(Overload, NameSuffix) \
{ \
- { \
- INTRIN(Sqrt, SideEffects_F, ReturnsTwice_F), \
- { Overload, Overload }, 2 }, \
- "sqrt." NameSuffix \
+ { INTRIN(Sqrt, SideEffects_F, ReturnsTwice_F), {Overload, Overload}, 2 } \
+ , "sqrt." NameSuffix \
}
- SqrtInit(IceType_f32, "f32"),
- SqrtInit(IceType_f64, "f64"),
+ SqrtInit(IceType_f32, "f32"),
+ SqrtInit(IceType_f64, "f64"),
#undef SqrtInit
- { { INTRIN(Stacksave, SideEffects_T, ReturnsTwice_F),
- { IceType_i32 }, 1 },
- "stacksave" },
- { { INTRIN(Stackrestore, SideEffects_T, ReturnsTwice_F),
- { IceType_void, IceType_i32 }, 2 },
- "stackrestore" },
- { { INTRIN(Trap, SideEffects_T, ReturnsTwice_F),
- { IceType_void }, 1 },
- "trap" }
-};
+ {{INTRIN(Stacksave, SideEffects_T, ReturnsTwice_F), {IceType_i32}, 1},
+ "stacksave"},
+ {{INTRIN(Stackrestore, SideEffects_T, ReturnsTwice_F),
+ {IceType_void, IceType_i32},
+ 2},
+ "stackrestore"},
+ {{INTRIN(Trap, SideEffects_T, ReturnsTwice_F), {IceType_void}, 1},
+ "trap"}};
const size_t IceIntrinsicsTableSize = llvm::array_lengthof(IceIntrinsicsTable);
#undef INTRIN
diff --git a/src/IceIntrinsics.h b/src/IceIntrinsics.h
index f631158..0fee205 100644
--- a/src/IceIntrinsics.h
+++ b/src/IceIntrinsics.h
@@ -93,15 +93,9 @@
static bool VerifyMemoryOrder(uint64_t Order);
- enum SideEffects {
- SideEffects_F=0,
- SideEffects_T=1
- };
+ enum SideEffects { SideEffects_F = 0, SideEffects_T = 1 };
- enum ReturnsTwice {
- ReturnsTwice_F=0,
- ReturnsTwice_T=1
- };
+ enum ReturnsTwice { ReturnsTwice_F = 0, ReturnsTwice_T = 1 };
// Basic attributes related to each intrinsic, that are relevant to
// code generation. Perhaps the attributes representation can be shared
diff --git a/src/IceOperand.cpp b/src/IceOperand.cpp
index 102fe7d..9338bdc 100644
--- a/src/IceOperand.cpp
+++ b/src/IceOperand.cpp
@@ -190,7 +190,7 @@
// be careful not to omit all uses of the variable if markDef() and
// markUse() both use this optimization.
assert(Node);
- // Verify that instructions are added in increasing order.
+// Verify that instructions are added in increasing order.
#ifndef NDEBUG
if (TrackingKind == VMK_All) {
const Inst *LastInstruction =
@@ -274,8 +274,8 @@
const CfgNode *EntryNode = Func->getEntryNode();
const bool IsFromDef = false;
const bool IsImplicit = true;
- Metadata[Var->getIndex()]
- .markUse(Kind, NoInst, EntryNode, IsFromDef, IsImplicit);
+ Metadata[Var->getIndex()].markUse(Kind, NoInst, EntryNode, IsFromDef,
+ IsImplicit);
}
for (CfgNode *Node : Func->getNodes())
@@ -409,8 +409,9 @@
} else if (Func->getTarget()->hasComputedFrame()) {
if (Func->isVerbose(IceV_RegOrigins))
Str << ":";
- Str << "[" << Func->getTarget()->getRegName(
- Func->getTarget()->getFrameOrStackReg(), IceType_i32);
+ Str << "["
+ << Func->getTarget()->getRegName(
+ Func->getTarget()->getFrameOrStackReg(), IceType_i32);
int32_t Offset = getStackOffset();
if (Offset) {
if (Offset > 0)
diff --git a/src/IceOperand.h b/src/IceOperand.h
index 3bbc0e3..5019e29 100644
--- a/src/IceOperand.h
+++ b/src/IceOperand.h
@@ -88,7 +88,7 @@
Variable **Vars;
};
-template<class StreamType>
+template <class StreamType>
inline StreamType &operator<<(StreamType &Str, const Operand &Op) {
Op.dump(Str);
return Str;
@@ -170,7 +170,8 @@
typedef ConstantPrimitive<float, Operand::kConstFloat> ConstantFloat;
typedef ConstantPrimitive<double, Operand::kConstDouble> ConstantDouble;
-template <> inline void ConstantInteger32::dump(const Cfg *, Ostream &Str) const {
+template <>
+inline void ConstantInteger32::dump(const Cfg *, Ostream &Str) const {
if (!ALLOW_DUMP)
return;
if (getType() == IceType_i1)
@@ -179,7 +180,8 @@
Str << static_cast<int32_t>(getValue());
}
-template <> inline void ConstantInteger64::dump(const Cfg *, Ostream &Str) const {
+template <>
+inline void ConstantInteger64::dump(const Cfg *, Ostream &Str) const {
if (!ALLOW_DUMP)
return;
assert(getType() == IceType_i64);
@@ -244,7 +246,7 @@
Name(Name), SuppressMangling(SuppressMangling) {}
~ConstantRelocatable() override {}
const RelocOffsetT Offset; // fixed offset to add
- const IceString Name; // optional for debug/dump
+ const IceString Name; // optional for debug/dump
bool SuppressMangling;
};
@@ -360,7 +362,7 @@
typedef std::pair<InstNumberT, InstNumberT> RangeElementType;
// RangeType is arena-allocated from the Cfg's allocator.
typedef std::vector<RangeElementType, CfgLocalAllocator<RangeElementType>>
- RangeType;
+ RangeType;
RangeType Range;
RegWeight Weight;
// TrimmedBegin is an optimization for the overlaps() computation.
@@ -540,11 +542,7 @@
MDS_MultiDefSingleBlock,
MDS_MultiDefMultiBlock
};
- enum MultiBlockState {
- MBS_Unknown,
- MBS_SingleBlock,
- MBS_MultiBlock
- };
+ enum MultiBlockState { MBS_Unknown, MBS_SingleBlock, MBS_MultiBlock };
VariableTracking()
: MultiDef(MDS_Unknown), MultiBlock(MBS_Unknown), SingleUseNode(nullptr),
SingleDefNode(nullptr), FirstOrSingleDefinition(nullptr) {}
diff --git a/src/IceRNG.cpp b/src/IceRNG.cpp
index ed3467b..03171ad 100644
--- a/src/IceRNG.cpp
+++ b/src/IceRNG.cpp
@@ -26,8 +26,8 @@
// and implementation. I expect the implementation is different and
// therefore the tests would need to be changed.
cl::opt<unsigned long long>
-RandomSeed("sz-seed", cl::desc("Seed the random number generator"),
- cl::init(time(0)));
+ RandomSeed("sz-seed", cl::desc("Seed the random number generator"),
+ cl::init(time(0)));
const unsigned MAX = 2147483647;
diff --git a/src/IceTargetLowering.cpp b/src/IceTargetLowering.cpp
index 4373c6c..27a2d60 100644
--- a/src/IceTargetLowering.cpp
+++ b/src/IceTargetLowering.cpp
@@ -43,9 +43,9 @@
cl::desc("Nop insertion probability as percentage"), cl::init(10));
cl::opt<bool>
-CLRandomizeRegisterAllocation("randomize-regalloc",
- cl::desc("Randomize register allocation"),
- cl::init(false));
+ CLRandomizeRegisterAllocation("randomize-regalloc",
+ cl::desc("Randomize register allocation"),
+ cl::init(false));
} // end of anonymous namespace
void LoweringContext::init(CfgNode *N) {
diff --git a/src/IceTargetLowering.h b/src/IceTargetLowering.h
index 49108fa..17d785e 100644
--- a/src/IceTargetLowering.h
+++ b/src/IceTargetLowering.h
@@ -164,9 +164,7 @@
// Returns true if this function calls a function that has the
// "returns twice" attribute.
bool callsReturnsTwice() const { return CallsReturnsTwice; }
- void setCallsReturnsTwice(bool RetTwice) {
- CallsReturnsTwice = RetTwice;
- }
+ void setCallsReturnsTwice(bool RetTwice) { CallsReturnsTwice = RetTwice; }
int32_t getStackAdjustment() const { return StackAdjustment; }
void updateStackAdjustment(int32_t Offset) { StackAdjustment += Offset; }
void resetStackAdjustment() { StackAdjustment = 0; }
diff --git a/src/IceTargetLoweringX8632.cpp b/src/IceTargetLoweringX8632.cpp
index 79c79cc..8c59499 100644
--- a/src/IceTargetLoweringX8632.cpp
+++ b/src/IceTargetLoweringX8632.cpp
@@ -61,9 +61,9 @@
#define X(val, dflt, swapS, C1, C2, swapV, pred) \
{ dflt, swapS, CondX86::C1, CondX86::C2, swapV, CondX86::pred } \
,
- FCMPX8632_TABLE
+ FCMPX8632_TABLE
#undef X
- };
+};
const size_t TableFcmpSize = llvm::array_lengthof(TableFcmp);
// The following table summarizes the logic for lowering the icmp instruction
@@ -76,9 +76,9 @@
#define X(val, C_32, C1_64, C2_64, C3_64) \
{ CondX86::C_32 } \
,
- ICMPX8632_TABLE
+ ICMPX8632_TABLE
#undef X
- };
+};
const size_t TableIcmp32Size = llvm::array_lengthof(TableIcmp32);
// The following table summarizes the logic for lowering the icmp instruction
@@ -91,9 +91,9 @@
#define X(val, C_32, C1_64, C2_64, C3_64) \
{ CondX86::C1_64, CondX86::C2_64, CondX86::C3_64 } \
,
- ICMPX8632_TABLE
+ ICMPX8632_TABLE
#undef X
- };
+};
const size_t TableIcmp64Size = llvm::array_lengthof(TableIcmp64);
CondX86::BrCond getIcmp32Mapping(InstIcmp::ICond Cond) {
@@ -108,9 +108,9 @@
#define X(tag, elementty, cvt, sdss, pack, width, fld) \
{ elementty } \
,
- ICETYPEX8632_TABLE
+ ICETYPEX8632_TABLE
#undef X
- };
+};
const size_t TableTypeX8632AttributesSize =
llvm::array_lengthof(TableTypeX8632Attributes);
@@ -155,14 +155,13 @@
// Instruction set options
namespace cl = ::llvm::cl;
-cl::opt<TargetX8632::X86InstructionSet>
-CLInstructionSet("mattr", cl::desc("X86 target attributes"),
- cl::init(TargetX8632::SSE2),
- cl::values(clEnumValN(TargetX8632::SSE2, "sse2",
- "Enable SSE2 instructions (default)"),
- clEnumValN(TargetX8632::SSE4_1, "sse4.1",
- "Enable SSE 4.1 instructions"),
- clEnumValEnd));
+cl::opt<TargetX8632::X86InstructionSet> CLInstructionSet(
+ "mattr", cl::desc("X86 target attributes"), cl::init(TargetX8632::SSE2),
+ cl::values(clEnumValN(TargetX8632::SSE2, "sse2",
+ "Enable SSE2 instructions (default)"),
+ clEnumValN(TargetX8632::SSE4_1, "sse4.1",
+ "Enable SSE 4.1 instructions"),
+ clEnumValEnd));
// In some cases, there are x-macros tables for both high-level and
// low-level instructions/operands that use the same enum key value.
@@ -454,7 +453,7 @@
#define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \
frameptr, isI8, isInt, isFP) \
name,
- REGX8632_TABLE
+ REGX8632_TABLE
#undef X
};
@@ -485,14 +484,14 @@
#define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \
frameptr, isI8, isInt, isFP) \
name8,
- REGX8632_TABLE
+ REGX8632_TABLE
#undef X
};
static IceString RegNames16[] = {
#define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \
frameptr, isI8, isInt, isFP) \
name16,
- REGX8632_TABLE
+ REGX8632_TABLE
#undef X
};
switch (Ty) {
@@ -2762,8 +2761,8 @@
// T := SourceVectRM
// ElementR := ElementR[0, 0] T[0, 2]
// T := T[0, 1] ElementR[3, 0]
- const unsigned char Mask1[3] = { 0, 192, 128 };
- const unsigned char Mask2[3] = { 227, 196, 52 };
+ const unsigned char Mask1[3] = {0, 192, 128};
+ const unsigned char Mask2[3] = {227, 196, 52};
Constant *Mask1Constant = Ctx->getConstantInt32(Mask1[Index - 1]);
Constant *Mask2Constant = Ctx->getConstantInt32(Mask2[Index - 1]);
@@ -2806,12 +2805,12 @@
switch (Instr->getIntrinsicInfo().ID) {
case Intrinsics::AtomicCmpxchg: {
if (!Intrinsics::VerifyMemoryOrder(
- llvm::cast<ConstantInteger32>(Instr->getArg(3))->getValue())) {
+ llvm::cast<ConstantInteger32>(Instr->getArg(3))->getValue())) {
Func->setError("Unexpected memory ordering (success) for AtomicCmpxchg");
return;
}
if (!Intrinsics::VerifyMemoryOrder(
- llvm::cast<ConstantInteger32>(Instr->getArg(4))->getValue())) {
+ llvm::cast<ConstantInteger32>(Instr->getArg(4))->getValue())) {
Func->setError("Unexpected memory ordering (failure) for AtomicCmpxchg");
return;
}
@@ -2826,7 +2825,7 @@
}
case Intrinsics::AtomicFence:
if (!Intrinsics::VerifyMemoryOrder(
- llvm::cast<ConstantInteger32>(Instr->getArg(0))->getValue())) {
+ llvm::cast<ConstantInteger32>(Instr->getArg(0))->getValue())) {
Func->setError("Unexpected memory ordering for AtomicFence");
return;
}
@@ -2872,7 +2871,7 @@
// We require the memory address to be naturally aligned.
// Given that is the case, then normal loads are atomic.
if (!Intrinsics::VerifyMemoryOrder(
- llvm::cast<ConstantInteger32>(Instr->getArg(1))->getValue())) {
+ llvm::cast<ConstantInteger32>(Instr->getArg(1))->getValue())) {
Func->setError("Unexpected memory ordering for AtomicLoad");
return;
}
@@ -2905,18 +2904,18 @@
}
case Intrinsics::AtomicRMW:
if (!Intrinsics::VerifyMemoryOrder(
- llvm::cast<ConstantInteger32>(Instr->getArg(3))->getValue())) {
+ llvm::cast<ConstantInteger32>(Instr->getArg(3))->getValue())) {
Func->setError("Unexpected memory ordering for AtomicRMW");
return;
}
lowerAtomicRMW(Instr->getDest(),
static_cast<uint32_t>(llvm::cast<ConstantInteger32>(
- Instr->getArg(0))->getValue()),
+ Instr->getArg(0))->getValue()),
Instr->getArg(1), Instr->getArg(2));
return;
case Intrinsics::AtomicStore: {
if (!Intrinsics::VerifyMemoryOrder(
- llvm::cast<ConstantInteger32>(Instr->getArg(2))->getValue())) {
+ llvm::cast<ConstantInteger32>(Instr->getArg(2))->getValue())) {
Func->setError("Unexpected memory ordering for AtomicStore");
return;
}
@@ -4577,7 +4576,8 @@
// If external and not initialized, this must be a cross test.
// Don't generate a declaration for such cases.
bool IsExternal = Var.isExternal() || Ctx->getFlags().DisableInternal;
- if (IsExternal && !Var.hasInitializer()) return;
+ if (IsExternal && !Var.hasInitializer())
+ return;
bool HasNonzeroInitializer = Var.hasNonzeroInitializer();
bool IsConstant = Var.getIsConstant();
diff --git a/src/IceTimerTree.h b/src/IceTimerTree.h
index bf122fd..795bbee 100644
--- a/src/IceTimerTree.h
+++ b/src/IceTimerTree.h
@@ -69,10 +69,10 @@
uint64_t StateChangeCount;
// IDsIndex maps a symbolic timer name to its integer ID.
std::map<IceString, TimerIdT> IDsIndex;
- std::vector<IceString> IDs; // indexed by TimerIdT
- std::vector<TimerTreeNode> Nodes; // indexed by TTindex
- std::vector<double> LeafTimes; // indexed by TimerIdT
- std::vector<size_t> LeafCounts; // indexed by TimerIdT
+ std::vector<IceString> IDs; // indexed by TimerIdT
+ std::vector<TimerTreeNode> Nodes; // indexed by TTindex
+ std::vector<double> LeafTimes; // indexed by TimerIdT
+ std::vector<size_t> LeafCounts; // indexed by TimerIdT
TTindex StackTop;
};
diff --git a/src/IceTypes.cpp b/src/IceTypes.cpp
index e6dbadf..838361c 100644
--- a/src/IceTypes.cpp
+++ b/src/IceTypes.cpp
@@ -92,7 +92,7 @@
#define X(tag, size, align, elts, elty, str) \
{ size, align, elts, elty, str } \
,
- ICETYPE_TABLE
+ ICETYPE_TABLE
#undef X
};
@@ -116,7 +116,7 @@
IsFloat && !IsVec, IsFloat && IsVec, IsLoadStore, CompareResult \
} \
,
- ICETYPE_PROPS_TABLE
+ ICETYPE_PROPS_TABLE
#undef X
};
diff --git a/src/IceTypes.h b/src/IceTypes.h
index 2b4c2cd..2cf5e40 100644
--- a/src/IceTypes.h
+++ b/src/IceTypes.h
@@ -40,12 +40,7 @@
return Stream << targetArchString(Arch);
}
-enum OptLevel {
- Opt_m1,
- Opt_0,
- Opt_1,
- Opt_2
-};
+enum OptLevel { Opt_m1, Opt_0, Opt_1, Opt_2 };
size_t typeWidthInBytes(Type Ty);
size_t typeAlignInBytes(Type Ty);
@@ -114,6 +109,7 @@
/// Models a type signature for a function.
class FuncSigType {
FuncSigType &operator=(const FuncSigType &Ty) = delete;
+
public:
typedef std::vector<Type> ArgListType;
diff --git a/src/PNaClTranslator.cpp b/src/PNaClTranslator.cpp
index 6a74dd2..344b749 100644
--- a/src/PNaClTranslator.cpp
+++ b/src/PNaClTranslator.cpp
@@ -42,6 +42,7 @@
// the extended type.
class ExtendedType {
ExtendedType &operator=(const ExtendedType &Ty) = delete;
+
public:
/// Discriminator for LLVM-style RTTI.
enum TypeKind { Undefined, Simple, FuncSig };
@@ -106,6 +107,7 @@
class SimpleExtendedType : public ExtendedType {
SimpleExtendedType(const SimpleExtendedType &) = delete;
SimpleExtendedType &operator=(const SimpleExtendedType &) = delete;
+
public:
Ice::Type getType() const { return Signature.getReturnType(); }
@@ -118,6 +120,7 @@
class FuncSigExtendedType : public ExtendedType {
FuncSigExtendedType(const FuncSigExtendedType &) = delete;
FuncSigExtendedType &operator=(const FuncSigExtendedType &) = delete;
+
public:
const Ice::FuncSigType &getSignature() const { return Signature; }
void setReturnType(Ice::Type ReturnType) {
@@ -201,7 +204,7 @@
if (Ty)
return Ty;
if (ID >= TypeIDValues.size())
- TypeIDValues.resize(ID+1);
+ TypeIDValues.resize(ID + 1);
return &TypeIDValues[ID];
}
@@ -1006,7 +1009,6 @@
virtual void setBbName(uint64_t Index, StringType &Name) = 0;
private:
-
void ProcessRecord() override;
void ConvertToString(StringType &ConvertedName) {
@@ -1092,13 +1094,9 @@
const char *getBlockName() const override { return "function"; }
- Ice::Cfg *getFunc() const {
- return Func;
- }
+ Ice::Cfg *getFunc() const { return Func; }
- uint32_t getNumGlobalIDs() const {
- return CachedNumGlobalValueIDs;
- }
+ uint32_t getNumGlobalIDs() const { return CachedNumGlobalValueIDs; }
void setNextLocalInstIndex(Ice::Operand *Op) {
setOperand(NextLocalInstIndex++, Op);
@@ -1578,19 +1576,17 @@
/// Returns true iff an integer truncation from SourceType to TargetType is
/// valid.
static bool isIntTruncCastValid(Ice::Type SourceType, Ice::Type TargetType) {
- return Ice::isIntegerType(SourceType)
- && Ice::isIntegerType(TargetType)
- && simplifyOutCommonVectorType(SourceType, TargetType)
- && getScalarIntBitWidth(SourceType) > getScalarIntBitWidth(TargetType);
+ return Ice::isIntegerType(SourceType) && Ice::isIntegerType(TargetType) &&
+ simplifyOutCommonVectorType(SourceType, TargetType) &&
+ getScalarIntBitWidth(SourceType) > getScalarIntBitWidth(TargetType);
}
/// Returns true iff a floating type truncation from SourceType to TargetType
/// is valid.
static bool isFloatTruncCastValid(Ice::Type SourceType,
Ice::Type TargetType) {
- return simplifyOutCommonVectorType(SourceType, TargetType)
- && SourceType == Ice::IceType_f64
- && TargetType == Ice::IceType_f32;
+ return simplifyOutCommonVectorType(SourceType, TargetType) &&
+ SourceType == Ice::IceType_f64 && TargetType == Ice::IceType_f32;
}
/// Returns true iff an integer extension from SourceType to TargetType is
@@ -1996,8 +1992,8 @@
} else if (CondVal->getType() != Ice::IceType_i1) {
std::string Buffer;
raw_string_ostream StrBuf(Buffer);
- StrBuf << "Select condition " << CondVal << " not type i1. Found: "
- << CondVal->getType();
+ StrBuf << "Select condition " << CondVal
+ << " not type i1. Found: " << CondVal->getType();
Error(StrBuf.str());
appendErrorInstruction(ThenType);
return;
@@ -2079,8 +2075,8 @@
if (Op1Type != Op2Type) {
std::string Buffer;
raw_string_ostream StrBuf(Buffer);
- StrBuf << "Compare argument types differ: " << Op1Type
- << " and " << Op2Type;
+ StrBuf << "Compare argument types differ: " << Op1Type << " and "
+ << Op2Type;
Error(StrBuf.str());
appendErrorInstruction(DestType);
Op2 = Op1;
@@ -2105,7 +2101,7 @@
}
CurrentNode->appendInst(
Ice::InstIcmp::create(Func, Cond, Dest, Op1, Op2));
- } else if (isFloatingType(Op1Type)){
+ } else if (isFloatingType(Op1Type)) {
Ice::InstFcmp::FCond Cond;
if (!convertNaClBitcFCompOpToIce(Values[2], Cond)) {
std::string Buffer;
@@ -2168,8 +2164,8 @@
if (Cond->getType() != Ice::IceType_i1) {
std::string Buffer;
raw_string_ostream StrBuf(Buffer);
- StrBuf << "Branch condition " << *Cond << " not i1. Found: "
- << Cond->getType();
+ StrBuf << "Branch condition " << *Cond
+ << " not i1. Found: " << Cond->getType();
Error(StrBuf.str());
return;
}
@@ -2227,10 +2223,10 @@
Ice::InstSwitch *Switch =
isIRGenDisabled ? nullptr : Ice::InstSwitch::create(Func, NumCases,
Cond, DefaultLabel);
- unsigned ValCaseIndex = 4; // index to beginning of case entry.
+ unsigned ValCaseIndex = 4; // index to beginning of case entry.
for (unsigned CaseIndex = 0; CaseIndex < NumCases;
++CaseIndex, ValCaseIndex += 4) {
- if (Values[ValCaseIndex] != 1 || Values[ValCaseIndex+1] != 1) {
+ if (Values[ValCaseIndex] != 1 || Values[ValCaseIndex + 1] != 1) {
std::string Buffer;
raw_string_ostream StrBuf(Buffer);
StrBuf << "Sequence [1, 1, value, label] expected for case entry "
@@ -2257,8 +2253,7 @@
return;
if (isIRGenerationDisabled())
return;
- CurrentNode->appendInst(
- Ice::InstUnreachable::create(Func));
+ CurrentNode->appendInst(Ice::InstUnreachable::create(Func));
InstIsTerminating = true;
return;
}
@@ -2464,9 +2459,8 @@
: getNextInstVar(ReturnType);
Ice::InstCall *Inst = nullptr;
if (IntrinsicInfo) {
- Inst =
- Ice::InstIntrinsicCall::create(Func, NumParams, Dest, Callee,
- IntrinsicInfo->Info);
+ Inst = Ice::InstIntrinsicCall::create(Func, NumParams, Dest, Callee,
+ IntrinsicInfo->Info);
} else {
Inst = Ice::InstCall::create(Func, NumParams, Dest, Callee, IsTailCall);
}
@@ -2808,9 +2802,7 @@
bool ParseBlock(unsigned BlockID) override;
- void ExitBlock() override {
- InstallGlobalNamesAndGlobalVarInitializers();
- }
+ void ExitBlock() override { InstallGlobalNamesAndGlobalVarInitializers(); }
void ProcessRecord() override;
};
diff --git a/src/assembler.h b/src/assembler.h
index 7997865..40f50fd 100644
--- a/src/assembler.h
+++ b/src/assembler.h
@@ -57,9 +57,7 @@
}
// Emit a fixup at the current location.
- void EmitFixup(AssemblerFixup *fixup) {
- fixup->set_position(Size());
- }
+ void EmitFixup(AssemblerFixup *fixup) { fixup->set_position(Size()); }
// Get the size of the emitted code.
intptr_t Size() const { return cursor_ - contents_; }
diff --git a/src/llvm2ice.cpp b/src/llvm2ice.cpp
index 51757b8..702d0b1 100644
--- a/src/llvm2ice.cpp
+++ b/src/llvm2ice.cpp
@@ -73,13 +73,13 @@
DataSections("fdata-sections",
cl::desc("Emit (global) data into separate sections"));
static cl::opt<Ice::OptLevel>
-OptLevel(cl::desc("Optimization level"), cl::init(Ice::Opt_m1),
- cl::value_desc("level"),
- cl::values(clEnumValN(Ice::Opt_m1, "Om1", "-1"),
- clEnumValN(Ice::Opt_m1, "O-1", "-1"),
- clEnumValN(Ice::Opt_0, "O0", "0"),
- clEnumValN(Ice::Opt_1, "O1", "1"),
- clEnumValN(Ice::Opt_2, "O2", "2"), clEnumValEnd));
+ OptLevel(cl::desc("Optimization level"), cl::init(Ice::Opt_m1),
+ cl::value_desc("level"),
+ cl::values(clEnumValN(Ice::Opt_m1, "Om1", "-1"),
+ clEnumValN(Ice::Opt_m1, "O-1", "-1"),
+ clEnumValN(Ice::Opt_0, "O0", "0"),
+ clEnumValN(Ice::Opt_1, "O1", "1"),
+ clEnumValN(Ice::Opt_2, "O2", "2"), clEnumValEnd));
static cl::opt<std::string> IRFilename(cl::Positional, cl::desc("<IR file>"),
cl::init("-"));
static cl::opt<std::string> OutputFilename("o",
@@ -90,27 +90,26 @@
cl::init("-"),
cl::value_desc("filename"));
static cl::opt<std::string>
-TestPrefix("prefix", cl::desc("Prepend a prefix to symbol names for testing"),
- cl::init(""), cl::value_desc("prefix"));
+ TestPrefix("prefix",
+ cl::desc("Prepend a prefix to symbol names for testing"),
+ cl::init(""), cl::value_desc("prefix"));
+static cl::opt<bool> DisableInternal("externalize",
+ cl::desc("Externalize all symbols"));
static cl::opt<bool>
-DisableInternal("externalize",
- cl::desc("Externalize all symbols"));
-static cl::opt<bool>
-DisableTranslation("notranslate", cl::desc("Disable Subzero translation"));
+ DisableTranslation("notranslate", cl::desc("Disable Subzero translation"));
// Note: Modifiable only if ALLOW_DISABLE_IR_GEN.
static cl::opt<bool>
DisableIRGeneration("no-ir-gen",
cl::desc("Disable generating Subzero IR."));
static cl::opt<std::string>
-TranslateOnly("translate-only", cl::desc("Translate only the given function"),
- cl::init(""));
+ TranslateOnly("translate-only",
+ cl::desc("Translate only the given function"), cl::init(""));
static cl::opt<bool> SubzeroTimingEnabled(
"timing", cl::desc("Enable breakdown timing of Subzero translation"));
-static cl::opt<bool>
-TimeEachFunction("timing-funcs",
- cl::desc("Print total translation time for each function"));
+static cl::opt<bool> TimeEachFunction(
+ "timing-funcs", cl::desc("Print total translation time for each function"));
static cl::opt<std::string> TimingFocusOn(
"timing-focus",
@@ -123,17 +122,17 @@
cl::init(""));
static cl::opt<bool>
-EnablePhiEdgeSplit("phi-edge-split",
- cl::desc("Enable edge splitting for Phi lowering"),
- cl::init(true));
+ EnablePhiEdgeSplit("phi-edge-split",
+ cl::desc("Enable edge splitting for Phi lowering"),
+ cl::init(true));
static cl::opt<bool> DecorateAsm(
"asm-verbose",
cl::desc("Decorate textual asm output with register liveness info"));
static cl::opt<bool>
-DumpStats("szstats",
- cl::desc("Print statistics after translating each function"));
+ DumpStats("szstats",
+ cl::desc("Print statistics after translating each function"));
// This is currently needed by crosstest.py.
static cl::opt<bool> AllowUninitializedGlobals(
@@ -173,8 +172,7 @@
cl::desc("Allow error recovery when reading PNaCl bitcode."),
cl::init(false));
-static cl::opt<bool>
-LLVMVerboseErrors(
+static cl::opt<bool> LLVMVerboseErrors(
"verbose-llvm-parse-errors",
cl::desc("Print out more descriptive PNaCl bitcode parse errors when "
"building LLVM IR first"),
@@ -197,23 +195,22 @@
"exit-success", cl::desc("Exit with success status, even if errors found"),
cl::init(false));
-static cl::opt<bool>
-GenerateBuildAtts("build-atts",
- cl::desc("Generate list of build attributes associated with "
+static cl::opt<bool> GenerateBuildAtts(
+ "build-atts", cl::desc("Generate list of build attributes associated with "
"this executable."),
- cl::init(false));
+ cl::init(false));
// Number of translation threads (in addition to the parser thread and
// the emitter thread). The special case of 0 means purely
// sequential, i.e. parser, translator, and emitter all within the
// same single thread. (This may need a slight rework if we expand to
// multiple parser or emitter threads.)
-static cl::opt<uint32_t>
-NumThreads("threads",
- cl::desc("Number of translation threads (0 for purely sequential)"),
- // TODO(stichnot): Settle on a good default. Consider
- // something related to std::thread::hardware_concurrency().
- cl::init(0));
+static cl::opt<uint32_t> NumThreads(
+ "threads",
+ cl::desc("Number of translation threads (0 for purely sequential)"),
+ // TODO(stichnot): Settle on a good default. Consider
+ // something related to std::thread::hardware_concurrency().
+ cl::init(0));
static int GetReturnValue(int Val) {
if (AlwaysExitSuccess)
@@ -377,9 +374,8 @@
SMDiagnostic Err;
Ice::TimerMarker T1(Ice::TimerStack::TT_parse, &Ctx);
raw_ostream *Verbose = LLVMVerboseErrors ? &errs() : nullptr;
- Module *Mod =
- NaClParseIRFile(IRFilename, InputFileFormat, Err, Verbose,
- getGlobalContext());
+ Module *Mod = NaClParseIRFile(IRFilename, InputFileFormat, Err, Verbose,
+ getGlobalContext());
if (!Mod) {
Err.print(argv[0], errs());
