Squashed 'third_party/SPIRV-Headers/' changes from 6a55fade6..b765c355f
b765c355f Merge pull request #279 from dgkoch/SPV_KHR_ray_cull_mask
b74edd553 Add SPV_KHR_ray_cull_mask
46b791821 Merge pull request #274 from rayanht/patch-1
bfaccff6e Merge pull request #277 from kpet/spv-khr-subgroup-rotate
ee9e6ddf3 do not enable the instruction with the extension
c0bd60422 Add SPV_KHR_subgroup_rotate
ef6eceddd Register magic number for SPIRVSmith
82becc8a8 Merge pull request #273 from Tachi107/patch-1
d9234dee3 build: use ARCH_INDEPENDENT if possible
9c3fd01c8 Merge pull request #270 from kpet/sycl
5bb42a80d Merge pull request #272 from DmitryBushev/open_master
5ecb8bc82 Removed extension section
bf5bffa93 Add NamedBarrierCountINTEL execution mode
064395f0f Add a SourceLanguage for SYCL
4995a2f27 Merge pull request #269 from KornevNikita/uniform_group_instructions
7744288e2 Remove extensions tag from instructions
0e994ee9c Merge pull request #261 from ProkopRandacek/master
48fadab86 Merge branch 'master' of https://github.com/KhronosGroup/SPIRV-Headers into uniform_group_instructions
a4a03f677 Implement SPV_KHR_uniform_group_instructions extension
f75fc98ba Merge pull request #268 from bashbaug/SPV_INTEL_split_barrier
24c841de7 Merge pull request #263 from DataBeaver/master
f85647cbf Merge pull request #264 from gnl21/demote-ext-tag
ed206e381 update SPIR-V headers for SPV_INTEL_split_barrier
bf985e99e regenerate headers
c89cabce9 Add EXT tag to capability to DemoteToHelperInvocationEXT
c31dbf6c1 Reserve enum range for MSP extensions
e14816714 regenerate the headers
6e7a6754b Include bool type for C
git-subtree-dir: third_party/SPIRV-Headers
git-subtree-split: b765c355f488837ca4c77980ba69484f3ff277f5
Change-Id: Ie0e87011f32da046895827431c211e55f4d3cb05
diff --git a/CMakeLists.txt b/CMakeLists.txt
index f19390a..147f7ad 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -89,9 +89,14 @@
set(namespace "${PROJECT_NAME}::")
include(CMakePackageConfigHelpers)
+
+ if (NOT CMAKE_VERSION VERSION_LESS 3.14)
+ set(arch_independent_str ARCH_INDEPENDENT)
+ endif()
write_basic_package_version_file(
"${version_config}"
COMPATIBILITY SameMajorVersion
+ ${arch_independent_str}
)
configure_package_config_file(
diff --git a/include/spirv/spir-v.xml b/include/spirv/spir-v.xml
index 6b578a5..7acaed3 100644
--- a/include/spirv/spir-v.xml
+++ b/include/spirv/spir-v.xml
@@ -84,7 +84,8 @@
<id value="31" vendor="Google" tool="Skia SkSL" comment="Contact Ethan Nicholas, ethannicholas@google.com"/>
<id value="32" vendor="TornadoVM" tool="SPIRV Beehive Toolkit" comment="https://github.com/beehive-lab/spirv-beehive-toolkit"/>
<id value="33" vendor="DragonJoker" tool="ShaderWriter" comment="Contact Sylvain Doremus, https://github.com/DragonJoker/ShaderWriter"/>
- <unused start="34" end="0xFFFF" comment="Tool ID range reservable for future use by vendors"/>
+ <id value="34" vendor="Rayan Hatout" tool="SPIRVSmith" comment="Contact Rayan Hatout rayan.hatout@gmail.com, Repo https://github.com/rayanht/SPIRVSmith"/>
+ <unused start="35" end="0xFFFF" comment="Tool ID range reservable for future use by vendors"/>
</ids>
<!-- SECTION: SPIR-V Opcodes and Enumerants -->
@@ -166,13 +167,14 @@
<ids type="enumerant" start="6144" end="6271" vendor="Intel" comment="Contact michael.kinsner@intel.com"/>
<ids type="enumerant" start="6272" end="6399" vendor="Huawei" comment="Contact wanghuilong2@xunweitech.com"/>
<ids type="enumerant" start="6400" end="6463" vendor="Intel" comment="Contact ben.ashbaugh@intel.com"/>
+ <ids type="enumerant" start="6464" end="6527" vendor="Mikkosoft Productions" comment="Contact Mikko Rasa, tdb@tdb.fi"/>
<!-- Enumerants to reserve for future use. To get a block, allocate
multiples of 64 starting at the lowest available point in this
block and add a corresponding <ids> tag immediately above. Make
sure to fill in the vendor attribute, and preferably add a contact
person/address in a comment attribute. -->
<!-- Example new block: <ids type="enumerant" start="XXXX" end="XXXX+64n-1" vendor="Add vendor" comment="Contact TBD"/> -->
- <ids type="enumerant" start="6464" end="4294967295" comment="Enumerant range reservable for future use by vendors"/>
+ <ids type="enumerant" start="6528" end="4294967295" comment="Enumerant range reservable for future use by vendors"/>
<!-- End reservations of enumerants -->
diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json
index 8b98770..8b63c39 100644
--- a/include/spirv/unified1/spirv.core.grammar.json
+++ b/include/spirv/unified1/spirv.core.grammar.json
@@ -4184,6 +4184,21 @@
"version" : "None"
},
{
+ "opname" : "OpGroupNonUniformRotateKHR",
+ "class" : "Group",
+ "opcode" : 4431,
+ "operands" : [
+ { "kind" : "IdResultType" },
+ { "kind" : "IdResult" },
+ { "kind" : "IdScope", "name" : "'Execution'" },
+ { "kind" : "IdRef", "name" : "'Value'" },
+ { "kind" : "IdRef", "name" : "'Delta'" },
+ { "kind" : "IdRef", "name" : "'ClusterSize'", "quantifier" : "?" }
+ ],
+ "capabilities" : [ "GroupNonUniformRotateKHR" ],
+ "version" : "None"
+ },
+ {
"opname" : "OpSubgroupReadInvocationKHR",
"class" : "Group",
"opcode" : 4432,
@@ -5029,7 +5044,7 @@
"opname" : "OpDemoteToHelperInvocationEXT",
"class" : "Control-Flow",
"opcode" : 5380,
- "capabilities" : [ "DemoteToHelperInvocation" ],
+ "capabilities" : [ "DemoteToHelperInvocationEXT" ],
"version" : "1.6"
},
{
@@ -8549,6 +8564,142 @@
],
"capabilities" : [ "LongConstantCompositeINTEL" ],
"version" : "None"
+ },
+ {
+ "opname" : "OpControlBarrierArriveINTEL",
+ "class" : "Barrier",
+ "opcode" : 6142,
+ "operands" : [
+ { "kind" : "IdScope", "name" : "'Execution'" },
+ { "kind" : "IdScope", "name" : "'Memory'" },
+ { "kind" : "IdMemorySemantics", "name" : "'Semantics'" }
+ ],
+ "capabilities" : [ "SplitBarrierINTEL" ],
+ "version" : "None"
+ },
+ {
+ "opname" : "OpControlBarrierWaitINTEL",
+ "class" : "Barrier",
+ "opcode" : 6143,
+ "operands" : [
+ { "kind" : "IdScope", "name" : "'Execution'" },
+ { "kind" : "IdScope", "name" : "'Memory'" },
+ { "kind" : "IdMemorySemantics", "name" : "'Semantics'" }
+ ],
+ "capabilities" : [ "SplitBarrierINTEL" ],
+ "version" : "None"
+ },
+ {
+ "opname" : "OpGroupIMulKHR",
+ "class" : "Group",
+ "opcode" : 6401,
+ "operands" : [
+ { "kind" : "IdResultType" },
+ { "kind" : "IdResult" },
+ { "kind" : "IdScope", "name" : "'Execution'" },
+ { "kind" : "GroupOperation", "name" : "'Operation'" },
+ { "kind" : "IdRef", "name" : "'X'" }
+ ],
+ "capabilities" : [ "GroupUniformArithmeticKHR" ],
+ "version" : "None"
+ },
+ {
+ "opname" : "OpGroupFMulKHR",
+ "class" : "Group",
+ "opcode" : 6402,
+ "operands" : [
+ { "kind" : "IdResultType" },
+ { "kind" : "IdResult" },
+ { "kind" : "IdScope", "name" : "'Execution'" },
+ { "kind" : "GroupOperation", "name" : "'Operation'" },
+ { "kind" : "IdRef", "name" : "'X'" }
+ ],
+ "capabilities" : [ "GroupUniformArithmeticKHR" ],
+ "version" : "None"
+ },
+ {
+ "opname" : "OpGroupBitwiseAndKHR",
+ "class" : "Group",
+ "opcode" : 6403,
+ "operands" : [
+ { "kind" : "IdResultType" },
+ { "kind" : "IdResult" },
+ { "kind" : "IdScope", "name" : "'Execution'" },
+ { "kind" : "GroupOperation", "name" : "'Operation'" },
+ { "kind" : "IdRef", "name" : "'X'" }
+ ],
+ "capabilities" : [ "GroupUniformArithmeticKHR" ],
+ "version" : "None"
+ },
+ {
+ "opname" : "OpGroupBitwiseOrKHR",
+ "class" : "Group",
+ "opcode" : 6404,
+ "operands" : [
+ { "kind" : "IdResultType" },
+ { "kind" : "IdResult" },
+ { "kind" : "IdScope", "name" : "'Execution'" },
+ { "kind" : "GroupOperation", "name" : "'Operation'" },
+ { "kind" : "IdRef", "name" : "'X'" }
+ ],
+ "capabilities" : [ "GroupUniformArithmeticKHR" ],
+ "version" : "None"
+ },
+ {
+ "opname" : "OpGroupBitwiseXorKHR",
+ "class" : "Group",
+ "opcode" : 6405,
+ "operands" : [
+ { "kind" : "IdResultType" },
+ { "kind" : "IdResult" },
+ { "kind" : "IdScope", "name" : "'Execution'" },
+ { "kind" : "GroupOperation", "name" : "'Operation'" },
+ { "kind" : "IdRef", "name" : "'X'" }
+ ],
+ "capabilities" : [ "GroupUniformArithmeticKHR" ],
+ "version" : "None"
+ },
+ {
+ "opname" : "OpGroupLogicalAndKHR",
+ "class" : "Group",
+ "opcode" : 6406,
+ "operands" : [
+ { "kind" : "IdResultType" },
+ { "kind" : "IdResult" },
+ { "kind" : "IdScope", "name" : "'Execution'" },
+ { "kind" : "GroupOperation", "name" : "'Operation'" },
+ { "kind" : "IdRef", "name" : "'X'" }
+ ],
+ "capabilities" : [ "GroupUniformArithmeticKHR" ],
+ "version" : "None"
+ },
+ {
+ "opname" : "OpGroupLogicalOrKHR",
+ "class" : "Group",
+ "opcode" : 6407,
+ "operands" : [
+ { "kind" : "IdResultType" },
+ { "kind" : "IdResult" },
+ { "kind" : "IdScope", "name" : "'Execution'" },
+ { "kind" : "GroupOperation", "name" : "'Operation'" },
+ { "kind" : "IdRef", "name" : "'X'" }
+ ],
+ "capabilities" : [ "GroupUniformArithmeticKHR" ],
+ "version" : "None"
+ },
+ {
+ "opname" : "OpGroupLogicalXorKHR",
+ "class" : "Group",
+ "opcode" : 6408,
+ "operands" : [
+ { "kind" : "IdResultType" },
+ { "kind" : "IdResult" },
+ { "kind" : "IdScope", "name" : "'Execution'" },
+ { "kind" : "GroupOperation", "name" : "'Operation'" },
+ { "kind" : "IdRef", "name" : "'X'" }
+ ],
+ "capabilities" : [ "GroupUniformArithmeticKHR" ],
+ "version" : "None"
}
],
"operand_kinds" : [
@@ -9298,6 +9449,10 @@
{
"enumerant" : "CPP_for_OpenCL",
"value" : 6
+ },
+ {
+ "enumerant" : "SYCL",
+ "value" : 7
}
]
},
@@ -9974,6 +10129,15 @@
],
"capabilities" : [ "FPGAKernelAttributesINTEL" ],
"version" : "None"
+ },
+ {
+ "enumerant" : "NamedBarrierCountINTEL",
+ "value" : 6417,
+ "parameters" : [
+ { "kind" : "LiteralInteger", "name" : "'Barrier Count'" }
+ ],
+ "capabilities" : [ "VectorComputeINTEL" ],
+ "version" : "None"
}
]
},
@@ -12452,6 +12616,13 @@
"capabilities" : [ "ShaderSMBuiltinsNV" ],
"extensions" : [ "SPV_NV_shader_sm_builtins" ],
"version" : "None"
+ },
+ {
+ "enumerant" : "CullMaskKHR",
+ "value" : 6021,
+ "capabilities" : [ "RayCullMaskKHR" ],
+ "extensions" : [ "SPV_KHR_ray_cull_mask" ],
+ "version" : "None"
}
]
},
@@ -13841,12 +14012,25 @@
"version" : "1.6"
},
{
+ "enumerant" : "RayCullMaskKHR",
+ "value" : 6020,
+ "extensions" : [ "SPV_KHR_ray_cull_mask" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "BitInstructions",
"value" : 6025,
"extensions" : [ "SPV_KHR_bit_instructions" ],
"version" : "None"
},
{
+ "enumerant" : "GroupNonUniformRotateKHR",
+ "value" : 6026,
+ "capabilities" : [ "GroupNonUniform" ],
+ "extensions" : [ "SPV_KHR_subgroup_rotate" ],
+ "version" : "None"
+ },
+ {
"enumerant" : "AtomicFloat32AddEXT",
"value" : 6033,
"extensions" : [ "SPV_EXT_shader_atomic_float_add" ],
@@ -13881,6 +14065,18 @@
"value" : 6114,
"extensions" : [ "SPV_INTEL_debug_module" ],
"version" : "None"
+ },
+ {
+ "enumerant" : "SplitBarrierINTEL",
+ "value" : 6141,
+ "extensions" : [ "SPV_INTEL_split_barrier" ],
+ "version" : "None"
+ },
+ {
+ "enumerant" : "GroupUniformArithmeticKHR",
+ "value" : 6400,
+ "extensions" : [ "SPV_KHR_uniform_group_instructions"],
+ "version" : "None"
}
]
},
diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs
index 9e2bccd..9899dc3 100644
--- a/include/spirv/unified1/spirv.cs
+++ b/include/spirv/unified1/spirv.cs
@@ -62,6 +62,7 @@
OpenCL_CPP = 4,
HLSL = 5,
CPP_for_OpenCL = 6,
+ SYCL = 7,
}
public enum ExecutionModel
@@ -176,6 +177,7 @@
NoGlobalOffsetINTEL = 5895,
NumSIMDWorkitemsINTEL = 5896,
SchedulerTargetFmaxMhzINTEL = 5903,
+ NamedBarrierCountINTEL = 6417,
}
public enum StorageClass
@@ -673,6 +675,7 @@
SMCountNV = 5375,
WarpIDNV = 5376,
SMIDNV = 5377,
+ CullMaskKHR = 6021,
}
public enum SelectionControlShift
@@ -1080,13 +1083,17 @@
DotProductInput4x8BitPackedKHR = 6018,
DotProduct = 6019,
DotProductKHR = 6019,
+ RayCullMaskKHR = 6020,
BitInstructions = 6025,
+ GroupNonUniformRotateKHR = 6026,
AtomicFloat32AddEXT = 6033,
AtomicFloat64AddEXT = 6034,
LongConstantCompositeINTEL = 6089,
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ SplitBarrierINTEL = 6141,
+ GroupUniformArithmeticKHR = 6400,
}
public enum RayFlagsShift
@@ -1544,6 +1551,7 @@
OpSubgroupAllKHR = 4428,
OpSubgroupAnyKHR = 4429,
OpSubgroupAllEqualKHR = 4430,
+ OpGroupNonUniformRotateKHR = 4431,
OpSubgroupReadInvocationKHR = 4432,
OpTraceRayKHR = 4445,
OpExecuteCallableKHR = 4446,
@@ -1851,6 +1859,16 @@
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpControlBarrierArriveINTEL = 6142,
+ OpControlBarrierWaitINTEL = 6143,
+ OpGroupIMulKHR = 6401,
+ OpGroupFMulKHR = 6402,
+ OpGroupBitwiseAndKHR = 6403,
+ OpGroupBitwiseOrKHR = 6404,
+ OpGroupBitwiseXorKHR = 6405,
+ OpGroupLogicalAndKHR = 6406,
+ OpGroupLogicalOrKHR = 6407,
+ OpGroupLogicalXorKHR = 6408,
}
}
}
diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h
index 3d617da..eca9ca8 100644
--- a/include/spirv/unified1/spirv.h
+++ b/include/spirv/unified1/spirv.h
@@ -70,6 +70,7 @@
SpvSourceLanguageOpenCL_CPP = 4,
SpvSourceLanguageHLSL = 5,
SpvSourceLanguageCPP_for_OpenCL = 6,
+ SpvSourceLanguageSYCL = 7,
SpvSourceLanguageMax = 0x7fffffff,
} SpvSourceLanguage;
@@ -184,6 +185,7 @@
SpvExecutionModeNoGlobalOffsetINTEL = 5895,
SpvExecutionModeNumSIMDWorkitemsINTEL = 5896,
SpvExecutionModeSchedulerTargetFmaxMhzINTEL = 5903,
+ SpvExecutionModeNamedBarrierCountINTEL = 6417,
SpvExecutionModeMax = 0x7fffffff,
} SpvExecutionMode;
@@ -679,6 +681,7 @@
SpvBuiltInSMCountNV = 5375,
SpvBuiltInWarpIDNV = 5376,
SpvBuiltInSMIDNV = 5377,
+ SpvBuiltInCullMaskKHR = 6021,
SpvBuiltInMax = 0x7fffffff,
} SpvBuiltIn;
@@ -1080,13 +1083,17 @@
SpvCapabilityDotProductInput4x8BitPackedKHR = 6018,
SpvCapabilityDotProduct = 6019,
SpvCapabilityDotProductKHR = 6019,
+ SpvCapabilityRayCullMaskKHR = 6020,
SpvCapabilityBitInstructions = 6025,
+ SpvCapabilityGroupNonUniformRotateKHR = 6026,
SpvCapabilityAtomicFloat32AddEXT = 6033,
SpvCapabilityAtomicFloat64AddEXT = 6034,
SpvCapabilityLongConstantCompositeINTEL = 6089,
SpvCapabilityOptNoneINTEL = 6094,
SpvCapabilityAtomicFloat16AddEXT = 6095,
SpvCapabilityDebugInfoModuleINTEL = 6114,
+ SpvCapabilitySplitBarrierINTEL = 6141,
+ SpvCapabilityGroupUniformArithmeticKHR = 6400,
SpvCapabilityMax = 0x7fffffff,
} SpvCapability;
@@ -1542,6 +1549,7 @@
SpvOpSubgroupAllKHR = 4428,
SpvOpSubgroupAnyKHR = 4429,
SpvOpSubgroupAllEqualKHR = 4430,
+ SpvOpGroupNonUniformRotateKHR = 4431,
SpvOpSubgroupReadInvocationKHR = 4432,
SpvOpTraceRayKHR = 4445,
SpvOpExecuteCallableKHR = 4446,
@@ -1849,10 +1857,23 @@
SpvOpTypeStructContinuedINTEL = 6090,
SpvOpConstantCompositeContinuedINTEL = 6091,
SpvOpSpecConstantCompositeContinuedINTEL = 6092,
+ SpvOpControlBarrierArriveINTEL = 6142,
+ SpvOpControlBarrierWaitINTEL = 6143,
+ SpvOpGroupIMulKHR = 6401,
+ SpvOpGroupFMulKHR = 6402,
+ SpvOpGroupBitwiseAndKHR = 6403,
+ SpvOpGroupBitwiseOrKHR = 6404,
+ SpvOpGroupBitwiseXorKHR = 6405,
+ SpvOpGroupLogicalAndKHR = 6406,
+ SpvOpGroupLogicalOrKHR = 6407,
+ SpvOpGroupLogicalXorKHR = 6408,
SpvOpMax = 0x7fffffff,
} SpvOp;
#ifdef SPV_ENABLE_UTILITY_CODE
+#ifndef __cplusplus
+#include <stdbool.h>
+#endif
inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultType) {
*hasResult = *hasResultType = false;
switch (opcode) {
@@ -2207,6 +2228,7 @@
case SpvOpSubgroupAllKHR: *hasResult = true; *hasResultType = true; break;
case SpvOpSubgroupAnyKHR: *hasResult = true; *hasResultType = true; break;
case SpvOpSubgroupAllEqualKHR: *hasResult = true; *hasResultType = true; break;
+ case SpvOpGroupNonUniformRotateKHR: *hasResult = true; *hasResultType = true; break;
case SpvOpSubgroupReadInvocationKHR: *hasResult = true; *hasResultType = true; break;
case SpvOpTraceRayKHR: *hasResult = false; *hasResultType = false; break;
case SpvOpExecuteCallableKHR: *hasResult = false; *hasResultType = false; break;
@@ -2503,6 +2525,16 @@
case SpvOpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
+ case SpvOpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
+ case SpvOpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
+ case SpvOpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
+ case SpvOpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
+ case SpvOpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
+ case SpvOpGroupBitwiseOrKHR: *hasResult = true; *hasResultType = true; break;
+ case SpvOpGroupBitwiseXorKHR: *hasResult = true; *hasResultType = true; break;
+ case SpvOpGroupLogicalAndKHR: *hasResult = true; *hasResultType = true; break;
+ case SpvOpGroupLogicalOrKHR: *hasResult = true; *hasResultType = true; break;
+ case SpvOpGroupLogicalXorKHR: *hasResult = true; *hasResultType = true; break;
}
}
#endif /* SPV_ENABLE_UTILITY_CODE */
diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp
index 97a5101..8c679d9 100644
--- a/include/spirv/unified1/spirv.hpp
+++ b/include/spirv/unified1/spirv.hpp
@@ -66,6 +66,7 @@
SourceLanguageOpenCL_CPP = 4,
SourceLanguageHLSL = 5,
SourceLanguageCPP_for_OpenCL = 6,
+ SourceLanguageSYCL = 7,
SourceLanguageMax = 0x7fffffff,
};
@@ -180,6 +181,7 @@
ExecutionModeNoGlobalOffsetINTEL = 5895,
ExecutionModeNumSIMDWorkitemsINTEL = 5896,
ExecutionModeSchedulerTargetFmaxMhzINTEL = 5903,
+ ExecutionModeNamedBarrierCountINTEL = 6417,
ExecutionModeMax = 0x7fffffff,
};
@@ -675,6 +677,7 @@
BuiltInSMCountNV = 5375,
BuiltInWarpIDNV = 5376,
BuiltInSMIDNV = 5377,
+ BuiltInCullMaskKHR = 6021,
BuiltInMax = 0x7fffffff,
};
@@ -1076,13 +1079,17 @@
CapabilityDotProductInput4x8BitPackedKHR = 6018,
CapabilityDotProduct = 6019,
CapabilityDotProductKHR = 6019,
+ CapabilityRayCullMaskKHR = 6020,
CapabilityBitInstructions = 6025,
+ CapabilityGroupNonUniformRotateKHR = 6026,
CapabilityAtomicFloat32AddEXT = 6033,
CapabilityAtomicFloat64AddEXT = 6034,
CapabilityLongConstantCompositeINTEL = 6089,
CapabilityOptNoneINTEL = 6094,
CapabilityAtomicFloat16AddEXT = 6095,
CapabilityDebugInfoModuleINTEL = 6114,
+ CapabilitySplitBarrierINTEL = 6141,
+ CapabilityGroupUniformArithmeticKHR = 6400,
CapabilityMax = 0x7fffffff,
};
@@ -1538,6 +1545,7 @@
OpSubgroupAllKHR = 4428,
OpSubgroupAnyKHR = 4429,
OpSubgroupAllEqualKHR = 4430,
+ OpGroupNonUniformRotateKHR = 4431,
OpSubgroupReadInvocationKHR = 4432,
OpTraceRayKHR = 4445,
OpExecuteCallableKHR = 4446,
@@ -1845,10 +1853,23 @@
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpControlBarrierArriveINTEL = 6142,
+ OpControlBarrierWaitINTEL = 6143,
+ OpGroupIMulKHR = 6401,
+ OpGroupFMulKHR = 6402,
+ OpGroupBitwiseAndKHR = 6403,
+ OpGroupBitwiseOrKHR = 6404,
+ OpGroupBitwiseXorKHR = 6405,
+ OpGroupLogicalAndKHR = 6406,
+ OpGroupLogicalOrKHR = 6407,
+ OpGroupLogicalXorKHR = 6408,
OpMax = 0x7fffffff,
};
#ifdef SPV_ENABLE_UTILITY_CODE
+#ifndef __cplusplus
+#include <stdbool.h>
+#endif
inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
*hasResult = *hasResultType = false;
switch (opcode) {
@@ -2203,6 +2224,7 @@
case OpSubgroupAllKHR: *hasResult = true; *hasResultType = true; break;
case OpSubgroupAnyKHR: *hasResult = true; *hasResultType = true; break;
case OpSubgroupAllEqualKHR: *hasResult = true; *hasResultType = true; break;
+ case OpGroupNonUniformRotateKHR: *hasResult = true; *hasResultType = true; break;
case OpSubgroupReadInvocationKHR: *hasResult = true; *hasResultType = true; break;
case OpTraceRayKHR: *hasResult = false; *hasResultType = false; break;
case OpExecuteCallableKHR: *hasResult = false; *hasResultType = false; break;
@@ -2499,6 +2521,16 @@
case OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
+ case OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
+ case OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
+ case OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
+ case OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
+ case OpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
+ case OpGroupBitwiseOrKHR: *hasResult = true; *hasResultType = true; break;
+ case OpGroupBitwiseXorKHR: *hasResult = true; *hasResultType = true; break;
+ case OpGroupLogicalAndKHR: *hasResult = true; *hasResultType = true; break;
+ case OpGroupLogicalOrKHR: *hasResult = true; *hasResultType = true; break;
+ case OpGroupLogicalXorKHR: *hasResult = true; *hasResultType = true; break;
}
}
#endif /* SPV_ENABLE_UTILITY_CODE */
diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11
index a5de0be..961b3fd 100644
--- a/include/spirv/unified1/spirv.hpp11
+++ b/include/spirv/unified1/spirv.hpp11
@@ -66,6 +66,7 @@
OpenCL_CPP = 4,
HLSL = 5,
CPP_for_OpenCL = 6,
+ SYCL = 7,
Max = 0x7fffffff,
};
@@ -180,6 +181,7 @@
NoGlobalOffsetINTEL = 5895,
NumSIMDWorkitemsINTEL = 5896,
SchedulerTargetFmaxMhzINTEL = 5903,
+ NamedBarrierCountINTEL = 6417,
Max = 0x7fffffff,
};
@@ -675,6 +677,7 @@
SMCountNV = 5375,
WarpIDNV = 5376,
SMIDNV = 5377,
+ CullMaskKHR = 6021,
Max = 0x7fffffff,
};
@@ -1076,13 +1079,17 @@
DotProductInput4x8BitPackedKHR = 6018,
DotProduct = 6019,
DotProductKHR = 6019,
+ RayCullMaskKHR = 6020,
BitInstructions = 6025,
+ GroupNonUniformRotateKHR = 6026,
AtomicFloat32AddEXT = 6033,
AtomicFloat64AddEXT = 6034,
LongConstantCompositeINTEL = 6089,
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ SplitBarrierINTEL = 6141,
+ GroupUniformArithmeticKHR = 6400,
Max = 0x7fffffff,
};
@@ -1538,6 +1545,7 @@
OpSubgroupAllKHR = 4428,
OpSubgroupAnyKHR = 4429,
OpSubgroupAllEqualKHR = 4430,
+ OpGroupNonUniformRotateKHR = 4431,
OpSubgroupReadInvocationKHR = 4432,
OpTraceRayKHR = 4445,
OpExecuteCallableKHR = 4446,
@@ -1845,10 +1853,23 @@
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpControlBarrierArriveINTEL = 6142,
+ OpControlBarrierWaitINTEL = 6143,
+ OpGroupIMulKHR = 6401,
+ OpGroupFMulKHR = 6402,
+ OpGroupBitwiseAndKHR = 6403,
+ OpGroupBitwiseOrKHR = 6404,
+ OpGroupBitwiseXorKHR = 6405,
+ OpGroupLogicalAndKHR = 6406,
+ OpGroupLogicalOrKHR = 6407,
+ OpGroupLogicalXorKHR = 6408,
Max = 0x7fffffff,
};
#ifdef SPV_ENABLE_UTILITY_CODE
+#ifndef __cplusplus
+#include <stdbool.h>
+#endif
inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
*hasResult = *hasResultType = false;
switch (opcode) {
@@ -2203,6 +2224,7 @@
case Op::OpSubgroupAllKHR: *hasResult = true; *hasResultType = true; break;
case Op::OpSubgroupAnyKHR: *hasResult = true; *hasResultType = true; break;
case Op::OpSubgroupAllEqualKHR: *hasResult = true; *hasResultType = true; break;
+ case Op::OpGroupNonUniformRotateKHR: *hasResult = true; *hasResultType = true; break;
case Op::OpSubgroupReadInvocationKHR: *hasResult = true; *hasResultType = true; break;
case Op::OpTraceRayKHR: *hasResult = false; *hasResultType = false; break;
case Op::OpExecuteCallableKHR: *hasResult = false; *hasResultType = false; break;
@@ -2499,6 +2521,16 @@
case Op::OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break;
+ case Op::OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
+ case Op::OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
+ case Op::OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
+ case Op::OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
+ case Op::OpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
+ case Op::OpGroupBitwiseOrKHR: *hasResult = true; *hasResultType = true; break;
+ case Op::OpGroupBitwiseXorKHR: *hasResult = true; *hasResultType = true; break;
+ case Op::OpGroupLogicalAndKHR: *hasResult = true; *hasResultType = true; break;
+ case Op::OpGroupLogicalOrKHR: *hasResult = true; *hasResultType = true; break;
+ case Op::OpGroupLogicalXorKHR: *hasResult = true; *hasResultType = true; break;
}
}
#endif /* SPV_ENABLE_UTILITY_CODE */
diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json
index 34d157b..ec3e0a5 100644
--- a/include/spirv/unified1/spirv.json
+++ b/include/spirv/unified1/spirv.json
@@ -72,7 +72,8 @@
"OpenCL_C": 3,
"OpenCL_CPP": 4,
"HLSL": 5,
- "CPP_for_OpenCL": 6
+ "CPP_for_OpenCL": 6,
+ "SYCL": 7
}
},
{
@@ -198,7 +199,8 @@
"MaxWorkDimINTEL": 5894,
"NoGlobalOffsetINTEL": 5895,
"NumSIMDWorkitemsINTEL": 5896,
- "SchedulerTargetFmaxMhzINTEL": 5903
+ "SchedulerTargetFmaxMhzINTEL": 5903,
+ "NamedBarrierCountINTEL": 6417
}
},
{
@@ -703,7 +705,8 @@
"WarpsPerSMNV": 5374,
"SMCountNV": 5375,
"WarpIDNV": 5376,
- "SMIDNV": 5377
+ "SMIDNV": 5377,
+ "CullMaskKHR": 6021
}
},
{
@@ -1058,13 +1061,17 @@
"DotProductInput4x8BitPackedKHR": 6018,
"DotProduct": 6019,
"DotProductKHR": 6019,
+ "RayCullMaskKHR": 6020,
"BitInstructions": 6025,
+ "GroupNonUniformRotateKHR": 6026,
"AtomicFloat32AddEXT": 6033,
"AtomicFloat64AddEXT": 6034,
"LongConstantCompositeINTEL": 6089,
"OptNoneINTEL": 6094,
"AtomicFloat16AddEXT": 6095,
- "DebugInfoModuleINTEL": 6114
+ "DebugInfoModuleINTEL": 6114,
+ "SplitBarrierINTEL": 6141,
+ "GroupUniformArithmeticKHR": 6400
}
},
{
@@ -1531,6 +1538,7 @@
"OpSubgroupAllKHR": 4428,
"OpSubgroupAnyKHR": 4429,
"OpSubgroupAllEqualKHR": 4430,
+ "OpGroupNonUniformRotateKHR": 4431,
"OpSubgroupReadInvocationKHR": 4432,
"OpTraceRayKHR": 4445,
"OpExecuteCallableKHR": 4446,
@@ -1837,7 +1845,17 @@
"OpTypeBufferSurfaceINTEL": 6086,
"OpTypeStructContinuedINTEL": 6090,
"OpConstantCompositeContinuedINTEL": 6091,
- "OpSpecConstantCompositeContinuedINTEL": 6092
+ "OpSpecConstantCompositeContinuedINTEL": 6092,
+ "OpControlBarrierArriveINTEL": 6142,
+ "OpControlBarrierWaitINTEL": 6143,
+ "OpGroupIMulKHR": 6401,
+ "OpGroupFMulKHR": 6402,
+ "OpGroupBitwiseAndKHR": 6403,
+ "OpGroupBitwiseOrKHR": 6404,
+ "OpGroupBitwiseXorKHR": 6405,
+ "OpGroupLogicalAndKHR": 6406,
+ "OpGroupLogicalOrKHR": 6407,
+ "OpGroupLogicalXorKHR": 6408
}
}
]
diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua
index 6d512a6..69cc45d 100644
--- a/include/spirv/unified1/spirv.lua
+++ b/include/spirv/unified1/spirv.lua
@@ -57,6 +57,7 @@
OpenCL_CPP = 4,
HLSL = 5,
CPP_for_OpenCL = 6,
+ SYCL = 7,
},
ExecutionModel = {
@@ -167,6 +168,7 @@
NoGlobalOffsetINTEL = 5895,
NumSIMDWorkitemsINTEL = 5896,
SchedulerTargetFmaxMhzINTEL = 5903,
+ NamedBarrierCountINTEL = 6417,
},
StorageClass = {
@@ -647,6 +649,7 @@
SMCountNV = 5375,
WarpIDNV = 5376,
SMIDNV = 5377,
+ CullMaskKHR = 6021,
},
SelectionControlShift = {
@@ -1038,13 +1041,17 @@
DotProductInput4x8BitPackedKHR = 6018,
DotProduct = 6019,
DotProductKHR = 6019,
+ RayCullMaskKHR = 6020,
BitInstructions = 6025,
+ GroupNonUniformRotateKHR = 6026,
AtomicFloat32AddEXT = 6033,
AtomicFloat64AddEXT = 6034,
LongConstantCompositeINTEL = 6089,
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ SplitBarrierINTEL = 6141,
+ GroupUniformArithmeticKHR = 6400,
},
RayFlagsShift = {
@@ -1489,6 +1496,7 @@
OpSubgroupAllKHR = 4428,
OpSubgroupAnyKHR = 4429,
OpSubgroupAllEqualKHR = 4430,
+ OpGroupNonUniformRotateKHR = 4431,
OpSubgroupReadInvocationKHR = 4432,
OpTraceRayKHR = 4445,
OpExecuteCallableKHR = 4446,
@@ -1796,6 +1804,16 @@
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpControlBarrierArriveINTEL = 6142,
+ OpControlBarrierWaitINTEL = 6143,
+ OpGroupIMulKHR = 6401,
+ OpGroupFMulKHR = 6402,
+ OpGroupBitwiseAndKHR = 6403,
+ OpGroupBitwiseOrKHR = 6404,
+ OpGroupBitwiseXorKHR = 6405,
+ OpGroupLogicalAndKHR = 6406,
+ OpGroupLogicalOrKHR = 6407,
+ OpGroupLogicalXorKHR = 6408,
},
}
diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py
index 66cde27..7db0861 100644
--- a/include/spirv/unified1/spirv.py
+++ b/include/spirv/unified1/spirv.py
@@ -57,6 +57,7 @@
'OpenCL_CPP' : 4,
'HLSL' : 5,
'CPP_for_OpenCL' : 6,
+ 'SYCL' : 7,
},
'ExecutionModel' : {
@@ -167,6 +168,7 @@
'NoGlobalOffsetINTEL' : 5895,
'NumSIMDWorkitemsINTEL' : 5896,
'SchedulerTargetFmaxMhzINTEL' : 5903,
+ 'NamedBarrierCountINTEL' : 6417,
},
'StorageClass' : {
@@ -647,6 +649,7 @@
'SMCountNV' : 5375,
'WarpIDNV' : 5376,
'SMIDNV' : 5377,
+ 'CullMaskKHR' : 6021,
},
'SelectionControlShift' : {
@@ -1038,13 +1041,17 @@
'DotProductInput4x8BitPackedKHR' : 6018,
'DotProduct' : 6019,
'DotProductKHR' : 6019,
+ 'RayCullMaskKHR' : 6020,
'BitInstructions' : 6025,
+ 'GroupNonUniformRotateKHR' : 6026,
'AtomicFloat32AddEXT' : 6033,
'AtomicFloat64AddEXT' : 6034,
'LongConstantCompositeINTEL' : 6089,
'OptNoneINTEL' : 6094,
'AtomicFloat16AddEXT' : 6095,
'DebugInfoModuleINTEL' : 6114,
+ 'SplitBarrierINTEL' : 6141,
+ 'GroupUniformArithmeticKHR' : 6400,
},
'RayFlagsShift' : {
@@ -1489,6 +1496,7 @@
'OpSubgroupAllKHR' : 4428,
'OpSubgroupAnyKHR' : 4429,
'OpSubgroupAllEqualKHR' : 4430,
+ 'OpGroupNonUniformRotateKHR' : 4431,
'OpSubgroupReadInvocationKHR' : 4432,
'OpTraceRayKHR' : 4445,
'OpExecuteCallableKHR' : 4446,
@@ -1796,6 +1804,16 @@
'OpTypeStructContinuedINTEL' : 6090,
'OpConstantCompositeContinuedINTEL' : 6091,
'OpSpecConstantCompositeContinuedINTEL' : 6092,
+ 'OpControlBarrierArriveINTEL' : 6142,
+ 'OpControlBarrierWaitINTEL' : 6143,
+ 'OpGroupIMulKHR' : 6401,
+ 'OpGroupFMulKHR' : 6402,
+ 'OpGroupBitwiseAndKHR' : 6403,
+ 'OpGroupBitwiseOrKHR' : 6404,
+ 'OpGroupBitwiseXorKHR' : 6405,
+ 'OpGroupLogicalAndKHR' : 6406,
+ 'OpGroupLogicalOrKHR' : 6407,
+ 'OpGroupLogicalXorKHR' : 6408,
},
}
diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d
index c9b443c..387c4ff 100644
--- a/include/spirv/unified1/spv.d
+++ b/include/spirv/unified1/spv.d
@@ -65,6 +65,7 @@
OpenCL_CPP = 4,
HLSL = 5,
CPP_for_OpenCL = 6,
+ SYCL = 7,
}
enum ExecutionModel : uint
@@ -179,6 +180,7 @@
NoGlobalOffsetINTEL = 5895,
NumSIMDWorkitemsINTEL = 5896,
SchedulerTargetFmaxMhzINTEL = 5903,
+ NamedBarrierCountINTEL = 6417,
}
enum StorageClass : uint
@@ -676,6 +678,7 @@
SMCountNV = 5375,
WarpIDNV = 5376,
SMIDNV = 5377,
+ CullMaskKHR = 6021,
}
enum SelectionControlShift : uint
@@ -1083,13 +1086,17 @@
DotProductInput4x8BitPackedKHR = 6018,
DotProduct = 6019,
DotProductKHR = 6019,
+ RayCullMaskKHR = 6020,
BitInstructions = 6025,
+ GroupNonUniformRotateKHR = 6026,
AtomicFloat32AddEXT = 6033,
AtomicFloat64AddEXT = 6034,
LongConstantCompositeINTEL = 6089,
OptNoneINTEL = 6094,
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
+ SplitBarrierINTEL = 6141,
+ GroupUniformArithmeticKHR = 6400,
}
enum RayFlagsShift : uint
@@ -1547,6 +1554,7 @@
OpSubgroupAllKHR = 4428,
OpSubgroupAnyKHR = 4429,
OpSubgroupAllEqualKHR = 4430,
+ OpGroupNonUniformRotateKHR = 4431,
OpSubgroupReadInvocationKHR = 4432,
OpTraceRayKHR = 4445,
OpExecuteCallableKHR = 4446,
@@ -1854,6 +1862,16 @@
OpTypeStructContinuedINTEL = 6090,
OpConstantCompositeContinuedINTEL = 6091,
OpSpecConstantCompositeContinuedINTEL = 6092,
+ OpControlBarrierArriveINTEL = 6142,
+ OpControlBarrierWaitINTEL = 6143,
+ OpGroupIMulKHR = 6401,
+ OpGroupFMulKHR = 6402,
+ OpGroupBitwiseAndKHR = 6403,
+ OpGroupBitwiseOrKHR = 6404,
+ OpGroupBitwiseXorKHR = 6405,
+ OpGroupLogicalAndKHR = 6406,
+ OpGroupLogicalOrKHR = 6407,
+ OpGroupLogicalXorKHR = 6408,
}
diff --git a/tools/buildHeaders/header.cpp b/tools/buildHeaders/header.cpp
index febc6f2..f2f16b3 100644
--- a/tools/buildHeaders/header.cpp
+++ b/tools/buildHeaders/header.cpp
@@ -513,6 +513,9 @@
}
out << "#ifdef SPV_ENABLE_UTILITY_CODE" << std::endl;
+ out << "#ifndef __cplusplus" << std::endl;
+ out << "#include <stdbool.h>" << std::endl;
+ out << "#endif" << std::endl;
out << "inline void " << pre() << "HasResultAndType(" << pre() << opName << " opcode, bool *hasResult, bool *hasResultType) {" << std::endl;
out << " *hasResult = *hasResultType = false;" << std::endl;
out << " switch (opcode) {" << std::endl;
