ARM32 vector division lowering.

Enables vector division by scalarization.

Also, removed an assert as suggested by Karl in a previous CL:
https://codereview.chromium.org/1646033002/diff/1/src/IceInstARM32.cpp#newcode717

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4076
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1681003002 .
diff --git a/src/IceTargetLoweringARM32.cpp b/src/IceTargetLoweringARM32.cpp
index 9fa218bd..1dde797 100644
--- a/src/IceTargetLoweringARM32.cpp
+++ b/src/IceTargetLoweringARM32.cpp
@@ -430,6 +430,18 @@
     const Type DestTy = Dest->getType();
     const InstArithmetic::OpKind Op =
         llvm::cast<InstArithmetic>(Instr)->getOp();
+    if (isVectorType(DestTy)) {
+      switch (Op) {
+      default:
+        break;
+      case InstArithmetic::Fdiv:
+      case InstArithmetic::Udiv:
+      case InstArithmetic::Sdiv:
+        scalarizeArithmetic(Op, Dest, Instr->getSrc(0), Instr->getSrc(1));
+        Instr->setDeleted();
+        return;
+      }
+    }
     switch (DestTy) {
     default:
       return;
@@ -2015,7 +2027,8 @@
   Variable *SrcLoReg = legalizeToReg(SrcLo);
   switch (Ty) {
   default:
-    llvm::report_fatal_error("Unexpected type");
+    llvm_unreachable(
+        ("Unexpected type in div0Check: " + typeIceString(Ty)).c_str());
   case IceType_i8:
   case IceType_i16: {
     Operand *ShAmtImm = shAmtImm(32 - getScalarIntBitWidth(Ty));
@@ -5508,7 +5521,8 @@
 Variable *TargetARM32::makeVectorOfZeros(Type Ty, int32_t RegNum) {
   Variable *Reg = makeReg(Ty, RegNum);
   Context.insert<InstFakeDef>(Reg);
-  UnimplementedError(Func->getContext()->getFlags());
+  assert(isVectorType(Ty));
+  _veor(Reg, Reg, Reg);
   return Reg;
 }