commit cad0b7597cdee839950dae55fccaaa7b54734d79
author Eric Holk <eholk@chromium.org> Wed Jan 27 14:56:22 2016 -0800
committer Eric Holk <eholk@chromium.org> Wed Jan 27 14:56:22 2016 -0800
tree b3698e8c8c3e806cb23b3c0756eaae074ddf5185
parent e37076a176e04eee0f35058ccd2109754c193015

ARM32 vorr lowering

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4076
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1639403004 .

src/IceInstARM32.cpp

diff --git a/src/IceInstARM32.cpp b/src/IceInstARM32.cpp
index be8488c..9ca1085 100644
--- a/src/IceInstARM32.cpp
+++ b/src/IceInstARM32.cpp
@@ -673,6 +673,11 @@
   }
 }
 
+template <> void InstARM32Vorr::emitIAS(const Cfg *Func) const {
+  // TODO(kschimpf): add support for these instructions
+  emitUsingTextFixup(Func);
+}
+
 template <> void InstARM32Vsub::emitIAS(const Cfg *Func) const {
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   const Variable *Dest = getDest();
@@ -1040,6 +1045,7 @@
 template <> const char *InstARM32Vmla::Opcode = "vmla";
 template <> const char *InstARM32Vmls::Opcode = "vmls";
 template <> const char *InstARM32Vmul::Opcode = "vmul";
+template <> const char *InstARM32Vorr::Opcode = "vorr";
 template <> const char *InstARM32Vsub::Opcode = "vsub";
 // Four-addr ops
 template <> const char *InstARM32Mla::Opcode = "mla";

src/IceInstARM32.h

diff --git a/src/IceInstARM32.h b/src/IceInstARM32.h
index 2d51e89..413f0f5 100644
--- a/src/IceInstARM32.h
+++ b/src/IceInstARM32.h
@@ -431,6 +431,7 @@
     Vmls,
     Vmrs,
     Vmul,
+    Vorr,
     Vsqrt,
     Vsub
   };
@@ -925,6 +926,7 @@
 using InstARM32Vmla = InstARM32FourAddrFP<InstARM32::Vmla>;
 using InstARM32Vmls = InstARM32FourAddrFP<InstARM32::Vmls>;
 using InstARM32Vmul = InstARM32ThreeAddrFP<InstARM32::Vmul>;
+using InstARM32Vorr = InstARM32ThreeAddrFP<InstARM32::Vorr>;
 using InstARM32Vsub = InstARM32ThreeAddrFP<InstARM32::Vsub>;
 using InstARM32Ldr = InstARM32LoadBase<InstARM32::Ldr>;
 using InstARM32Ldrex = InstARM32LoadBase<InstARM32::Ldrex>;

src/IceTargetLoweringARM32.cpp

diff --git a/src/IceTargetLoweringARM32.cpp b/src/IceTargetLoweringARM32.cpp
index f836fe5..4b2dc98 100644
--- a/src/IceTargetLoweringARM32.cpp
+++ b/src/IceTargetLoweringARM32.cpp
@@ -2808,6 +2808,7 @@
     case InstArithmetic::Fsub:
     case InstArithmetic::Sub:
     case InstArithmetic::And:
+    case InstArithmetic::Or:
       break;
     }
   }
@@ -2968,8 +2969,13 @@
   }
   case InstArithmetic::Or: {
     Variable *Src0R = Srcs.src0R(this);
-    Operand *Src1RF = Srcs.src1RF(this);
-    _orr(T, Src0R, Src1RF);
+    if (isVectorType(DestTy)) {
+      Variable *Src1R = legalizeToReg(Src1);
+      _vorr(T, Src0R, Src1R);
+    } else {
+      Operand *Src1RF = Srcs.src1RF(this);
+      _orr(T, Src0R, Src1RF);
+    }
     _mov(Dest, T);
     return;
   }

src/IceTargetLoweringARM32.h

diff --git a/src/IceTargetLoweringARM32.h b/src/IceTargetLoweringARM32.h
index 8779beb..b8c1040 100644
--- a/src/IceTargetLoweringARM32.h
+++ b/src/IceTargetLoweringARM32.h
@@ -802,6 +802,9 @@
   void _vmul(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstARM32Vmul>(Dest, Src0, Src1);
   }
+  void _vorr(Variable *Dest, Variable *Src0, Variable *Src1) {
+    Context.insert<InstARM32Vorr>(Dest, Src0, Src1);
+  }
   void _vsqrt(Variable *Dest, Variable *Src,
               CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32Vsqrt>(Dest, Src, Pred);