/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Assembly Matcher Source Fragment                                           *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_ASSEMBLER_HEADER
#undef GET_ASSEMBLER_HEADER
  // This should be included into the middle of the declaration of
  // your subclasses implementation of MCTargetAsmParser.
  uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;
  void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
                       const OperandVector &Operands);
  void convertToMapAndConstraints(unsigned Kind,
                           const OperandVector &Operands) override;
  unsigned MatchInstructionImpl(const OperandVector &Operands,
                                MCInst &Inst,
                                uint64_t &ErrorInfo,
                                bool matchingInlineAsm,
                                unsigned VariantID = 0);
  OperandMatchResultTy MatchOperandParserImpl(
    OperandVector &Operands,
    StringRef Mnemonic,
    bool ParseForAllFeatures = false);
  OperandMatchResultTy tryCustomParseOperand(
    OperandVector &Operands,
    unsigned MCK);

#endif // GET_ASSEMBLER_HEADER_INFO


#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
#undef GET_OPERAND_DIAGNOSTIC_TYPES

  Match_Immz,
  Match_MemSImm10,
  Match_MemSImm10Lsl1,
  Match_MemSImm10Lsl2,
  Match_MemSImm10Lsl3,
  Match_MemSImm11,
  Match_MemSImm12,
  Match_MemSImm16,
  Match_MemSImm9,
  Match_MemSImmPtr,
  Match_SImm10_0,
  Match_SImm10_Lsl1,
  Match_SImm10_Lsl2,
  Match_SImm10_Lsl3,
  Match_SImm11_0,
  Match_SImm16,
  Match_SImm16_Relaxed,
  Match_SImm19_Lsl2,
  Match_SImm32,
  Match_SImm32_Relaxed,
  Match_SImm4_0,
  Match_SImm5_0,
  Match_SImm6_0,
  Match_SImm7_Lsl2,
  Match_SImm9_0,
  Match_UImm10_0,
  Match_UImm16,
  Match_UImm16_AltRelaxed,
  Match_UImm16_Relaxed,
  Match_UImm1_0,
  Match_UImm20_0,
  Match_UImm26_0,
  Match_UImm2_0,
  Match_UImm2_1,
  Match_UImm32_Coerced,
  Match_UImm3_0,
  Match_UImm4_0,
  Match_UImm5_0,
  Match_UImm5_0_Report_UImm6,
  Match_UImm5_1,
  Match_UImm5_32,
  Match_UImm5_33,
  Match_UImm5_Lsl2,
  Match_UImm6_0,
  Match_UImm6_Lsl2,
  Match_UImm7_0,
  Match_UImm7_N1,
  Match_UImm8_0,
  Match_UImmRange2_64,
  END_OPERAND_DIAGNOSTIC_TYPES
#endif // GET_OPERAND_DIAGNOSTIC_TYPES


#ifdef GET_REGISTER_MATCHER
#undef GET_REGISTER_MATCHER

// Flags for subtarget features that participate in instruction matching.
enum SubtargetFeatureFlag : uint64_t {
  Feature_HasMips2 = (1ULL << 10),
  Feature_HasMips3_32 = (1ULL << 16),
  Feature_HasMips3_32r2 = (1ULL << 17),
  Feature_HasMips3 = (1ULL << 11),
  Feature_NotMips3 = (1ULL << 44),
  Feature_HasMips4_32 = (1ULL << 18),
  Feature_NotMips4_32 = (1ULL << 46),
  Feature_HasMips4_32r2 = (1ULL << 19),
  Feature_HasMips5_32r2 = (1ULL << 20),
  Feature_HasMips32 = (1ULL << 12),
  Feature_HasMips32r2 = (1ULL << 13),
  Feature_HasMips32r5 = (1ULL << 14),
  Feature_HasMips32r6 = (1ULL << 15),
  Feature_NotMips32r6 = (1ULL << 45),
  Feature_IsGP64bit = (1ULL << 31),
  Feature_IsGP32bit = (1ULL << 30),
  Feature_IsPTR64bit = (1ULL << 35),
  Feature_IsPTR32bit = (1ULL << 34),
  Feature_HasMips64 = (1ULL << 21),
  Feature_NotMips64 = (1ULL << 47),
  Feature_HasMips64r2 = (1ULL << 22),
  Feature_HasMips64r5 = (1ULL << 23),
  Feature_HasMips64r6 = (1ULL << 24),
  Feature_NotMips64r6 = (1ULL << 48),
  Feature_InMips16Mode = (1ULL << 28),
  Feature_NotInMips16Mode = (1ULL << 43),
  Feature_HasCnMips = (1ULL << 1),
  Feature_NotCnMips = (1ULL << 40),
  Feature_IsSym32 = (1ULL << 37),
  Feature_IsSym64 = (1ULL << 38),
  Feature_HasStdEnc = (1ULL << 25),
  Feature_InMicroMips = (1ULL << 27),
  Feature_NotInMicroMips = (1ULL << 42),
  Feature_HasEVA = (1ULL << 5),
  Feature_HasMSA = (1ULL << 7),
  Feature_HasMadd4 = (1ULL << 9),
  Feature_HasMT = (1ULL << 8),
  Feature_UseIndirectJumpsHazard = (1ULL << 49),
  Feature_NoIndirectJumpGuards = (1ULL << 39),
  Feature_HasCRC = (1ULL << 0),
  Feature_HasVirt = (1ULL << 26),
  Feature_HasGINV = (1ULL << 6),
  Feature_IsFP64bit = (1ULL << 29),
  Feature_NotFP64bit = (1ULL << 41),
  Feature_IsSingleFloat = (1ULL << 36),
  Feature_IsNotSingleFloat = (1ULL << 32),
  Feature_IsNotSoftFloat = (1ULL << 33),
  Feature_HasDSP = (1ULL << 2),
  Feature_HasDSPR2 = (1ULL << 3),
  Feature_HasDSPR3 = (1ULL << 4),
  Feature_None = 0
};

#endif // GET_REGISTER_MATCHER


#ifdef GET_SUBTARGET_FEATURE_NAME
#undef GET_SUBTARGET_FEATURE_NAME

// User-level names for subtarget features that participate in
// instruction matching.
static const char *getSubtargetFeatureName(uint64_t Val) {
  switch(Val) {
  case Feature_HasMips2: return "";
  case Feature_HasMips3_32: return "";
  case Feature_HasMips3_32r2: return "";
  case Feature_HasMips3: return "";
  case Feature_NotMips3: return "";
  case Feature_HasMips4_32: return "";
  case Feature_NotMips4_32: return "";
  case Feature_HasMips4_32r2: return "";
  case Feature_HasMips5_32r2: return "";
  case Feature_HasMips32: return "";
  case Feature_HasMips32r2: return "";
  case Feature_HasMips32r5: return "";
  case Feature_HasMips32r6: return "";
  case Feature_NotMips32r6: return "";
  case Feature_IsGP64bit: return "";
  case Feature_IsGP32bit: return "";
  case Feature_IsPTR64bit: return "";
  case Feature_IsPTR32bit: return "";
  case Feature_HasMips64: return "";
  case Feature_NotMips64: return "";
  case Feature_HasMips64r2: return "";
  case Feature_HasMips64r5: return "";
  case Feature_HasMips64r6: return "";
  case Feature_NotMips64r6: return "";
  case Feature_InMips16Mode: return "";
  case Feature_NotInMips16Mode: return "";
  case Feature_HasCnMips: return "";
  case Feature_NotCnMips: return "";
  case Feature_IsSym32: return "";
  case Feature_IsSym64: return "";
  case Feature_HasStdEnc: return "";
  case Feature_InMicroMips: return "";
  case Feature_NotInMicroMips: return "";
  case Feature_HasEVA: return "";
  case Feature_HasMSA: return "";
  case Feature_HasMadd4: return "";
  case Feature_HasMT: return "";
  case Feature_UseIndirectJumpsHazard: return "";
  case Feature_NoIndirectJumpGuards: return "";
  case Feature_HasCRC: return "";
  case Feature_HasVirt: return "";
  case Feature_HasGINV: return "";
  case Feature_IsFP64bit: return "";
  case Feature_NotFP64bit: return "";
  case Feature_IsSingleFloat: return "";
  case Feature_IsNotSingleFloat: return "";
  case Feature_IsNotSoftFloat: return "";
  case Feature_HasDSP: return "";
  case Feature_HasDSPR2: return "";
  case Feature_HasDSPR3: return "";
  default: return "(unknown)";
  }
}

#endif // GET_SUBTARGET_FEATURE_NAME


#ifdef GET_MATCHER_IMPLEMENTATION
#undef GET_MATCHER_IMPLEMENTATION

enum {
  Tie0_1_1,
  Tie0_1_2,
};

static const uint8_t TiedAsmOperandTable[][3] = {
  /* Tie0_1_1 */ { 0, 1, 1 },
  /* Tie0_1_2 */ { 0, 1, 2 },
};

namespace {
enum OperatorConversionKind {
  CVT_Done,
  CVT_Reg,
  CVT_Tied,
  CVT_95_addGPR32AsmRegOperands,
  CVT_95_addAFGR64AsmRegOperands,
  CVT_95_addFGR64AsmRegOperands,
  CVT_95_addFGR32AsmRegOperands,
  CVT_95_addSImmOperands_LT_32_GT_,
  CVT_95_addMSA128AsmRegOperands,
  CVT_95_addSImmOperands_LT_16_GT_,
  CVT_95_Reg,
  CVT_95_addImmOperands,
  CVT_95_addGPRMM16AsmRegOperands,
  CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_,
  CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_,
  CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_,
  CVT_95_addUImmOperands_LT_16_GT_,
  CVT_95_addGPR64AsmRegOperands,
  CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_,
  CVT_regZERO,
  CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_,
  CVT_regFCC0,
  CVT_95_addFCCAsmRegOperands,
  CVT_95_addCOP2AsmRegOperands,
  CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_,
  CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_,
  CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_,
  CVT_imm_95_0,
  CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_,
  CVT_95_addMemOperands,
  CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_,
  CVT_95_addCCRAsmRegOperands,
  CVT_95_addMSACtrlAsmRegOperands,
  CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_,
  CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_,
  CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_,
  CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_,
  CVT_95_addGPR32NonZeroAsmRegOperands,
  CVT_95_addGPR32ZeroAsmRegOperands,
  CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_,
  CVT_95_addCOP0AsmRegOperands,
  CVT_regZERO_64,
  CVT_95_addACC64DSPAsmRegOperands,
  CVT_95_addConstantUImmOperands_LT_1_GT_,
  CVT_regRA,
  CVT_regRA_64,
  CVT_95_addMicroMipsMemOperands,
  CVT_95_addCOP3AsmRegOperands,
  CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_,
  CVT_95_addConstantUImmOperands_LT_32_GT_,
  CVT_95_addStrictlyAFGR64AsmRegOperands,
  CVT_95_addStrictlyFGR64AsmRegOperands,
  CVT_95_addStrictlyFGR32AsmRegOperands,
  CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_,
  CVT_95_addRegListOperands,
  CVT_ConvertXWPOperands,
  CVT_regAC0,
  CVT_95_addMovePRegPairOperands,
  CVT_95_addGPRMM16AsmRegMovePOperands,
  CVT_95_addHI32DSPAsmRegOperands,
  CVT_95_addLO32DSPAsmRegOperands,
  CVT_regS0,
  CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_,
  CVT_95_addHWRegsAsmRegOperands,
  CVT_95_addGPRMM16AsmRegZeroOperands,
  CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_,
  CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_,
  CVT_imm_95_2,
  CVT_imm_95_6,
  CVT_imm_95_4,
  CVT_imm_95_5,
  CVT_imm_95_31,
  CVT_NUM_CONVERTERS
};

enum InstructionConversionKind {
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1,
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1,
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1,
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2,
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2,
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1,
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2,
  Convert__SImm161_1,
  Convert__Reg1_0__SImm161_1,
  Convert__Reg1_0__SImm161_2,
  Convert__Reg1_0__Reg1_1__SImm161_2,
  Convert__Reg1_0__Tie0_1_1__SImm161_1,
  Convert__GPR32AsmReg1_0__Simm19_Lsl21_1,
  Convert__GPRMM16AsmReg1_0__Imm1_1,
  Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1,
  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2,
  Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1,
  Convert__Imm1_0,
  Convert__Reg1_0__Reg1_1__Reg1_2,
  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2,
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3,
  Convert__GPR32AsmReg1_0__SImm161_1,
  Convert__Reg1_0__Tie0_1_1__Reg1_1,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2,
  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1,
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1,
  Convert__regZERO__regZERO__JumpTarget1_0,
  Convert__JumpTarget1_0,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2,
  Convert__regZERO__JumpTarget1_0,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1,
  Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2,
  Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2,
  Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2,
  Convert__FGR64AsmReg1_0__JumpTarget1_1,
  Convert__regFCC0__JumpTarget1_0,
  Convert__FCCAsmReg1_0__JumpTarget1_1,
  Convert__COP2AsmReg1_0__JumpTarget1_1,
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2,
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2,
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2,
  Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2,
  Convert__Reg1_0__JumpTarget1_1,
  Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1,
  Convert__GPRMM16AsmReg1_0__JumpTarget1_1,
  Convert__GPR32AsmReg1_0__JumpTarget1_1,
  Convert__GPR64AsmReg1_0__JumpTarget1_1,
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2,
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2,
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2,
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2,
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2,
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2,
  Convert__MSA128AsmReg1_0__JumpTarget1_1,
  Convert__imm_95_0__imm_95_0,
  Convert_NoOperands,
  Convert__ConstantUImm10_01_0__imm_95_0,
  Convert__ConstantUImm10_01_0__ConstantUImm10_01_1,
  Convert__ConstantUImm4_01_0,
  Convert__SImm161_0,
  Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1,
  Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1,
  Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2,
  Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
  Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1,
  Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
  Convert__MemOffsetSimm92_1__ConstantUImm5_01_0,
  Convert__Mem2_1__ConstantUImm5_01_0,
  Convert__FGR64AsmReg1_0__FGR32AsmReg1_1,
  Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1,
  Convert__FGR32AsmReg1_0__FGR64AsmReg1_1,
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2,
  Convert__GPR32AsmReg1_0__CCRAsmReg1_1,
  Convert__GPR32AsmReg1_0__COP2AsmReg1_1,
  Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1,
  Convert__GPR32AsmReg1_0__FGR32AsmReg1_1,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3,
  Convert__Reg1_0__Reg1_1,
  Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
  Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3,
  Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3,
  Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3,
  Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3,
  Convert__CCRAsmReg1_1__GPR32AsmReg1_0,
  Convert__COP2AsmReg1_1__GPR32AsmReg1_0,
  Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1,
  Convert__FGR32AsmReg1_1__GPR32AsmReg1_0,
  Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2,
  Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1,
  Convert__GPR64AsmReg1_1__GPR64AsmReg1_2,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3,
  Convert__regZERO,
  Convert__GPR32AsmReg1_0,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1,
  Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1,
  Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1,
  Convert__Reg1_1__Reg1_2,
  Convert__GPR32AsmReg1_1__GPR32AsmReg1_2,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2,
  Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
  Convert__GPR64AsmReg1_0__Imm1_1,
  Convert__GPR64AsmReg1_0__Mem2_1,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3,
  Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0,
  Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2,
  Convert__GPR64AsmReg1_0__FGR64AsmReg1_1,
  Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0,
  Convert__GPR64AsmReg1_0__UImm161_1,
  Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2,
  Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0,
  Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2,
  Convert__FGR64AsmReg1_1__GPR64AsmReg1_0,
  Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0,
  Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2,
  Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0,
  Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1,
  Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3,
  Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2,
  Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2,
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1,
  Convert__MSA128AsmReg1_0__GPR32AsmReg1_1,
  Convert__MSA128AsmReg1_0__GPR64AsmReg1_1,
  Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2,
  Convert__GPR32AsmReg1_0__ConstantUImm2_01_1,
  Convert__imm_95_0,
  Convert__ConstantUImm10_01_0,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1,
  Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2,
  Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2,
  Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2,
  Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2,
  Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1,
  Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
  Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
  Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
  Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
  Convert__regRA__GPR32AsmReg1_0,
  Convert__regRA_64__GPR64AsmReg1_0,
  Convert__Reg1_0,
  Convert__GPR32AsmReg1_0__imm_95_0,
  Convert__GPR64AsmReg1_0__imm_95_0,
  Convert__regZERO__GPR32AsmReg1_0,
  Convert__GPR64AsmReg1_0,
  Convert__regZERO_64__GPR64AsmReg1_0,
  Convert__UImm5Lsl21_0,
  Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1,
  Convert__FGR64AsmReg1_0__MemOffsetSimm162_1,
  Convert__FGR32AsmReg1_0__MemOffsetSimm162_1,
  Convert__GPR32AsmReg1_0__Imm1_1,
  Convert__GPR32AsmReg1_0__Mem2_1,
  Convert__GPR32AsmReg1_0__MemOffsetSimm162_1,
  Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1,
  Convert__GPR32AsmReg1_0__MemOffsetSimm92_1,
  Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
  Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1,
  Convert__MSA128AsmReg1_0__MemOffsetSimm102_1,
  Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1,
  Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1,
  Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1,
  Convert__COP2AsmReg1_0__MemOffsetSimm112_1,
  Convert__COP2AsmReg1_0__MemOffsetSimm162_1,
  Convert__COP3AsmReg1_0__Mem2_1,
  Convert__MSA128AsmReg1_0__ConstantSImm10_01_1,
  Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1,
  Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
  Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
  Convert__GPR32AsmReg1_0__UImm32_Coerced1_1,
  Convert__StrictlyAFGR64AsmReg1_0__Imm1_1,
  Convert__StrictlyFGR64AsmReg1_0__Imm1_1,
  Convert__StrictlyFGR32AsmReg1_0__Imm1_1,
  Convert__GPRMM16AsmReg1_0__UImm7_N11_1,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3,
  Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3,
  Convert__GPR32AsmReg1_0__UImm161_1,
  Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1,
  Convert__Reg1_0__Imm1_1__imm_95_0,
  Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1,
  Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1,
  Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1,
  Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1,
  Convert__RegList1_0__Mem2_1,
  Convert__RegList161_0__MemOffsetUimm42_1,
  ConvertCustom_ConvertXWPOperands,
  Convert__GPR32AsmReg1_0__MemOffsetSimm122_1,
  Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3,
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3,
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3,
  Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2,
  Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2,
  Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0,
  Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2,
  Convert__GPR32AsmReg1_0__FGR64AsmReg1_1,
  Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0,
  Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2,
  Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1,
  Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1,
  Convert__GPR32AsmReg1_0__regAC0,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64,
  Convert__MovePRegPair2_0__GPRMM16AsmRegMoveP1_1__GPRMM16AsmRegMoveP1_2,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
  Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0,
  Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2,
  Convert__FGR64AsmReg1_1__GPR32AsmReg1_0,
  Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0,
  Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2,
  Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0,
  Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0,
  Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0,
  Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1,
  Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0,
  Convert__regAC0__GPR32AsmReg1_0,
  Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0,
  Convert__GPR32AsmReg1_1__GPR32AsmReg1_0,
  Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4,
  Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
  Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0,
  Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1,
  Convert__regZERO__regZERO__imm_95_0,
  Convert__regZERO__regS0,
  Convert__regZERO__regZERO,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO,
  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0,
  Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0,
  Convert__GPR32AsmReg1_0__ConstantUImm7_01_1,
  Convert__GPR32AsmReg1_0__ConstantUImm10_01_1,
  Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0,
  Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2,
  Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2,
  Convert__GPR32AsmReg1_0__ConstantSImm10_01_1,
  Convert__GPR32AsmReg1_0__ConstantUImm8_01_1,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2,
  Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1,
  Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1,
  Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1,
  Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1,
  Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1,
  Convert__ConstantUImm20_01_0,
  Convert__Reg1_0__Tie0_1_1,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1,
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1,
  Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1,
  Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2,
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3,
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3,
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3,
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3,
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3,
  Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2,
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3,
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3,
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3,
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3,
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2,
  Convert__ConstantUImm5_01_0,
  Convert__MemOffsetSimm162_0,
  Convert__imm_95_2,
  Convert__imm_95_6,
  Convert__imm_95_4,
  Convert__imm_95_5,
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2,
  Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2,
  Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2,
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2,
  Convert__GPR32AsmReg1_0__imm_95_31,
  CVT_NUM_SIGNATURES
};

} // end anonymous namespace

static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][11] = {
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done },
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
  // Convert__SImm161_1
  { CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
  // Convert__Reg1_0__SImm161_1
  { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
  // Convert__Reg1_0__SImm161_2
  { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
  // Convert__Reg1_0__Reg1_1__SImm161_2
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
  // Convert__Reg1_0__Tie0_1_1__SImm161_1
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__Simm19_Lsl21_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
  // Convert__GPRMM16AsmReg1_0__Imm1_1
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
  // Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
  // Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_, 2, CVT_Done },
  // Convert__Imm1_0
  { CVT_95_addImmOperands, 1, CVT_Done },
  // Convert__Reg1_0__Reg1_1__Reg1_2
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addGPRMM16AsmRegOperands, 3, CVT_Done },
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
  // Convert__GPR32AsmReg1_0__SImm161_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
  // Convert__Reg1_0__Tie0_1_1__Reg1_1
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done },
  // Convert__regZERO__regZERO__JumpTarget1_0
  { CVT_regZERO, 0, CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done },
  // Convert__JumpTarget1_0
  { CVT_95_addImmOperands, 1, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
  // Convert__regZERO__JumpTarget1_0
  { CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done },
  // Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
  // Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
  // Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
  // Convert__FGR64AsmReg1_0__JumpTarget1_1
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
  // Convert__regFCC0__JumpTarget1_0
  { CVT_regFCC0, 0, CVT_95_addImmOperands, 1, CVT_Done },
  // Convert__FCCAsmReg1_0__JumpTarget1_1
  { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
  // Convert__COP2AsmReg1_0__JumpTarget1_1
  { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
  // Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
  // Convert__Reg1_0__JumpTarget1_1
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addImmOperands, 2, CVT_Done },
  // Convert__GPRMM16AsmReg1_0__JumpTarget1_1
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__JumpTarget1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
  // Convert__GPR64AsmReg1_0__JumpTarget1_1
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done },
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
  // Convert__MSA128AsmReg1_0__JumpTarget1_1
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
  // Convert__imm_95_0__imm_95_0
  { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
  // Convert_NoOperands
  { CVT_Done },
  // Convert__ConstantUImm10_01_0__imm_95_0
  { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_imm_95_0, 0, CVT_Done },
  // Convert__ConstantUImm10_01_0__ConstantUImm10_01_1
  { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
  // Convert__ConstantUImm4_01_0
  { CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 1, CVT_Done },
  // Convert__SImm161_0
  { CVT_95_addSImmOperands_LT_16_GT_, 1, CVT_Done },
  // Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1
  { CVT_regFCC0, 0, CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
  // Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1
  { CVT_regFCC0, 0, CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
  // Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2
  { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done },
  // Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
  { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
  // Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1
  { CVT_regFCC0, 0, CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
  // Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
  { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
  // Convert__MemOffsetSimm92_1__ConstantUImm5_01_0
  { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
  // Convert__Mem2_1__ConstantUImm5_01_0
  { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
  // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
  // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
  // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
  // Convert__GPR32AsmReg1_0__CCRAsmReg1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCCRAsmRegOperands, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__COP2AsmReg1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSACtrlAsmRegOperands, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__FGR32AsmReg1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done },
  // Convert__Reg1_0__Reg1_1
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
  // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
  // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
  // Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
  // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
  // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
  // Convert__CCRAsmReg1_1__GPR32AsmReg1_0
  { CVT_95_addCCRAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
  // Convert__COP2AsmReg1_1__GPR32AsmReg1_0
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
  // Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1
  { CVT_95_addMSACtrlAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
  // Convert__FGR32AsmReg1_1__GPR32AsmReg1_0
  { CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
  // Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
  // Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
  // Convert__GPR64AsmReg1_1__GPR64AsmReg1_2
  { CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_, 4, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
  // Convert__regZERO
  { CVT_regZERO, 0, CVT_Done },
  // Convert__GPR32AsmReg1_0
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addImmOperands, 4, CVT_Tied, Tie0_1_1, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
  // Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1
  { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
  // Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1
  { CVT_95_addGPR32ZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
  // Convert__Reg1_1__Reg1_2
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
  // Convert__GPR32AsmReg1_1__GPR32AsmReg1_2
  { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
  // Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
  { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
  // Convert__GPR64AsmReg1_0__Imm1_1
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
  // Convert__GPR64AsmReg1_0__Mem2_1
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
  // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
  // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
  // Convert__GPR64AsmReg1_0__FGR64AsmReg1_1
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
  // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
  // Convert__GPR64AsmReg1_0__UImm161_1
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
  // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
  // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0
  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
  // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2
  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
  // Convert__FGR64AsmReg1_1__GPR64AsmReg1_0
  { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
  // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
  // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
  // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
  // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
  // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 2, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
  // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
  // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_Done },
  // Convert__MSA128AsmReg1_0__GPR32AsmReg1_1
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
  // Convert__MSA128AsmReg1_0__GPR64AsmReg1_1
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
  // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2
  { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
  // Convert__GPR32AsmReg1_0__ConstantUImm2_01_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 2, CVT_Done },
  // Convert__imm_95_0
  { CVT_imm_95_0, 0, CVT_Done },
  // Convert__ConstantUImm10_01_0
  { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
  // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
  // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR64AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_Done },
  // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
  // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Done },
  // Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
  // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
  // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
  // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
  // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
  // Convert__regRA__GPR32AsmReg1_0
  { CVT_regRA, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
  // Convert__regRA_64__GPR64AsmReg1_0
  { CVT_regRA_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
  // Convert__Reg1_0
  { CVT_95_Reg, 1, CVT_Done },
  // Convert__GPR32AsmReg1_0__imm_95_0
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
  // Convert__GPR64AsmReg1_0__imm_95_0
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
  // Convert__regZERO__GPR32AsmReg1_0
  { CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
  // Convert__GPR64AsmReg1_0
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
  // Convert__regZERO_64__GPR64AsmReg1_0
  { CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
  // Convert__UImm5Lsl21_0
  { CVT_95_addImmOperands, 1, CVT_Done },
  // Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
  // Convert__FGR64AsmReg1_0__MemOffsetSimm162_1
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
  // Convert__FGR32AsmReg1_0__MemOffsetSimm162_1
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__Imm1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__Mem2_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__MemOffsetSimm162_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__MemOffsetSimm92_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
  // Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
  // Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
  // Convert__MSA128AsmReg1_0__MemOffsetSimm102_1
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
  // Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
  // Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
  // Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
  // Convert__COP2AsmReg1_0__MemOffsetSimm112_1
  { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
  // Convert__COP2AsmReg1_0__MemOffsetSimm162_1
  { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
  // Convert__COP3AsmReg1_0__Mem2_1
  { CVT_95_addCOP3AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
  // Convert__MSA128AsmReg1_0__ConstantSImm10_01_1
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
  // Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
  // Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
  // Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__UImm32_Coerced1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_32_GT_, 2, CVT_Done },
  // Convert__StrictlyAFGR64AsmReg1_0__Imm1_1
  { CVT_95_addStrictlyAFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
  // Convert__StrictlyFGR64AsmReg1_0__Imm1_1
  { CVT_95_addStrictlyFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
  // Convert__StrictlyFGR32AsmReg1_0__Imm1_1
  { CVT_95_addStrictlyFGR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
  // Convert__GPRMM16AsmReg1_0__UImm7_N11_1
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
  // Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3
  { CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
  // Convert__GPR32AsmReg1_0__UImm161_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
  // Convert__Reg1_0__Imm1_1__imm_95_0
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
  // Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
  // Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
  // Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
  // Convert__RegList1_0__Mem2_1
  { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
  // Convert__RegList161_0__MemOffsetUimm42_1
  { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
  // ConvertCustom_ConvertXWPOperands
  { CVT_ConvertXWPOperands, 0, CVT_Done },
  // Convert__GPR32AsmReg1_0__MemOffsetSimm122_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
  // Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_95_addAFGR64AsmRegOperands, 4, CVT_Done },
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_95_addFGR64AsmRegOperands, 4, CVT_Done },
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 4, CVT_Done },
  // Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
  // Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
  // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
  // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
  // Convert__GPR32AsmReg1_0__FGR64AsmReg1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
  // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
  // Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__regAC0
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regAC0, 0, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_regZERO, 0, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_regZERO_64, 0, CVT_Done },
  // Convert__MovePRegPair2_0__GPRMM16AsmRegMoveP1_1__GPRMM16AsmRegMoveP1_2
  { CVT_95_addMovePRegPairOperands, 1, CVT_95_addGPRMM16AsmRegMovePOperands, 2, CVT_95_addGPRMM16AsmRegMovePOperands, 3, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
  // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0
  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
  // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2
  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
  // Convert__FGR64AsmReg1_1__GPR32AsmReg1_0
  { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
  // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
  // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
  // Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0
  { CVT_95_addAFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
  // Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0
  { CVT_95_addFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
  // Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0
  { CVT_95_addHI32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
  // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1
  { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_Done },
  // Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0
  { CVT_95_addLO32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
  // Convert__regAC0__GPR32AsmReg1_0
  { CVT_regAC0, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
  // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0
  { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
  // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0
  { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
  // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4
  { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done },
  // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
  // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
  // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
  // Convert__regZERO__regZERO__imm_95_0
  { CVT_regZERO, 0, CVT_regZERO, 0, CVT_imm_95_0, 0, CVT_Done },
  // Convert__regZERO__regS0
  { CVT_regZERO, 0, CVT_regS0, 0, CVT_Done },
  // Convert__regZERO__regZERO
  { CVT_regZERO, 0, CVT_regZERO, 0, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_Done },
  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
  // Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0
  { CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
  // Convert__GPR32AsmReg1_0__ConstantUImm7_01_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__ConstantUImm10_01_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
  // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
  // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
  // Convert__GPR32AsmReg1_0__ConstantSImm10_01_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__ConstantUImm8_01_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
  // Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1
  { CVT_95_addGPRMM16AsmRegZeroOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
  // Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
  // Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
  // Convert__ConstantUImm20_01_0
  { CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_, 1, CVT_Done },
  // Convert__Reg1_0__Tie0_1_1
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
  // Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1
  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_, 2, CVT_Tied, Tie0_1_1, CVT_Done },
  // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1
  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done },
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
  // Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done },
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
  // Convert__ConstantUImm5_01_0
  { CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
  // Convert__MemOffsetSimm162_0
  { CVT_95_addMemOperands, 1, CVT_Done },
  // Convert__imm_95_2
  { CVT_imm_95_2, 0, CVT_Done },
  // Convert__imm_95_6
  { CVT_imm_95_6, 0, CVT_Done },
  // Convert__imm_95_4
  { CVT_imm_95_4, 0, CVT_Done },
  // Convert__imm_95_5
  { CVT_imm_95_5, 0, CVT_Done },
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done },
  // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
  // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
  // Convert__GPR32AsmReg1_0__imm_95_31
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_31, 0, CVT_Done },
};

void MipsAsmParser::
convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
                const OperandVector &Operands) {
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
  const uint8_t *Converter = ConversionTable[Kind];
  unsigned OpIdx;
  Inst.setOpcode(Opcode);
  for (const uint8_t *p = Converter; *p; p+= 2) {
    OpIdx = *(p + 1);
    switch (*p) {
    default: llvm_unreachable("invalid conversion entry!");
    case CVT_Reg:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
      break;
    case CVT_Tied: {
      assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
                          std::begin(TiedAsmOperandTable)) &&
             "Tied operand not found");
      unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];
      if (TiedResOpnd != (uint8_t) -1)
        Inst.addOperand(Inst.getOperand(TiedResOpnd));
      break;
    }
    case CVT_95_addGPR32AsmRegOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32AsmRegOperands(Inst, 1);
      break;
    case CVT_95_addAFGR64AsmRegOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addAFGR64AsmRegOperands(Inst, 1);
      break;
    case CVT_95_addFGR64AsmRegOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addFGR64AsmRegOperands(Inst, 1);
      break;
    case CVT_95_addFGR32AsmRegOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addFGR32AsmRegOperands(Inst, 1);
      break;
    case CVT_95_addSImmOperands_LT_32_GT_:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addSImmOperands<32>(Inst, 1);
      break;
    case CVT_95_addMSA128AsmRegOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addMSA128AsmRegOperands(Inst, 1);
      break;
    case CVT_95_addSImmOperands_LT_16_GT_:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addSImmOperands<16>(Inst, 1);
      break;
    case CVT_95_Reg:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
      break;
    case CVT_95_addImmOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
      break;
    case CVT_95_addGPRMM16AsmRegOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegOperands(Inst, 1);
      break;
    case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<4, 0>(Inst, 1);
      break;
    case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 0>(Inst, 1);
      break;
    case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<2, 0>(Inst, 1);
      break;
    case CVT_95_addUImmOperands_LT_16_GT_:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addUImmOperands<16>(Inst, 1);
      break;
    case CVT_95_addGPR64AsmRegOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR64AsmRegOperands(Inst, 1);
      break;
    case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<8, 0>(Inst, 1);
      break;
    case CVT_regZERO:
      Inst.addOperand(MCOperand::createReg(Mips::ZERO));
      break;
    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 32, -32>(Inst, 1);
      break;
    case CVT_regFCC0:
      Inst.addOperand(MCOperand::createReg(Mips::FCC0));
      break;
    case CVT_95_addFCCAsmRegOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addFCCAsmRegOperands(Inst, 1);
      break;
    case CVT_95_addCOP2AsmRegOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP2AsmRegOperands(Inst, 1);
      break;
    case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<3, 0>(Inst, 1);
      break;
    case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<6, 0>(Inst, 1);
      break;
    case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<4, 0>(Inst, 1);
      break;
    case CVT_imm_95_0:
      Inst.addOperand(MCOperand::createImm(0));
      break;
    case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<10, 0>(Inst, 1);
      break;
    case CVT_95_addMemOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addMemOperands(Inst, 2);
      break;
    case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<5, 0>(Inst, 1);
      break;
    case CVT_95_addCCRAsmRegOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addCCRAsmRegOperands(Inst, 1);
      break;
    case CVT_95_addMSACtrlAsmRegOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addMSACtrlAsmRegOperands(Inst, 1);
      break;
    case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<1, 0>(Inst, 1);
      break;
    case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 33>(Inst, 1);
      break;
    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 32>(Inst, 1);
      break;
    case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 1>(Inst, 1);
      break;
    case CVT_95_addGPR32NonZeroAsmRegOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32NonZeroAsmRegOperands(Inst, 1);
      break;
    case CVT_95_addGPR32ZeroAsmRegOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32ZeroAsmRegOperands(Inst, 1);
      break;
    case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<2, 1>(Inst, 1);
      break;
    case CVT_95_addCOP0AsmRegOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP0AsmRegOperands(Inst, 1);
      break;
    case CVT_regZERO_64:
      Inst.addOperand(MCOperand::createReg(Mips::ZERO_64));
      break;
    case CVT_95_addACC64DSPAsmRegOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addACC64DSPAsmRegOperands(Inst, 1);
      break;
    case CVT_95_addConstantUImmOperands_LT_1_GT_:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<1>(Inst, 1);
      break;
    case CVT_regRA:
      Inst.addOperand(MCOperand::createReg(Mips::RA));
      break;
    case CVT_regRA_64:
      Inst.addOperand(MCOperand::createReg(Mips::RA_64));
      break;
    case CVT_95_addMicroMipsMemOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addMicroMipsMemOperands(Inst, 2);
      break;
    case CVT_95_addCOP3AsmRegOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP3AsmRegOperands(Inst, 1);
      break;
    case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<10, 0>(Inst, 1);
      break;
    case CVT_95_addConstantUImmOperands_LT_32_GT_:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<32>(Inst, 1);
      break;
    case CVT_95_addStrictlyAFGR64AsmRegOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyAFGR64AsmRegOperands(Inst, 1);
      break;
    case CVT_95_addStrictlyFGR64AsmRegOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyFGR64AsmRegOperands(Inst, 1);
      break;
    case CVT_95_addStrictlyFGR32AsmRegOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyFGR32AsmRegOperands(Inst, 1);
      break;
    case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<7, -1>(Inst, 1);
      break;
    case CVT_95_addRegListOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addRegListOperands(Inst, 1);
      break;
    case CVT_ConvertXWPOperands:
      ConvertXWPOperands(Inst, Operands);
      break;
    case CVT_regAC0:
      Inst.addOperand(MCOperand::createReg(Mips::AC0));
      break;
    case CVT_95_addMovePRegPairOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addMovePRegPairOperands(Inst, 2);
      break;
    case CVT_95_addGPRMM16AsmRegMovePOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegMovePOperands(Inst, 1);
      break;
    case CVT_95_addHI32DSPAsmRegOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addHI32DSPAsmRegOperands(Inst, 1);
      break;
    case CVT_95_addLO32DSPAsmRegOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addLO32DSPAsmRegOperands(Inst, 1);
      break;
    case CVT_regS0:
      Inst.addOperand(MCOperand::createReg(Mips::S0));
      break;
    case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<7, 0>(Inst, 1);
      break;
    case CVT_95_addHWRegsAsmRegOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addHWRegsAsmRegOperands(Inst, 1);
      break;
    case CVT_95_addGPRMM16AsmRegZeroOperands:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegZeroOperands(Inst, 1);
      break;
    case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<20, 0>(Inst, 1);
      break;
    case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_:
      static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<6, 0>(Inst, 1);
      break;
    case CVT_imm_95_2:
      Inst.addOperand(MCOperand::createImm(2));
      break;
    case CVT_imm_95_6:
      Inst.addOperand(MCOperand::createImm(6));
      break;
    case CVT_imm_95_4:
      Inst.addOperand(MCOperand::createImm(4));
      break;
    case CVT_imm_95_5:
      Inst.addOperand(MCOperand::createImm(5));
      break;
    case CVT_imm_95_31:
      Inst.addOperand(MCOperand::createImm(31));
      break;
    }
  }
}

void MipsAsmParser::
convertToMapAndConstraints(unsigned Kind,
                           const OperandVector &Operands) {
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
  unsigned NumMCOperands = 0;
  const uint8_t *Converter = ConversionTable[Kind];
  for (const uint8_t *p = Converter; *p; p+= 2) {
    switch (*p) {
    default: llvm_unreachable("invalid conversion entry!");
    case CVT_Reg:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("r");
      ++NumMCOperands;
      break;
    case CVT_Tied:
      ++NumMCOperands;
      break;
    case CVT_95_addGPR32AsmRegOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addAFGR64AsmRegOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addFGR64AsmRegOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addFGR32AsmRegOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addSImmOperands_LT_32_GT_:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addMSA128AsmRegOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addSImmOperands_LT_16_GT_:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_Reg:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("r");
      NumMCOperands += 1;
      break;
    case CVT_95_addImmOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addGPRMM16AsmRegOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addUImmOperands_LT_16_GT_:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addGPR64AsmRegOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_regZERO:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      ++NumMCOperands;
      break;
    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_regFCC0:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      ++NumMCOperands;
      break;
    case CVT_95_addFCCAsmRegOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addCOP2AsmRegOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_imm_95_0:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("");
      ++NumMCOperands;
      break;
    case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addMemOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 2;
      break;
    case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addCCRAsmRegOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addMSACtrlAsmRegOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addGPR32NonZeroAsmRegOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addGPR32ZeroAsmRegOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addCOP0AsmRegOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_regZERO_64:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      ++NumMCOperands;
      break;
    case CVT_95_addACC64DSPAsmRegOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addConstantUImmOperands_LT_1_GT_:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_regRA:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      ++NumMCOperands;
      break;
    case CVT_regRA_64:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      ++NumMCOperands;
      break;
    case CVT_95_addMicroMipsMemOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 2;
      break;
    case CVT_95_addCOP3AsmRegOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addConstantUImmOperands_LT_32_GT_:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addStrictlyAFGR64AsmRegOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addStrictlyFGR64AsmRegOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addStrictlyFGR32AsmRegOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addRegListOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_regAC0:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      ++NumMCOperands;
      break;
    case CVT_95_addMovePRegPairOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 2;
      break;
    case CVT_95_addGPRMM16AsmRegMovePOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addHI32DSPAsmRegOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addLO32DSPAsmRegOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_regS0:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      ++NumMCOperands;
      break;
    case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addHWRegsAsmRegOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addGPRMM16AsmRegZeroOperands:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("m");
      NumMCOperands += 1;
      break;
    case CVT_imm_95_2:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("");
      ++NumMCOperands;
      break;
    case CVT_imm_95_6:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("");
      ++NumMCOperands;
      break;
    case CVT_imm_95_4:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("");
      ++NumMCOperands;
      break;
    case CVT_imm_95_5:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("");
      ++NumMCOperands;
      break;
    case CVT_imm_95_31:
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
      Operands[*(p + 1)]->setConstraint("");
      ++NumMCOperands;
      break;
    }
  }
}

namespace {

/// MatchClassKind - The kinds of classes which participate in
/// instruction matching.
enum MatchClassKind {
  InvalidMatchClass = 0,
  OptionalMatchClass = 1,
  MCK__35_, // '#'
  MCK__40_, // '('
  MCK__41_, // ')'
  MCK_0, // '0'
  MCK_16, // '16'
  MCK__91_, // '['
  MCK__93_, // ']'
  MCK_bit, // 'bit'
  MCK_inst, // 'inst'
  MCK_LAST_TOKEN = MCK_inst,
  MCK_Reg15, // derived register class
  MCK_Reg29, // derived register class
  MCK_ACC128, // register class 'ACC128'
  MCK_ACC64, // register class 'ACC64'
  MCK_CPURAReg, // register class 'CPURAReg,RA'
  MCK_CPUSPReg, // register class 'CPUSPReg,SP32,SP'
  MCK_DSPCC, // register class 'DSPCC'
  MCK_GP32, // register class 'GP32'
  MCK_GP64, // register class 'GP64'
  MCK_GPR32ZERO, // register class 'GPR32ZERO,ZERO'
  MCK_HI32, // register class 'HI32'
  MCK_HI64, // register class 'HI64'
  MCK_LO32, // register class 'LO32'
  MCK_LO64, // register class 'LO64'
  MCK_PC, // register class 'PC'
  MCK_SP64, // register class 'SP64'
  MCK_Reg11, // derived register class
  MCK_Reg26, // derived register class
  MCK_OCTEON_MPL, // register class 'OCTEON_MPL'
  MCK_OCTEON_P, // register class 'OCTEON_P'
  MCK_Reg4, // derived register class
  MCK_Reg9, // derived register class
  MCK_Reg19, // derived register class
  MCK_Reg24, // derived register class
  MCK_ACC64DSP, // register class 'ACC64DSP'
  MCK_HI32DSP, // register class 'HI32DSP'
  MCK_LO32DSP, // register class 'LO32DSP'
  MCK_Reg8, // derived register class
  MCK_Reg10, // derived register class
  MCK_Reg23, // derived register class
  MCK_Reg25, // derived register class
  MCK_Reg17, // derived register class
  MCK_Reg18, // derived register class
  MCK_Reg21, // derived register class
  MCK_Reg36, // derived register class
  MCK_CPU16Regs, // register class 'CPU16Regs,GPRMM16'
  MCK_FCC, // register class 'FCC'
  MCK_GPRMM16MoveP, // register class 'GPRMM16MoveP'
  MCK_GPRMM16Zero, // register class 'GPRMM16Zero'
  MCK_MSACtrl, // register class 'MSACtrl'
  MCK_Reg22, // derived register class
  MCK_CPU16RegsPlusSP, // register class 'CPU16RegsPlusSP'
  MCK_Reg31, // derived register class
  MCK_Reg34, // derived register class
  MCK_Reg39, // derived register class
  MCK_Reg42, // derived register class
  MCK_AFGR64, // register class 'AFGR64'
  MCK_MSA128WEvens, // register class 'MSA128WEvens'
  MCK_Reg37, // derived register class
  MCK_Reg20, // derived register class
  MCK_GPR32NONZERO, // register class 'GPR32NONZERO'
  MCK_CCR, // register class 'CCR'
  MCK_COP0, // register class 'COP0'
  MCK_COP2, // register class 'COP2'
  MCK_COP3, // register class 'COP3'
  MCK_DSPR, // register class 'DSPR,GPR32'
  MCK_FGR32, // register class 'FGR32,FGRCC'
  MCK_FGR64, // register class 'FGR64'
  MCK_FGRH32, // register class 'FGRH32'
  MCK_GPR64, // register class 'GPR64'
  MCK_HWRegs, // register class 'HWRegs'
  MCK_MSA128F16, // register class 'MSA128F16,MSA128B,MSA128D,MSA128H,MSA128W'
  MCK_OddSP, // register class 'OddSP'
  MCK_LAST_REGISTER = MCK_OddSP,
  MCK_ACC64DSPAsmReg, // user defined class 'ACC64DSPAsmOperand'
  MCK_AFGR64AsmReg, // user defined class 'AFGR64AsmOperand'
  MCK_CCRAsmReg, // user defined class 'CCRAsmOperand'
  MCK_COP0AsmReg, // user defined class 'COP0AsmOperand'
  MCK_COP2AsmReg, // user defined class 'COP2AsmOperand'
  MCK_COP3AsmReg, // user defined class 'COP3AsmOperand'
  MCK_FCCAsmReg, // user defined class 'FCCRegsAsmOperand'
  MCK_FGR32AsmReg, // user defined class 'FGR32AsmOperand'
  MCK_FGR64AsmReg, // user defined class 'FGR64AsmOperand'
  MCK_FGRH32AsmReg, // user defined class 'FGRH32AsmOperand'
  MCK_GPR32AsmReg, // user defined class 'GPR32AsmOperand'
  MCK_GPR32NonZeroAsmReg, // user defined class 'GPR32NonZeroAsmOperand'
  MCK_GPR32ZeroAsmReg, // user defined class 'GPR32ZeroAsmOperand'
  MCK_GPR64AsmReg, // user defined class 'GPR64AsmOperand'
  MCK_GPRMM16AsmReg, // user defined class 'GPRMM16AsmOperand'
  MCK_GPRMM16AsmRegMoveP, // user defined class 'GPRMM16AsmOperandMoveP'
  MCK_GPRMM16AsmRegZero, // user defined class 'GPRMM16AsmOperandZero'
  MCK_HI32DSPAsmReg, // user defined class 'HI32DSPAsmOperand'
  MCK_HWRegsAsmReg, // user defined class 'HWRegsAsmOperand'
  MCK_Imm, // user defined class 'ImmAsmOperand'
  MCK_LO32DSPAsmReg, // user defined class 'LO32DSPAsmOperand'
  MCK_MSA128AsmReg, // user defined class 'MSA128AsmOperand'
  MCK_MSACtrlAsmReg, // user defined class 'MSACtrlAsmOperand'
  MCK_MicroMipsMemGP, // user defined class 'MicroMipsMemGPAsmOperand'
  MCK_MicroMipsMem, // user defined class 'MicroMipsMemGPRMM16AsmOperand'
  MCK_MicroMipsMemSP, // user defined class 'MicroMipsMemSPAsmOperand'
  MCK_InvNum, // user defined class 'MipsInvertedImmoperand'
  MCK_JumpTarget, // user defined class 'MipsJumpTargetAsmOperand'
  MCK_MemOffsetSimm10, // user defined class 'MipsMemSimm10AsmOperand'
  MCK_MemOffsetSimm10_1, // user defined class 'MipsMemSimm10Lsl1AsmOperand'
  MCK_MemOffsetSimm10_2, // user defined class 'MipsMemSimm10Lsl2AsmOperand'
  MCK_MemOffsetSimm10_3, // user defined class 'MipsMemSimm10Lsl3AsmOperand'
  MCK_MemOffsetSimm11, // user defined class 'MipsMemSimm11AsmOperand'
  MCK_MemOffsetSimm12, // user defined class 'MipsMemSimm12AsmOperand'
  MCK_MemOffsetSimm16, // user defined class 'MipsMemSimm16AsmOperand'
  MCK_MemOffsetSimm9, // user defined class 'MipsMemSimm9AsmOperand'
  MCK_MemOffsetSimmPtr, // user defined class 'MipsMemSimmPtrAsmOperand'
  MCK_MemOffsetUimm4, // user defined class 'MipsMemUimm4AsmOperand'
  MCK_Mem, // user defined class 'MipsMemAsmOperand'
  MCK_MovePRegPair, // user defined class 'MovePRegPairAsmOperand'
  MCK_RegList16, // user defined class 'RegList16AsmOperand'
  MCK_RegList, // user defined class 'RegListAsmOperand'
  MCK_Simm19_Lsl2, // user defined class 'Simm19Lsl2AsmOperand'
  MCK_StrictlyAFGR64AsmReg, // user defined class 'StrictlyAFGR64AsmOperand'
  MCK_StrictlyFGR32AsmReg, // user defined class 'StrictlyFGR32AsmOperand'
  MCK_StrictlyFGR64AsmReg, // user defined class 'StrictlyFGR64AsmOperand'
  MCK_ConstantImmz, // user defined class 'ConstantImmzAsmOperandClass'
  MCK_ConstantUImm1_0, // user defined class 'ConstantUImm1AsmOperandClass'
  MCK_ConstantUImm2_0, // user defined class 'ConstantUImm2AsmOperandClass'
  MCK_ConstantUImm2_1, // user defined class 'ConstantUImm2Plus1AsmOperandClass'
  MCK_ConstantUImm3_0, // user defined class 'ConstantUImm3AsmOperandClass'
  MCK_ConstantSImm4_0, // user defined class 'ConstantSImm4AsmOperandClass'
  MCK_ConstantUImm4_0, // user defined class 'ConstantUImm4AsmOperandClass'
  MCK_ConstantSImm5_0, // user defined class 'ConstantSImm5AsmOperandClass'
  MCK_ConstantUImm5_0, // user defined class 'ConstantUImm5AsmOperandClass'
  MCK_ConstantUImm5_1, // user defined class 'ConstantUImm5Plus1AsmOperandClass'
  MCK_ConstantUImm5_Plus1_Report_UImm6, // user defined class 'ConstantUImm5Plus1ReportUImm6AsmOperandClass'
  MCK_ConstantUImm5_32_Norm, // user defined class 'ConstantUImm5Plus32NormalizeAsmOperandClass'
  MCK_ConstantUImm5_32, // user defined class 'ConstantUImm5Plus32AsmOperandClass'
  MCK_ConstantUImm5_0_Report_UImm6, // user defined class 'ConstantUImm5ReportUImm6AsmOperandClass'
  MCK_ConstantUImm5_33, // user defined class 'ConstantUImm5Plus33AsmOperandClass'
  MCK_ConstantUImmRange2_64, // user defined class 'ConstantUImm5_Range2_64AsmOperandClass'
  MCK_UImm5Lsl2, // user defined class 'ConstantUImm5Lsl2AsmOperandClass'
  MCK_ConstantSImm6_0, // user defined class 'ConstantSImm6AsmOperandClass'
  MCK_ConstantUImm6_0, // user defined class 'ConstantUImm6AsmOperandClass'
  MCK_UImm6Lsl2, // user defined class 'ConstantUImm6Lsl2AsmOperandClass'
  MCK_ConstantUImm7_0, // user defined class 'ConstantUImm7AsmOperandClass'
  MCK_UImm7_N1, // user defined class 'ConstantUImm7Sub1AsmOperandClass'
  MCK_ConstantUImm8_0, // user defined class 'ConstantUImm8AsmOperandClass'
  MCK_SImm7Lsl2, // user defined class 'ConstantSImm7Lsl2AsmOperandClass'
  MCK_ConstantSImm9_0, // user defined class 'ConstantSImm9AsmOperandClass'
  MCK_ConstantSImm10_0, // user defined class 'ConstantSImm10AsmOperandClass'
  MCK_ConstantUImm10_0, // user defined class 'ConstantUImm10AsmOperandClass'
  MCK_SImm10Lsl1, // user defined class 'ConstantSImm10Lsl1AsmOperandClass'
  MCK_ConstantSImm11_0, // user defined class 'ConstantSImm11AsmOperandClass'
  MCK_SImm10Lsl2, // user defined class 'ConstantSImm10Lsl2AsmOperandClass'
  MCK_SImm10Lsl3, // user defined class 'ConstantSImm10Lsl3AsmOperandClass'
  MCK_SImm16, // user defined class 'SImm16AsmOperandClass'
  MCK_SImm16_Relaxed, // user defined class 'SImm16RelaxedAsmOperandClass'
  MCK_UImm16_AltRelaxed, // user defined class 'UImm16AltRelaxedAsmOperandClass'
  MCK_UImm16, // user defined class 'UImm16AsmOperandClass'
  MCK_SImm19Lsl2, // user defined class 'ConstantSImm19Lsl2AsmOperandClass'
  MCK_UImm16_Relaxed, // user defined class 'UImm16RelaxedAsmOperandClass'
  MCK_ConstantUImm20_0, // user defined class 'ConstantUImm20AsmOperandClass'
  MCK_ConstantUImm26_0, // user defined class 'ConstantUImm26AsmOperandClass'
  MCK_SImm32, // user defined class 'SImm32AsmOperandClass'
  MCK_SImm32_Relaxed, // user defined class 'SImm32RelaxedAsmOperandClass'
  MCK_UImm32_Coerced, // user defined class 'UImm32CoercedAsmOperandClass'
  NumMatchClassKinds
};

}

static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
  return MCTargetAsmParser::Match_InvalidOperand;
}

static MatchClassKind matchTokenString(StringRef Name) {
  switch (Name.size()) {
  default: break;
  case 1:	 // 6 strings to match.
    switch (Name[0]) {
    default: break;
    case '#':	 // 1 string to match.
      return MCK__35_;	 // "#"
    case '(':	 // 1 string to match.
      return MCK__40_;	 // "("
    case ')':	 // 1 string to match.
      return MCK__41_;	 // ")"
    case '0':	 // 1 string to match.
      return MCK_0;	 // "0"
    case '[':	 // 1 string to match.
      return MCK__91_;	 // "["
    case ']':	 // 1 string to match.
      return MCK__93_;	 // "]"
    }
    break;
  case 2:	 // 1 string to match.
    if (memcmp(Name.data()+0, "16", 2) != 0)
      break;
    return MCK_16;	 // "16"
  case 3:	 // 1 string to match.
    if (memcmp(Name.data()+0, "bit", 3) != 0)
      break;
    return MCK_bit;	 // "bit"
  case 4:	 // 1 string to match.
    if (memcmp(Name.data()+0, "inst", 4) != 0)
      break;
    return MCK_inst;	 // "inst"
  }
  return InvalidMatchClass;
}

/// isSubclass - Compute whether \p A is a subclass of \p B.
static bool isSubclass(MatchClassKind A, MatchClassKind B) {
  if (A == B)
    return true;

  switch (A) {
  default:
    return false;

  case MCK_Reg15:
    switch (B) {
    default: return false;
    case MCK_Reg19: return true;
    case MCK_Reg17: return true;
    case MCK_Reg18: return true;
    case MCK_GPR64: return true;
    }

  case MCK_Reg29:
    switch (B) {
    default: return false;
    case MCK_Reg20: return true;
    case MCK_GPR64: return true;
    }

  case MCK_ACC64:
    return B == MCK_ACC64DSP;

  case MCK_CPURAReg:
    switch (B) {
    default: return false;
    case MCK_GPR32NONZERO: return true;
    case MCK_DSPR: return true;
    }

  case MCK_CPUSPReg:
    switch (B) {
    default: return false;
    case MCK_CPU16RegsPlusSP: return true;
    case MCK_GPR32NONZERO: return true;
    case MCK_DSPR: return true;
    }

  case MCK_GP32:
    switch (B) {
    default: return false;
    case MCK_GPR32NONZERO: return true;
    case MCK_DSPR: return true;
    }

  case MCK_GP64:
    switch (B) {
    default: return false;
    case MCK_Reg20: return true;
    case MCK_GPR64: return true;
    }

  case MCK_GPR32ZERO:
    switch (B) {
    default: return false;
    case MCK_Reg4: return true;
    case MCK_GPRMM16MoveP: return true;
    case MCK_GPRMM16Zero: return true;
    case MCK_DSPR: return true;
    }

  case MCK_HI32:
    return B == MCK_HI32DSP;

  case MCK_LO32:
    return B == MCK_LO32DSP;

  case MCK_SP64:
    switch (B) {
    default: return false;
    case MCK_Reg22: return true;
    case MCK_Reg20: return true;
    case MCK_GPR64: return true;
    }

  case MCK_Reg11:
    switch (B) {
    default: return false;
    case MCK_Reg4: return true;
    case MCK_Reg9: return true;
    case MCK_Reg8: return true;
    case MCK_Reg10: return true;
    case MCK_CPU16Regs: return true;
    case MCK_GPRMM16MoveP: return true;
    case MCK_GPRMM16Zero: return true;
    case MCK_CPU16RegsPlusSP: return true;
    case MCK_GPR32NONZERO: return true;
    case MCK_DSPR: return true;
    }

  case MCK_Reg26:
    switch (B) {
    default: return false;
    case MCK_Reg19: return true;
    case MCK_Reg24: return true;
    case MCK_Reg23: return true;
    case MCK_Reg25: return true;
    case MCK_Reg17: return true;
    case MCK_Reg18: return true;
    case MCK_Reg21: return true;
    case MCK_Reg22: return true;
    case MCK_Reg20: return true;
    case MCK_GPR64: return true;
    }

  case MCK_Reg4:
    switch (B) {
    default: return false;
    case MCK_GPRMM16MoveP: return true;
    case MCK_GPRMM16Zero: return true;
    case MCK_DSPR: return true;
    }

  case MCK_Reg9:
    switch (B) {
    default: return false;
    case MCK_Reg10: return true;
    case MCK_CPU16Regs: return true;
    case MCK_GPRMM16MoveP: return true;
    case MCK_CPU16RegsPlusSP: return true;
    case MCK_GPR32NONZERO: return true;
    case MCK_DSPR: return true;
    }

  case MCK_Reg19:
    switch (B) {
    default: return false;
    case MCK_Reg17: return true;
    case MCK_Reg18: return true;
    case MCK_GPR64: return true;
    }

  case MCK_Reg24:
    switch (B) {
    default: return false;
    case MCK_Reg25: return true;
    case MCK_Reg18: return true;
    case MCK_Reg21: return true;
    case MCK_Reg22: return true;
    case MCK_Reg20: return true;
    case MCK_GPR64: return true;
    }

  case MCK_Reg8:
    switch (B) {
    default: return false;
    case MCK_CPU16Regs: return true;
    case MCK_GPRMM16Zero: return true;
    case MCK_CPU16RegsPlusSP: return true;
    case MCK_GPR32NONZERO: return true;
    case MCK_DSPR: return true;
    }

  case MCK_Reg10:
    switch (B) {
    default: return false;
    case MCK_GPRMM16MoveP: return true;
    case MCK_GPR32NONZERO: return true;
    case MCK_DSPR: return true;
    }

  case MCK_Reg23:
    switch (B) {
    default: return false;
    case MCK_Reg17: return true;
    case MCK_Reg21: return true;
    case MCK_Reg22: return true;
    case MCK_Reg20: return true;
    case MCK_GPR64: return true;
    }

  case MCK_Reg25:
    switch (B) {
    default: return false;
    case MCK_Reg18: return true;
    case MCK_Reg20: return true;
    case MCK_GPR64: return true;
    }

  case MCK_Reg17:
    return B == MCK_GPR64;

  case MCK_Reg18:
    return B == MCK_GPR64;

  case MCK_Reg21:
    switch (B) {
    default: return false;
    case MCK_Reg22: return true;
    case MCK_Reg20: return true;
    case MCK_GPR64: return true;
    }

  case MCK_Reg36:
    switch (B) {
    default: return false;
    case MCK_AFGR64: return true;
    case MCK_Reg37: return true;
    case MCK_OddSP: return true;
    }

  case MCK_CPU16Regs:
    switch (B) {
    default: return false;
    case MCK_CPU16RegsPlusSP: return true;
    case MCK_GPR32NONZERO: return true;
    case MCK_DSPR: return true;
    }

  case MCK_GPRMM16MoveP:
    return B == MCK_DSPR;

  case MCK_GPRMM16Zero:
    return B == MCK_DSPR;

  case MCK_Reg22:
    switch (B) {
    default: return false;
    case MCK_Reg20: return true;
    case MCK_GPR64: return true;
    }

  case MCK_CPU16RegsPlusSP:
    switch (B) {
    default: return false;
    case MCK_GPR32NONZERO: return true;
    case MCK_DSPR: return true;
    }

  case MCK_Reg31:
    switch (B) {
    default: return false;
    case MCK_FGR32: return true;
    case MCK_OddSP: return true;
    }

  case MCK_Reg34:
    switch (B) {
    default: return false;
    case MCK_FGRH32: return true;
    case MCK_OddSP: return true;
    }

  case MCK_Reg39:
    switch (B) {
    default: return false;
    case MCK_Reg37: return true;
    case MCK_FGR64: return true;
    case MCK_OddSP: return true;
    }

  case MCK_Reg42:
    return B == MCK_MSA128F16;

  case MCK_MSA128WEvens:
    return B == MCK_MSA128F16;

  case MCK_Reg37:
    return B == MCK_OddSP;

  case MCK_Reg20:
    return B == MCK_GPR64;

  case MCK_GPR32NONZERO:
    return B == MCK_DSPR;

  case MCK_MemOffsetSimm10:
    return B == MCK_Mem;

  case MCK_MemOffsetSimm10_1:
    return B == MCK_Mem;

  case MCK_MemOffsetSimm10_2:
    return B == MCK_Mem;

  case MCK_MemOffsetSimm10_3:
    return B == MCK_Mem;

  case MCK_MemOffsetSimm11:
    return B == MCK_Mem;

  case MCK_MemOffsetSimm12:
    return B == MCK_Mem;

  case MCK_MemOffsetSimm16:
    return B == MCK_Mem;

  case MCK_MemOffsetSimm9:
    return B == MCK_Mem;

  case MCK_MemOffsetSimmPtr:
    return B == MCK_Mem;

  case MCK_MemOffsetUimm4:
    return B == MCK_Mem;

  case MCK_ConstantImmz:
    switch (B) {
    default: return false;
    case MCK_ConstantUImm1_0: return true;
    case MCK_ConstantUImm2_0: return true;
    case MCK_ConstantUImm3_0: return true;
    case MCK_ConstantSImm4_0: return true;
    case MCK_ConstantUImm4_0: return true;
    case MCK_ConstantSImm5_0: return true;
    case MCK_ConstantUImm5_0: return true;
    case MCK_ConstantUImm5_1: return true;
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
    case MCK_ConstantUImm5_32_Norm: return true;
    case MCK_ConstantUImm5_32: return true;
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
    case MCK_ConstantUImm5_33: return true;
    case MCK_ConstantUImmRange2_64: return true;
    case MCK_UImm5Lsl2: return true;
    case MCK_ConstantSImm6_0: return true;
    case MCK_ConstantUImm6_0: return true;
    case MCK_UImm6Lsl2: return true;
    case MCK_ConstantUImm7_0: return true;
    case MCK_UImm7_N1: return true;
    case MCK_ConstantUImm8_0: return true;
    case MCK_SImm7Lsl2: return true;
    case MCK_ConstantSImm9_0: return true;
    case MCK_ConstantSImm10_0: return true;
    case MCK_ConstantUImm10_0: return true;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_ConstantUImm1_0:
    switch (B) {
    default: return false;
    case MCK_ConstantUImm2_0: return true;
    case MCK_ConstantUImm3_0: return true;
    case MCK_ConstantSImm4_0: return true;
    case MCK_ConstantUImm4_0: return true;
    case MCK_ConstantSImm5_0: return true;
    case MCK_ConstantUImm5_0: return true;
    case MCK_ConstantUImm5_1: return true;
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
    case MCK_ConstantUImm5_32_Norm: return true;
    case MCK_ConstantUImm5_32: return true;
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
    case MCK_ConstantUImm5_33: return true;
    case MCK_ConstantUImmRange2_64: return true;
    case MCK_UImm5Lsl2: return true;
    case MCK_ConstantSImm6_0: return true;
    case MCK_ConstantUImm6_0: return true;
    case MCK_UImm6Lsl2: return true;
    case MCK_ConstantUImm7_0: return true;
    case MCK_UImm7_N1: return true;
    case MCK_ConstantUImm8_0: return true;
    case MCK_SImm7Lsl2: return true;
    case MCK_ConstantSImm9_0: return true;
    case MCK_ConstantSImm10_0: return true;
    case MCK_ConstantUImm10_0: return true;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_ConstantUImm2_0:
    switch (B) {
    default: return false;
    case MCK_ConstantUImm3_0: return true;
    case MCK_ConstantSImm4_0: return true;
    case MCK_ConstantUImm4_0: return true;
    case MCK_ConstantSImm5_0: return true;
    case MCK_ConstantUImm5_0: return true;
    case MCK_ConstantUImm5_1: return true;
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
    case MCK_ConstantUImm5_32_Norm: return true;
    case MCK_ConstantUImm5_32: return true;
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
    case MCK_ConstantUImm5_33: return true;
    case MCK_ConstantUImmRange2_64: return true;
    case MCK_UImm5Lsl2: return true;
    case MCK_ConstantSImm6_0: return true;
    case MCK_ConstantUImm6_0: return true;
    case MCK_UImm6Lsl2: return true;
    case MCK_ConstantUImm7_0: return true;
    case MCK_UImm7_N1: return true;
    case MCK_ConstantUImm8_0: return true;
    case MCK_SImm7Lsl2: return true;
    case MCK_ConstantSImm9_0: return true;
    case MCK_ConstantSImm10_0: return true;
    case MCK_ConstantUImm10_0: return true;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_ConstantUImm2_1:
    switch (B) {
    default: return false;
    case MCK_ConstantUImm3_0: return true;
    case MCK_ConstantSImm4_0: return true;
    case MCK_ConstantUImm4_0: return true;
    case MCK_ConstantSImm5_0: return true;
    case MCK_ConstantUImm5_0: return true;
    case MCK_ConstantUImm5_1: return true;
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
    case MCK_ConstantUImm5_32_Norm: return true;
    case MCK_ConstantUImm5_32: return true;
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
    case MCK_ConstantUImm5_33: return true;
    case MCK_ConstantUImmRange2_64: return true;
    case MCK_UImm5Lsl2: return true;
    case MCK_ConstantSImm6_0: return true;
    case MCK_ConstantUImm6_0: return true;
    case MCK_UImm6Lsl2: return true;
    case MCK_ConstantUImm7_0: return true;
    case MCK_UImm7_N1: return true;
    case MCK_ConstantUImm8_0: return true;
    case MCK_SImm7Lsl2: return true;
    case MCK_ConstantSImm9_0: return true;
    case MCK_ConstantSImm10_0: return true;
    case MCK_ConstantUImm10_0: return true;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_ConstantUImm3_0:
    switch (B) {
    default: return false;
    case MCK_ConstantSImm4_0: return true;
    case MCK_ConstantUImm4_0: return true;
    case MCK_ConstantSImm5_0: return true;
    case MCK_ConstantUImm5_0: return true;
    case MCK_ConstantUImm5_1: return true;
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
    case MCK_ConstantUImm5_32_Norm: return true;
    case MCK_ConstantUImm5_32: return true;
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
    case MCK_ConstantUImm5_33: return true;
    case MCK_ConstantUImmRange2_64: return true;
    case MCK_UImm5Lsl2: return true;
    case MCK_ConstantSImm6_0: return true;
    case MCK_ConstantUImm6_0: return true;
    case MCK_UImm6Lsl2: return true;
    case MCK_ConstantUImm7_0: return true;
    case MCK_UImm7_N1: return true;
    case MCK_ConstantUImm8_0: return true;
    case MCK_SImm7Lsl2: return true;
    case MCK_ConstantSImm9_0: return true;
    case MCK_ConstantSImm10_0: return true;
    case MCK_ConstantUImm10_0: return true;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_ConstantSImm4_0:
    switch (B) {
    default: return false;
    case MCK_ConstantUImm4_0: return true;
    case MCK_ConstantSImm5_0: return true;
    case MCK_ConstantUImm5_0: return true;
    case MCK_ConstantUImm5_1: return true;
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
    case MCK_ConstantUImm5_32_Norm: return true;
    case MCK_ConstantUImm5_32: return true;
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
    case MCK_ConstantUImm5_33: return true;
    case MCK_ConstantUImmRange2_64: return true;
    case MCK_UImm5Lsl2: return true;
    case MCK_ConstantSImm6_0: return true;
    case MCK_ConstantUImm6_0: return true;
    case MCK_UImm6Lsl2: return true;
    case MCK_ConstantUImm7_0: return true;
    case MCK_UImm7_N1: return true;
    case MCK_ConstantUImm8_0: return true;
    case MCK_SImm7Lsl2: return true;
    case MCK_ConstantSImm9_0: return true;
    case MCK_ConstantSImm10_0: return true;
    case MCK_ConstantUImm10_0: return true;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_ConstantUImm4_0:
    switch (B) {
    default: return false;
    case MCK_ConstantSImm5_0: return true;
    case MCK_ConstantUImm5_0: return true;
    case MCK_ConstantUImm5_1: return true;
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
    case MCK_ConstantUImm5_32_Norm: return true;
    case MCK_ConstantUImm5_32: return true;
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
    case MCK_ConstantUImm5_33: return true;
    case MCK_ConstantUImmRange2_64: return true;
    case MCK_UImm5Lsl2: return true;
    case MCK_ConstantSImm6_0: return true;
    case MCK_ConstantUImm6_0: return true;
    case MCK_UImm6Lsl2: return true;
    case MCK_ConstantUImm7_0: return true;
    case MCK_UImm7_N1: return true;
    case MCK_ConstantUImm8_0: return true;
    case MCK_SImm7Lsl2: return true;
    case MCK_ConstantSImm9_0: return true;
    case MCK_ConstantSImm10_0: return true;
    case MCK_ConstantUImm10_0: return true;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_ConstantSImm5_0:
    switch (B) {
    default: return false;
    case MCK_ConstantUImm5_0: return true;
    case MCK_ConstantUImm5_1: return true;
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
    case MCK_ConstantUImm5_32_Norm: return true;
    case MCK_ConstantUImm5_32: return true;
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
    case MCK_ConstantUImm5_33: return true;
    case MCK_ConstantUImmRange2_64: return true;
    case MCK_UImm5Lsl2: return true;
    case MCK_ConstantSImm6_0: return true;
    case MCK_ConstantUImm6_0: return true;
    case MCK_UImm6Lsl2: return true;
    case MCK_ConstantUImm7_0: return true;
    case MCK_UImm7_N1: return true;
    case MCK_ConstantUImm8_0: return true;
    case MCK_SImm7Lsl2: return true;
    case MCK_ConstantSImm9_0: return true;
    case MCK_ConstantSImm10_0: return true;
    case MCK_ConstantUImm10_0: return true;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_ConstantUImm5_0:
    switch (B) {
    default: return false;
    case MCK_ConstantUImm5_1: return true;
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
    case MCK_ConstantUImm5_32_Norm: return true;
    case MCK_ConstantUImm5_32: return true;
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
    case MCK_ConstantUImm5_33: return true;
    case MCK_ConstantUImmRange2_64: return true;
    case MCK_UImm5Lsl2: return true;
    case MCK_ConstantSImm6_0: return true;
    case MCK_ConstantUImm6_0: return true;
    case MCK_UImm6Lsl2: return true;
    case MCK_ConstantUImm7_0: return true;
    case MCK_UImm7_N1: return true;
    case MCK_ConstantUImm8_0: return true;
    case MCK_SImm7Lsl2: return true;
    case MCK_ConstantSImm9_0: return true;
    case MCK_ConstantSImm10_0: return true;
    case MCK_ConstantUImm10_0: return true;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_ConstantUImm5_1:
    switch (B) {
    default: return false;
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
    case MCK_ConstantUImm5_32_Norm: return true;
    case MCK_ConstantUImm5_32: return true;
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
    case MCK_ConstantUImm5_33: return true;
    case MCK_ConstantUImmRange2_64: return true;
    case MCK_UImm5Lsl2: return true;
    case MCK_ConstantSImm6_0: return true;
    case MCK_ConstantUImm6_0: return true;
    case MCK_UImm6Lsl2: return true;
    case MCK_ConstantUImm7_0: return true;
    case MCK_UImm7_N1: return true;
    case MCK_ConstantUImm8_0: return true;
    case MCK_SImm7Lsl2: return true;
    case MCK_ConstantSImm9_0: return true;
    case MCK_ConstantSImm10_0: return true;
    case MCK_ConstantUImm10_0: return true;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_ConstantUImm5_Plus1_Report_UImm6:
    switch (B) {
    default: return false;
    case MCK_ConstantUImm5_32_Norm: return true;
    case MCK_ConstantUImm5_32: return true;
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
    case MCK_ConstantUImm5_33: return true;
    case MCK_ConstantUImmRange2_64: return true;
    case MCK_UImm5Lsl2: return true;
    case MCK_ConstantSImm6_0: return true;
    case MCK_ConstantUImm6_0: return true;
    case MCK_UImm6Lsl2: return true;
    case MCK_ConstantUImm7_0: return true;
    case MCK_UImm7_N1: return true;
    case MCK_ConstantUImm8_0: return true;
    case MCK_SImm7Lsl2: return true;
    case MCK_ConstantSImm9_0: return true;
    case MCK_ConstantSImm10_0: return true;
    case MCK_ConstantUImm10_0: return true;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_ConstantUImm5_32_Norm:
    switch (B) {
    default: return false;
    case MCK_ConstantUImm5_32: return true;
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
    case MCK_ConstantUImm5_33: return true;
    case MCK_ConstantUImmRange2_64: return true;
    case MCK_UImm5Lsl2: return true;
    case MCK_ConstantSImm6_0: return true;
    case MCK_ConstantUImm6_0: return true;
    case MCK_UImm6Lsl2: return true;
    case MCK_ConstantUImm7_0: return true;
    case MCK_UImm7_N1: return true;
    case MCK_ConstantUImm8_0: return true;
    case MCK_SImm7Lsl2: return true;
    case MCK_ConstantSImm9_0: return true;
    case MCK_ConstantSImm10_0: return true;
    case MCK_ConstantUImm10_0: return true;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_ConstantUImm5_32:
    switch (B) {
    default: return false;
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
    case MCK_ConstantUImm5_33: return true;
    case MCK_ConstantUImmRange2_64: return true;
    case MCK_UImm5Lsl2: return true;
    case MCK_ConstantSImm6_0: return true;
    case MCK_ConstantUImm6_0: return true;
    case MCK_UImm6Lsl2: return true;
    case MCK_ConstantUImm7_0: return true;
    case MCK_UImm7_N1: return true;
    case MCK_ConstantUImm8_0: return true;
    case MCK_SImm7Lsl2: return true;
    case MCK_ConstantSImm9_0: return true;
    case MCK_ConstantSImm10_0: return true;
    case MCK_ConstantUImm10_0: return true;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_ConstantUImm5_0_Report_UImm6:
    switch (B) {
    default: return false;
    case MCK_ConstantUImm5_33: return true;
    case MCK_ConstantUImmRange2_64: return true;
    case MCK_UImm5Lsl2: return true;
    case MCK_ConstantSImm6_0: return true;
    case MCK_ConstantUImm6_0: return true;
    case MCK_UImm6Lsl2: return true;
    case MCK_ConstantUImm7_0: return true;
    case MCK_UImm7_N1: return true;
    case MCK_ConstantUImm8_0: return true;
    case MCK_SImm7Lsl2: return true;
    case MCK_ConstantSImm9_0: return true;
    case MCK_ConstantSImm10_0: return true;
    case MCK_ConstantUImm10_0: return true;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_ConstantUImm5_33:
    switch (B) {
    default: return false;
    case MCK_ConstantUImmRange2_64: return true;
    case MCK_UImm5Lsl2: return true;
    case MCK_ConstantSImm6_0: return true;
    case MCK_ConstantUImm6_0: return true;
    case MCK_UImm6Lsl2: return true;
    case MCK_ConstantUImm7_0: return true;
    case MCK_UImm7_N1: return true;
    case MCK_ConstantUImm8_0: return true;
    case MCK_SImm7Lsl2: return true;
    case MCK_ConstantSImm9_0: return true;
    case MCK_ConstantSImm10_0: return true;
    case MCK_ConstantUImm10_0: return true;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_ConstantUImmRange2_64:
    switch (B) {
    default: return false;
    case MCK_UImm5Lsl2: return true;
    case MCK_ConstantSImm6_0: return true;
    case MCK_ConstantUImm6_0: return true;
    case MCK_UImm6Lsl2: return true;
    case MCK_ConstantUImm7_0: return true;
    case MCK_UImm7_N1: return true;
    case MCK_ConstantUImm8_0: return true;
    case MCK_SImm7Lsl2: return true;
    case MCK_ConstantSImm9_0: return true;
    case MCK_ConstantSImm10_0: return true;
    case MCK_ConstantUImm10_0: return true;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_UImm5Lsl2:
    switch (B) {
    default: return false;
    case MCK_ConstantSImm6_0: return true;
    case MCK_ConstantUImm6_0: return true;
    case MCK_UImm6Lsl2: return true;
    case MCK_ConstantUImm7_0: return true;
    case MCK_UImm7_N1: return true;
    case MCK_ConstantUImm8_0: return true;
    case MCK_SImm7Lsl2: return true;
    case MCK_ConstantSImm9_0: return true;
    case MCK_ConstantSImm10_0: return true;
    case MCK_ConstantUImm10_0: return true;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_ConstantSImm6_0:
    switch (B) {
    default: return false;
    case MCK_ConstantUImm6_0: return true;
    case MCK_UImm6Lsl2: return true;
    case MCK_ConstantUImm7_0: return true;
    case MCK_UImm7_N1: return true;
    case MCK_ConstantUImm8_0: return true;
    case MCK_SImm7Lsl2: return true;
    case MCK_ConstantSImm9_0: return true;
    case MCK_ConstantSImm10_0: return true;
    case MCK_ConstantUImm10_0: return true;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_ConstantUImm6_0:
    switch (B) {
    default: return false;
    case MCK_UImm6Lsl2: return true;
    case MCK_ConstantUImm7_0: return true;
    case MCK_UImm7_N1: return true;
    case MCK_ConstantUImm8_0: return true;
    case MCK_SImm7Lsl2: return true;
    case MCK_ConstantSImm9_0: return true;
    case MCK_ConstantSImm10_0: return true;
    case MCK_ConstantUImm10_0: return true;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_UImm6Lsl2:
    switch (B) {
    default: return false;
    case MCK_ConstantUImm7_0: return true;
    case MCK_UImm7_N1: return true;
    case MCK_ConstantUImm8_0: return true;
    case MCK_SImm7Lsl2: return true;
    case MCK_ConstantSImm9_0: return true;
    case MCK_ConstantSImm10_0: return true;
    case MCK_ConstantUImm10_0: return true;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_ConstantUImm7_0:
    switch (B) {
    default: return false;
    case MCK_UImm7_N1: return true;
    case MCK_ConstantUImm8_0: return true;
    case MCK_SImm7Lsl2: return true;
    case MCK_ConstantSImm9_0: return true;
    case MCK_ConstantSImm10_0: return true;
    case MCK_ConstantUImm10_0: return true;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_UImm7_N1:
    switch (B) {
    default: return false;
    case MCK_ConstantUImm8_0: return true;
    case MCK_SImm7Lsl2: return true;
    case MCK_ConstantSImm9_0: return true;
    case MCK_ConstantSImm10_0: return true;
    case MCK_ConstantUImm10_0: return true;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_ConstantUImm8_0:
    switch (B) {
    default: return false;
    case MCK_SImm7Lsl2: return true;
    case MCK_ConstantSImm9_0: return true;
    case MCK_ConstantSImm10_0: return true;
    case MCK_ConstantUImm10_0: return true;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_SImm7Lsl2:
    switch (B) {
    default: return false;
    case MCK_ConstantSImm9_0: return true;
    case MCK_ConstantSImm10_0: return true;
    case MCK_ConstantUImm10_0: return true;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_ConstantSImm9_0:
    switch (B) {
    default: return false;
    case MCK_ConstantSImm10_0: return true;
    case MCK_ConstantUImm10_0: return true;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_ConstantSImm10_0:
    switch (B) {
    default: return false;
    case MCK_ConstantUImm10_0: return true;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_ConstantUImm10_0:
    switch (B) {
    default: return false;
    case MCK_SImm10Lsl1: return true;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_SImm10Lsl1:
    switch (B) {
    default: return false;
    case MCK_ConstantSImm11_0: return true;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_ConstantSImm11_0:
    switch (B) {
    default: return false;
    case MCK_SImm10Lsl2: return true;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_SImm10Lsl2:
    switch (B) {
    default: return false;
    case MCK_SImm10Lsl3: return true;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_SImm10Lsl3:
    switch (B) {
    default: return false;
    case MCK_SImm16: return true;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_SImm16:
    switch (B) {
    default: return false;
    case MCK_SImm16_Relaxed: return true;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_SImm16_Relaxed:
    switch (B) {
    default: return false;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_UImm16_AltRelaxed:
    switch (B) {
    default: return false;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_UImm16:
    switch (B) {
    default: return false;
    case MCK_UImm16_Relaxed: return true;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_SImm19Lsl2:
    switch (B) {
    default: return false;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_UImm16_Relaxed:
    switch (B) {
    default: return false;
    case MCK_ConstantUImm20_0: return true;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_ConstantUImm20_0:
    switch (B) {
    default: return false;
    case MCK_ConstantUImm26_0: return true;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_ConstantUImm26_0:
    switch (B) {
    default: return false;
    case MCK_SImm32: return true;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_SImm32:
    switch (B) {
    default: return false;
    case MCK_SImm32_Relaxed: return true;
    case MCK_UImm32_Coerced: return true;
    }

  case MCK_SImm32_Relaxed:
    return B == MCK_UImm32_Coerced;
  }
}

static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
  MipsOperand &Operand = (MipsOperand&)GOp;
  if (Kind == InvalidMatchClass)
    return MCTargetAsmParser::Match_InvalidOperand;

  if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
    return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
             MCTargetAsmParser::Match_Success :
             MCTargetAsmParser::Match_InvalidOperand;

  switch (Kind) {
  default: break;
  // 'ACC64DSPAsmReg' class
  case MCK_ACC64DSPAsmReg: {
    DiagnosticPredicate DP(Operand.isACCAsmReg());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'AFGR64AsmReg' class
  case MCK_AFGR64AsmReg: {
    DiagnosticPredicate DP(Operand.isFGRAsmReg());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'CCRAsmReg' class
  case MCK_CCRAsmReg: {
    DiagnosticPredicate DP(Operand.isCCRAsmReg());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'COP0AsmReg' class
  case MCK_COP0AsmReg: {
    DiagnosticPredicate DP(Operand.isCOP0AsmReg());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'COP2AsmReg' class
  case MCK_COP2AsmReg: {
    DiagnosticPredicate DP(Operand.isCOP2AsmReg());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'COP3AsmReg' class
  case MCK_COP3AsmReg: {
    DiagnosticPredicate DP(Operand.isCOP3AsmReg());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'FCCAsmReg' class
  case MCK_FCCAsmReg: {
    DiagnosticPredicate DP(Operand.isFCCAsmReg());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'FGR32AsmReg' class
  case MCK_FGR32AsmReg: {
    DiagnosticPredicate DP(Operand.isFGRAsmReg());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'FGR64AsmReg' class
  case MCK_FGR64AsmReg: {
    DiagnosticPredicate DP(Operand.isFGRAsmReg());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'FGRH32AsmReg' class
  case MCK_FGRH32AsmReg: {
    DiagnosticPredicate DP(Operand.isFGRAsmReg());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'GPR32AsmReg' class
  case MCK_GPR32AsmReg: {
    DiagnosticPredicate DP(Operand.isGPRAsmReg());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'GPR32NonZeroAsmReg' class
  case MCK_GPR32NonZeroAsmReg: {
    DiagnosticPredicate DP(Operand.isGPRNonZeroAsmReg());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'GPR32ZeroAsmReg' class
  case MCK_GPR32ZeroAsmReg: {
    DiagnosticPredicate DP(Operand.isGPRZeroAsmReg());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'GPR64AsmReg' class
  case MCK_GPR64AsmReg: {
    DiagnosticPredicate DP(Operand.isGPRAsmReg());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'GPRMM16AsmReg' class
  case MCK_GPRMM16AsmReg: {
    DiagnosticPredicate DP(Operand.isMM16AsmReg());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'GPRMM16AsmRegMoveP' class
  case MCK_GPRMM16AsmRegMoveP: {
    DiagnosticPredicate DP(Operand.isMM16AsmRegMoveP());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'GPRMM16AsmRegZero' class
  case MCK_GPRMM16AsmRegZero: {
    DiagnosticPredicate DP(Operand.isMM16AsmRegZero());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'HI32DSPAsmReg' class
  case MCK_HI32DSPAsmReg: {
    DiagnosticPredicate DP(Operand.isACCAsmReg());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'HWRegsAsmReg' class
  case MCK_HWRegsAsmReg: {
    DiagnosticPredicate DP(Operand.isHWRegsAsmReg());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'Imm' class
  case MCK_Imm: {
    DiagnosticPredicate DP(Operand.isImm());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'LO32DSPAsmReg' class
  case MCK_LO32DSPAsmReg: {
    DiagnosticPredicate DP(Operand.isACCAsmReg());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'MSA128AsmReg' class
  case MCK_MSA128AsmReg: {
    DiagnosticPredicate DP(Operand.isMSA128AsmReg());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'MSACtrlAsmReg' class
  case MCK_MSACtrlAsmReg: {
    DiagnosticPredicate DP(Operand.isMSACtrlAsmReg());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'MicroMipsMemGP' class
  case MCK_MicroMipsMemGP: {
    DiagnosticPredicate DP(Operand.isMemWithSimmWordAlignedOffsetGP<9>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'MicroMipsMem' class
  case MCK_MicroMipsMem: {
    DiagnosticPredicate DP(Operand.isMemWithGRPMM16Base());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'MicroMipsMemSP' class
  case MCK_MicroMipsMemSP: {
    DiagnosticPredicate DP(Operand.isMemWithUimmWordAlignedOffsetSP<7>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'InvNum' class
  case MCK_InvNum: {
    DiagnosticPredicate DP(Operand.isInvNum());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'JumpTarget' class
  case MCK_JumpTarget: {
    DiagnosticPredicate DP(Operand.isImm());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'MemOffsetSimm10' class
  case MCK_MemOffsetSimm10: {
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_MemSImm10;
    break;
    }
  // 'MemOffsetSimm10_1' class
  case MCK_MemOffsetSimm10_1: {
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 1>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_MemSImm10Lsl1;
    break;
    }
  // 'MemOffsetSimm10_2' class
  case MCK_MemOffsetSimm10_2: {
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 2>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_MemSImm10Lsl2;
    break;
    }
  // 'MemOffsetSimm10_3' class
  case MCK_MemOffsetSimm10_3: {
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 3>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_MemSImm10Lsl3;
    break;
    }
  // 'MemOffsetSimm11' class
  case MCK_MemOffsetSimm11: {
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<11>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_MemSImm11;
    break;
    }
  // 'MemOffsetSimm12' class
  case MCK_MemOffsetSimm12: {
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<12>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_MemSImm12;
    break;
    }
  // 'MemOffsetSimm16' class
  case MCK_MemOffsetSimm16: {
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<16>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_MemSImm16;
    break;
    }
  // 'MemOffsetSimm9' class
  case MCK_MemOffsetSimm9: {
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<9>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_MemSImm9;
    break;
    }
  // 'MemOffsetSimmPtr' class
  case MCK_MemOffsetSimmPtr: {
    DiagnosticPredicate DP(Operand.isMemWithPtrSizeOffset());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_MemSImmPtr;
    break;
    }
  // 'MemOffsetUimm4' class
  case MCK_MemOffsetUimm4: {
    DiagnosticPredicate DP(Operand.isMemWithUimmOffsetSP<6>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'Mem' class
  case MCK_Mem: {
    DiagnosticPredicate DP(Operand.isMem());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'MovePRegPair' class
  case MCK_MovePRegPair: {
    DiagnosticPredicate DP(Operand.isMovePRegPair());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'RegList16' class
  case MCK_RegList16: {
    DiagnosticPredicate DP(Operand.isRegList16());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'RegList' class
  case MCK_RegList: {
    DiagnosticPredicate DP(Operand.isRegList());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'Simm19_Lsl2' class
  case MCK_Simm19_Lsl2: {
    DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_SImm19_Lsl2;
    break;
    }
  // 'StrictlyAFGR64AsmReg' class
  case MCK_StrictlyAFGR64AsmReg: {
    DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'StrictlyFGR32AsmReg' class
  case MCK_StrictlyFGR32AsmReg: {
    DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'StrictlyFGR64AsmReg' class
  case MCK_StrictlyFGR64AsmReg: {
    DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    break;
    }
  // 'ConstantImmz' class
  case MCK_ConstantImmz: {
    DiagnosticPredicate DP(Operand.isConstantImmz());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_Immz;
    break;
    }
  // 'ConstantUImm1_0' class
  case MCK_ConstantUImm1_0: {
    DiagnosticPredicate DP(Operand.isConstantUImm<1, 0>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_UImm1_0;
    break;
    }
  // 'ConstantUImm2_0' class
  case MCK_ConstantUImm2_0: {
    DiagnosticPredicate DP(Operand.isConstantUImm<2, 0>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_UImm2_0;
    break;
    }
  // 'ConstantUImm2_1' class
  case MCK_ConstantUImm2_1: {
    DiagnosticPredicate DP(Operand.isConstantUImm<2, 1>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_UImm2_1;
    break;
    }
  // 'ConstantUImm3_0' class
  case MCK_ConstantUImm3_0: {
    DiagnosticPredicate DP(Operand.isConstantUImm<3, 0>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_UImm3_0;
    break;
    }
  // 'ConstantSImm4_0' class
  case MCK_ConstantSImm4_0: {
    DiagnosticPredicate DP(Operand.isConstantSImm<4, 0>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_SImm4_0;
    break;
    }
  // 'ConstantUImm4_0' class
  case MCK_ConstantUImm4_0: {
    DiagnosticPredicate DP(Operand.isConstantUImm<4, 0>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_UImm4_0;
    break;
    }
  // 'ConstantSImm5_0' class
  case MCK_ConstantSImm5_0: {
    DiagnosticPredicate DP(Operand.isConstantSImm<5, 0>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_SImm5_0;
    break;
    }
  // 'ConstantUImm5_0' class
  case MCK_ConstantUImm5_0: {
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_UImm5_0;
    break;
    }
  // 'ConstantUImm5_1' class
  case MCK_ConstantUImm5_1: {
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_UImm5_1;
    break;
    }
  // 'ConstantUImm5_Plus1_Report_UImm6' class
  case MCK_ConstantUImm5_Plus1_Report_UImm6: {
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_UImm5_1;
    break;
    }
  // 'ConstantUImm5_32_Norm' class
  case MCK_ConstantUImm5_32_Norm: {
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_UImm5_32;
    break;
    }
  // 'ConstantUImm5_32' class
  case MCK_ConstantUImm5_32: {
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_UImm5_32;
    break;
    }
  // 'ConstantUImm5_0_Report_UImm6' class
  case MCK_ConstantUImm5_0_Report_UImm6: {
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_UImm5_0_Report_UImm6;
    break;
    }
  // 'ConstantUImm5_33' class
  case MCK_ConstantUImm5_33: {
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 33>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_UImm5_33;
    break;
    }
  // 'ConstantUImmRange2_64' class
  case MCK_ConstantUImmRange2_64: {
    DiagnosticPredicate DP(Operand.isConstantUImmRange<2, 64>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_UImmRange2_64;
    break;
    }
  // 'UImm5Lsl2' class
  case MCK_UImm5Lsl2: {
    DiagnosticPredicate DP(Operand.isScaledUImm<5, 2>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_UImm5_Lsl2;
    break;
    }
  // 'ConstantSImm6_0' class
  case MCK_ConstantSImm6_0: {
    DiagnosticPredicate DP(Operand.isConstantSImm<6, 0>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_SImm6_0;
    break;
    }
  // 'ConstantUImm6_0' class
  case MCK_ConstantUImm6_0: {
    DiagnosticPredicate DP(Operand.isConstantUImm<6, 0>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_UImm6_0;
    break;
    }
  // 'UImm6Lsl2' class
  case MCK_UImm6Lsl2: {
    DiagnosticPredicate DP(Operand.isScaledUImm<6, 2>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_UImm6_Lsl2;
    break;
    }
  // 'ConstantUImm7_0' class
  case MCK_ConstantUImm7_0: {
    DiagnosticPredicate DP(Operand.isConstantUImm<7, 0>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_UImm7_0;
    break;
    }
  // 'UImm7_N1' class
  case MCK_UImm7_N1: {
    DiagnosticPredicate DP(Operand.isConstantUImm<7, -1>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_UImm7_N1;
    break;
    }
  // 'ConstantUImm8_0' class
  case MCK_ConstantUImm8_0: {
    DiagnosticPredicate DP(Operand.isConstantUImm<8, 0>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_UImm8_0;
    break;
    }
  // 'SImm7Lsl2' class
  case MCK_SImm7Lsl2: {
    DiagnosticPredicate DP(Operand.isScaledSImm<7, 2>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_SImm7_Lsl2;
    break;
    }
  // 'ConstantSImm9_0' class
  case MCK_ConstantSImm9_0: {
    DiagnosticPredicate DP(Operand.isConstantSImm<9, 0>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_SImm9_0;
    break;
    }
  // 'ConstantSImm10_0' class
  case MCK_ConstantSImm10_0: {
    DiagnosticPredicate DP(Operand.isConstantSImm<10, 0>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_SImm10_0;
    break;
    }
  // 'ConstantUImm10_0' class
  case MCK_ConstantUImm10_0: {
    DiagnosticPredicate DP(Operand.isConstantUImm<10, 0>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_UImm10_0;
    break;
    }
  // 'SImm10Lsl1' class
  case MCK_SImm10Lsl1: {
    DiagnosticPredicate DP(Operand.isScaledSImm<10, 1>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_SImm10_Lsl1;
    break;
    }
  // 'ConstantSImm11_0' class
  case MCK_ConstantSImm11_0: {
    DiagnosticPredicate DP(Operand.isConstantSImm<11, 0>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_SImm11_0;
    break;
    }
  // 'SImm10Lsl2' class
  case MCK_SImm10Lsl2: {
    DiagnosticPredicate DP(Operand.isScaledSImm<10, 2>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_SImm10_Lsl2;
    break;
    }
  // 'SImm10Lsl3' class
  case MCK_SImm10Lsl3: {
    DiagnosticPredicate DP(Operand.isScaledSImm<10, 3>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_SImm10_Lsl3;
    break;
    }
  // 'SImm16' class
  case MCK_SImm16: {
    DiagnosticPredicate DP(Operand.isSImm<16>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_SImm16;
    break;
    }
  // 'SImm16_Relaxed' class
  case MCK_SImm16_Relaxed: {
    DiagnosticPredicate DP(Operand.isAnyImm<16>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_SImm16_Relaxed;
    break;
    }
  // 'UImm16_AltRelaxed' class
  case MCK_UImm16_AltRelaxed: {
    DiagnosticPredicate DP(Operand.isUImm<16>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_UImm16_AltRelaxed;
    break;
    }
  // 'UImm16' class
  case MCK_UImm16: {
    DiagnosticPredicate DP(Operand.isUImm<16>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_UImm16;
    break;
    }
  // 'SImm19Lsl2' class
  case MCK_SImm19Lsl2: {
    DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_SImm19_Lsl2;
    break;
    }
  // 'UImm16_Relaxed' class
  case MCK_UImm16_Relaxed: {
    DiagnosticPredicate DP(Operand.isAnyImm<16>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_UImm16_Relaxed;
    break;
    }
  // 'ConstantUImm20_0' class
  case MCK_ConstantUImm20_0: {
    DiagnosticPredicate DP(Operand.isConstantUImm<20, 0>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_UImm20_0;
    break;
    }
  // 'ConstantUImm26_0' class
  case MCK_ConstantUImm26_0: {
    DiagnosticPredicate DP(Operand.isConstantUImm<26, 0>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_UImm26_0;
    break;
    }
  // 'SImm32' class
  case MCK_SImm32: {
    DiagnosticPredicate DP(Operand.isSImm<32>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_SImm32;
    break;
    }
  // 'SImm32_Relaxed' class
  case MCK_SImm32_Relaxed: {
    DiagnosticPredicate DP(Operand.isAnyImm<33>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_SImm32_Relaxed;
    break;
    }
  // 'UImm32_Coerced' class
  case MCK_UImm32_Coerced: {
    DiagnosticPredicate DP(Operand.isSImm<33>());
    if (DP.isMatch())
      return MCTargetAsmParser::Match_Success;
    if (DP.isNearMatch())
      return MipsAsmParser::Match_UImm32_Coerced;
    break;
    }
  } // end switch (Kind)

  if (Operand.isReg()) {
    MatchClassKind OpKind;
    switch (Operand.getReg()) {
    default: OpKind = InvalidMatchClass; break;
    case Mips::ZERO: OpKind = MCK_GPR32ZERO; break;
    case Mips::AT: OpKind = MCK_GPR32NONZERO; break;
    case Mips::V0: OpKind = MCK_Reg11; break;
    case Mips::V1: OpKind = MCK_Reg11; break;
    case Mips::A0: OpKind = MCK_Reg8; break;
    case Mips::A1: OpKind = MCK_Reg8; break;
    case Mips::A2: OpKind = MCK_Reg8; break;
    case Mips::A3: OpKind = MCK_Reg8; break;
    case Mips::T0: OpKind = MCK_GPR32NONZERO; break;
    case Mips::T1: OpKind = MCK_GPR32NONZERO; break;
    case Mips::T2: OpKind = MCK_GPR32NONZERO; break;
    case Mips::T3: OpKind = MCK_GPR32NONZERO; break;
    case Mips::T4: OpKind = MCK_GPR32NONZERO; break;
    case Mips::T5: OpKind = MCK_GPR32NONZERO; break;
    case Mips::T6: OpKind = MCK_GPR32NONZERO; break;
    case Mips::T7: OpKind = MCK_GPR32NONZERO; break;
    case Mips::S0: OpKind = MCK_Reg9; break;
    case Mips::S1: OpKind = MCK_Reg11; break;
    case Mips::S2: OpKind = MCK_Reg10; break;
    case Mips::S3: OpKind = MCK_Reg10; break;
    case Mips::S4: OpKind = MCK_Reg10; break;
    case Mips::S5: OpKind = MCK_GPR32NONZERO; break;
    case Mips::S6: OpKind = MCK_GPR32NONZERO; break;
    case Mips::S7: OpKind = MCK_GPR32NONZERO; break;
    case Mips::T8: OpKind = MCK_GPR32NONZERO; break;
    case Mips::T9: OpKind = MCK_GPR32NONZERO; break;
    case Mips::K0: OpKind = MCK_GPR32NONZERO; break;
    case Mips::K1: OpKind = MCK_GPR32NONZERO; break;
    case Mips::GP: OpKind = MCK_GP32; break;
    case Mips::SP: OpKind = MCK_CPUSPReg; break;
    case Mips::FP: OpKind = MCK_GPR32NONZERO; break;
    case Mips::RA: OpKind = MCK_CPURAReg; break;
    case Mips::ZERO_64: OpKind = MCK_Reg15; break;
    case Mips::AT_64: OpKind = MCK_Reg20; break;
    case Mips::V0_64: OpKind = MCK_Reg26; break;
    case Mips::V1_64: OpKind = MCK_Reg26; break;
    case Mips::A0_64: OpKind = MCK_Reg23; break;
    case Mips::A1_64: OpKind = MCK_Reg23; break;
    case Mips::A2_64: OpKind = MCK_Reg23; break;
    case Mips::A3_64: OpKind = MCK_Reg23; break;
    case Mips::T0_64: OpKind = MCK_Reg20; break;
    case Mips::T1_64: OpKind = MCK_Reg20; break;
    case Mips::T2_64: OpKind = MCK_Reg20; break;
    case Mips::T3_64: OpKind = MCK_Reg20; break;
    case Mips::T4_64: OpKind = MCK_Reg20; break;
    case Mips::T5_64: OpKind = MCK_Reg20; break;
    case Mips::T6_64: OpKind = MCK_Reg20; break;
    case Mips::T7_64: OpKind = MCK_Reg20; break;
    case Mips::S0_64: OpKind = MCK_Reg24; break;
    case Mips::S1_64: OpKind = MCK_Reg26; break;
    case Mips::S2_64: OpKind = MCK_Reg25; break;
    case Mips::S3_64: OpKind = MCK_Reg25; break;
    case Mips::S4_64: OpKind = MCK_Reg25; break;
    case Mips::S5_64: OpKind = MCK_Reg20; break;
    case Mips::S6_64: OpKind = MCK_Reg20; break;
    case Mips::S7_64: OpKind = MCK_Reg20; break;
    case Mips::T8_64: OpKind = MCK_Reg20; break;
    case Mips::T9_64: OpKind = MCK_Reg20; break;
    case Mips::K0_64: OpKind = MCK_Reg20; break;
    case Mips::K1_64: OpKind = MCK_Reg20; break;
    case Mips::GP_64: OpKind = MCK_GP64; break;
    case Mips::SP_64: OpKind = MCK_SP64; break;
    case Mips::FP_64: OpKind = MCK_Reg20; break;
    case Mips::RA_64: OpKind = MCK_Reg29; break;
    case Mips::F0: OpKind = MCK_FGR32; break;
    case Mips::F1: OpKind = MCK_Reg31; break;
    case Mips::F2: OpKind = MCK_FGR32; break;
    case Mips::F3: OpKind = MCK_Reg31; break;
    case Mips::F4: OpKind = MCK_FGR32; break;
    case Mips::F5: OpKind = MCK_Reg31; break;
    case Mips::F6: OpKind = MCK_FGR32; break;
    case Mips::F7: OpKind = MCK_Reg31; break;
    case Mips::F8: OpKind = MCK_FGR32; break;
    case Mips::F9: OpKind = MCK_Reg31; break;
    case Mips::F10: OpKind = MCK_FGR32; break;
    case Mips::F11: OpKind = MCK_Reg31; break;
    case Mips::F12: OpKind = MCK_FGR32; break;
    case Mips::F13: OpKind = MCK_Reg31; break;
    case Mips::F14: OpKind = MCK_FGR32; break;
    case Mips::F15: OpKind = MCK_Reg31; break;
    case Mips::F16: OpKind = MCK_FGR32; break;
    case Mips::F17: OpKind = MCK_Reg31; break;
    case Mips::F18: OpKind = MCK_FGR32; break;
    case Mips::F19: OpKind = MCK_Reg31; break;
    case Mips::F20: OpKind = MCK_FGR32; break;
    case Mips::F21: OpKind = MCK_Reg31; break;
    case Mips::F22: OpKind = MCK_FGR32; break;
    case Mips::F23: OpKind = MCK_Reg31; break;
    case Mips::F24: OpKind = MCK_FGR32; break;
    case Mips::F25: OpKind = MCK_Reg31; break;
    case Mips::F26: OpKind = MCK_FGR32; break;
    case Mips::F27: OpKind = MCK_Reg31; break;
    case Mips::F28: OpKind = MCK_FGR32; break;
    case Mips::F29: OpKind = MCK_Reg31; break;
    case Mips::F30: OpKind = MCK_FGR32; break;
    case Mips::F31: OpKind = MCK_Reg31; break;
    case Mips::F_HI0: OpKind = MCK_FGRH32; break;
    case Mips::F_HI1: OpKind = MCK_Reg34; break;
    case Mips::F_HI2: OpKind = MCK_FGRH32; break;
    case Mips::F_HI3: OpKind = MCK_Reg34; break;
    case Mips::F_HI4: OpKind = MCK_FGRH32; break;
    case Mips::F_HI5: OpKind = MCK_Reg34; break;
    case Mips::F_HI6: OpKind = MCK_FGRH32; break;
    case Mips::F_HI7: OpKind = MCK_Reg34; break;
    case Mips::F_HI8: OpKind = MCK_FGRH32; break;
    case Mips::F_HI9: OpKind = MCK_Reg34; break;
    case Mips::F_HI10: OpKind = MCK_FGRH32; break;
    case Mips::F_HI11: OpKind = MCK_Reg34; break;
    case Mips::F_HI12: OpKind = MCK_FGRH32; break;
    case Mips::F_HI13: OpKind = MCK_Reg34; break;
    case Mips::F_HI14: OpKind = MCK_FGRH32; break;
    case Mips::F_HI15: OpKind = MCK_Reg34; break;
    case Mips::F_HI16: OpKind = MCK_FGRH32; break;
    case Mips::F_HI17: OpKind = MCK_Reg34; break;
    case Mips::F_HI18: OpKind = MCK_FGRH32; break;
    case Mips::F_HI19: OpKind = MCK_Reg34; break;
    case Mips::F_HI20: OpKind = MCK_FGRH32; break;
    case Mips::F_HI21: OpKind = MCK_Reg34; break;
    case Mips::F_HI22: OpKind = MCK_FGRH32; break;
    case Mips::F_HI23: OpKind = MCK_Reg34; break;
    case Mips::F_HI24: OpKind = MCK_FGRH32; break;
    case Mips::F_HI25: OpKind = MCK_Reg34; break;
    case Mips::F_HI26: OpKind = MCK_FGRH32; break;
    case Mips::F_HI27: OpKind = MCK_Reg34; break;
    case Mips::F_HI28: OpKind = MCK_FGRH32; break;
    case Mips::F_HI29: OpKind = MCK_Reg34; break;
    case Mips::F_HI30: OpKind = MCK_FGRH32; break;
    case Mips::F_HI31: OpKind = MCK_Reg34; break;
    case Mips::D0: OpKind = MCK_AFGR64; break;
    case Mips::D1: OpKind = MCK_Reg36; break;
    case Mips::D2: OpKind = MCK_AFGR64; break;
    case Mips::D3: OpKind = MCK_Reg36; break;
    case Mips::D4: OpKind = MCK_AFGR64; break;
    case Mips::D5: OpKind = MCK_Reg36; break;
    case Mips::D6: OpKind = MCK_AFGR64; break;
    case Mips::D7: OpKind = MCK_Reg36; break;
    case Mips::D8: OpKind = MCK_AFGR64; break;
    case Mips::D9: OpKind = MCK_Reg36; break;
    case Mips::D10: OpKind = MCK_AFGR64; break;
    case Mips::D11: OpKind = MCK_Reg36; break;
    case Mips::D12: OpKind = MCK_AFGR64; break;
    case Mips::D13: OpKind = MCK_Reg36; break;
    case Mips::D14: OpKind = MCK_AFGR64; break;
    case Mips::D15: OpKind = MCK_Reg36; break;
    case Mips::D0_64: OpKind = MCK_FGR64; break;
    case Mips::D1_64: OpKind = MCK_Reg39; break;
    case Mips::D2_64: OpKind = MCK_FGR64; break;
    case Mips::D3_64: OpKind = MCK_Reg39; break;
    case Mips::D4_64: OpKind = MCK_FGR64; break;
    case Mips::D5_64: OpKind = MCK_Reg39; break;
    case Mips::D6_64: OpKind = MCK_FGR64; break;
    case Mips::D7_64: OpKind = MCK_Reg39; break;
    case Mips::D8_64: OpKind = MCK_FGR64; break;
    case Mips::D9_64: OpKind = MCK_Reg39; break;
    case Mips::D10_64: OpKind = MCK_FGR64; break;
    case Mips::D11_64: OpKind = MCK_Reg39; break;
    case Mips::D12_64: OpKind = MCK_FGR64; break;
    case Mips::D13_64: OpKind = MCK_Reg39; break;
    case Mips::D14_64: OpKind = MCK_FGR64; break;
    case Mips::D15_64: OpKind = MCK_Reg39; break;
    case Mips::D16_64: OpKind = MCK_FGR64; break;
    case Mips::D17_64: OpKind = MCK_Reg39; break;
    case Mips::D18_64: OpKind = MCK_FGR64; break;
    case Mips::D19_64: OpKind = MCK_Reg39; break;
    case Mips::D20_64: OpKind = MCK_FGR64; break;
    case Mips::D21_64: OpKind = MCK_Reg39; break;
    case Mips::D22_64: OpKind = MCK_FGR64; break;
    case Mips::D23_64: OpKind = MCK_Reg39; break;
    case Mips::D24_64: OpKind = MCK_FGR64; break;
    case Mips::D25_64: OpKind = MCK_Reg39; break;
    case Mips::D26_64: OpKind = MCK_FGR64; break;
    case Mips::D27_64: OpKind = MCK_Reg39; break;
    case Mips::D28_64: OpKind = MCK_FGR64; break;
    case Mips::D29_64: OpKind = MCK_Reg39; break;
    case Mips::D30_64: OpKind = MCK_FGR64; break;
    case Mips::D31_64: OpKind = MCK_Reg39; break;
    case Mips::W0: OpKind = MCK_MSA128WEvens; break;
    case Mips::W1: OpKind = MCK_Reg42; break;
    case Mips::W2: OpKind = MCK_MSA128WEvens; break;
    case Mips::W3: OpKind = MCK_Reg42; break;
    case Mips::W4: OpKind = MCK_MSA128WEvens; break;
    case Mips::W5: OpKind = MCK_Reg42; break;
    case Mips::W6: OpKind = MCK_MSA128WEvens; break;
    case Mips::W7: OpKind = MCK_Reg42; break;
    case Mips::W8: OpKind = MCK_MSA128WEvens; break;
    case Mips::W9: OpKind = MCK_Reg42; break;
    case Mips::W10: OpKind = MCK_MSA128WEvens; break;
    case Mips::W11: OpKind = MCK_Reg42; break;
    case Mips::W12: OpKind = MCK_MSA128WEvens; break;
    case Mips::W13: OpKind = MCK_Reg42; break;
    case Mips::W14: OpKind = MCK_MSA128WEvens; break;
    case Mips::W15: OpKind = MCK_Reg42; break;
    case Mips::W16: OpKind = MCK_MSA128WEvens; break;
    case Mips::W17: OpKind = MCK_Reg42; break;
    case Mips::W18: OpKind = MCK_MSA128WEvens; break;
    case Mips::W19: OpKind = MCK_Reg42; break;
    case Mips::W20: OpKind = MCK_MSA128WEvens; break;
    case Mips::W21: OpKind = MCK_Reg42; break;
    case Mips::W22: OpKind = MCK_MSA128WEvens; break;
    case Mips::W23: OpKind = MCK_Reg42; break;
    case Mips::W24: OpKind = MCK_MSA128WEvens; break;
    case Mips::W25: OpKind = MCK_Reg42; break;
    case Mips::W26: OpKind = MCK_MSA128WEvens; break;
    case Mips::W27: OpKind = MCK_Reg42; break;
    case Mips::W28: OpKind = MCK_MSA128WEvens; break;
    case Mips::W29: OpKind = MCK_Reg42; break;
    case Mips::W30: OpKind = MCK_MSA128WEvens; break;
    case Mips::W31: OpKind = MCK_Reg42; break;
    case Mips::HI0: OpKind = MCK_HI32; break;
    case Mips::HI1: OpKind = MCK_HI32DSP; break;
    case Mips::HI2: OpKind = MCK_HI32DSP; break;
    case Mips::HI3: OpKind = MCK_HI32DSP; break;
    case Mips::LO0: OpKind = MCK_LO32; break;
    case Mips::LO1: OpKind = MCK_LO32DSP; break;
    case Mips::LO2: OpKind = MCK_LO32DSP; break;
    case Mips::LO3: OpKind = MCK_LO32DSP; break;
    case Mips::HI0_64: OpKind = MCK_HI64; break;
    case Mips::LO0_64: OpKind = MCK_LO64; break;
    case Mips::FCR0: OpKind = MCK_CCR; break;
    case Mips::FCR1: OpKind = MCK_CCR; break;
    case Mips::FCR2: OpKind = MCK_CCR; break;
    case Mips::FCR3: OpKind = MCK_CCR; break;
    case Mips::FCR4: OpKind = MCK_CCR; break;
    case Mips::FCR5: OpKind = MCK_CCR; break;
    case Mips::FCR6: OpKind = MCK_CCR; break;
    case Mips::FCR7: OpKind = MCK_CCR; break;
    case Mips::FCR8: OpKind = MCK_CCR; break;
    case Mips::FCR9: OpKind = MCK_CCR; break;
    case Mips::FCR10: OpKind = MCK_CCR; break;
    case Mips::FCR11: OpKind = MCK_CCR; break;
    case Mips::FCR12: OpKind = MCK_CCR; break;
    case Mips::FCR13: OpKind = MCK_CCR; break;
    case Mips::FCR14: OpKind = MCK_CCR; break;
    case Mips::FCR15: OpKind = MCK_CCR; break;
    case Mips::FCR16: OpKind = MCK_CCR; break;
    case Mips::FCR17: OpKind = MCK_CCR; break;
    case Mips::FCR18: OpKind = MCK_CCR; break;
    case Mips::FCR19: OpKind = MCK_CCR; break;
    case Mips::FCR20: OpKind = MCK_CCR; break;
    case Mips::FCR21: OpKind = MCK_CCR; break;
    case Mips::FCR22: OpKind = MCK_CCR; break;
    case Mips::FCR23: OpKind = MCK_CCR; break;
    case Mips::FCR24: OpKind = MCK_CCR; break;
    case Mips::FCR25: OpKind = MCK_CCR; break;
    case Mips::FCR26: OpKind = MCK_CCR; break;
    case Mips::FCR27: OpKind = MCK_CCR; break;
    case Mips::FCR28: OpKind = MCK_CCR; break;
    case Mips::FCR29: OpKind = MCK_CCR; break;
    case Mips::FCR30: OpKind = MCK_CCR; break;
    case Mips::FCR31: OpKind = MCK_CCR; break;
    case Mips::FCC0: OpKind = MCK_FCC; break;
    case Mips::FCC1: OpKind = MCK_FCC; break;
    case Mips::FCC2: OpKind = MCK_FCC; break;
    case Mips::FCC3: OpKind = MCK_FCC; break;
    case Mips::FCC4: OpKind = MCK_FCC; break;
    case Mips::FCC5: OpKind = MCK_FCC; break;
    case Mips::FCC6: OpKind = MCK_FCC; break;
    case Mips::FCC7: OpKind = MCK_FCC; break;
    case Mips::COP00: OpKind = MCK_COP0; break;
    case Mips::COP01: OpKind = MCK_COP0; break;
    case Mips::COP02: OpKind = MCK_COP0; break;
    case Mips::COP03: OpKind = MCK_COP0; break;
    case Mips::COP04: OpKind = MCK_COP0; break;
    case Mips::COP05: OpKind = MCK_COP0; break;
    case Mips::COP06: OpKind = MCK_COP0; break;
    case Mips::COP07: OpKind = MCK_COP0; break;
    case Mips::COP08: OpKind = MCK_COP0; break;
    case Mips::COP09: OpKind = MCK_COP0; break;
    case Mips::COP010: OpKind = MCK_COP0; break;
    case Mips::COP011: OpKind = MCK_COP0; break;
    case Mips::COP012: OpKind = MCK_COP0; break;
    case Mips::COP013: OpKind = MCK_COP0; break;
    case Mips::COP014: OpKind = MCK_COP0; break;
    case Mips::COP015: OpKind = MCK_COP0; break;
    case Mips::COP016: OpKind = MCK_COP0; break;
    case Mips::COP017: OpKind = MCK_COP0; break;
    case Mips::COP018: OpKind = MCK_COP0; break;
    case Mips::COP019: OpKind = MCK_COP0; break;
    case Mips::COP020: OpKind = MCK_COP0; break;
    case Mips::COP021: OpKind = MCK_COP0; break;
    case Mips::COP022: OpKind = MCK_COP0; break;
    case Mips::COP023: OpKind = MCK_COP0; break;
    case Mips::COP024: OpKind = MCK_COP0; break;
    case Mips::COP025: OpKind = MCK_COP0; break;
    case Mips::COP026: OpKind = MCK_COP0; break;
    case Mips::COP027: OpKind = MCK_COP0; break;
    case Mips::COP028: OpKind = MCK_COP0; break;
    case Mips::COP029: OpKind = MCK_COP0; break;
    case Mips::COP030: OpKind = MCK_COP0; break;
    case Mips::COP031: OpKind = MCK_COP0; break;
    case Mips::COP20: OpKind = MCK_COP2; break;
    case Mips::COP21: OpKind = MCK_COP2; break;
    case Mips::COP22: OpKind = MCK_COP2; break;
    case Mips::COP23: OpKind = MCK_COP2; break;
    case Mips::COP24: OpKind = MCK_COP2; break;
    case Mips::COP25: OpKind = MCK_COP2; break;
    case Mips::COP26: OpKind = MCK_COP2; break;
    case Mips::COP27: OpKind = MCK_COP2; break;
    case Mips::COP28: OpKind = MCK_COP2; break;
    case Mips::COP29: OpKind = MCK_COP2; break;
    case Mips::COP210: OpKind = MCK_COP2; break;
    case Mips::COP211: OpKind = MCK_COP2; break;
    case Mips::COP212: OpKind = MCK_COP2; break;
    case Mips::COP213: OpKind = MCK_COP2; break;
    case Mips::COP214: OpKind = MCK_COP2; break;
    case Mips::COP215: OpKind = MCK_COP2; break;
    case Mips::COP216: OpKind = MCK_COP2; break;
    case Mips::COP217: OpKind = MCK_COP2; break;
    case Mips::COP218: OpKind = MCK_COP2; break;
    case Mips::COP219: OpKind = MCK_COP2; break;
    case Mips::COP220: OpKind = MCK_COP2; break;
    case Mips::COP221: OpKind = MCK_COP2; break;
    case Mips::COP222: OpKind = MCK_COP2; break;
    case Mips::COP223: OpKind = MCK_COP2; break;
    case Mips::COP224: OpKind = MCK_COP2; break;
    case Mips::COP225: OpKind = MCK_COP2; break;
    case Mips::COP226: OpKind = MCK_COP2; break;
    case Mips::COP227: OpKind = MCK_COP2; break;
    case Mips::COP228: OpKind = MCK_COP2; break;
    case Mips::COP229: OpKind = MCK_COP2; break;
    case Mips::COP230: OpKind = MCK_COP2; break;
    case Mips::COP231: OpKind = MCK_COP2; break;
    case Mips::COP30: OpKind = MCK_COP3; break;
    case Mips::COP31: OpKind = MCK_COP3; break;
    case Mips::COP32: OpKind = MCK_COP3; break;
    case Mips::COP33: OpKind = MCK_COP3; break;
    case Mips::COP34: OpKind = MCK_COP3; break;
    case Mips::COP35: OpKind = MCK_COP3; break;
    case Mips::COP36: OpKind = MCK_COP3; break;
    case Mips::COP37: OpKind = MCK_COP3; break;
    case Mips::COP38: OpKind = MCK_COP3; break;
    case Mips::COP39: OpKind = MCK_COP3; break;
    case Mips::COP310: OpKind = MCK_COP3; break;
    case Mips::COP311: OpKind = MCK_COP3; break;
    case Mips::COP312: OpKind = MCK_COP3; break;
    case Mips::COP313: OpKind = MCK_COP3; break;
    case Mips::COP314: OpKind = MCK_COP3; break;
    case Mips::COP315: OpKind = MCK_COP3; break;
    case Mips::COP316: OpKind = MCK_COP3; break;
    case Mips::COP317: OpKind = MCK_COP3; break;
    case Mips::COP318: OpKind = MCK_COP3; break;
    case Mips::COP319: OpKind = MCK_COP3; break;
    case Mips::COP320: OpKind = MCK_COP3; break;
    case Mips::COP321: OpKind = MCK_COP3; break;
    case Mips::COP322: OpKind = MCK_COP3; break;
    case Mips::COP323: OpKind = MCK_COP3; break;
    case Mips::COP324: OpKind = MCK_COP3; break;
    case Mips::COP325: OpKind = MCK_COP3; break;
    case Mips::COP326: OpKind = MCK_COP3; break;
    case Mips::COP327: OpKind = MCK_COP3; break;
    case Mips::COP328: OpKind = MCK_COP3; break;
    case Mips::COP329: OpKind = MCK_COP3; break;
    case Mips::COP330: OpKind = MCK_COP3; break;
    case Mips::COP331: OpKind = MCK_COP3; break;
    case Mips::PC: OpKind = MCK_PC; break;
    case Mips::HWR0: OpKind = MCK_HWRegs; break;
    case Mips::HWR1: OpKind = MCK_HWRegs; break;
    case Mips::HWR2: OpKind = MCK_HWRegs; break;
    case Mips::HWR3: OpKind = MCK_HWRegs; break;
    case Mips::HWR4: OpKind = MCK_HWRegs; break;
    case Mips::HWR5: OpKind = MCK_HWRegs; break;
    case Mips::HWR6: OpKind = MCK_HWRegs; break;
    case Mips::HWR7: OpKind = MCK_HWRegs; break;
    case Mips::HWR8: OpKind = MCK_HWRegs; break;
    case Mips::HWR9: OpKind = MCK_HWRegs; break;
    case Mips::HWR10: OpKind = MCK_HWRegs; break;
    case Mips::HWR11: OpKind = MCK_HWRegs; break;
    case Mips::HWR12: OpKind = MCK_HWRegs; break;
    case Mips::HWR13: OpKind = MCK_HWRegs; break;
    case Mips::HWR14: OpKind = MCK_HWRegs; break;
    case Mips::HWR15: OpKind = MCK_HWRegs; break;
    case Mips::HWR16: OpKind = MCK_HWRegs; break;
    case Mips::HWR17: OpKind = MCK_HWRegs; break;
    case Mips::HWR18: OpKind = MCK_HWRegs; break;
    case Mips::HWR19: OpKind = MCK_HWRegs; break;
    case Mips::HWR20: OpKind = MCK_HWRegs; break;
    case Mips::HWR21: OpKind = MCK_HWRegs; break;
    case Mips::HWR22: OpKind = MCK_HWRegs; break;
    case Mips::HWR23: OpKind = MCK_HWRegs; break;
    case Mips::HWR24: OpKind = MCK_HWRegs; break;
    case Mips::HWR25: OpKind = MCK_HWRegs; break;
    case Mips::HWR26: OpKind = MCK_HWRegs; break;
    case Mips::HWR27: OpKind = MCK_HWRegs; break;
    case Mips::HWR28: OpKind = MCK_HWRegs; break;
    case Mips::HWR29: OpKind = MCK_HWRegs; break;
    case Mips::HWR30: OpKind = MCK_HWRegs; break;
    case Mips::HWR31: OpKind = MCK_HWRegs; break;
    case Mips::AC0: OpKind = MCK_ACC64; break;
    case Mips::AC1: OpKind = MCK_ACC64DSP; break;
    case Mips::AC2: OpKind = MCK_ACC64DSP; break;
    case Mips::AC3: OpKind = MCK_ACC64DSP; break;
    case Mips::AC0_64: OpKind = MCK_ACC128; break;
    case Mips::DSPCCond: OpKind = MCK_DSPCC; break;
    case Mips::MSAIR: OpKind = MCK_MSACtrl; break;
    case Mips::MSACSR: OpKind = MCK_MSACtrl; break;
    case Mips::MSAAccess: OpKind = MCK_MSACtrl; break;
    case Mips::MSASave: OpKind = MCK_MSACtrl; break;
    case Mips::MSAModify: OpKind = MCK_MSACtrl; break;
    case Mips::MSARequest: OpKind = MCK_MSACtrl; break;
    case Mips::MSAMap: OpKind = MCK_MSACtrl; break;
    case Mips::MSAUnmap: OpKind = MCK_MSACtrl; break;
    case Mips::MPL0: OpKind = MCK_OCTEON_MPL; break;
    case Mips::MPL1: OpKind = MCK_OCTEON_MPL; break;
    case Mips::MPL2: OpKind = MCK_OCTEON_MPL; break;
    case Mips::P0: OpKind = MCK_OCTEON_P; break;
    case Mips::P1: OpKind = MCK_OCTEON_P; break;
    case Mips::P2: OpKind = MCK_OCTEON_P; break;
    }
    return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
                                      getDiagKindFromRegisterClass(Kind);
  }

  if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
    return getDiagKindFromRegisterClass(Kind);

  return MCTargetAsmParser::Match_InvalidOperand;
}

#ifndef NDEBUG
const char *getMatchClassName(MatchClassKind Kind) {
  switch (Kind) {
  case InvalidMatchClass: return "InvalidMatchClass";
  case OptionalMatchClass: return "OptionalMatchClass";
  case MCK__35_: return "MCK__35_";
  case MCK__40_: return "MCK__40_";
  case MCK__41_: return "MCK__41_";
  case MCK_0: return "MCK_0";
  case MCK_16: return "MCK_16";
  case MCK__91_: return "MCK__91_";
  case MCK__93_: return "MCK__93_";
  case MCK_bit: return "MCK_bit";
  case MCK_inst: return "MCK_inst";
  case MCK_Reg15: return "MCK_Reg15";
  case MCK_Reg29: return "MCK_Reg29";
  case MCK_ACC128: return "MCK_ACC128";
  case MCK_ACC64: return "MCK_ACC64";
  case MCK_CPURAReg: return "MCK_CPURAReg";
  case MCK_CPUSPReg: return "MCK_CPUSPReg";
  case MCK_DSPCC: return "MCK_DSPCC";
  case MCK_GP32: return "MCK_GP32";
  case MCK_GP64: return "MCK_GP64";
  case MCK_GPR32ZERO: return "MCK_GPR32ZERO";
  case MCK_HI32: return "MCK_HI32";
  case MCK_HI64: return "MCK_HI64";
  case MCK_LO32: return "MCK_LO32";
  case MCK_LO64: return "MCK_LO64";
  case MCK_PC: return "MCK_PC";
  case MCK_SP64: return "MCK_SP64";
  case MCK_Reg11: return "MCK_Reg11";
  case MCK_Reg26: return "MCK_Reg26";
  case MCK_OCTEON_MPL: return "MCK_OCTEON_MPL";
  case MCK_OCTEON_P: return "MCK_OCTEON_P";
  case MCK_Reg4: return "MCK_Reg4";
  case MCK_Reg9: return "MCK_Reg9";
  case MCK_Reg19: return "MCK_Reg19";
  case MCK_Reg24: return "MCK_Reg24";
  case MCK_ACC64DSP: return "MCK_ACC64DSP";
  case MCK_HI32DSP: return "MCK_HI32DSP";
  case MCK_LO32DSP: return "MCK_LO32DSP";
  case MCK_Reg8: return "MCK_Reg8";
  case MCK_Reg10: return "MCK_Reg10";
  case MCK_Reg23: return "MCK_Reg23";
  case MCK_Reg25: return "MCK_Reg25";
  case MCK_Reg17: return "MCK_Reg17";
  case MCK_Reg18: return "MCK_Reg18";
  case MCK_Reg21: return "MCK_Reg21";
  case MCK_Reg36: return "MCK_Reg36";
  case MCK_CPU16Regs: return "MCK_CPU16Regs";
  case MCK_FCC: return "MCK_FCC";
  case MCK_GPRMM16MoveP: return "MCK_GPRMM16MoveP";
  case MCK_GPRMM16Zero: return "MCK_GPRMM16Zero";
  case MCK_MSACtrl: return "MCK_MSACtrl";
  case MCK_Reg22: return "MCK_Reg22";
  case MCK_CPU16RegsPlusSP: return "MCK_CPU16RegsPlusSP";
  case MCK_Reg31: return "MCK_Reg31";
  case MCK_Reg34: return "MCK_Reg34";
  case MCK_Reg39: return "MCK_Reg39";
  case MCK_Reg42: return "MCK_Reg42";
  case MCK_AFGR64: return "MCK_AFGR64";
  case MCK_MSA128WEvens: return "MCK_MSA128WEvens";
  case MCK_Reg37: return "MCK_Reg37";
  case MCK_Reg20: return "MCK_Reg20";
  case MCK_GPR32NONZERO: return "MCK_GPR32NONZERO";
  case MCK_CCR: return "MCK_CCR";
  case MCK_COP0: return "MCK_COP0";
  case MCK_COP2: return "MCK_COP2";
  case MCK_COP3: return "MCK_COP3";
  case MCK_DSPR: return "MCK_DSPR";
  case MCK_FGR32: return "MCK_FGR32";
  case MCK_FGR64: return "MCK_FGR64";
  case MCK_FGRH32: return "MCK_FGRH32";
  case MCK_GPR64: return "MCK_GPR64";
  case MCK_HWRegs: return "MCK_HWRegs";
  case MCK_MSA128F16: return "MCK_MSA128F16";
  case MCK_OddSP: return "MCK_OddSP";
  case MCK_ACC64DSPAsmReg: return "MCK_ACC64DSPAsmReg";
  case MCK_AFGR64AsmReg: return "MCK_AFGR64AsmReg";
  case MCK_CCRAsmReg: return "MCK_CCRAsmReg";
  case MCK_COP0AsmReg: return "MCK_COP0AsmReg";
  case MCK_COP2AsmReg: return "MCK_COP2AsmReg";
  case MCK_COP3AsmReg: return "MCK_COP3AsmReg";
  case MCK_FCCAsmReg: return "MCK_FCCAsmReg";
  case MCK_FGR32AsmReg: return "MCK_FGR32AsmReg";
  case MCK_FGR64AsmReg: return "MCK_FGR64AsmReg";
  case MCK_FGRH32AsmReg: return "MCK_FGRH32AsmReg";
  case MCK_GPR32AsmReg: return "MCK_GPR32AsmReg";
  case MCK_GPR32NonZeroAsmReg: return "MCK_GPR32NonZeroAsmReg";
  case MCK_GPR32ZeroAsmReg: return "MCK_GPR32ZeroAsmReg";
  case MCK_GPR64AsmReg: return "MCK_GPR64AsmReg";
  case MCK_GPRMM16AsmReg: return "MCK_GPRMM16AsmReg";
  case MCK_GPRMM16AsmRegMoveP: return "MCK_GPRMM16AsmRegMoveP";
  case MCK_GPRMM16AsmRegZero: return "MCK_GPRMM16AsmRegZero";
  case MCK_HI32DSPAsmReg: return "MCK_HI32DSPAsmReg";
  case MCK_HWRegsAsmReg: return "MCK_HWRegsAsmReg";
  case MCK_Imm: return "MCK_Imm";
  case MCK_LO32DSPAsmReg: return "MCK_LO32DSPAsmReg";
  case MCK_MSA128AsmReg: return "MCK_MSA128AsmReg";
  case MCK_MSACtrlAsmReg: return "MCK_MSACtrlAsmReg";
  case MCK_MicroMipsMemGP: return "MCK_MicroMipsMemGP";
  case MCK_MicroMipsMem: return "MCK_MicroMipsMem";
  case MCK_MicroMipsMemSP: return "MCK_MicroMipsMemSP";
  case MCK_InvNum: return "MCK_InvNum";
  case MCK_JumpTarget: return "MCK_JumpTarget";
  case MCK_MemOffsetSimm10: return "MCK_MemOffsetSimm10";
  case MCK_MemOffsetSimm10_1: return "MCK_MemOffsetSimm10_1";
  case MCK_MemOffsetSimm10_2: return "MCK_MemOffsetSimm10_2";
  case MCK_MemOffsetSimm10_3: return "MCK_MemOffsetSimm10_3";
  case MCK_MemOffsetSimm11: return "MCK_MemOffsetSimm11";
  case MCK_MemOffsetSimm12: return "MCK_MemOffsetSimm12";
  case MCK_MemOffsetSimm16: return "MCK_MemOffsetSimm16";
  case MCK_MemOffsetSimm9: return "MCK_MemOffsetSimm9";
  case MCK_MemOffsetSimmPtr: return "MCK_MemOffsetSimmPtr";
  case MCK_MemOffsetUimm4: return "MCK_MemOffsetUimm4";
  case MCK_Mem: return "MCK_Mem";
  case MCK_MovePRegPair: return "MCK_MovePRegPair";
  case MCK_RegList16: return "MCK_RegList16";
  case MCK_RegList: return "MCK_RegList";
  case MCK_Simm19_Lsl2: return "MCK_Simm19_Lsl2";
  case MCK_StrictlyAFGR64AsmReg: return "MCK_StrictlyAFGR64AsmReg";
  case MCK_StrictlyFGR32AsmReg: return "MCK_StrictlyFGR32AsmReg";
  case MCK_StrictlyFGR64AsmReg: return "MCK_StrictlyFGR64AsmReg";
  case MCK_ConstantImmz: return "MCK_ConstantImmz";
  case MCK_ConstantUImm1_0: return "MCK_ConstantUImm1_0";
  case MCK_ConstantUImm2_0: return "MCK_ConstantUImm2_0";
  case MCK_ConstantUImm2_1: return "MCK_ConstantUImm2_1";
  case MCK_ConstantUImm3_0: return "MCK_ConstantUImm3_0";
  case MCK_ConstantSImm4_0: return "MCK_ConstantSImm4_0";
  case MCK_ConstantUImm4_0: return "MCK_ConstantUImm4_0";
  case MCK_ConstantSImm5_0: return "MCK_ConstantSImm5_0";
  case MCK_ConstantUImm5_0: return "MCK_ConstantUImm5_0";
  case MCK_ConstantUImm5_1: return "MCK_ConstantUImm5_1";
  case MCK_ConstantUImm5_Plus1_Report_UImm6: return "MCK_ConstantUImm5_Plus1_Report_UImm6";
  case MCK_ConstantUImm5_32_Norm: return "MCK_ConstantUImm5_32_Norm";
  case MCK_ConstantUImm5_32: return "MCK_ConstantUImm5_32";
  case MCK_ConstantUImm5_0_Report_UImm6: return "MCK_ConstantUImm5_0_Report_UImm6";
  case MCK_ConstantUImm5_33: return "MCK_ConstantUImm5_33";
  case MCK_ConstantUImmRange2_64: return "MCK_ConstantUImmRange2_64";
  case MCK_UImm5Lsl2: return "MCK_UImm5Lsl2";
  case MCK_ConstantSImm6_0: return "MCK_ConstantSImm6_0";
  case MCK_ConstantUImm6_0: return "MCK_ConstantUImm6_0";
  case MCK_UImm6Lsl2: return "MCK_UImm6Lsl2";
  case MCK_ConstantUImm7_0: return "MCK_ConstantUImm7_0";
  case MCK_UImm7_N1: return "MCK_UImm7_N1";
  case MCK_ConstantUImm8_0: return "MCK_ConstantUImm8_0";
  case MCK_SImm7Lsl2: return "MCK_SImm7Lsl2";
  case MCK_ConstantSImm9_0: return "MCK_ConstantSImm9_0";
  case MCK_ConstantSImm10_0: return "MCK_ConstantSImm10_0";
  case MCK_ConstantUImm10_0: return "MCK_ConstantUImm10_0";
  case MCK_SImm10Lsl1: return "MCK_SImm10Lsl1";
  case MCK_ConstantSImm11_0: return "MCK_ConstantSImm11_0";
  case MCK_SImm10Lsl2: return "MCK_SImm10Lsl2";
  case MCK_SImm10Lsl3: return "MCK_SImm10Lsl3";
  case MCK_SImm16: return "MCK_SImm16";
  case MCK_SImm16_Relaxed: return "MCK_SImm16_Relaxed";
  case MCK_UImm16_AltRelaxed: return "MCK_UImm16_AltRelaxed";
  case MCK_UImm16: return "MCK_UImm16";
  case MCK_SImm19Lsl2: return "MCK_SImm19Lsl2";
  case MCK_UImm16_Relaxed: return "MCK_UImm16_Relaxed";
  case MCK_ConstantUImm20_0: return "MCK_ConstantUImm20_0";
  case MCK_ConstantUImm26_0: return "MCK_ConstantUImm26_0";
  case MCK_SImm32: return "MCK_SImm32";
  case MCK_SImm32_Relaxed: return "MCK_SImm32_Relaxed";
  case MCK_UImm32_Coerced: return "MCK_UImm32_Coerced";
  case NumMatchClassKinds: return "NumMatchClassKinds";
  }
  llvm_unreachable("unhandled MatchClassKind!");
}

#endif // NDEBUG
uint64_t MipsAsmParser::
ComputeAvailableFeatures(const FeatureBitset& FB) const {
  uint64_t Features = 0;
  if ((FB[Mips::FeatureMips2]))
    Features |= Feature_HasMips2;
  if ((FB[Mips::FeatureMips3_32]))
    Features |= Feature_HasMips3_32;
  if ((FB[Mips::FeatureMips3_32r2]))
    Features |= Feature_HasMips3_32r2;
  if ((FB[Mips::FeatureMips3]))
    Features |= Feature_HasMips3;
  if ((!FB[Mips::FeatureMips3]))
    Features |= Feature_NotMips3;
  if ((FB[Mips::FeatureMips4_32]))
    Features |= Feature_HasMips4_32;
  if ((!FB[Mips::FeatureMips4_32]))
    Features |= Feature_NotMips4_32;
  if ((FB[Mips::FeatureMips4_32r2]))
    Features |= Feature_HasMips4_32r2;
  if ((FB[Mips::FeatureMips5_32r2]))
    Features |= Feature_HasMips5_32r2;
  if ((FB[Mips::FeatureMips32]))
    Features |= Feature_HasMips32;
  if ((FB[Mips::FeatureMips32r2]))
    Features |= Feature_HasMips32r2;
  if ((FB[Mips::FeatureMips32r5]))
    Features |= Feature_HasMips32r5;
  if ((FB[Mips::FeatureMips32r6]))
    Features |= Feature_HasMips32r6;
  if ((!FB[Mips::FeatureMips32r6]))
    Features |= Feature_NotMips32r6;
  if ((FB[Mips::FeatureGP64Bit]))
    Features |= Feature_IsGP64bit;
  if ((!FB[Mips::FeatureGP64Bit]))
    Features |= Feature_IsGP32bit;
  if ((FB[Mips::FeaturePTR64Bit]))
    Features |= Feature_IsPTR64bit;
  if ((!FB[Mips::FeaturePTR64Bit]))
    Features |= Feature_IsPTR32bit;
  if ((FB[Mips::FeatureMips64]))
    Features |= Feature_HasMips64;
  if ((!FB[Mips::FeatureMips64]))
    Features |= Feature_NotMips64;
  if ((FB[Mips::FeatureMips64r2]))
    Features |= Feature_HasMips64r2;
  if ((FB[Mips::FeatureMips64r5]))
    Features |= Feature_HasMips64r5;
  if ((FB[Mips::FeatureMips64r6]))
    Features |= Feature_HasMips64r6;
  if ((!FB[Mips::FeatureMips64r6]))
    Features |= Feature_NotMips64r6;
  if ((FB[Mips::FeatureMips16]))
    Features |= Feature_InMips16Mode;
  if ((!FB[Mips::FeatureMips16]))
    Features |= Feature_NotInMips16Mode;
  if ((FB[Mips::FeatureCnMips]))
    Features |= Feature_HasCnMips;
  if ((!FB[Mips::FeatureCnMips]))
    Features |= Feature_NotCnMips;
  if ((FB[Mips::FeatureSym32]))
    Features |= Feature_IsSym32;
  if ((!FB[Mips::FeatureSym32]))
    Features |= Feature_IsSym64;
  if ((!FB[Mips::FeatureMips16]))
    Features |= Feature_HasStdEnc;
  if ((FB[Mips::FeatureMicroMips]))
    Features |= Feature_InMicroMips;
  if ((!FB[Mips::FeatureMicroMips]))
    Features |= Feature_NotInMicroMips;
  if ((FB[Mips::FeatureEVA]))
    Features |= Feature_HasEVA;
  if ((FB[Mips::FeatureMSA]))
    Features |= Feature_HasMSA;
  if ((!FB[Mips::FeatureMadd4]))
    Features |= Feature_HasMadd4;
  if ((FB[Mips::FeatureMT]))
    Features |= Feature_HasMT;
  if ((FB[Mips::FeatureUseIndirectJumpsHazard]))
    Features |= Feature_UseIndirectJumpsHazard;
  if ((!FB[Mips::FeatureUseIndirectJumpsHazard]))
    Features |= Feature_NoIndirectJumpGuards;
  if ((FB[Mips::FeatureCRC]))
    Features |= Feature_HasCRC;
  if ((FB[Mips::FeatureVirt]))
    Features |= Feature_HasVirt;
  if ((FB[Mips::FeatureGINV]))
    Features |= Feature_HasGINV;
  if ((FB[Mips::FeatureFP64Bit]))
    Features |= Feature_IsFP64bit;
  if ((!FB[Mips::FeatureFP64Bit]))
    Features |= Feature_NotFP64bit;
  if ((FB[Mips::FeatureSingleFloat]))
    Features |= Feature_IsSingleFloat;
  if ((!FB[Mips::FeatureSingleFloat]))
    Features |= Feature_IsNotSingleFloat;
  if ((!FB[Mips::FeatureSoftFloat]))
    Features |= Feature_IsNotSoftFloat;
  if ((FB[Mips::FeatureDSP]))
    Features |= Feature_HasDSP;
  if ((FB[Mips::FeatureDSPR2]))
    Features |= Feature_HasDSPR2;
  if ((FB[Mips::FeatureDSPR3]))
    Features |= Feature_HasDSPR3;
  return Features;
}

static bool checkAsmTiedOperandConstraints(const MipsAsmParser&AsmParser,
                               unsigned Kind,
                               const OperandVector &Operands,
                               uint64_t &ErrorInfo) {
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
  const uint8_t *Converter = ConversionTable[Kind];
  for (const uint8_t *p = Converter; *p; p+= 2) {
    switch (*p) {
    case CVT_Tied: {
      unsigned OpIdx = *(p+1);
      assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
                              std::begin(TiedAsmOperandTable)) &&
             "Tied operand not found");
      unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];
      unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];
      if (OpndNum1 != OpndNum2) {
        auto &SrcOp1 = Operands[OpndNum1];
        auto &SrcOp2 = Operands[OpndNum2];
        if (SrcOp1->isReg() && SrcOp2->isReg()) {
          if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) {
            ErrorInfo = OpndNum2;
            return false;
          }
        }
      }
      break;
    }
    default:
      break;
    }
  }
  return true;
}

static const char *const MnemonicTable =
    "\003abs\005abs.d\005abs.s\tabsq_s.ph\tabsq_s.qb\010absq_s.w\003add\005a"
    "dd.d\005add.s\007add_a.b\007add_a.d\007add_a.h\007add_a.w\004addi\005ad"
    "diu\007addiupc\taddiur1sp\007addiur2\007addius5\007addiusp\007addq.ph\t"
    "addq_s.ph\010addq_s.w\010addqh.ph\007addqh.w\naddqh_r.ph\taddqh_r.w\010"
    "adds_a.b\010adds_a.d\010adds_a.h\010adds_a.w\010adds_s.b\010adds_s.d\010"
    "adds_s.h\010adds_s.w\010adds_u.b\010adds_u.d\010adds_u.h\010adds_u.w\005"
    "addsc\004addu\007addu.ph\007addu.qb\006addu16\taddu_s.ph\taddu_s.qb\010"
    "adduh.qb\nadduh_r.qb\006addv.b\006addv.d\006addv.h\006addv.w\007addvi.b"
    "\007addvi.d\007addvi.h\007addvi.w\005addwc\005align\006aluipc\003and\005"
    "and.v\005and16\004andi\006andi.b\006andi16\006append\010asub_s.b\010asu"
    "b_s.d\010asub_s.h\010asub_s.w\010asub_u.b\010asub_u.d\010asub_u.h\010as"
    "ub_u.w\003aui\005auipc\007ave_s.b\007ave_s.d\007ave_s.h\007ave_s.w\007a"
    "ve_u.b\007ave_u.d\007ave_u.h\007ave_u.w\010aver_s.b\010aver_s.d\010aver"
    "_s.h\010aver_s.w\010aver_u.b\010aver_u.d\010aver_u.h\010aver_u.w\001b\003"
    "b16\005baddu\003bal\004balc\006balign\005bbit0\007bbit032\005bbit1\007b"
    "bit132\002bc\004bc16\006bc1eqz\007bc1eqzc\004bc1f\005bc1fl\006bc1nez\007"
    "bc1nezc\004bc1t\005bc1tl\006bc2eqz\007bc2eqzc\006bc2nez\007bc2nezc\006b"
    "clr.b\006bclr.d\006bclr.h\006bclr.w\007bclri.b\007bclri.d\007bclri.h\007"
    "bclri.w\003beq\004beqc\004beql\004beqz\006beqz16\007beqzalc\005beqzc\007"
    "beqzc16\005beqzl\003bge\004bgec\004bgel\004bgeu\005bgeuc\005bgeul\004bg"
    "ez\006bgezal\007bgezalc\007bgezall\007bgezals\005bgezc\005bgezl\003bgt\004"
    "bgtl\004bgtu\005bgtul\004bgtz\007bgtzalc\005bgtzc\005bgtzl\007binsl.b\007"
    "binsl.d\007binsl.h\007binsl.w\010binsli.b\010binsli.d\010binsli.h\010bi"
    "nsli.w\007binsr.b\007binsr.d\007binsr.h\007binsr.w\010binsri.b\010binsr"
    "i.d\010binsri.h\010binsri.w\006bitrev\007bitswap\003ble\004blel\004bleu"
    "\005bleul\004blez\007blezalc\005blezc\005blezl\003blt\004bltc\004bltl\004"
    "bltu\005bltuc\005bltul\004bltz\006bltzal\007bltzalc\007bltzall\007bltza"
    "ls\005bltzc\005bltzl\006bmnz.v\007bmnzi.b\005bmz.v\006bmzi.b\003bne\004"
    "bnec\006bneg.b\006bneg.d\006bneg.h\006bneg.w\007bnegi.b\007bnegi.d\007b"
    "negi.h\007bnegi.w\004bnel\004bnez\006bnez16\007bnezalc\005bnezc\007bnez"
    "c16\005bnezl\004bnvc\005bnz.b\005bnz.d\005bnz.h\005bnz.v\005bnz.w\004bo"
    "vc\010bposge32\tbposge32c\005break\007break16\006bsel.v\007bseli.b\006b"
    "set.b\006bset.d\006bset.h\006bset.w\007bseti.b\007bseti.d\007bseti.h\007"
    "bseti.w\005bteqz\005btnez\004bz.b\004bz.d\004bz.h\004bz.v\004bz.w\006c."
    "eq.d\006c.eq.s\005c.f.d\005c.f.s\006c.le.d\006c.le.s\006c.lt.d\006c.lt."
    "s\007c.nge.d\007c.nge.s\007c.ngl.d\007c.ngl.s\010c.ngle.d\010c.ngle.s\007"
    "c.ngt.d\007c.ngt.s\007c.ole.d\007c.ole.s\007c.olt.d\007c.olt.s\007c.seq"
    ".d\007c.seq.s\006c.sf.d\006c.sf.s\007c.ueq.d\007c.ueq.s\007c.ule.d\007c"
    ".ule.s\007c.ult.d\007c.ult.s\006c.un.d\006c.un.s\005cache\006cachee\010"
    "ceil.l.d\010ceil.l.s\010ceil.w.d\010ceil.w.s\005ceq.b\005ceq.d\005ceq.h"
    "\005ceq.w\006ceqi.b\006ceqi.d\006ceqi.h\006ceqi.w\004cfc1\004cfc2\006cf"
    "cmsa\005cftc1\004cins\006cins32\007class.d\007class.s\007cle_s.b\007cle"
    "_s.d\007cle_s.h\007cle_s.w\007cle_u.b\007cle_u.d\007cle_u.h\007cle_u.w\010"
    "clei_s.b\010clei_s.d\010clei_s.h\010clei_s.w\010clei_u.b\010clei_u.d\010"
    "clei_u.h\010clei_u.w\003clo\007clt_s.b\007clt_s.d\007clt_s.h\007clt_s.w"
    "\007clt_u.b\007clt_u.d\007clt_u.h\007clt_u.w\010clti_s.b\010clti_s.d\010"
    "clti_s.h\010clti_s.w\010clti_u.b\010clti_u.d\010clti_u.h\010clti_u.w\003"
    "clz\003cmp\010cmp.af.d\010cmp.af.s\010cmp.eq.d\tcmp.eq.ph\010cmp.eq.s\010"
    "cmp.le.d\tcmp.le.ph\010cmp.le.s\010cmp.lt.d\tcmp.lt.ph\010cmp.lt.s\tcmp"
    ".saf.d\tcmp.saf.s\tcmp.seq.d\tcmp.seq.s\tcmp.sle.d\tcmp.sle.s\tcmp.slt."
    "d\tcmp.slt.s\ncmp.sueq.d\ncmp.sueq.s\ncmp.sule.d\ncmp.sule.s\ncmp.sult."
    "d\ncmp.sult.s\tcmp.sun.d\tcmp.sun.s\tcmp.ueq.d\tcmp.ueq.s\tcmp.ule.d\tc"
    "mp.ule.s\tcmp.ult.d\tcmp.ult.s\010cmp.un.d\010cmp.un.s\014cmpgdu.eq.qb\014"
    "cmpgdu.le.qb\014cmpgdu.lt.qb\013cmpgu.eq.qb\013cmpgu.le.qb\013cmpgu.lt."
    "qb\004cmpi\ncmpu.eq.qb\ncmpu.le.qb\ncmpu.lt.qb\010copy_s.b\010copy_s.d\010"
    "copy_s.h\010copy_s.w\010copy_u.b\010copy_u.h\010copy_u.w\006crc32b\007c"
    "rc32cb\007crc32cd\007crc32ch\007crc32cw\006crc32d\006crc32h\006crc32w\004"
    "ctc1\004ctc2\006ctcmsa\005cttc1\007cvt.d.l\007cvt.d.s\007cvt.d.w\007cvt"
    ".l.d\007cvt.l.s\007cvt.s.d\007cvt.s.l\007cvt.s.w\007cvt.w.d\007cvt.w.s\004"
    "dadd\005daddi\006daddiu\005daddu\004dahi\006dalign\004dati\004daui\010d"
    "bitswap\004dclo\004dclz\004ddiv\005ddivu\005deret\004dext\005dextm\005d"
    "extu\002di\004dins\005dinsm\005dinsu\003div\005div.d\005div.s\007div_s."
    "b\007div_s.d\007div_s.h\007div_s.w\007div_u.b\007div_u.d\007div_u.h\007"
    "div_u.w\004divu\003dla\003dli\004dlsa\005dmfc0\005dmfc1\005dmfc2\006dmf"
    "gc0\004dmod\005dmodu\003dmt\005dmtc0\005dmtc1\005dmtc2\006dmtgc0\004dmu"
    "h\005dmuhu\004dmul\005dmulo\006dmulou\005dmult\006dmultu\005dmulu\004dn"
    "eg\005dnegu\010dotp_s.d\010dotp_s.h\010dotp_s.w\010dotp_u.d\010dotp_u.h"
    "\010dotp_u.w\010dpa.w.ph\tdpadd_s.d\tdpadd_s.h\tdpadd_s.w\tdpadd_u.d\td"
    "padd_u.h\tdpadd_u.w\013dpaq_s.w.ph\013dpaq_sa.l.w\014dpaqx_s.w.ph\015dp"
    "aqx_sa.w.ph\ndpau.h.qbl\ndpau.h.qbr\tdpax.w.ph\004dpop\010dps.w.ph\013d"
    "psq_s.w.ph\013dpsq_sa.l.w\014dpsqx_s.w.ph\015dpsqx_sa.w.ph\ndpsu.h.qbl\n"
    "dpsu.h.qbr\tdpsub_s.d\tdpsub_s.h\tdpsub_s.w\tdpsub_u.d\tdpsub_u.h\tdpsu"
    "b_u.w\tdpsx.w.ph\004drem\005dremu\004drol\004dror\005drotr\007drotr32\006"
    "drotrv\004dsbh\004dshd\004dsll\006dsll32\005dsllv\004dsra\006dsra32\005"
    "dsrav\004dsrl\006dsrl32\005dsrlv\004dsub\005dsubi\005dsubu\003dvp\004dv"
    "pe\003ehb\002ei\003emt\004eret\006eretnc\003evp\004evpe\003ext\004extp\006"
    "extpdp\007extpdpv\005extpv\006extr.w\010extr_r.w\textr_rs.w\010extr_s.h"
    "\007extrv.w\textrv_r.w\nextrv_rs.w\textrv_s.h\004exts\006exts32\006fadd"
    ".d\006fadd.w\006fcaf.d\006fcaf.w\006fceq.d\006fceq.w\010fclass.d\010fcl"
    "ass.w\006fcle.d\006fcle.w\006fclt.d\006fclt.w\006fcne.d\006fcne.w\006fc"
    "or.d\006fcor.w\007fcueq.d\007fcueq.w\007fcule.d\007fcule.w\007fcult.d\007"
    "fcult.w\006fcun.d\006fcun.w\007fcune.d\007fcune.w\006fdiv.d\006fdiv.w\007"
    "fexdo.h\007fexdo.w\007fexp2.d\007fexp2.w\010fexupl.d\010fexupl.w\010fex"
    "upr.d\010fexupr.w\tffint_s.d\tffint_s.w\tffint_u.d\tffint_u.w\006ffql.d"
    "\006ffql.w\006ffqr.d\006ffqr.w\006fill.b\006fill.d\006fill.h\006fill.w\007"
    "flog2.d\007flog2.w\tfloor.l.d\tfloor.l.s\tfloor.w.d\tfloor.w.s\007fmadd"
    ".d\007fmadd.w\006fmax.d\006fmax.w\010fmax_a.d\010fmax_a.w\006fmin.d\006"
    "fmin.w\010fmin_a.d\010fmin_a.w\007fmsub.d\007fmsub.w\006fmul.d\006fmul."
    "w\004fork\006frcp.d\006frcp.w\007frint.d\007frint.w\010frsqrt.d\010frsq"
    "rt.w\006fsaf.d\006fsaf.w\006fseq.d\006fseq.w\006fsle.d\006fsle.w\006fsl"
    "t.d\006fslt.w\006fsne.d\006fsne.w\006fsor.d\006fsor.w\007fsqrt.d\007fsq"
    "rt.w\006fsub.d\006fsub.w\007fsueq.d\007fsueq.w\007fsule.d\007fsule.w\007"
    "fsult.d\007fsult.w\006fsun.d\006fsun.w\007fsune.d\007fsune.w\tftint_s.d"
    "\tftint_s.w\tftint_u.d\tftint_u.w\005ftq.h\005ftq.w\nftrunc_s.d\nftrunc"
    "_s.w\nftrunc_u.d\nftrunc_u.w\005ginvi\005ginvt\010hadd_s.d\010hadd_s.h\010"
    "hadd_s.w\010hadd_u.d\010hadd_u.h\010hadd_u.w\010hsub_s.d\010hsub_s.h\010"
    "hsub_s.w\010hsub_u.d\010hsub_u.h\010hsub_u.w\007hypcall\007ilvev.b\007i"
    "lvev.d\007ilvev.h\007ilvev.w\006ilvl.b\006ilvl.d\006ilvl.h\006ilvl.w\007"
    "ilvod.b\007ilvod.d\007ilvod.h\007ilvod.w\006ilvr.b\006ilvr.d\006ilvr.h\006"
    "ilvr.w\003ins\010insert.b\010insert.d\010insert.h\010insert.w\004insv\007"
    "insve.b\007insve.d\007insve.h\007insve.w\001j\003jal\004jalr\007jalr.hb"
    "\005jalrc\010jalrc.hb\005jalrs\007jalrs16\004jals\004jalx\005jialc\003j"
    "ic\002jr\005jr.hb\004jr16\tjraddiusp\003jrc\005jrc16\njrcaddiusp\003l.d"
    "\003l.s\002la\004lapc\002lb\003lbe\003lbu\005lbu16\004lbue\004lbux\002l"
    "d\004ld.b\004ld.d\004ld.h\004ld.w\004ldc1\004ldc2\004ldc3\005ldi.b\005l"
    "di.d\005ldi.h\005ldi.w\003ldl\004ldpc\003ldr\005ldxc1\002lh\003lhe\003l"
    "hu\005lhu16\004lhue\003lhx\002li\004li.d\004li.s\004li16\002ll\003lld\003"
    "lle\003lsa\003lui\005luxc1\002lw\004lw16\004lwc1\004lwc2\004lwc3\003lwe"
    "\003lwl\004lwle\003lwm\005lwm16\005lwm32\003lwp\004lwpc\003lwr\004lwre\003"
    "lwu\005lwupc\003lwx\005lwxc1\004lwxs\004madd\006madd.d\006madd.s\010mad"
    "d_q.h\010madd_q.w\007maddf.d\007maddf.s\tmaddr_q.h\tmaddr_q.w\005maddu\007"
    "maddv.b\007maddv.d\007maddv.h\007maddv.w\013maq_s.w.phl\013maq_s.w.phr\014"
    "maq_sa.w.phl\014maq_sa.w.phr\005max.d\005max.s\007max_a.b\007max_a.d\007"
    "max_a.h\007max_a.w\007max_s.b\007max_s.d\007max_s.h\007max_s.w\007max_u"
    ".b\007max_u.d\007max_u.h\007max_u.w\006maxa.d\006maxa.s\010maxi_s.b\010"
    "maxi_s.d\010maxi_s.h\010maxi_s.w\010maxi_u.b\010maxi_u.d\010maxi_u.h\010"
    "maxi_u.w\004mfc0\004mfc1\004mfc2\005mfgc0\005mfhc0\005mfhc1\005mfhc2\006"
    "mfhgc0\004mfhi\006mfhi16\004mflo\006mflo16\006mftacx\005mftc0\005mftc1\006"
    "mftdsp\006mftgpr\006mfthc1\005mfthi\005mftlo\004mftr\005min.d\005min.s\007"
    "min_a.b\007min_a.d\007min_a.h\007min_a.w\007min_s.b\007min_s.d\007min_s"
    ".h\007min_s.w\007min_u.b\007min_u.d\007min_u.h\007min_u.w\006mina.d\006"
    "mina.s\010mini_s.b\010mini_s.d\010mini_s.h\010mini_s.w\010mini_u.b\010m"
    "ini_u.d\010mini_u.h\010mini_u.w\003mod\007mod_s.b\007mod_s.d\007mod_s.h"
    "\007mod_s.w\007mod_u.b\007mod_u.d\007mod_u.h\007mod_u.w\006modsub\004mo"
    "du\005mov.d\005mov.s\004move\006move.v\006move16\005movep\004movf\006mo"
    "vf.d\006movf.s\004movn\006movn.d\006movn.s\004movt\006movt.d\006movt.s\004"
    "movz\006movz.d\006movz.s\004msub\006msub.d\006msub.s\010msub_q.h\010msu"
    "b_q.w\007msubf.d\007msubf.s\tmsubr_q.h\tmsubr_q.w\005msubu\007msubv.b\007"
    "msubv.d\007msubv.h\007msubv.w\004mtc0\004mtc1\004mtc2\005mtgc0\005mthc0"
    "\005mthc1\005mthc2\006mthgc0\004mthi\006mthlip\004mtlo\004mtm0\004mtm1\004"
    "mtm2\004mtp0\004mtp1\004mtp2\006mttacx\005mttc0\005mttc1\006mttdsp\006m"
    "ttgpr\006mtthc1\005mtthi\005mttlo\004mttr\003muh\004muhu\003mul\005mul."
    "d\006mul.ph\005mul.s\007mul_q.h\007mul_q.w\010mul_s.ph\015muleq_s.w.phl"
    "\015muleq_s.w.phr\016muleu_s.ph.qbl\016muleu_s.ph.qbr\004mulo\005mulou\n"
    "mulq_rs.ph\tmulq_rs.w\tmulq_s.ph\010mulq_s.w\010mulr_q.h\010mulr_q.w\nm"
    "ulsa.w.ph\015mulsaq_s.w.ph\004mult\005multu\004mulu\006mulv.b\006mulv.d"
    "\006mulv.h\006mulv.w\003neg\005neg.d\005neg.s\004negu\006nloc.b\006nloc"
    ".d\006nloc.h\006nloc.w\006nlzc.b\006nlzc.d\006nlzc.h\006nlzc.w\007nmadd"
    ".d\007nmadd.s\007nmsub.d\007nmsub.s\003nop\003nor\005nor.v\006nori.b\003"
    "not\005not16\002or\004or.v\004or16\003ori\005ori.b\tpackrl.ph\005pause\007"
    "pckev.b\007pckev.d\007pckev.h\007pckev.w\007pckod.b\007pckod.d\007pckod"
    ".h\007pckod.w\006pcnt.b\006pcnt.d\006pcnt.h\006pcnt.w\007pick.ph\007pic"
    "k.qb\003pop\014preceq.w.phl\014preceq.w.phr\016precequ.ph.qbl\017preceq"
    "u.ph.qbla\016precequ.ph.qbr\017precequ.ph.qbra\015preceu.ph.qbl\016prec"
    "eu.ph.qbla\015preceu.ph.qbr\016preceu.ph.qbra\013precr.qb.ph\016precr_s"
    "ra.ph.w\020precr_sra_r.ph.w\013precrq.ph.w\014precrq.qb.ph\016precrq_rs"
    ".ph.w\017precrqu_s.qb.ph\004pref\005prefe\005prefx\007prepend\nraddu.w."
    "qb\005rddsp\005rdhwr\006rdpgpr\007recip.d\007recip.s\003rem\004remu\007"
    "repl.ph\007repl.qb\010replv.ph\010replv.qb\006rint.d\006rint.s\003rol\003"
    "ror\004rotr\005rotrv\tround.l.d\tround.l.s\tround.w.d\tround.w.s\007rsq"
    "rt.d\007rsqrt.s\003s.d\003s.s\007sat_s.b\007sat_s.d\007sat_s.h\007sat_s"
    ".w\007sat_u.b\007sat_u.d\007sat_u.h\007sat_u.w\002sb\004sb16\003sbe\002"
    "sc\003scd\003sce\002sd\005sdbbp\007sdbbp16\004sdc1\004sdc2\004sdc3\003s"
    "dl\003sdr\005sdxc1\003seb\003seh\005sel.d\005sel.s\006seleqz\010seleqz."
    "d\010seleqz.s\006selnez\010selnez.d\010selnez.s\003seq\004seqi\003sgt\004"
    "sgtu\002sh\004sh16\003she\005shf.b\005shf.h\005shf.w\005shilo\006shilov"
    "\007shll.ph\007shll.qb\tshll_s.ph\010shll_s.w\010shllv.ph\010shllv.qb\n"
    "shllv_s.ph\tshllv_s.w\007shra.ph\007shra.qb\tshra_r.ph\tshra_r.qb\010sh"
    "ra_r.w\010shrav.ph\010shrav.qb\nshrav_r.ph\nshrav_r.qb\tshrav_r.w\007sh"
    "rl.ph\007shrl.qb\010shrlv.ph\010shrlv.qb\005sld.b\005sld.d\005sld.h\005"
    "sld.w\006sldi.b\006sldi.d\006sldi.h\006sldi.w\003sll\005sll.b\005sll.d\005"
    "sll.h\005sll.w\005sll16\006slli.b\006slli.d\006slli.h\006slli.w\004sllv"
    "\003slt\004slti\005sltiu\004sltu\003sne\004snei\007splat.b\007splat.d\007"
    "splat.h\007splat.w\010splati.b\010splati.d\010splati.h\010splati.w\006s"
    "qrt.d\006sqrt.s\003sra\005sra.b\005sra.d\005sra.h\005sra.w\006srai.b\006"
    "srai.d\006srai.h\006srai.w\006srar.b\006srar.d\006srar.h\006srar.w\007s"
    "rari.b\007srari.d\007srari.h\007srari.w\004srav\003srl\005srl.b\005srl."
    "d\005srl.h\005srl.w\005srl16\006srli.b\006srli.d\006srli.h\006srli.w\006"
    "srlr.b\006srlr.d\006srlr.h\006srlr.w\007srlri.b\007srlri.d\007srlri.h\007"
    "srlri.w\004srlv\005ssnop\004st.b\004st.d\004st.h\004st.w\003sub\005sub."
    "d\005sub.s\007subq.ph\tsubq_s.ph\010subq_s.w\010subqh.ph\007subqh.w\nsu"
    "bqh_r.ph\tsubqh_r.w\010subs_s.b\010subs_s.d\010subs_s.h\010subs_s.w\010"
    "subs_u.b\010subs_u.d\010subs_u.h\010subs_u.w\nsubsus_u.b\nsubsus_u.d\ns"
    "ubsus_u.h\nsubsus_u.w\nsubsuu_s.b\nsubsuu_s.d\nsubsuu_s.h\nsubsuu_s.w\004"
    "subu\007subu.ph\007subu.qb\006subu16\tsubu_s.ph\tsubu_s.qb\010subuh.qb\n"
    "subuh_r.qb\006subv.b\006subv.d\006subv.h\006subv.w\007subvi.b\007subvi."
    "d\007subvi.h\007subvi.w\005suxc1\002sw\004sw16\004swc1\004swc2\004swc3\003"
    "swe\003swl\004swle\003swm\005swm16\005swm32\003swp\003swr\004swre\005sw"
    "xc1\004sync\005synci\nsynciobdma\005syncs\005syncw\006syncws\007syscall"
    "\003teq\004teqi\003tge\004tgei\005tgeiu\004tgeu\007tlbginv\010tlbginvf\005"
    "tlbgp\005tlbgr\006tlbgwi\006tlbgwr\006tlbinv\007tlbinvf\004tlbp\004tlbr"
    "\005tlbwi\005tlbwr\003tlt\004tlti\005tltiu\004tltu\003tne\004tnei\ttrun"
    "c.l.d\ttrunc.l.s\ttrunc.w.d\ttrunc.w.s\003ulh\004ulhu\003ulw\003ush\003"
    "usw\006v3mulu\004vmm0\005vmulu\006vshf.b\006vshf.d\006vshf.h\006vshf.w\004"
    "wait\005wrdsp\006wrpgpr\004wsbh\003xor\005xor.v\005xor16\004xori\006xor"
    "i.b\005yield";

namespace {
  struct MatchEntry {
    uint16_t Mnemonic;
    uint16_t Opcode;
    uint16_t ConvertFn;
    uint64_t RequiredFeatures;
    uint8_t Classes[8];
    StringRef getMnemonic() const {
      return StringRef(MnemonicTable + Mnemonic + 1,
                       MnemonicTable[Mnemonic]);
    }
  };

  // Predicate for searching for an opcode.
  struct LessOpcode {
    bool operator()(const MatchEntry &LHS, StringRef RHS) {
      return LHS.getMnemonic() < RHS;
    }
    bool operator()(StringRef LHS, const MatchEntry &RHS) {
      return LHS < RHS.getMnemonic();
    }
    bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
      return LHS.getMnemonic() < RHS.getMnemonic();
    }
  };
} // end anonymous namespace.

static const MatchEntry MatchTable0[] = {
  { 0 /* abs */, Mips::ABSMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 4 /* abs.d */, Mips::FABS_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 4 /* abs.d */, Mips::FABS_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 4 /* abs.d */, Mips::FABS_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 4 /* abs.d */, Mips::FABS_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 10 /* abs.s */, Mips::FABS_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 10 /* abs.s */, Mips::FABS_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 16 /* absq_s.ph */, Mips::ABSQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 16 /* absq_s.ph */, Mips::ABSQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 26 /* absq_s.qb */, Mips::ABSQ_S_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 26 /* absq_s.qb */, Mips::ABSQ_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 36 /* absq_s.w */, Mips::ABSQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 36 /* absq_s.w */, Mips::ABSQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 45 /* add */, Mips::ADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 45 /* add */, Mips::ADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 45 /* add */, Mips::ADD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 45 /* add */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 45 /* add */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 45 /* add */, Mips::ADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 45 /* add */, Mips::ADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 45 /* add */, Mips::ADD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 45 /* add */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 45 /* add */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 49 /* add.d */, Mips::FADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 49 /* add.d */, Mips::FADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 49 /* add.d */, Mips::FADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 49 /* add.d */, Mips::FADD_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 55 /* add.s */, Mips::FADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 55 /* add.s */, Mips::FADD_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 55 /* add.s */, Mips::FADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 61 /* add_a.b */, Mips::ADD_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 69 /* add_a.d */, Mips::ADD_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 77 /* add_a.h */, Mips::ADD_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 85 /* add_a.w */, Mips::ADD_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 93 /* addi */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 93 /* addi */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
  { 93 /* addi */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 93 /* addi */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
  { 98 /* addiu */, Mips::AddiuSpImmX16, Convert__SImm161_1, Feature_InMips16Mode, { MCK_CPUSPReg, MCK_SImm16 }, },
  { 98 /* addiu */, Mips::AddiuRxImmX16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
  { 98 /* addiu */, Mips::ADDIU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 98 /* addiu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 98 /* addiu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
  { 98 /* addiu */, Mips::AddiuRxPcImmX16, Convert__Reg1_0__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_PC, MCK_SImm16 }, },
  { 98 /* addiu */, Mips::AddiuRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, },
  { 98 /* addiu */, Mips::ADDIU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 98 /* addiu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 98 /* addiu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
  { 98 /* addiu */, Mips::AddiuSpImm16, Convert__SImm161_1, Feature_InMips16Mode, { MCK_CPUSPReg, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
  { 98 /* addiu */, Mips::AddiuRxRxImm16, Convert__Reg1_0__Tie0_1_1__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
  { 104 /* addiupc */, Mips::ADDIUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
  { 104 /* addiupc */, Mips::ADDIUPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
  { 104 /* addiupc */, Mips::ADDIUPC_MM, Convert__GPRMM16AsmReg1_0__Imm1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_Imm }, },
  { 112 /* addiur1sp */, Mips::ADDIUR1SP_MM, Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_UImm6Lsl2 }, },
  { 122 /* addiur2 */, Mips::ADDIUR2_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
  { 130 /* addius5 */, Mips::ADDIUS5_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantSImm4_0 }, },
  { 138 /* addiusp */, Mips::ADDIUSP_MM, Convert__Imm1_0, Feature_InMicroMips, { MCK_Imm }, },
  { 146 /* addq.ph */, Mips::ADDQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 146 /* addq.ph */, Mips::ADDQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 154 /* addq_s.ph */, Mips::ADDQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 154 /* addq_s.ph */, Mips::ADDQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 164 /* addq_s.w */, Mips::ADDQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 164 /* addq_s.w */, Mips::ADDQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 173 /* addqh.ph */, Mips::ADDQH_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 173 /* addqh.ph */, Mips::ADDQH_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 182 /* addqh.w */, Mips::ADDQH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 182 /* addqh.w */, Mips::ADDQH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 190 /* addqh_r.ph */, Mips::ADDQH_R_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 190 /* addqh_r.ph */, Mips::ADDQH_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 201 /* addqh_r.w */, Mips::ADDQH_R_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 201 /* addqh_r.w */, Mips::ADDQH_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 211 /* adds_a.b */, Mips::ADDS_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 220 /* adds_a.d */, Mips::ADDS_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 229 /* adds_a.h */, Mips::ADDS_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 238 /* adds_a.w */, Mips::ADDS_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 247 /* adds_s.b */, Mips::ADDS_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 256 /* adds_s.d */, Mips::ADDS_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 265 /* adds_s.h */, Mips::ADDS_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 274 /* adds_s.w */, Mips::ADDS_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 283 /* adds_u.b */, Mips::ADDS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 292 /* adds_u.d */, Mips::ADDS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 301 /* adds_u.h */, Mips::ADDS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 310 /* adds_u.w */, Mips::ADDS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 319 /* addsc */, Mips::ADDSC_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 319 /* addsc */, Mips::ADDSC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 325 /* addu */, Mips::ADDU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 325 /* addu */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 325 /* addu */, Mips::ADDu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 325 /* addu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 325 /* addu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 325 /* addu */, Mips::AdduRxRyRz16, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_CPU16Regs }, },
  { 325 /* addu */, Mips::ADDU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 325 /* addu */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 325 /* addu */, Mips::ADDu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 325 /* addu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 325 /* addu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 330 /* addu.ph */, Mips::ADDU_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 330 /* addu.ph */, Mips::ADDU_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 338 /* addu.qb */, Mips::ADDU_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 338 /* addu.qb */, Mips::ADDU_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 346 /* addu16 */, Mips::ADDU16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
  { 346 /* addu16 */, Mips::ADDU16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
  { 353 /* addu_s.ph */, Mips::ADDU_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 353 /* addu_s.ph */, Mips::ADDU_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 363 /* addu_s.qb */, Mips::ADDU_S_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 363 /* addu_s.qb */, Mips::ADDU_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 373 /* adduh.qb */, Mips::ADDUH_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 373 /* adduh.qb */, Mips::ADDUH_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 382 /* adduh_r.qb */, Mips::ADDUH_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 382 /* adduh_r.qb */, Mips::ADDUH_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 393 /* addv.b */, Mips::ADDV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 400 /* addv.d */, Mips::ADDV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 407 /* addv.h */, Mips::ADDV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 414 /* addv.w */, Mips::ADDV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 421 /* addvi.b */, Mips::ADDVI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 429 /* addvi.d */, Mips::ADDVI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 437 /* addvi.h */, Mips::ADDVI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 445 /* addvi.w */, Mips::ADDVI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 453 /* addwc */, Mips::ADDWC_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 453 /* addwc */, Mips::ADDWC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 459 /* align */, Mips::ALIGN, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
  { 459 /* align */, Mips::ALIGN_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
  { 465 /* aluipc */, Mips::ALUIPC, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 465 /* aluipc */, Mips::ALUIPC_MMR6, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 472 /* and */, Mips::AndRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
  { 472 /* and */, Mips::AND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 472 /* and */, Mips::AND_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 472 /* and */, Mips::AND_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 472 /* and */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 472 /* and */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 472 /* and */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 472 /* and */, Mips::ANDi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
  { 472 /* and */, Mips::AND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 472 /* and */, Mips::AND_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 472 /* and */, Mips::AND_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 472 /* and */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 472 /* and */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 472 /* and */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 472 /* and */, Mips::ANDi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
  { 476 /* and.v */, Mips::AND_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 482 /* and16 */, Mips::AND16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
  { 482 /* and16 */, Mips::AND16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
  { 488 /* andi */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 488 /* andi */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 488 /* andi */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 488 /* andi */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 488 /* andi */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 488 /* andi */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 493 /* andi.b */, Mips::ANDI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
  { 500 /* andi16 */, Mips::ANDI16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
  { 500 /* andi16 */, Mips::ANDI16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
  { 507 /* append */, Mips::APPEND_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 507 /* append */, Mips::APPEND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 514 /* asub_s.b */, Mips::ASUB_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 523 /* asub_s.d */, Mips::ASUB_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 532 /* asub_s.h */, Mips::ASUB_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 541 /* asub_s.w */, Mips::ASUB_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 550 /* asub_u.b */, Mips::ASUB_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 559 /* asub_u.d */, Mips::ASUB_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 568 /* asub_u.h */, Mips::ASUB_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 577 /* asub_u.w */, Mips::ASUB_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 586 /* aui */, Mips::AUI, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 586 /* aui */, Mips::AUI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 590 /* auipc */, Mips::AUIPC, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 590 /* auipc */, Mips::AUIPC_MMR6, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 596 /* ave_s.b */, Mips::AVE_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 604 /* ave_s.d */, Mips::AVE_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 612 /* ave_s.h */, Mips::AVE_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 620 /* ave_s.w */, Mips::AVE_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 628 /* ave_u.b */, Mips::AVE_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 636 /* ave_u.d */, Mips::AVE_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 644 /* ave_u.h */, Mips::AVE_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 652 /* ave_u.w */, Mips::AVE_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 660 /* aver_s.b */, Mips::AVER_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 669 /* aver_s.d */, Mips::AVER_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 678 /* aver_s.h */, Mips::AVER_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 687 /* aver_s.w */, Mips::AVER_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 696 /* aver_u.b */, Mips::AVER_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 705 /* aver_u.d */, Mips::AVER_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 714 /* aver_u.h */, Mips::AVER_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 723 /* aver_u.w */, Mips::AVER_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 732 /* b */, Mips::BEQ, Convert__regZERO__regZERO__JumpTarget1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_JumpTarget }, },
  { 732 /* b */, Mips::B_MM_Pseudo, Convert__JumpTarget1_0, Feature_InMicroMips, { MCK_JumpTarget }, },
  { 732 /* b */, Mips::BimmX16, Convert__JumpTarget1_0, Feature_InMips16Mode, { MCK_JumpTarget }, },
  { 732 /* b */, Mips::B_MMR6_Pseudo, Convert__JumpTarget1_0, 0, { MCK_JumpTarget }, },
  { 732 /* b */, Mips::Bimm16, Convert__JumpTarget1_0, Feature_InMips16Mode, { MCK_JumpTarget, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
  { 734 /* b16 */, Mips::BC16_MMR6, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_JumpTarget }, },
  { 734 /* b16 */, Mips::B16_MM, Convert__JumpTarget1_0, Feature_InMicroMips, { MCK_JumpTarget }, },
  { 738 /* baddu */, Mips::BADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 738 /* baddu */, Mips::BADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 744 /* bal */, Mips::BGEZAL, Convert__regZERO__JumpTarget1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_JumpTarget }, },
  { 744 /* bal */, Mips::BAL, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_JumpTarget }, },
  { 744 /* bal */, Mips::BGEZAL_MM, Convert__regZERO__JumpTarget1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_JumpTarget }, },
  { 748 /* balc */, Mips::BALC, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_JumpTarget }, },
  { 748 /* balc */, Mips::BALC_MMR6, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_JumpTarget }, },
  { 753 /* balign */, Mips::BALIGN_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
  { 753 /* balign */, Mips::BALIGN, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
  { 760 /* bbit0 */, Mips::BBIT032, Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_JumpTarget }, },
  { 760 /* bbit0 */, Mips::BBIT0, Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_JumpTarget }, },
  { 766 /* bbit032 */, Mips::BBIT032, Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_JumpTarget }, },
  { 774 /* bbit1 */, Mips::BBIT132, Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_JumpTarget }, },
  { 774 /* bbit1 */, Mips::BBIT1, Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_JumpTarget }, },
  { 780 /* bbit132 */, Mips::BBIT132, Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_JumpTarget }, },
  { 788 /* bc */, Mips::BC, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_JumpTarget }, },
  { 788 /* bc */, Mips::BC_MMR6, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_JumpTarget }, },
  { 791 /* bc16 */, Mips::BC16_MMR6, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_JumpTarget }, },
  { 796 /* bc1eqz */, Mips::BC1EQZ, Convert__FGR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_JumpTarget }, },
  { 803 /* bc1eqzc */, Mips::BC1EQZC_MMR6, Convert__FGR64AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_JumpTarget }, },
  { 811 /* bc1f */, Mips::BC1F, Convert__regFCC0__JumpTarget1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_JumpTarget }, },
  { 811 /* bc1f */, Mips::BC1F_MM, Convert__regFCC0__JumpTarget1_0, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_JumpTarget }, },
  { 811 /* bc1f */, Mips::BC1F, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, },
  { 811 /* bc1f */, Mips::BC1F_MM, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, },
  { 816 /* bc1fl */, Mips::BC1FL, Convert__regFCC0__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_JumpTarget }, },
  { 816 /* bc1fl */, Mips::BC1FL, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, },
  { 822 /* bc1nez */, Mips::BC1NEZ, Convert__FGR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_JumpTarget }, },
  { 829 /* bc1nezc */, Mips::BC1NEZC_MMR6, Convert__FGR64AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_JumpTarget }, },
  { 837 /* bc1t */, Mips::BC1T, Convert__regFCC0__JumpTarget1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_JumpTarget }, },
  { 837 /* bc1t */, Mips::BC1T_MM, Convert__regFCC0__JumpTarget1_0, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_JumpTarget }, },
  { 837 /* bc1t */, Mips::BC1T, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, },
  { 837 /* bc1t */, Mips::BC1T_MM, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, },
  { 842 /* bc1tl */, Mips::BC1TL, Convert__regFCC0__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_JumpTarget }, },
  { 842 /* bc1tl */, Mips::BC1TL, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, },
  { 848 /* bc2eqz */, Mips::BC2EQZ, Convert__COP2AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_JumpTarget }, },
  { 855 /* bc2eqzc */, Mips::BC2EQZC_MMR6, Convert__COP2AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_JumpTarget }, },
  { 863 /* bc2nez */, Mips::BC2NEZ, Convert__COP2AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_JumpTarget }, },
  { 870 /* bc2nezc */, Mips::BC2NEZC_MMR6, Convert__COP2AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_JumpTarget }, },
  { 878 /* bclr.b */, Mips::BCLR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 885 /* bclr.d */, Mips::BCLR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 892 /* bclr.h */, Mips::BCLR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 899 /* bclr.w */, Mips::BCLR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 906 /* bclri.b */, Mips::BCLRI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
  { 914 /* bclri.d */, Mips::BCLRI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
  { 922 /* bclri.h */, Mips::BCLRI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
  { 930 /* bclri.w */, Mips::BCLRI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 938 /* beq */, Mips::BEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 938 /* beq */, Mips::BEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 938 /* beq */, Mips::BeqImm, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
  { 942 /* beqc */, Mips::BEQC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 942 /* beqc */, Mips::BEQC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 942 /* beqc */, Mips::BEQC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
  { 947 /* beql */, Mips::BEQL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 947 /* beql */, Mips::BEQLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
  { 952 /* beqz */, Mips::BeqzRxImmX16, Convert__Reg1_0__JumpTarget1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget }, },
  { 952 /* beqz */, Mips::BEQ, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 952 /* beqz */, Mips::BEQ_MM, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 952 /* beqz */, Mips::BeqzRxImm16, Convert__Reg1_0__JumpTarget1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
  { 957 /* beqz16 */, Mips::BEQZ16_MM, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
  { 957 /* beqz16 */, Mips::BEQZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
  { 964 /* beqzalc */, Mips::BEQZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 964 /* beqzalc */, Mips::BEQZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 972 /* beqzc */, Mips::BEQZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 972 /* beqzc */, Mips::BEQZC_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 972 /* beqzc */, Mips::BEQZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 972 /* beqzc */, Mips::BEQZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
  { 978 /* beqzc16 */, Mips::BEQZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
  { 986 /* beqzl */, Mips::BEQL, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 992 /* bge */, Mips::BGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 992 /* bge */, Mips::BGEImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
  { 996 /* bgec */, Mips::BGEC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 996 /* bgec */, Mips::BGEC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 996 /* bgec */, Mips::BGEC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
  { 1001 /* bgel */, Mips::BGEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1001 /* bgel */, Mips::BGELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
  { 1006 /* bgeu */, Mips::BGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1006 /* bgeu */, Mips::BGEUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
  { 1011 /* bgeuc */, Mips::BGEUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1011 /* bgeuc */, Mips::BGEUC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1011 /* bgeuc */, Mips::BGEUC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
  { 1017 /* bgeul */, Mips::BGEUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1017 /* bgeul */, Mips::BGEULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
  { 1023 /* bgez */, Mips::BGEZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1023 /* bgez */, Mips::BGEZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1028 /* bgezal */, Mips::BGEZAL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1028 /* bgezal */, Mips::BGEZAL_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1035 /* bgezalc */, Mips::BGEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1035 /* bgezalc */, Mips::BGEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1043 /* bgezall */, Mips::BGEZALL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1051 /* bgezals */, Mips::BGEZALS_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1059 /* bgezc */, Mips::BGEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1059 /* bgezc */, Mips::BGEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1059 /* bgezc */, Mips::BGEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
  { 1065 /* bgezl */, Mips::BGEZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1071 /* bgt */, Mips::BGT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1071 /* bgt */, Mips::BGTImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
  { 1075 /* bgtl */, Mips::BGTL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1075 /* bgtl */, Mips::BGTLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
  { 1080 /* bgtu */, Mips::BGTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1080 /* bgtu */, Mips::BGTUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
  { 1085 /* bgtul */, Mips::BGTUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1085 /* bgtul */, Mips::BGTULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
  { 1091 /* bgtz */, Mips::BGTZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1091 /* bgtz */, Mips::BGTZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1096 /* bgtzalc */, Mips::BGTZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1096 /* bgtzalc */, Mips::BGTZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1104 /* bgtzc */, Mips::BGTZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1104 /* bgtzc */, Mips::BGTZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1104 /* bgtzc */, Mips::BGTZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
  { 1110 /* bgtzl */, Mips::BGTZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1116 /* binsl.b */, Mips::BINSL_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 1124 /* binsl.d */, Mips::BINSL_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 1132 /* binsl.h */, Mips::BINSL_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 1140 /* binsl.w */, Mips::BINSL_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 1148 /* binsli.b */, Mips::BINSLI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
  { 1157 /* binsli.d */, Mips::BINSLI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
  { 1166 /* binsli.h */, Mips::BINSLI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
  { 1175 /* binsli.w */, Mips::BINSLI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 1184 /* binsr.b */, Mips::BINSR_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 1192 /* binsr.d */, Mips::BINSR_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 1200 /* binsr.h */, Mips::BINSR_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 1208 /* binsr.w */, Mips::BINSR_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 1216 /* binsri.b */, Mips::BINSRI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
  { 1225 /* binsri.d */, Mips::BINSRI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
  { 1234 /* binsri.h */, Mips::BINSRI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
  { 1243 /* binsri.w */, Mips::BINSRI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 1252 /* bitrev */, Mips::BITREV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 1252 /* bitrev */, Mips::BITREV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 1259 /* bitswap */, Mips::BITSWAP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 1259 /* bitswap */, Mips::BITSWAP_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 1267 /* ble */, Mips::BLE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1267 /* ble */, Mips::BLEImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
  { 1271 /* blel */, Mips::BLEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1271 /* blel */, Mips::BLELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
  { 1276 /* bleu */, Mips::BLEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1276 /* bleu */, Mips::BLEUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
  { 1281 /* bleul */, Mips::BLEUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1281 /* bleul */, Mips::BLEULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
  { 1287 /* blez */, Mips::BLEZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1287 /* blez */, Mips::BLEZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1292 /* blezalc */, Mips::BLEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1292 /* blezalc */, Mips::BLEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1300 /* blezc */, Mips::BLEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1300 /* blezc */, Mips::BLEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1300 /* blezc */, Mips::BLEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
  { 1306 /* blezl */, Mips::BLEZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1312 /* blt */, Mips::BLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1312 /* blt */, Mips::BLTImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
  { 1316 /* bltc */, Mips::BLTC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1316 /* bltc */, Mips::BLTC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1316 /* bltc */, Mips::BLTC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
  { 1321 /* bltl */, Mips::BLTL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1321 /* bltl */, Mips::BLTLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
  { 1326 /* bltu */, Mips::BLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1326 /* bltu */, Mips::BLTUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
  { 1331 /* bltuc */, Mips::BLTUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1331 /* bltuc */, Mips::BLTUC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1331 /* bltuc */, Mips::BLTUC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
  { 1337 /* bltul */, Mips::BLTUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1337 /* bltul */, Mips::BLTULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
  { 1343 /* bltz */, Mips::BLTZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1343 /* bltz */, Mips::BLTZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1348 /* bltzal */, Mips::BLTZAL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1348 /* bltzal */, Mips::BLTZAL_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1355 /* bltzalc */, Mips::BLTZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1355 /* bltzalc */, Mips::BLTZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1363 /* bltzall */, Mips::BLTZALL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1371 /* bltzals */, Mips::BLTZALS_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1379 /* bltzc */, Mips::BLTZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1379 /* bltzc */, Mips::BLTZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1379 /* bltzc */, Mips::BLTZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
  { 1385 /* bltzl */, Mips::BLTZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1391 /* bmnz.v */, Mips::BMNZ_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 1398 /* bmnzi.b */, Mips::BMNZI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
  { 1406 /* bmz.v */, Mips::BMZ_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 1412 /* bmzi.b */, Mips::BMZI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
  { 1419 /* bne */, Mips::BNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1419 /* bne */, Mips::BNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1419 /* bne */, Mips::BneImm, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
  { 1423 /* bnec */, Mips::BNEC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1423 /* bnec */, Mips::BNEC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1423 /* bnec */, Mips::BNEC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
  { 1428 /* bneg.b */, Mips::BNEG_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 1435 /* bneg.d */, Mips::BNEG_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 1442 /* bneg.h */, Mips::BNEG_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 1449 /* bneg.w */, Mips::BNEG_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 1456 /* bnegi.b */, Mips::BNEGI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
  { 1464 /* bnegi.d */, Mips::BNEGI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
  { 1472 /* bnegi.h */, Mips::BNEGI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
  { 1480 /* bnegi.w */, Mips::BNEGI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 1488 /* bnel */, Mips::BNEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1488 /* bnel */, Mips::BNELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
  { 1493 /* bnez */, Mips::BnezRxImmX16, Convert__Reg1_0__JumpTarget1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget }, },
  { 1493 /* bnez */, Mips::BNE, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1493 /* bnez */, Mips::BNE_MM, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1493 /* bnez */, Mips::BnezRxImm16, Convert__Reg1_0__JumpTarget1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
  { 1498 /* bnez16 */, Mips::BNEZ16_MM, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
  { 1498 /* bnez16 */, Mips::BNEZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
  { 1505 /* bnezalc */, Mips::BNEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1505 /* bnezalc */, Mips::BNEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1513 /* bnezc */, Mips::BNEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1513 /* bnezc */, Mips::BNEZC_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1513 /* bnezc */, Mips::BNEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1513 /* bnezc */, Mips::BNEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
  { 1519 /* bnezc16 */, Mips::BNEZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
  { 1527 /* bnezl */, Mips::BNEL, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1533 /* bnvc */, Mips::BNVC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1533 /* bnvc */, Mips::BNVC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1538 /* bnz.b */, Mips::BNZ_B, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
  { 1544 /* bnz.d */, Mips::BNZ_D, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
  { 1550 /* bnz.h */, Mips::BNZ_H, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
  { 1556 /* bnz.v */, Mips::BNZ_V, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
  { 1562 /* bnz.w */, Mips::BNZ_W, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
  { 1568 /* bovc */, Mips::BOVC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1568 /* bovc */, Mips::BOVC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 1573 /* bposge32 */, Mips::BPOSGE32_MM, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_NotMips32r6|Feature_HasDSP, { MCK_JumpTarget }, },
  { 1573 /* bposge32 */, Mips::BPOSGE32, Convert__JumpTarget1_0, Feature_HasDSP|Feature_NotInMicroMips, { MCK_JumpTarget }, },
  { 1582 /* bposge32c */, Mips::BPOSGE32C_MMR3, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_HasDSPR3, { MCK_JumpTarget }, },
  { 1592 /* break */, Mips::BREAK, Convert__imm_95_0__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, {  }, },
  { 1592 /* break */, Mips::BREAK_MM, Convert__imm_95_0__imm_95_0, Feature_InMicroMips, {  }, },
  { 1592 /* break */, Mips::Break16, Convert_NoOperands, Feature_InMips16Mode, { MCK_0 }, },
  { 1592 /* break */, Mips::BREAK, Convert__ConstantUImm10_01_0__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_ConstantUImm10_0 }, },
  { 1592 /* break */, Mips::BREAK_MM, Convert__ConstantUImm10_01_0__imm_95_0, Feature_InMicroMips, { MCK_ConstantUImm10_0 }, },
  { 1592 /* break */, Mips::BREAK, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, },
  { 1592 /* break */, Mips::BREAK_MMR6, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, },
  { 1592 /* break */, Mips::BREAK_MM, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, Feature_InMicroMips, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, },
  { 1598 /* break16 */, Mips::BREAK16_MM, Convert__ConstantUImm4_01_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_ConstantUImm4_0 }, },
  { 1598 /* break16 */, Mips::BREAK16_MMR6, Convert__ConstantUImm4_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm4_0 }, },
  { 1606 /* bsel.v */, Mips::BSEL_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 1613 /* bseli.b */, Mips::BSELI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
  { 1621 /* bset.b */, Mips::BSET_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 1628 /* bset.d */, Mips::BSET_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 1635 /* bset.h */, Mips::BSET_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 1642 /* bset.w */, Mips::BSET_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 1649 /* bseti.b */, Mips::BSETI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
  { 1657 /* bseti.d */, Mips::BSETI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
  { 1665 /* bseti.h */, Mips::BSETI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
  { 1673 /* bseti.w */, Mips::BSETI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 1681 /* bteqz */, Mips::BteqzX16, Convert__SImm161_0, Feature_InMips16Mode, { MCK_SImm16 }, },
  { 1681 /* bteqz */, Mips::Bteqz16, Convert__SImm161_0, Feature_InMips16Mode, { MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
  { 1687 /* btnez */, Mips::BtnezX16, Convert__SImm161_0, Feature_InMips16Mode, { MCK_SImm16 }, },
  { 1687 /* btnez */, Mips::Btnez16, Convert__SImm161_0, Feature_InMips16Mode, { MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
  { 1693 /* bz.b */, Mips::BZ_B, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
  { 1698 /* bz.d */, Mips::BZ_D, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
  { 1703 /* bz.h */, Mips::BZ_H, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
  { 1708 /* bz.v */, Mips::BZ_V, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
  { 1713 /* bz.w */, Mips::BZ_W, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
  { 1718 /* c.eq.d */, Mips::C_EQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1718 /* c.eq.d */, Mips::C_EQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1718 /* c.eq.d */, Mips::C_EQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1718 /* c.eq.d */, Mips::C_EQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1718 /* c.eq.d */, Mips::C_EQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1718 /* c.eq.d */, Mips::C_EQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1718 /* c.eq.d */, Mips::C_EQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1718 /* c.eq.d */, Mips::C_EQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1725 /* c.eq.s */, Mips::C_EQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1725 /* c.eq.s */, Mips::C_EQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1725 /* c.eq.s */, Mips::C_EQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1725 /* c.eq.s */, Mips::C_EQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1732 /* c.f.d */, Mips::C_F_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1732 /* c.f.d */, Mips::C_F_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1732 /* c.f.d */, Mips::C_F_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1732 /* c.f.d */, Mips::C_F_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1732 /* c.f.d */, Mips::C_F_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1732 /* c.f.d */, Mips::C_F_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1732 /* c.f.d */, Mips::C_F_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1732 /* c.f.d */, Mips::C_F_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1738 /* c.f.s */, Mips::C_F_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1738 /* c.f.s */, Mips::C_F_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1738 /* c.f.s */, Mips::C_F_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1738 /* c.f.s */, Mips::C_F_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1744 /* c.le.d */, Mips::C_LE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1744 /* c.le.d */, Mips::C_LE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1744 /* c.le.d */, Mips::C_LE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1744 /* c.le.d */, Mips::C_LE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1744 /* c.le.d */, Mips::C_LE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1744 /* c.le.d */, Mips::C_LE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1744 /* c.le.d */, Mips::C_LE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1744 /* c.le.d */, Mips::C_LE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1751 /* c.le.s */, Mips::C_LE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1751 /* c.le.s */, Mips::C_LE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1751 /* c.le.s */, Mips::C_LE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1751 /* c.le.s */, Mips::C_LE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1758 /* c.lt.d */, Mips::C_LT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1758 /* c.lt.d */, Mips::C_LT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1758 /* c.lt.d */, Mips::C_LT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1758 /* c.lt.d */, Mips::C_LT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1758 /* c.lt.d */, Mips::C_LT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1758 /* c.lt.d */, Mips::C_LT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1758 /* c.lt.d */, Mips::C_LT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1758 /* c.lt.d */, Mips::C_LT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1765 /* c.lt.s */, Mips::C_LT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1765 /* c.lt.s */, Mips::C_LT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1765 /* c.lt.s */, Mips::C_LT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1765 /* c.lt.s */, Mips::C_LT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1772 /* c.nge.d */, Mips::C_NGE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1772 /* c.nge.d */, Mips::C_NGE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1772 /* c.nge.d */, Mips::C_NGE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1772 /* c.nge.d */, Mips::C_NGE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1772 /* c.nge.d */, Mips::C_NGE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1772 /* c.nge.d */, Mips::C_NGE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1772 /* c.nge.d */, Mips::C_NGE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1772 /* c.nge.d */, Mips::C_NGE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1780 /* c.nge.s */, Mips::C_NGE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1780 /* c.nge.s */, Mips::C_NGE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1780 /* c.nge.s */, Mips::C_NGE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1780 /* c.nge.s */, Mips::C_NGE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1788 /* c.ngl.d */, Mips::C_NGL_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1788 /* c.ngl.d */, Mips::C_NGL_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1788 /* c.ngl.d */, Mips::C_NGL_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1788 /* c.ngl.d */, Mips::C_NGL_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1788 /* c.ngl.d */, Mips::C_NGL_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1788 /* c.ngl.d */, Mips::C_NGL_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1788 /* c.ngl.d */, Mips::C_NGL_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1788 /* c.ngl.d */, Mips::C_NGL_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1796 /* c.ngl.s */, Mips::C_NGL_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1796 /* c.ngl.s */, Mips::C_NGL_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1796 /* c.ngl.s */, Mips::C_NGL_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1796 /* c.ngl.s */, Mips::C_NGL_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1804 /* c.ngle.d */, Mips::C_NGLE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1804 /* c.ngle.d */, Mips::C_NGLE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1804 /* c.ngle.d */, Mips::C_NGLE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1804 /* c.ngle.d */, Mips::C_NGLE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1804 /* c.ngle.d */, Mips::C_NGLE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1804 /* c.ngle.d */, Mips::C_NGLE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1804 /* c.ngle.d */, Mips::C_NGLE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1804 /* c.ngle.d */, Mips::C_NGLE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1813 /* c.ngle.s */, Mips::C_NGLE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1813 /* c.ngle.s */, Mips::C_NGLE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1813 /* c.ngle.s */, Mips::C_NGLE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1813 /* c.ngle.s */, Mips::C_NGLE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1822 /* c.ngt.d */, Mips::C_NGT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1822 /* c.ngt.d */, Mips::C_NGT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1822 /* c.ngt.d */, Mips::C_NGT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1822 /* c.ngt.d */, Mips::C_NGT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1822 /* c.ngt.d */, Mips::C_NGT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1822 /* c.ngt.d */, Mips::C_NGT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1822 /* c.ngt.d */, Mips::C_NGT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1822 /* c.ngt.d */, Mips::C_NGT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1830 /* c.ngt.s */, Mips::C_NGT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1830 /* c.ngt.s */, Mips::C_NGT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1830 /* c.ngt.s */, Mips::C_NGT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1830 /* c.ngt.s */, Mips::C_NGT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1838 /* c.ole.d */, Mips::C_OLE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1838 /* c.ole.d */, Mips::C_OLE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1838 /* c.ole.d */, Mips::C_OLE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1838 /* c.ole.d */, Mips::C_OLE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1838 /* c.ole.d */, Mips::C_OLE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1838 /* c.ole.d */, Mips::C_OLE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1838 /* c.ole.d */, Mips::C_OLE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1838 /* c.ole.d */, Mips::C_OLE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1846 /* c.ole.s */, Mips::C_OLE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1846 /* c.ole.s */, Mips::C_OLE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1846 /* c.ole.s */, Mips::C_OLE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1846 /* c.ole.s */, Mips::C_OLE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1854 /* c.olt.d */, Mips::C_OLT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1854 /* c.olt.d */, Mips::C_OLT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1854 /* c.olt.d */, Mips::C_OLT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1854 /* c.olt.d */, Mips::C_OLT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1854 /* c.olt.d */, Mips::C_OLT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1854 /* c.olt.d */, Mips::C_OLT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1854 /* c.olt.d */, Mips::C_OLT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1854 /* c.olt.d */, Mips::C_OLT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1862 /* c.olt.s */, Mips::C_OLT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1862 /* c.olt.s */, Mips::C_OLT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1862 /* c.olt.s */, Mips::C_OLT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1862 /* c.olt.s */, Mips::C_OLT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1870 /* c.seq.d */, Mips::C_SEQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1870 /* c.seq.d */, Mips::C_SEQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1870 /* c.seq.d */, Mips::C_SEQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1870 /* c.seq.d */, Mips::C_SEQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1870 /* c.seq.d */, Mips::C_SEQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1870 /* c.seq.d */, Mips::C_SEQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1870 /* c.seq.d */, Mips::C_SEQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1870 /* c.seq.d */, Mips::C_SEQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1878 /* c.seq.s */, Mips::C_SEQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1878 /* c.seq.s */, Mips::C_SEQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1878 /* c.seq.s */, Mips::C_SEQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1878 /* c.seq.s */, Mips::C_SEQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1886 /* c.sf.d */, Mips::C_SF_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1886 /* c.sf.d */, Mips::C_SF_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1886 /* c.sf.d */, Mips::C_SF_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1886 /* c.sf.d */, Mips::C_SF_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1886 /* c.sf.d */, Mips::C_SF_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1886 /* c.sf.d */, Mips::C_SF_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1886 /* c.sf.d */, Mips::C_SF_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1886 /* c.sf.d */, Mips::C_SF_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1893 /* c.sf.s */, Mips::C_SF_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1893 /* c.sf.s */, Mips::C_SF_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1893 /* c.sf.s */, Mips::C_SF_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1893 /* c.sf.s */, Mips::C_SF_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1900 /* c.ueq.d */, Mips::C_UEQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1900 /* c.ueq.d */, Mips::C_UEQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1900 /* c.ueq.d */, Mips::C_UEQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1900 /* c.ueq.d */, Mips::C_UEQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1900 /* c.ueq.d */, Mips::C_UEQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1900 /* c.ueq.d */, Mips::C_UEQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1900 /* c.ueq.d */, Mips::C_UEQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1900 /* c.ueq.d */, Mips::C_UEQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1908 /* c.ueq.s */, Mips::C_UEQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1908 /* c.ueq.s */, Mips::C_UEQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1908 /* c.ueq.s */, Mips::C_UEQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1908 /* c.ueq.s */, Mips::C_UEQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1916 /* c.ule.d */, Mips::C_ULE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1916 /* c.ule.d */, Mips::C_ULE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1916 /* c.ule.d */, Mips::C_ULE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1916 /* c.ule.d */, Mips::C_ULE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1916 /* c.ule.d */, Mips::C_ULE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1916 /* c.ule.d */, Mips::C_ULE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1916 /* c.ule.d */, Mips::C_ULE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1916 /* c.ule.d */, Mips::C_ULE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1924 /* c.ule.s */, Mips::C_ULE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1924 /* c.ule.s */, Mips::C_ULE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1924 /* c.ule.s */, Mips::C_ULE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1924 /* c.ule.s */, Mips::C_ULE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1932 /* c.ult.d */, Mips::C_ULT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1932 /* c.ult.d */, Mips::C_ULT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1932 /* c.ult.d */, Mips::C_ULT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1932 /* c.ult.d */, Mips::C_ULT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1932 /* c.ult.d */, Mips::C_ULT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1932 /* c.ult.d */, Mips::C_ULT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1932 /* c.ult.d */, Mips::C_ULT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1932 /* c.ult.d */, Mips::C_ULT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1940 /* c.ult.s */, Mips::C_ULT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1940 /* c.ult.s */, Mips::C_ULT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1940 /* c.ult.s */, Mips::C_ULT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1940 /* c.ult.s */, Mips::C_ULT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1948 /* c.un.d */, Mips::C_UN_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1948 /* c.un.d */, Mips::C_UN_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1948 /* c.un.d */, Mips::C_UN_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1948 /* c.un.d */, Mips::C_UN_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1948 /* c.un.d */, Mips::C_UN_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1948 /* c.un.d */, Mips::C_UN_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 1948 /* c.un.d */, Mips::C_UN_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1948 /* c.un.d */, Mips::C_UN_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1955 /* c.un.s */, Mips::C_UN_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1955 /* c.un.s */, Mips::C_UN_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1955 /* c.un.s */, Mips::C_UN_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1955 /* c.un.s */, Mips::C_UN_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 1962 /* cache */, Mips::CACHE_R6, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
  { 1962 /* cache */, Mips::CACHE, Convert__Mem2_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_Mem }, },
  { 1962 /* cache */, Mips::CACHE_MM, Convert__Mem2_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
  { 1962 /* cache */, Mips::CACHE_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
  { 1968 /* cachee */, Mips::CACHEE, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
  { 1968 /* cachee */, Mips::CACHEE_MM, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_HasEVA, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
  { 1975 /* ceil.l.d */, Mips::CEIL_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1975 /* ceil.l.d */, Mips::CEIL_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 1984 /* ceil.l.s */, Mips::CEIL_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
  { 1984 /* ceil.l.s */, Mips::CEIL_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
  { 1993 /* ceil.w.d */, Mips::CEIL_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
  { 1993 /* ceil.w.d */, Mips::CEIL_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
  { 1993 /* ceil.w.d */, Mips::CEIL_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
  { 1993 /* ceil.w.d */, Mips::CEIL_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
  { 2002 /* ceil.w.s */, Mips::CEIL_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2002 /* ceil.w.s */, Mips::CEIL_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2002 /* ceil.w.s */, Mips::CEIL_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2011 /* ceq.b */, Mips::CEQ_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 2017 /* ceq.d */, Mips::CEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 2023 /* ceq.h */, Mips::CEQ_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 2029 /* ceq.w */, Mips::CEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 2035 /* ceqi.b */, Mips::CEQI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
  { 2042 /* ceqi.d */, Mips::CEQI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
  { 2049 /* ceqi.h */, Mips::CEQI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
  { 2056 /* ceqi.w */, Mips::CEQI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
  { 2063 /* cfc1 */, Mips::CFC1, Convert__GPR32AsmReg1_0__CCRAsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
  { 2063 /* cfc1 */, Mips::CFC1_MM, Convert__GPR32AsmReg1_0__CCRAsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
  { 2068 /* cfc2 */, Mips::CFC2_MM, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
  { 2073 /* cfcmsa */, Mips::CFCMSA, Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSACtrlAsmReg }, },
  { 2080 /* cftc1 */, Mips::CFTC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
  { 2086 /* cins */, Mips::CINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
  { 2086 /* cins */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
  { 2086 /* cins */, Mips::CINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
  { 2086 /* cins */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
  { 2091 /* cins32 */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
  { 2091 /* cins32 */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
  { 2098 /* class.d */, Mips::CLASS_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2098 /* class.d */, Mips::CLASS_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2106 /* class.s */, Mips::CLASS_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2106 /* class.s */, Mips::CLASS_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2114 /* cle_s.b */, Mips::CLE_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 2122 /* cle_s.d */, Mips::CLE_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 2130 /* cle_s.h */, Mips::CLE_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 2138 /* cle_s.w */, Mips::CLE_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 2146 /* cle_u.b */, Mips::CLE_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 2154 /* cle_u.d */, Mips::CLE_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 2162 /* cle_u.h */, Mips::CLE_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 2170 /* cle_u.w */, Mips::CLE_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 2178 /* clei_s.b */, Mips::CLEI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
  { 2187 /* clei_s.d */, Mips::CLEI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
  { 2196 /* clei_s.h */, Mips::CLEI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
  { 2205 /* clei_s.w */, Mips::CLEI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
  { 2214 /* clei_u.b */, Mips::CLEI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 2223 /* clei_u.d */, Mips::CLEI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 2232 /* clei_u.h */, Mips::CLEI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 2241 /* clei_u.w */, Mips::CLEI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 2250 /* clo */, Mips::CLO, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2250 /* clo */, Mips::CLO_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2250 /* clo */, Mips::CLO_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2250 /* clo */, Mips::CLO_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2254 /* clt_s.b */, Mips::CLT_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 2262 /* clt_s.d */, Mips::CLT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 2270 /* clt_s.h */, Mips::CLT_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 2278 /* clt_s.w */, Mips::CLT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 2286 /* clt_u.b */, Mips::CLT_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 2294 /* clt_u.d */, Mips::CLT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 2302 /* clt_u.h */, Mips::CLT_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 2310 /* clt_u.w */, Mips::CLT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 2318 /* clti_s.b */, Mips::CLTI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
  { 2327 /* clti_s.d */, Mips::CLTI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
  { 2336 /* clti_s.h */, Mips::CLTI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
  { 2345 /* clti_s.w */, Mips::CLTI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
  { 2354 /* clti_u.b */, Mips::CLTI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 2363 /* clti_u.d */, Mips::CLTI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 2372 /* clti_u.h */, Mips::CLTI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 2381 /* clti_u.w */, Mips::CLTI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 2390 /* clz */, Mips::CLZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2390 /* clz */, Mips::CLZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2390 /* clz */, Mips::CLZ_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2390 /* clz */, Mips::CLZ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2394 /* cmp */, Mips::CmpRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
  { 2398 /* cmp.af.d */, Mips::CMP_F_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2398 /* cmp.af.d */, Mips::CMP_AF_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2407 /* cmp.af.s */, Mips::CMP_F_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2407 /* cmp.af.s */, Mips::CMP_AF_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2416 /* cmp.eq.d */, Mips::CMP_EQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2416 /* cmp.eq.d */, Mips::CMP_EQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2425 /* cmp.eq.ph */, Mips::CMP_EQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2425 /* cmp.eq.ph */, Mips::CMP_EQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2435 /* cmp.eq.s */, Mips::CMP_EQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2435 /* cmp.eq.s */, Mips::CMP_EQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2444 /* cmp.le.d */, Mips::CMP_LE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2444 /* cmp.le.d */, Mips::CMP_LE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2453 /* cmp.le.ph */, Mips::CMP_LE_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2453 /* cmp.le.ph */, Mips::CMP_LE_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2463 /* cmp.le.s */, Mips::CMP_LE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2463 /* cmp.le.s */, Mips::CMP_LE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2472 /* cmp.lt.d */, Mips::CMP_LT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2472 /* cmp.lt.d */, Mips::CMP_LT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2481 /* cmp.lt.ph */, Mips::CMP_LT_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2481 /* cmp.lt.ph */, Mips::CMP_LT_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2491 /* cmp.lt.s */, Mips::CMP_LT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2491 /* cmp.lt.s */, Mips::CMP_LT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2500 /* cmp.saf.d */, Mips::CMP_SAF_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2500 /* cmp.saf.d */, Mips::CMP_SAF_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2510 /* cmp.saf.s */, Mips::CMP_SAF_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2510 /* cmp.saf.s */, Mips::CMP_SAF_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2520 /* cmp.seq.d */, Mips::CMP_SEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2520 /* cmp.seq.d */, Mips::CMP_SEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2530 /* cmp.seq.s */, Mips::CMP_SEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2530 /* cmp.seq.s */, Mips::CMP_SEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2540 /* cmp.sle.d */, Mips::CMP_SLE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2540 /* cmp.sle.d */, Mips::CMP_SLE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2550 /* cmp.sle.s */, Mips::CMP_SLE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2550 /* cmp.sle.s */, Mips::CMP_SLE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2560 /* cmp.slt.d */, Mips::CMP_SLT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2560 /* cmp.slt.d */, Mips::CMP_SLT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2570 /* cmp.slt.s */, Mips::CMP_SLT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2570 /* cmp.slt.s */, Mips::CMP_SLT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2580 /* cmp.sueq.d */, Mips::CMP_SUEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2580 /* cmp.sueq.d */, Mips::CMP_SUEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2591 /* cmp.sueq.s */, Mips::CMP_SUEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2591 /* cmp.sueq.s */, Mips::CMP_SUEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2602 /* cmp.sule.d */, Mips::CMP_SULE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2602 /* cmp.sule.d */, Mips::CMP_SULE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2613 /* cmp.sule.s */, Mips::CMP_SULE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2613 /* cmp.sule.s */, Mips::CMP_SULE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2624 /* cmp.sult.d */, Mips::CMP_SULT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2624 /* cmp.sult.d */, Mips::CMP_SULT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2635 /* cmp.sult.s */, Mips::CMP_SULT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2635 /* cmp.sult.s */, Mips::CMP_SULT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2646 /* cmp.sun.d */, Mips::CMP_SUN_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2646 /* cmp.sun.d */, Mips::CMP_SUN_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2656 /* cmp.sun.s */, Mips::CMP_SUN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2656 /* cmp.sun.s */, Mips::CMP_SUN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2666 /* cmp.ueq.d */, Mips::CMP_UEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2666 /* cmp.ueq.d */, Mips::CMP_UEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2676 /* cmp.ueq.s */, Mips::CMP_UEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2676 /* cmp.ueq.s */, Mips::CMP_UEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2686 /* cmp.ule.d */, Mips::CMP_ULE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2686 /* cmp.ule.d */, Mips::CMP_ULE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2696 /* cmp.ule.s */, Mips::CMP_ULE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2696 /* cmp.ule.s */, Mips::CMP_ULE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2706 /* cmp.ult.d */, Mips::CMP_ULT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2706 /* cmp.ult.d */, Mips::CMP_ULT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2716 /* cmp.ult.s */, Mips::CMP_ULT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2716 /* cmp.ult.s */, Mips::CMP_ULT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2726 /* cmp.un.d */, Mips::CMP_UN_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2726 /* cmp.un.d */, Mips::CMP_UN_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 2735 /* cmp.un.s */, Mips::CMP_UN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2735 /* cmp.un.s */, Mips::CMP_UN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 2744 /* cmpgdu.eq.qb */, Mips::CMPGDU_EQ_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2744 /* cmpgdu.eq.qb */, Mips::CMPGDU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2757 /* cmpgdu.le.qb */, Mips::CMPGDU_LE_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2757 /* cmpgdu.le.qb */, Mips::CMPGDU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2770 /* cmpgdu.lt.qb */, Mips::CMPGDU_LT_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2770 /* cmpgdu.lt.qb */, Mips::CMPGDU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2783 /* cmpgu.eq.qb */, Mips::CMPGU_EQ_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2783 /* cmpgu.eq.qb */, Mips::CMPGU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2795 /* cmpgu.le.qb */, Mips::CMPGU_LE_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2795 /* cmpgu.le.qb */, Mips::CMPGU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2807 /* cmpgu.lt.qb */, Mips::CMPGU_LT_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2807 /* cmpgu.lt.qb */, Mips::CMPGU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2819 /* cmpi */, Mips::CmpiRxImmX16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
  { 2819 /* cmpi */, Mips::CmpiRxImm16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
  { 2824 /* cmpu.eq.qb */, Mips::CMPU_EQ_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2824 /* cmpu.eq.qb */, Mips::CMPU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2835 /* cmpu.le.qb */, Mips::CMPU_LE_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2835 /* cmpu.le.qb */, Mips::CMPU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2846 /* cmpu.lt.qb */, Mips::CMPU_LT_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2846 /* cmpu.lt.qb */, Mips::CMPU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2857 /* copy_s.b */, Mips::COPY_S_B, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
  { 2866 /* copy_s.d */, Mips::COPY_S_D, Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_GPR64AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, },
  { 2875 /* copy_s.h */, Mips::COPY_S_H, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
  { 2884 /* copy_s.w */, Mips::COPY_S_W, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
  { 2893 /* copy_u.b */, Mips::COPY_U_B, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
  { 2902 /* copy_u.h */, Mips::COPY_U_H, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
  { 2911 /* copy_u.w */, Mips::COPY_U_W, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
  { 2920 /* crc32b */, Mips::CRC32B, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2927 /* crc32cb */, Mips::CRC32CB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2935 /* crc32cd */, Mips::CRC32CD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2943 /* crc32ch */, Mips::CRC32CH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2951 /* crc32cw */, Mips::CRC32CW, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2959 /* crc32d */, Mips::CRC32D, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2966 /* crc32h */, Mips::CRC32H, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2973 /* crc32w */, Mips::CRC32W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 2980 /* ctc1 */, Mips::CTC1, Convert__CCRAsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
  { 2980 /* ctc1 */, Mips::CTC1_MM, Convert__CCRAsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
  { 2985 /* ctc2 */, Mips::CTC2_MM, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
  { 2990 /* ctcmsa */, Mips::CTCMSA, Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSACtrlAsmReg, MCK_GPR32AsmReg }, },
  { 2997 /* cttc1 */, Mips::CTTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
  { 3003 /* cvt.d.l */, Mips::CVT_D64_L, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 3003 /* cvt.d.l */, Mips::CVT_D_L_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 3011 /* cvt.d.s */, Mips::CVT_D32_S, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
  { 3011 /* cvt.d.s */, Mips::CVT_D32_S_MM, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
  { 3011 /* cvt.d.s */, Mips::CVT_D64_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
  { 3011 /* cvt.d.s */, Mips::CVT_D64_S_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
  { 3019 /* cvt.d.w */, Mips::CVT_D32_W, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
  { 3019 /* cvt.d.w */, Mips::CVT_D32_W_MM, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
  { 3019 /* cvt.d.w */, Mips::CVT_D64_W, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
  { 3019 /* cvt.d.w */, Mips::CVT_D64_W_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
  { 3027 /* cvt.l.d */, Mips::CVT_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 3027 /* cvt.l.d */, Mips::CVT_L_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 3027 /* cvt.l.d */, Mips::CVT_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 3035 /* cvt.l.s */, Mips::CVT_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
  { 3035 /* cvt.l.s */, Mips::CVT_L_S_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
  { 3035 /* cvt.l.s */, Mips::CVT_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
  { 3043 /* cvt.s.d */, Mips::CVT_S_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
  { 3043 /* cvt.s.d */, Mips::CVT_S_D32_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
  { 3043 /* cvt.s.d */, Mips::CVT_S_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
  { 3043 /* cvt.s.d */, Mips::CVT_S_D64_MM, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
  { 3051 /* cvt.s.l */, Mips::CVT_S_L, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
  { 3051 /* cvt.s.l */, Mips::CVT_S_L_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
  { 3059 /* cvt.s.w */, Mips::CVT_S_W, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 3059 /* cvt.s.w */, Mips::CVT_S_W_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 3059 /* cvt.s.w */, Mips::CVT_S_W_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 3067 /* cvt.w.d */, Mips::CVT_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
  { 3067 /* cvt.w.d */, Mips::CVT_W_D32_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
  { 3067 /* cvt.w.d */, Mips::CVT_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
  { 3067 /* cvt.w.d */, Mips::CVT_W_D64_MM, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
  { 3075 /* cvt.w.s */, Mips::CVT_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 3075 /* cvt.w.s */, Mips::CVT_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 3075 /* cvt.w.s */, Mips::CVT_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 3083 /* dadd */, Mips::DADD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3083 /* dadd */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, },
  { 3083 /* dadd */, Mips::DADD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3083 /* dadd */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
  { 3088 /* daddi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_SImm16 }, },
  { 3088 /* daddi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
  { 3094 /* daddiu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, },
  { 3094 /* daddiu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
  { 3101 /* daddu */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3101 /* daddu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, },
  { 3101 /* daddu */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3101 /* daddu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
  { 3107 /* dahi */, Mips::DAHI, Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16_AltRelaxed }, },
  { 3112 /* dalign */, Mips::DALIGN, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm3_0 }, },
  { 3119 /* dati */, Mips::DATI, Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16_AltRelaxed }, },
  { 3124 /* daui */, Mips::DAUI, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16 }, },
  { 3129 /* dbitswap */, Mips::DBITSWAP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3138 /* dclo */, Mips::DCLO, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3138 /* dclo */, Mips::DCLO_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3143 /* dclz */, Mips::DCLZ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3143 /* dclz */, Mips::DCLZ_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3148 /* ddiv */, Mips::DSDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3148 /* ddiv */, Mips::DSDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
  { 3148 /* ddiv */, Mips::DSDIV, Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3148 /* ddiv */, Mips::DSDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3148 /* ddiv */, Mips::DDIV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3148 /* ddiv */, Mips::DSDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
  { 3153 /* ddivu */, Mips::DUDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3153 /* ddivu */, Mips::DUDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
  { 3153 /* ddivu */, Mips::DUDIV, Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3153 /* ddivu */, Mips::DUDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3153 /* ddivu */, Mips::DDIVU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3153 /* ddivu */, Mips::DUDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
  { 3159 /* deret */, Mips::DERET, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32|Feature_NotInMicroMips, {  }, },
  { 3159 /* deret */, Mips::DERET_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, {  }, },
  { 3159 /* deret */, Mips::DERET_MM, Convert_NoOperands, Feature_InMicroMips, {  }, },
  { 3165 /* dext */, Mips::DEXTM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_33 }, },
  { 3165 /* dext */, Mips::DEXTU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
  { 3165 /* dext */, Mips::DEXT, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_ConstantUImm5_Plus1_Report_UImm6 }, },
  { 3170 /* dextm */, Mips::DEXTM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_33 }, },
  { 3176 /* dextu */, Mips::DEXTU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
  { 3182 /* di */, Mips::DI, Convert__regZERO, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, {  }, },
  { 3182 /* di */, Mips::DI_MMR6, Convert__regZERO, Feature_InMicroMips|Feature_HasMips32r6, {  }, },
  { 3182 /* di */, Mips::DI_MM, Convert__regZERO, Feature_InMicroMips, {  }, },
  { 3182 /* di */, Mips::DI, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 3182 /* di */, Mips::DI_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
  { 3182 /* di */, Mips::DI_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
  { 3185 /* dins */, Mips::DINSM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImmRange2_64 }, },
  { 3185 /* dins */, Mips::DINSU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
  { 3185 /* dins */, Mips::DINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0, MCK_ConstantUImm5_1 }, },
  { 3190 /* dinsm */, Mips::DINSM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImmRange2_64 }, },
  { 3196 /* dinsu */, Mips::DINSU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
  { 3202 /* div */, Mips::DIV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3202 /* div */, Mips::SDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32 }, },
  { 3202 /* div */, Mips::SDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg }, },
  { 3202 /* div */, Mips::SDIV, Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32ZeroAsmReg, MCK_GPR32AsmReg }, },
  { 3202 /* div */, Mips::DivRxRy16, Convert__Reg1_1__Reg1_2, Feature_InMips16Mode, { MCK_GPR32ZERO, MCK_CPU16Regs, MCK_CPU16Regs }, },
  { 3202 /* div */, Mips::SDIV, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3202 /* div */, Mips::SDIV_MM, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3202 /* div */, Mips::DIV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3202 /* div */, Mips::DIV_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3202 /* div */, Mips::SDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },
  { 3202 /* div */, Mips::SDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3206 /* div.d */, Mips::FDIV_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 3206 /* div.d */, Mips::FDIV_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 3206 /* div.d */, Mips::FDIV_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 3206 /* div.d */, Mips::FDIV_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 3212 /* div.s */, Mips::FDIV_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 3212 /* div.s */, Mips::FDIV_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 3212 /* div.s */, Mips::FDIV_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 3218 /* div_s.b */, Mips::DIV_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 3226 /* div_s.d */, Mips::DIV_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 3234 /* div_s.h */, Mips::DIV_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 3242 /* div_s.w */, Mips::DIV_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 3250 /* div_u.b */, Mips::DIV_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 3258 /* div_u.d */, Mips::DIV_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 3266 /* div_u.h */, Mips::DIV_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 3274 /* div_u.w */, Mips::DIV_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 3282 /* divu */, Mips::DIVU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3282 /* divu */, Mips::UDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32 }, },
  { 3282 /* divu */, Mips::UDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg }, },
  { 3282 /* divu */, Mips::UDIV, Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32ZeroAsmReg, MCK_GPR32AsmReg }, },
  { 3282 /* divu */, Mips::DivuRxRy16, Convert__Reg1_1__Reg1_2, Feature_InMips16Mode, { MCK_GPR32ZERO, MCK_CPU16Regs, MCK_CPU16Regs }, },
  { 3282 /* divu */, Mips::UDIV, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3282 /* divu */, Mips::UDIV_MM, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3282 /* divu */, Mips::UDivMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3282 /* divu */, Mips::DIVU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3282 /* divu */, Mips::DIVU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3282 /* divu */, Mips::UDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },
  { 3287 /* dla */, Mips::LoadAddrImm64, Convert__GPR64AsmReg1_0__Imm1_1, 0, { MCK_GPR64AsmReg, MCK_Imm }, },
  { 3287 /* dla */, Mips::LoadAddrReg64, Convert__GPR64AsmReg1_0__Mem2_1, 0, { MCK_GPR64AsmReg, MCK_Mem }, },
  { 3291 /* dli */, Mips::LoadImm64, Convert__GPR64AsmReg1_0__Imm1_1, 0, { MCK_GPR64AsmReg, MCK_Imm }, },
  { 3295 /* dlsa */, Mips::DLSA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm2_1 }, },
  { 3295 /* dlsa */, Mips::DLSA_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm2_1 }, },
  { 3300 /* dmfc0 */, Mips::DMFC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
  { 3300 /* dmfc0 */, Mips::DMFC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasMips64, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
  { 3306 /* dmfc1 */, Mips::DMFC1, Convert__GPR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_FGR64AsmReg }, },
  { 3312 /* dmfc2 */, Mips::DMFC2, Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0, 0, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, },
  { 3312 /* dmfc2 */, Mips::DMFC2_OCTEON, Convert__GPR64AsmReg1_0__UImm161_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_UImm16 }, },
  { 3312 /* dmfc2 */, Mips::DMFC2, Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, Feature_HasMips64, { MCK_GPR64AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
  { 3318 /* dmfgc0 */, Mips::DMFGC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
  { 3318 /* dmfgc0 */, Mips::DMFGC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
  { 3325 /* dmod */, Mips::DMOD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3330 /* dmodu */, Mips::DMODU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3336 /* dmt */, Mips::DMT, Convert__regZERO, Feature_HasMT|Feature_NotInMicroMips, {  }, },
  { 3336 /* dmt */, Mips::DMT, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 3340 /* dmtc0 */, Mips::DMTC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
  { 3340 /* dmtc0 */, Mips::DMTC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, Feature_HasMips64, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
  { 3346 /* dmtc1 */, Mips::DMTC1, Convert__FGR64AsmReg1_1__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_FGR64AsmReg }, },
  { 3352 /* dmtc2 */, Mips::DMTC2, Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0, 0, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, },
  { 3352 /* dmtc2 */, Mips::DMTC2_OCTEON, Convert__GPR64AsmReg1_0__UImm161_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_UImm16 }, },
  { 3352 /* dmtc2 */, Mips::DMTC2, Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, Feature_HasMips64, { MCK_GPR64AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
  { 3358 /* dmtgc0 */, Mips::DMTGC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
  { 3358 /* dmtgc0 */, Mips::DMTGC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
  { 3365 /* dmuh */, Mips::DMUH, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3370 /* dmuhu */, Mips::DMUHU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3376 /* dmul */, Mips::DMUL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3376 /* dmul */, Mips::DMULMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasMips3|Feature_NotMips64r6|Feature_NotCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3376 /* dmul */, Mips::DMUL_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3376 /* dmul */, Mips::DMUL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3376 /* dmul */, Mips::DMULImmMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
  { 3381 /* dmulo */, Mips::DMULOMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3387 /* dmulou */, Mips::DMULOUMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3394 /* dmult */, Mips::DMULT, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3400 /* dmultu */, Mips::DMULTu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3407 /* dmulu */, Mips::DMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3413 /* dneg */, Mips::DSUB, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg }, },
  { 3413 /* dneg */, Mips::DSUB, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3418 /* dnegu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg }, },
  { 3418 /* dnegu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3424 /* dotp_s.d */, Mips::DOTP_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 3433 /* dotp_s.h */, Mips::DOTP_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 3442 /* dotp_s.w */, Mips::DOTP_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 3451 /* dotp_u.d */, Mips::DOTP_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 3460 /* dotp_u.h */, Mips::DOTP_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 3469 /* dotp_u.w */, Mips::DOTP_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 3478 /* dpa.w.ph */, Mips::DPA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3478 /* dpa.w.ph */, Mips::DPA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3487 /* dpadd_s.d */, Mips::DPADD_S_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 3497 /* dpadd_s.h */, Mips::DPADD_S_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 3507 /* dpadd_s.w */, Mips::DPADD_S_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 3517 /* dpadd_u.d */, Mips::DPADD_U_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 3527 /* dpadd_u.h */, Mips::DPADD_U_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 3537 /* dpadd_u.w */, Mips::DPADD_U_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 3547 /* dpaq_s.w.ph */, Mips::DPAQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3547 /* dpaq_s.w.ph */, Mips::DPAQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3559 /* dpaq_sa.l.w */, Mips::DPAQ_SA_L_W_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3559 /* dpaq_sa.l.w */, Mips::DPAQ_SA_L_W, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3571 /* dpaqx_s.w.ph */, Mips::DPAQX_S_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3571 /* dpaqx_s.w.ph */, Mips::DPAQX_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3584 /* dpaqx_sa.w.ph */, Mips::DPAQX_SA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3584 /* dpaqx_sa.w.ph */, Mips::DPAQX_SA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3598 /* dpau.h.qbl */, Mips::DPAU_H_QBL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3598 /* dpau.h.qbl */, Mips::DPAU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3609 /* dpau.h.qbr */, Mips::DPAU_H_QBR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3609 /* dpau.h.qbr */, Mips::DPAU_H_QBR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3620 /* dpax.w.ph */, Mips::DPAX_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3620 /* dpax.w.ph */, Mips::DPAX_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3630 /* dpop */, Mips::DPOP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
  { 3630 /* dpop */, Mips::DPOP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3635 /* dps.w.ph */, Mips::DPS_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3635 /* dps.w.ph */, Mips::DPS_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3644 /* dpsq_s.w.ph */, Mips::DPSQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3644 /* dpsq_s.w.ph */, Mips::DPSQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3656 /* dpsq_sa.l.w */, Mips::DPSQ_SA_L_W_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3656 /* dpsq_sa.l.w */, Mips::DPSQ_SA_L_W, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3668 /* dpsqx_s.w.ph */, Mips::DPSQX_S_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3668 /* dpsqx_s.w.ph */, Mips::DPSQX_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3681 /* dpsqx_sa.w.ph */, Mips::DPSQX_SA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3681 /* dpsqx_sa.w.ph */, Mips::DPSQX_SA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3695 /* dpsu.h.qbl */, Mips::DPSU_H_QBL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3695 /* dpsu.h.qbl */, Mips::DPSU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3706 /* dpsu.h.qbr */, Mips::DPSU_H_QBR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3706 /* dpsu.h.qbr */, Mips::DPSU_H_QBR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3717 /* dpsub_s.d */, Mips::DPSUB_S_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 3727 /* dpsub_s.h */, Mips::DPSUB_S_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 3737 /* dpsub_s.w */, Mips::DPSUB_S_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 3747 /* dpsub_u.d */, Mips::DPSUB_U_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 3757 /* dpsub_u.h */, Mips::DPSUB_U_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 3767 /* dpsub_u.w */, Mips::DPSUB_U_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 3777 /* dpsx.w.ph */, Mips::DPSX_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3777 /* dpsx.w.ph */, Mips::DPSX_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3787 /* drem */, Mips::DSRemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3787 /* drem */, Mips::DSRemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
  { 3787 /* drem */, Mips::DSRemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3787 /* drem */, Mips::DSRemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
  { 3792 /* dremu */, Mips::DURemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3792 /* dremu */, Mips::DURemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
  { 3792 /* dremu */, Mips::DURemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3792 /* dremu */, Mips::DURemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
  { 3798 /* drol */, Mips::DROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3798 /* drol */, Mips::DROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 3798 /* drol */, Mips::DROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3798 /* drol */, Mips::DROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 3803 /* dror */, Mips::DROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3803 /* dror */, Mips::DRORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 3803 /* dror */, Mips::DROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 3803 /* dror */, Mips::DRORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 3808 /* drotr */, Mips::DROTR, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
  { 3808 /* drotr */, Mips::DROTR, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
  { 3814 /* drotr32 */, Mips::DROTR32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
  { 3814 /* drotr32 */, Mips::DROTR32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
  { 3822 /* drotrv */, Mips::DROTRV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
  { 3829 /* dsbh */, Mips::DSBH, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3834 /* dshd */, Mips::DSHD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3839 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
  { 3839 /* dsll */, Mips::DSLL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
  { 3839 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
  { 3839 /* dsll */, Mips::DSLL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
  { 3844 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
  { 3844 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
  { 3851 /* dsllv */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
  { 3857 /* dsra */, Mips::DSRA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
  { 3857 /* dsra */, Mips::DSRAV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
  { 3857 /* dsra */, Mips::DSRA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
  { 3862 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
  { 3862 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
  { 3869 /* dsrav */, Mips::DSRAV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
  { 3875 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
  { 3875 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
  { 3875 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
  { 3875 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
  { 3880 /* dsrl32 */, Mips::DSRL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
  { 3880 /* dsrl32 */, Mips::DSRL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
  { 3887 /* dsrlv */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
  { 3893 /* dsub */, Mips::DSUB, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3893 /* dsub */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_InvNum }, },
  { 3893 /* dsub */, Mips::DSUB, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3893 /* dsub */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, },
  { 3898 /* dsubi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_InvNum }, },
  { 3898 /* dsubi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, },
  { 3904 /* dsubu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3904 /* dsubu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_InvNum }, },
  { 3904 /* dsubu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 3904 /* dsubu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, },
  { 3910 /* dvp */, Mips::DVP, Convert__regZERO, Feature_HasStdEnc|Feature_HasMips32r6, {  }, },
  { 3910 /* dvp */, Mips::DVP_MMR6, Convert__regZERO, Feature_InMicroMips|Feature_HasMips32r6, {  }, },
  { 3910 /* dvp */, Mips::DVP, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
  { 3910 /* dvp */, Mips::DVP_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
  { 3914 /* dvpe */, Mips::DVPE, Convert__regZERO, Feature_HasMT|Feature_NotInMicroMips, {  }, },
  { 3914 /* dvpe */, Mips::DVPE, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 3919 /* ehb */, Mips::EHB, Convert_NoOperands, Feature_HasStdEnc|Feature_NotInMicroMips, {  }, },
  { 3919 /* ehb */, Mips::EHB_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, {  }, },
  { 3919 /* ehb */, Mips::EHB_MM, Convert_NoOperands, Feature_InMicroMips, {  }, },
  { 3923 /* ei */, Mips::EI, Convert__regZERO, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, {  }, },
  { 3923 /* ei */, Mips::EI_MMR6, Convert__regZERO, Feature_InMicroMips|Feature_HasMips32r6, {  }, },
  { 3923 /* ei */, Mips::EI_MM, Convert__regZERO, Feature_InMicroMips, {  }, },
  { 3923 /* ei */, Mips::EI, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 3923 /* ei */, Mips::EI_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
  { 3923 /* ei */, Mips::EI_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
  { 3926 /* emt */, Mips::EMT, Convert__regZERO, Feature_HasMT|Feature_NotInMicroMips, {  }, },
  { 3926 /* emt */, Mips::EMT, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 3930 /* eret */, Mips::ERET, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotInMicroMips, {  }, },
  { 3930 /* eret */, Mips::ERET_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, {  }, },
  { 3930 /* eret */, Mips::ERET_MM, Convert_NoOperands, Feature_InMicroMips, {  }, },
  { 3935 /* eretnc */, Mips::ERETNC, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_NotInMicroMips, {  }, },
  { 3935 /* eretnc */, Mips::ERETNC_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, {  }, },
  { 3942 /* evp */, Mips::EVP, Convert__regZERO, Feature_HasStdEnc|Feature_HasMips32r6, {  }, },
  { 3942 /* evp */, Mips::EVP_MMR6, Convert__regZERO, Feature_InMicroMips|Feature_HasMips32r6, {  }, },
  { 3942 /* evp */, Mips::EVP, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
  { 3942 /* evp */, Mips::EVP_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
  { 3946 /* evpe */, Mips::EVPE, Convert__regZERO, Feature_HasMT|Feature_NotInMicroMips, {  }, },
  { 3946 /* evpe */, Mips::EVPE, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 3951 /* ext */, Mips::EXT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
  { 3951 /* ext */, Mips::EXT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
  { 3951 /* ext */, Mips::EXT_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
  { 3955 /* extp */, Mips::EXTP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
  { 3955 /* extp */, Mips::EXTP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
  { 3960 /* extpdp */, Mips::EXTPDP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
  { 3960 /* extpdp */, Mips::EXTPDP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
  { 3967 /* extpdpv */, Mips::EXTPDPV_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
  { 3967 /* extpdpv */, Mips::EXTPDPV, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
  { 3975 /* extpv */, Mips::EXTPV_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
  { 3975 /* extpv */, Mips::EXTPV, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
  { 3981 /* extr.w */, Mips::EXTR_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
  { 3981 /* extr.w */, Mips::EXTR_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
  { 3988 /* extr_r.w */, Mips::EXTR_R_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
  { 3988 /* extr_r.w */, Mips::EXTR_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
  { 3997 /* extr_rs.w */, Mips::EXTR_RS_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
  { 3997 /* extr_rs.w */, Mips::EXTR_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
  { 4007 /* extr_s.h */, Mips::EXTR_S_H_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
  { 4007 /* extr_s.h */, Mips::EXTR_S_H, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
  { 4016 /* extrv.w */, Mips::EXTRV_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
  { 4016 /* extrv.w */, Mips::EXTRV_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
  { 4024 /* extrv_r.w */, Mips::EXTRV_R_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
  { 4024 /* extrv_r.w */, Mips::EXTRV_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
  { 4034 /* extrv_rs.w */, Mips::EXTRV_RS_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
  { 4034 /* extrv_rs.w */, Mips::EXTRV_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
  { 4045 /* extrv_s.h */, Mips::EXTRV_S_H_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
  { 4045 /* extrv_s.h */, Mips::EXTRV_S_H, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
  { 4055 /* exts */, Mips::EXTS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
  { 4055 /* exts */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
  { 4055 /* exts */, Mips::EXTS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
  { 4055 /* exts */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
  { 4060 /* exts32 */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
  { 4060 /* exts32 */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
  { 4067 /* fadd.d */, Mips::FADD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4074 /* fadd.w */, Mips::FADD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4081 /* fcaf.d */, Mips::FCAF_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4088 /* fcaf.w */, Mips::FCAF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4095 /* fceq.d */, Mips::FCEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4102 /* fceq.w */, Mips::FCEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4109 /* fclass.d */, Mips::FCLASS_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4118 /* fclass.w */, Mips::FCLASS_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4127 /* fcle.d */, Mips::FCLE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4134 /* fcle.w */, Mips::FCLE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4141 /* fclt.d */, Mips::FCLT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4148 /* fclt.w */, Mips::FCLT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4155 /* fcne.d */, Mips::FCNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4162 /* fcne.w */, Mips::FCNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4169 /* fcor.d */, Mips::FCOR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4176 /* fcor.w */, Mips::FCOR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4183 /* fcueq.d */, Mips::FCUEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4191 /* fcueq.w */, Mips::FCUEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4199 /* fcule.d */, Mips::FCULE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4207 /* fcule.w */, Mips::FCULE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4215 /* fcult.d */, Mips::FCULT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4223 /* fcult.w */, Mips::FCULT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4231 /* fcun.d */, Mips::FCUN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4238 /* fcun.w */, Mips::FCUN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4245 /* fcune.d */, Mips::FCUNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4253 /* fcune.w */, Mips::FCUNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4261 /* fdiv.d */, Mips::FDIV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4268 /* fdiv.w */, Mips::FDIV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4275 /* fexdo.h */, Mips::FEXDO_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4283 /* fexdo.w */, Mips::FEXDO_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4291 /* fexp2.d */, Mips::FEXP2_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4299 /* fexp2.w */, Mips::FEXP2_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4307 /* fexupl.d */, Mips::FEXUPL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4316 /* fexupl.w */, Mips::FEXUPL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4325 /* fexupr.d */, Mips::FEXUPR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4334 /* fexupr.w */, Mips::FEXUPR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4343 /* ffint_s.d */, Mips::FFINT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4353 /* ffint_s.w */, Mips::FFINT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4363 /* ffint_u.d */, Mips::FFINT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4373 /* ffint_u.w */, Mips::FFINT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4383 /* ffql.d */, Mips::FFQL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4390 /* ffql.w */, Mips::FFQL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4397 /* ffqr.d */, Mips::FFQR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4404 /* ffqr.w */, Mips::FFQR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4411 /* fill.b */, Mips::FILL_B, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, },
  { 4418 /* fill.d */, Mips::FILL_D, Convert__MSA128AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_MSA128AsmReg, MCK_GPR64AsmReg }, },
  { 4425 /* fill.h */, Mips::FILL_H, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, },
  { 4432 /* fill.w */, Mips::FILL_W, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, },
  { 4439 /* flog2.d */, Mips::FLOG2_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4447 /* flog2.w */, Mips::FLOG2_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4455 /* floor.l.d */, Mips::FLOOR_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 4455 /* floor.l.d */, Mips::FLOOR_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 4465 /* floor.l.s */, Mips::FLOOR_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
  { 4465 /* floor.l.s */, Mips::FLOOR_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
  { 4475 /* floor.w.d */, Mips::FLOOR_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
  { 4475 /* floor.w.d */, Mips::FLOOR_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
  { 4475 /* floor.w.d */, Mips::FLOOR_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
  { 4475 /* floor.w.d */, Mips::FLOOR_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
  { 4485 /* floor.w.s */, Mips::FLOOR_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 4485 /* floor.w.s */, Mips::FLOOR_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 4485 /* floor.w.s */, Mips::FLOOR_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 4495 /* fmadd.d */, Mips::FMADD_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4503 /* fmadd.w */, Mips::FMADD_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4511 /* fmax.d */, Mips::FMAX_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4518 /* fmax.w */, Mips::FMAX_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4525 /* fmax_a.d */, Mips::FMAX_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4534 /* fmax_a.w */, Mips::FMAX_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4543 /* fmin.d */, Mips::FMIN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4550 /* fmin.w */, Mips::FMIN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4557 /* fmin_a.d */, Mips::FMIN_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4566 /* fmin_a.w */, Mips::FMIN_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4575 /* fmsub.d */, Mips::FMSUB_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4583 /* fmsub.w */, Mips::FMSUB_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4591 /* fmul.d */, Mips::FMUL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4598 /* fmul.w */, Mips::FMUL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4605 /* fork */, Mips::FORK, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 4610 /* frcp.d */, Mips::FRCP_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4617 /* frcp.w */, Mips::FRCP_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4624 /* frint.d */, Mips::FRINT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4632 /* frint.w */, Mips::FRINT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4640 /* frsqrt.d */, Mips::FRSQRT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4649 /* frsqrt.w */, Mips::FRSQRT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4658 /* fsaf.d */, Mips::FSAF_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4665 /* fsaf.w */, Mips::FSAF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4672 /* fseq.d */, Mips::FSEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4679 /* fseq.w */, Mips::FSEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4686 /* fsle.d */, Mips::FSLE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4693 /* fsle.w */, Mips::FSLE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4700 /* fslt.d */, Mips::FSLT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4707 /* fslt.w */, Mips::FSLT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4714 /* fsne.d */, Mips::FSNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4721 /* fsne.w */, Mips::FSNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4728 /* fsor.d */, Mips::FSOR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4735 /* fsor.w */, Mips::FSOR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4742 /* fsqrt.d */, Mips::FSQRT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4750 /* fsqrt.w */, Mips::FSQRT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4758 /* fsub.d */, Mips::FSUB_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4765 /* fsub.w */, Mips::FSUB_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4772 /* fsueq.d */, Mips::FSUEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4780 /* fsueq.w */, Mips::FSUEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4788 /* fsule.d */, Mips::FSULE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4796 /* fsule.w */, Mips::FSULE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4804 /* fsult.d */, Mips::FSULT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4812 /* fsult.w */, Mips::FSULT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4820 /* fsun.d */, Mips::FSUN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4827 /* fsun.w */, Mips::FSUN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4834 /* fsune.d */, Mips::FSUNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4842 /* fsune.w */, Mips::FSUNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4850 /* ftint_s.d */, Mips::FTINT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4860 /* ftint_s.w */, Mips::FTINT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4870 /* ftint_u.d */, Mips::FTINT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4880 /* ftint_u.w */, Mips::FTINT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4890 /* ftq.h */, Mips::FTQ_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4896 /* ftq.w */, Mips::FTQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4902 /* ftrunc_s.d */, Mips::FTRUNC_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4913 /* ftrunc_s.w */, Mips::FTRUNC_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4924 /* ftrunc_u.d */, Mips::FTRUNC_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4935 /* ftrunc_u.w */, Mips::FTRUNC_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4946 /* ginvi */, Mips::GINVI, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasGINV|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 4946 /* ginvi */, Mips::GINVI_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6|Feature_HasGINV, { MCK_GPR32AsmReg }, },
  { 4952 /* ginvt */, Mips::GINVT, Convert__GPR32AsmReg1_0__ConstantUImm2_01_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasGINV|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
  { 4952 /* ginvt */, Mips::GINVT_MMR6, Convert__GPR32AsmReg1_0__ConstantUImm2_01_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_HasGINV, { MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
  { 4958 /* hadd_s.d */, Mips::HADD_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4967 /* hadd_s.h */, Mips::HADD_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4976 /* hadd_s.w */, Mips::HADD_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4985 /* hadd_u.d */, Mips::HADD_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 4994 /* hadd_u.h */, Mips::HADD_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5003 /* hadd_u.w */, Mips::HADD_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5012 /* hsub_s.d */, Mips::HSUB_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5021 /* hsub_s.h */, Mips::HSUB_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5030 /* hsub_s.w */, Mips::HSUB_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5039 /* hsub_u.d */, Mips::HSUB_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5048 /* hsub_u.h */, Mips::HSUB_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5057 /* hsub_u.w */, Mips::HSUB_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5066 /* hypcall */, Mips::HYPCALL, Convert__imm_95_0, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, {  }, },
  { 5066 /* hypcall */, Mips::HYPCALL_MM, Convert__imm_95_0, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, {  }, },
  { 5066 /* hypcall */, Mips::HYPCALL, Convert__ConstantUImm10_01_0, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_ConstantUImm10_0 }, },
  { 5066 /* hypcall */, Mips::HYPCALL_MM, Convert__ConstantUImm10_01_0, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_ConstantUImm10_0 }, },
  { 5074 /* ilvev.b */, Mips::ILVEV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5082 /* ilvev.d */, Mips::ILVEV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5090 /* ilvev.h */, Mips::ILVEV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5098 /* ilvev.w */, Mips::ILVEV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5106 /* ilvl.b */, Mips::ILVL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5113 /* ilvl.d */, Mips::ILVL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5120 /* ilvl.h */, Mips::ILVL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5127 /* ilvl.w */, Mips::ILVL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5134 /* ilvod.b */, Mips::ILVOD_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5142 /* ilvod.d */, Mips::ILVOD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5150 /* ilvod.h */, Mips::ILVOD_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5158 /* ilvod.w */, Mips::ILVOD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5166 /* ilvr.b */, Mips::ILVR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5173 /* ilvr.d */, Mips::ILVR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5180 /* ilvr.h */, Mips::ILVR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5187 /* ilvr.w */, Mips::ILVR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5194 /* ins */, Mips::INS, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
  { 5194 /* ins */, Mips::INS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
  { 5194 /* ins */, Mips::INS_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
  { 5198 /* insert.b */, Mips::INSERT_B, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_, MCK_GPR32AsmReg }, },
  { 5207 /* insert.d */, Mips::INSERT_D, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_, MCK_GPR64AsmReg }, },
  { 5216 /* insert.h */, Mips::INSERT_H, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_, MCK_GPR32AsmReg }, },
  { 5225 /* insert.w */, Mips::INSERT_W, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_, MCK_GPR32AsmReg }, },
  { 5234 /* insv */, Mips::INSV_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 5234 /* insv */, Mips::INSV, Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 5239 /* insve.b */, Mips::INSVE_B, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
  { 5247 /* insve.d */, Mips::INSVE_D, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
  { 5255 /* insve.h */, Mips::INSVE_H, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
  { 5263 /* insve.w */, Mips::INSVE_W, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
  { 5271 /* j */, Mips::JR, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 5271 /* j */, Mips::JR_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
  { 5271 /* j */, Mips::J_MM, Convert__Imm1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_Imm }, },
  { 5271 /* j */, Mips::J, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_JumpTarget }, },
  { 5273 /* jal */, Mips::JalOneReg, Convert__GPR32AsmReg1_0, 0, { MCK_GPR32AsmReg }, },
  { 5273 /* jal */, Mips::JAL_MM, Convert__Imm1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_Imm }, },
  { 5273 /* jal */, Mips::JAL, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_JumpTarget }, },
  { 5273 /* jal */, Mips::BALC_MMR6, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_JumpTarget }, },
  { 5273 /* jal */, Mips::JalTwoReg, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 5277 /* jalr */, Mips::JALR16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
  { 5277 /* jalr */, Mips::JALRC16_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
  { 5277 /* jalr */, Mips::JALR, Convert__regRA__GPR32AsmReg1_0, Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 5277 /* jalr */, Mips::JALR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips|Feature_NoIndirectJumpGuards, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 5277 /* jalr */, Mips::JALR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 5277 /* jalr */, Mips::JALR64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_NotInMips16Mode, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 5282 /* jalr.hb */, Mips::JALR_HB, Convert__regRA__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 5282 /* jalr.hb */, Mips::JALR_HB64, Convert__regRA_64__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips64|Feature_NotInMicroMips, { MCK_GPR64AsmReg }, },
  { 5282 /* jalr.hb */, Mips::JALR_HB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 5282 /* jalr.hb */, Mips::JALR_HB64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 5290 /* jalrc */, Mips::JumpLinkReg16, Convert__Reg1_0, Feature_InMips16Mode, { MCK_CPU16Regs }, },
  { 5290 /* jalrc */, Mips::JIALC, Convert__GPR32AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 5290 /* jalrc */, Mips::JALRC_MMR6, Convert__regRA__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
  { 5290 /* jalrc */, Mips::JIALC64, Convert__GPR64AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg }, },
  { 5290 /* jalrc */, Mips::JALRC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 5296 /* jalrc.hb */, Mips::JALRC_HB_MMR6, Convert__regRA__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
  { 5296 /* jalrc.hb */, Mips::JALRC_HB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 5305 /* jalrs */, Mips::JALRS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 5311 /* jalrs16 */, Mips::JALRS16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
  { 5319 /* jals */, Mips::JALS_MM, Convert__Imm1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_Imm }, },
  { 5324 /* jalx */, Mips::JALX, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_JumpTarget }, },
  { 5324 /* jalx */, Mips::JALX_MM, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_JumpTarget }, },
  { 5329 /* jialc */, Mips::JIALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 5329 /* jialc */, Mips::JIALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 5329 /* jialc */, Mips::JIALC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
  { 5335 /* jic */, Mips::JIC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 5335 /* jic */, Mips::JIC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
  { 5335 /* jic */, Mips::JIC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
  { 5339 /* jr */, Mips::JrRa16, Convert_NoOperands, Feature_InMips16Mode, { MCK_CPURAReg }, },
  { 5339 /* jr */, Mips::JR, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 5339 /* jr */, Mips::JALR, Convert__regZERO__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 5339 /* jr */, Mips::JR_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
  { 5339 /* jr */, Mips::JR64, Convert__GPR64AsmReg1_0, Feature_NotInMips16Mode|Feature_IsPTR64bit|Feature_NotInMicroMips, { MCK_GPR64AsmReg }, },
  { 5339 /* jr */, Mips::JALR64, Convert__regZERO_64__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg }, },
  { 5342 /* jr.hb */, Mips::JR_HB, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg }, },
  { 5342 /* jr.hb */, Mips::JR_HB_R6, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
  { 5342 /* jr.hb */, Mips::JR_HB64, Convert__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg }, },
  { 5342 /* jr.hb */, Mips::JR_HB64_R6, Convert__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR64AsmReg }, },
  { 5348 /* jr16 */, Mips::JR16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
  { 5353 /* jraddiusp */, Mips::JRADDIUSP, Convert__UImm5Lsl21_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_UImm5Lsl2 }, },
  { 5363 /* jrc */, Mips::JrcRa16, Convert_NoOperands, Feature_InMips16Mode, { MCK_CPURAReg }, },
  { 5363 /* jrc */, Mips::JrcRx16, Convert__Reg1_0, Feature_InMips16Mode, { MCK_CPU16Regs }, },
  { 5363 /* jrc */, Mips::JIC, Convert__GPR32AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
  { 5363 /* jrc */, Mips::JRC16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
  { 5363 /* jrc */, Mips::JIC64, Convert__GPR64AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg }, },
  { 5367 /* jrc16 */, Mips::JRC16_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
  { 5373 /* jrcaddiusp */, Mips::JRCADDIUSP_MMR6, Convert__UImm5Lsl21_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_UImm5Lsl2 }, },
  { 5384 /* l.d */, Mips::LDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, },
  { 5384 /* l.d */, Mips::LDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, },
  { 5388 /* l.s */, Mips::LWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, },
  { 5392 /* la */, Mips::LoadAddrImm32, Convert__GPR32AsmReg1_0__Imm1_1, 0, { MCK_GPR32AsmReg, MCK_Imm }, },
  { 5392 /* la */, Mips::LoadAddrReg32, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 5395 /* lapc */, Mips::ADDIUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
  { 5395 /* lapc */, Mips::ADDIUPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
  { 5400 /* lb */, Mips::LB_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
  { 5400 /* lb */, Mips::LB_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
  { 5400 /* lb */, Mips::LB, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
  { 5403 /* lbe */, Mips::LBE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 5403 /* lbe */, Mips::LBE_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 5407 /* lbu */, Mips::LBU_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
  { 5407 /* lbu */, Mips::LBu_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
  { 5407 /* lbu */, Mips::LBu, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
  { 5411 /* lbu16 */, Mips::LBU16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, },
  { 5417 /* lbue */, Mips::LBuE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 5417 /* lbue */, Mips::LBuE_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 5422 /* lbux */, Mips::LBUX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
  { 5422 /* lbux */, Mips::LBUX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
  { 5427 /* ld */, Mips::LDMacro, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotMips3, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
  { 5427 /* ld */, Mips::LD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, },
  { 5430 /* ld.b */, Mips::LD_B, Convert__MSA128AsmReg1_0__MemOffsetSimm102_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10 }, },
  { 5435 /* ld.d */, Mips::LD_D, Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_3 }, },
  { 5440 /* ld.h */, Mips::LD_H, Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_1 }, },
  { 5445 /* ld.w */, Mips::LD_W, Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_2 }, },
  { 5450 /* ldc1 */, Mips::LDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, },
  { 5450 /* ldc1 */, Mips::LDC1_MM, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, },
  { 5450 /* ldc1 */, Mips::LDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, },
  { 5450 /* ldc1 */, Mips::LDC1_D64_MMR6, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, },
  { 5455 /* ldc2 */, Mips::LDC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
  { 5455 /* ldc2 */, Mips::LDC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
  { 5455 /* ldc2 */, Mips::LDC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, },
  { 5460 /* ldc3 */, Mips::LDC3, Convert__COP3AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotCnMips|Feature_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
  { 5465 /* ldi.b */, Mips::LDI_B, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
  { 5471 /* ldi.d */, Mips::LDI_D, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
  { 5477 /* ldi.h */, Mips::LDI_H, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
  { 5483 /* ldi.w */, Mips::LDI_W, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
  { 5489 /* ldl */, Mips::LDL, Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
  { 5493 /* ldpc */, Mips::LDPC, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
  { 5498 /* ldr */, Mips::LDR, Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
  { 5502 /* ldxc1 */, Mips::LDXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
  { 5502 /* ldxc1 */, Mips::LDXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
  { 5508 /* lh */, Mips::LH, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
  { 5508 /* lh */, Mips::LH_MM, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
  { 5511 /* lhe */, Mips::LHE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 5511 /* lhe */, Mips::LHE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 5515 /* lhu */, Mips::LHu, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
  { 5515 /* lhu */, Mips::LHu_MM, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
  { 5519 /* lhu16 */, Mips::LHU16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, },
  { 5525 /* lhue */, Mips::LHuE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 5525 /* lhue */, Mips::LHuE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 5530 /* lhx */, Mips::LHX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
  { 5530 /* lhx */, Mips::LHX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
  { 5534 /* li */, Mips::LiRxImmX16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
  { 5534 /* li */, Mips::LoadImm32, Convert__GPR32AsmReg1_0__UImm32_Coerced1_1, 0, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, },
  { 5534 /* li */, Mips::LiRxImm16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
  { 5537 /* li.d */, Mips::LoadImmDoubleGPR, Convert__GPR32AsmReg1_0__Imm1_1, 0, { MCK_GPR32AsmReg, MCK_Imm }, },
  { 5537 /* li.d */, Mips::LoadImmDoubleFGR_32, Convert__StrictlyAFGR64AsmReg1_0__Imm1_1, Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_StrictlyAFGR64AsmReg, MCK_Imm }, },
  { 5537 /* li.d */, Mips::LoadImmDoubleFGR, Convert__StrictlyFGR64AsmReg1_0__Imm1_1, Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_StrictlyFGR64AsmReg, MCK_Imm }, },
  { 5542 /* li.s */, Mips::LoadImmSingleGPR, Convert__GPR32AsmReg1_0__Imm1_1, 0, { MCK_GPR32AsmReg, MCK_Imm }, },
  { 5542 /* li.s */, Mips::LoadImmSingleFGR, Convert__StrictlyFGR32AsmReg1_0__Imm1_1, Feature_IsNotSoftFloat, { MCK_StrictlyFGR32AsmReg, MCK_Imm }, },
  { 5547 /* li16 */, Mips::LI16_MM, Convert__GPRMM16AsmReg1_0__UImm7_N11_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_UImm7_N1 }, },
  { 5547 /* li16 */, Mips::LI16_MMR6, Convert__GPRMM16AsmReg1_0__UImm7_N11_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_UImm7_N1 }, },
  { 5552 /* ll */, Mips::LL64_R6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 5552 /* ll */, Mips::LL_R6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 5552 /* ll */, Mips::LL_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 5552 /* ll */, Mips::LL, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 5552 /* ll */, Mips::LL64, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 5552 /* ll */, Mips::LL_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 5555 /* lld */, Mips::LLD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, },
  { 5555 /* lld */, Mips::LLD_R6, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, },
  { 5559 /* lle */, Mips::LLE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 5559 /* lle */, Mips::LLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 5563 /* lsa */, Mips::LSA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, },
  { 5563 /* lsa */, Mips::LSA_MMR6, Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, },
  { 5563 /* lsa */, Mips::LSA_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, },
  { 5567 /* lui */, Mips::LUI_MMR6, Convert__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 5567 /* lui */, Mips::LUi, Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16_Relaxed }, },
  { 5567 /* lui */, Mips::LUi_MM, Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16_Relaxed }, },
  { 5571 /* luxc1 */, Mips::LUXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
  { 5571 /* luxc1 */, Mips::LUXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
  { 5571 /* luxc1 */, Mips::LUXC1_MM, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
  { 5577 /* lw */, Mips::LwRxPcTcpX16, Convert__Reg1_0__Imm1_1__imm_95_0, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_Imm }, },
  { 5577 /* lw */, Mips::LWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, },
  { 5577 /* lw */, Mips::LW, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 5577 /* lw */, Mips::LWDSP, Convert__GPR32AsmReg1_0__Mem2_1, Feature_NotInMips16Mode|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 5577 /* lw */, Mips::LWDSP_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 5577 /* lw */, Mips::LW_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 5577 /* lw */, Mips::LW_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 5577 /* lw */, Mips::LWGP_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMemGP }, },
  { 5577 /* lw */, Mips::LwRxSpImmX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, },
  { 5577 /* lw */, Mips::LwRxPcTcp16, Convert__Reg1_0__Imm1_1__imm_95_0, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_Imm, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
  { 5580 /* lw16 */, Mips::LW16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, },
  { 5585 /* lwc1 */, Mips::LWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, },
  { 5585 /* lwc1 */, Mips::LWC1_MM, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, },
  { 5590 /* lwc2 */, Mips::LWC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
  { 5590 /* lwc2 */, Mips::LWC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
  { 5590 /* lwc2 */, Mips::LWC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, },
  { 5595 /* lwc3 */, Mips::LWC3, Convert__COP3AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotCnMips|Feature_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
  { 5600 /* lwe */, Mips::LWE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 5600 /* lwe */, Mips::LWE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 5604 /* lwl */, Mips::LWL, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 5604 /* lwl */, Mips::LWL_MM, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 5608 /* lwle */, Mips::LWLE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 5608 /* lwle */, Mips::LWLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 5613 /* lwm */, Mips::LWM_MM, Convert__RegList1_0__Mem2_1, Feature_InMicroMips, { MCK_RegList, MCK_Mem }, },
  { 5617 /* lwm16 */, Mips::LWM16_MM, Convert__RegList161_0__MemOffsetUimm42_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
  { 5617 /* lwm16 */, Mips::LWM16_MMR6, Convert__RegList161_0__MemOffsetUimm42_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
  { 5623 /* lwm32 */, Mips::LWM32_MM, Convert__RegList1_0__Mem2_1, Feature_InMicroMips, { MCK_RegList, MCK_Mem }, },
  { 5629 /* lwp */, Mips::LWP_MM, ConvertCustom_ConvertXWPOperands, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12 }, },
  { 5633 /* lwpc */, Mips::LWPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
  { 5633 /* lwpc */, Mips::LWPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
  { 5638 /* lwr */, Mips::LWR, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 5638 /* lwr */, Mips::LWR_MM, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 5642 /* lwre */, Mips::LWRE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 5642 /* lwre */, Mips::LWRE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 5647 /* lwu */, Mips::LWU_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm122_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12 }, },
  { 5647 /* lwu */, Mips::LWu, Convert__GPR64AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Mem }, },
  { 5651 /* lwupc */, Mips::LWUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
  { 5657 /* lwx */, Mips::LWX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
  { 5657 /* lwx */, Mips::LWX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
  { 5661 /* lwxc1 */, Mips::LWXC1, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
  { 5661 /* lwxc1 */, Mips::LWXC1_MM, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
  { 5667 /* lwxs */, Mips::LWXS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
  { 5672 /* madd */, Mips::MADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 5672 /* madd */, Mips::MADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 5672 /* madd */, Mips::MADD_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 5672 /* madd */, Mips::MADD_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 5677 /* madd.d */, Mips::MADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 5677 /* madd.d */, Mips::MADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 5677 /* madd.d */, Mips::MADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 5684 /* madd.s */, Mips::MADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 5684 /* madd.s */, Mips::MADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 5691 /* madd_q.h */, Mips::MADD_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5700 /* madd_q.w */, Mips::MADD_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5709 /* maddf.d */, Mips::MADDF_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 5709 /* maddf.d */, Mips::MADDF_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 5717 /* maddf.s */, Mips::MADDF_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 5717 /* maddf.s */, Mips::MADDF_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 5725 /* maddr_q.h */, Mips::MADDR_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5735 /* maddr_q.w */, Mips::MADDR_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5745 /* maddu */, Mips::MADDU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 5745 /* maddu */, Mips::MADDU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 5745 /* maddu */, Mips::MADDU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 5745 /* maddu */, Mips::MADDU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 5751 /* maddv.b */, Mips::MADDV_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5759 /* maddv.d */, Mips::MADDV_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5767 /* maddv.h */, Mips::MADDV_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5775 /* maddv.w */, Mips::MADDV_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5783 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 5783 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 5795 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 5795 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 5807 /* maq_sa.w.phl */, Mips::MAQ_SA_W_PHL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 5807 /* maq_sa.w.phl */, Mips::MAQ_SA_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 5820 /* maq_sa.w.phr */, Mips::MAQ_SA_W_PHR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 5820 /* maq_sa.w.phr */, Mips::MAQ_SA_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 5833 /* max.d */, Mips::MAX_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 5833 /* max.d */, Mips::MAX_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 5839 /* max.s */, Mips::MAX_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 5839 /* max.s */, Mips::MAX_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 5845 /* max_a.b */, Mips::MAX_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5853 /* max_a.d */, Mips::MAX_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5861 /* max_a.h */, Mips::MAX_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5869 /* max_a.w */, Mips::MAX_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5877 /* max_s.b */, Mips::MAX_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5885 /* max_s.d */, Mips::MAX_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5893 /* max_s.h */, Mips::MAX_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5901 /* max_s.w */, Mips::MAX_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5909 /* max_u.b */, Mips::MAX_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5917 /* max_u.d */, Mips::MAX_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5925 /* max_u.h */, Mips::MAX_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5933 /* max_u.w */, Mips::MAX_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 5941 /* maxa.d */, Mips::MAXA_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 5941 /* maxa.d */, Mips::MAXA_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 5948 /* maxa.s */, Mips::MAXA_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 5948 /* maxa.s */, Mips::MAXA_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 5955 /* maxi_s.b */, Mips::MAXI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
  { 5964 /* maxi_s.d */, Mips::MAXI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
  { 5973 /* maxi_s.h */, Mips::MAXI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
  { 5982 /* maxi_s.w */, Mips::MAXI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
  { 5991 /* maxi_u.b */, Mips::MAXI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 6000 /* maxi_u.d */, Mips::MAXI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 6009 /* maxi_u.h */, Mips::MAXI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 6018 /* maxi_u.w */, Mips::MAXI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 6027 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
  { 6027 /* mfc0 */, Mips::MFC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
  { 6027 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
  { 6027 /* mfc0 */, Mips::MFC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
  { 6032 /* mfc1 */, Mips::MFC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
  { 6032 /* mfc1 */, Mips::MFC1_MMR6, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
  { 6032 /* mfc1 */, Mips::MFC1_MM, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
  { 6032 /* mfc1 */, Mips::MFC1_D64, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
  { 6037 /* mfc2 */, Mips::MFC2_MMR6, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
  { 6037 /* mfc2 */, Mips::MFC2, Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
  { 6037 /* mfc2 */, Mips::MFC2, Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
  { 6042 /* mfgc0 */, Mips::MFGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
  { 6042 /* mfgc0 */, Mips::MFGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
  { 6042 /* mfgc0 */, Mips::MFGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
  { 6042 /* mfgc0 */, Mips::MFGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
  { 6048 /* mfhc0 */, Mips::MFHC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
  { 6048 /* mfhc0 */, Mips::MFHC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
  { 6054 /* mfhc1 */, Mips::MFHC1_D32, Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
  { 6054 /* mfhc1 */, Mips::MFHC1_D32_MM, Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
  { 6054 /* mfhc1 */, Mips::MFHC1_D64, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
  { 6054 /* mfhc1 */, Mips::MFHC1_D64_MM, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
  { 6060 /* mfhc2 */, Mips::MFHC2_MMR6, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
  { 6066 /* mfhgc0 */, Mips::MFHGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
  { 6066 /* mfhgc0 */, Mips::MFHGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
  { 6066 /* mfhgc0 */, Mips::MFHGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
  { 6066 /* mfhgc0 */, Mips::MFHGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
  { 6073 /* mfhi */, Mips::Mfhi16, Convert__Reg1_0, Feature_InMips16Mode, { MCK_CPU16Regs }, },
  { 6073 /* mfhi */, Mips::MFHI, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 6073 /* mfhi */, Mips::MFHI_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
  { 6073 /* mfhi */, Mips::MFHI_DSP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
  { 6073 /* mfhi */, Mips::MFHI_DSP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
  { 6078 /* mfhi16 */, Mips::MFHI16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
  { 6085 /* mflo */, Mips::Mflo16, Convert__Reg1_0, Feature_InMips16Mode, { MCK_CPU16Regs }, },
  { 6085 /* mflo */, Mips::MFLO, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 6085 /* mflo */, Mips::MFLO_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
  { 6085 /* mflo */, Mips::MFLO_DSP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
  { 6085 /* mflo */, Mips::MFLO_DSP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
  { 6090 /* mflo16 */, Mips::MFLO16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
  { 6097 /* mftacx */, Mips::MFTACX, Convert__GPR32AsmReg1_0__regAC0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 6097 /* mftacx */, Mips::MFTACX, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
  { 6104 /* mftc0 */, Mips::MFTC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
  { 6104 /* mftc0 */, Mips::MFTC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasMT, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
  { 6110 /* mftc1 */, Mips::MFTC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
  { 6116 /* mftdsp */, Mips::MFTDSP, Convert__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg }, },
  { 6123 /* mftgpr */, Mips::MFTGPR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6130 /* mfthc1 */, Mips::MFTHC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
  { 6137 /* mfthi */, Mips::MFTHI, Convert__GPR32AsmReg1_0__regAC0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 6137 /* mfthi */, Mips::MFTHI, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
  { 6143 /* mftlo */, Mips::MFTLO, Convert__GPR32AsmReg1_0__regAC0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 6143 /* mftlo */, Mips::MFTLO, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
  { 6149 /* mftr */, Mips::MFTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm1_0, MCK_ConstantUImm3_0, MCK_ConstantUImm1_0 }, },
  { 6154 /* min.d */, Mips::MIN_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 6154 /* min.d */, Mips::MIN_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 6160 /* min.s */, Mips::MIN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 6160 /* min.s */, Mips::MIN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 6166 /* min_a.b */, Mips::MIN_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6174 /* min_a.d */, Mips::MIN_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6182 /* min_a.h */, Mips::MIN_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6190 /* min_a.w */, Mips::MIN_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6198 /* min_s.b */, Mips::MIN_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6206 /* min_s.d */, Mips::MIN_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6214 /* min_s.h */, Mips::MIN_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6222 /* min_s.w */, Mips::MIN_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6230 /* min_u.b */, Mips::MIN_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6238 /* min_u.d */, Mips::MIN_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6246 /* min_u.h */, Mips::MIN_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6254 /* min_u.w */, Mips::MIN_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6262 /* mina.d */, Mips::MINA_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 6262 /* mina.d */, Mips::MINA_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 6269 /* mina.s */, Mips::MINA_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 6269 /* mina.s */, Mips::MINA_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 6276 /* mini_s.b */, Mips::MINI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
  { 6285 /* mini_s.d */, Mips::MINI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
  { 6294 /* mini_s.h */, Mips::MINI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
  { 6303 /* mini_s.w */, Mips::MINI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
  { 6312 /* mini_u.b */, Mips::MINI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 6321 /* mini_u.d */, Mips::MINI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 6330 /* mini_u.h */, Mips::MINI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 6339 /* mini_u.w */, Mips::MINI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 6348 /* mod */, Mips::MOD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6348 /* mod */, Mips::MOD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6352 /* mod_s.b */, Mips::MOD_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6360 /* mod_s.d */, Mips::MOD_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6368 /* mod_s.h */, Mips::MOD_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6376 /* mod_s.w */, Mips::MOD_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6384 /* mod_u.b */, Mips::MOD_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6392 /* mod_u.d */, Mips::MOD_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6400 /* mod_u.h */, Mips::MOD_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6408 /* mod_u.w */, Mips::MOD_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6416 /* modsub */, Mips::MODSUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6416 /* modsub */, Mips::MODSUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6423 /* modu */, Mips::MODU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6423 /* modu */, Mips::MODU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6428 /* mov.d */, Mips::FMOV_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 6428 /* mov.d */, Mips::FMOV_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 6428 /* mov.d */, Mips::FMOV_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 6428 /* mov.d */, Mips::FMOV_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 6434 /* mov.s */, Mips::FMOV_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 6434 /* mov.s */, Mips::FMOV_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 6434 /* mov.s */, Mips::FMOV_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 6440 /* move */, Mips::MoveR3216, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_DSPR }, },
  { 6440 /* move */, Mips::Move32R16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_DSPR, MCK_CPU16Regs }, },
  { 6440 /* move */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6440 /* move */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6440 /* move */, Mips::MOVE16_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6440 /* move */, Mips::OR64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, Feature_IsGP64bit|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 6440 /* move */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, Feature_IsGP64bit|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 6445 /* move.v */, Mips::MOVE_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6452 /* move16 */, Mips::MOVE16_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6459 /* movep */, Mips::MOVEP_MM, Convert__MovePRegPair2_0__GPRMM16AsmRegMoveP1_1__GPRMM16AsmRegMoveP1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_MovePRegPair, MCK_GPRMM16AsmRegMoveP, MCK_GPRMM16AsmRegMoveP }, },
  { 6459 /* movep */, Mips::MOVEP_MMR6, Convert__MovePRegPair2_0__GPRMM16AsmRegMoveP1_1__GPRMM16AsmRegMoveP1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_MovePRegPair, MCK_GPRMM16AsmRegMoveP, MCK_GPRMM16AsmRegMoveP }, },
  { 6465 /* movf */, Mips::MOVF_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
  { 6465 /* movf */, Mips::MOVF_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
  { 6470 /* movf.d */, Mips::MOVF_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
  { 6470 /* movf.d */, Mips::MOVF_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
  { 6470 /* movf.d */, Mips::MOVF_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FCCAsmReg }, },
  { 6477 /* movf.s */, Mips::MOVF_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
  { 6477 /* movf.s */, Mips::MOVF_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
  { 6484 /* movn */, Mips::MOVN_I_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6484 /* movn */, Mips::MOVN_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6489 /* movn.d */, Mips::MOVN_I_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
  { 6489 /* movn.d */, Mips::MOVN_I_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
  { 6489 /* movn.d */, Mips::MOVN_I_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, },
  { 6496 /* movn.s */, Mips::MOVN_I_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
  { 6496 /* movn.s */, Mips::MOVN_I_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
  { 6503 /* movt */, Mips::MOVT_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
  { 6503 /* movt */, Mips::MOVT_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
  { 6508 /* movt.d */, Mips::MOVT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
  { 6508 /* movt.d */, Mips::MOVT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
  { 6508 /* movt.d */, Mips::MOVT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FCCAsmReg }, },
  { 6515 /* movt.s */, Mips::MOVT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
  { 6515 /* movt.s */, Mips::MOVT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
  { 6522 /* movz */, Mips::MOVZ_I_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6522 /* movz */, Mips::MOVZ_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6527 /* movz.d */, Mips::MOVZ_I_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
  { 6527 /* movz.d */, Mips::MOVZ_I_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
  { 6527 /* movz.d */, Mips::MOVZ_I_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, },
  { 6534 /* movz.s */, Mips::MOVZ_I_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
  { 6534 /* movz.s */, Mips::MOVZ_I_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
  { 6541 /* msub */, Mips::MSUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6541 /* msub */, Mips::MSUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6541 /* msub */, Mips::MSUB_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6541 /* msub */, Mips::MSUB_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6546 /* msub.d */, Mips::MSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 6546 /* msub.d */, Mips::MSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 6546 /* msub.d */, Mips::MSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 6553 /* msub.s */, Mips::MSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 6553 /* msub.s */, Mips::MSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 6560 /* msub_q.h */, Mips::MSUB_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6569 /* msub_q.w */, Mips::MSUB_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6578 /* msubf.d */, Mips::MSUBF_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 6578 /* msubf.d */, Mips::MSUBF_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 6586 /* msubf.s */, Mips::MSUBF_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 6586 /* msubf.s */, Mips::MSUBF_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 6594 /* msubr_q.h */, Mips::MSUBR_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6604 /* msubr_q.w */, Mips::MSUBR_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6614 /* msubu */, Mips::MSUBU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6614 /* msubu */, Mips::MSUBU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6614 /* msubu */, Mips::MSUBU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6614 /* msubu */, Mips::MSUBU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6620 /* msubv.b */, Mips::MSUBV_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6628 /* msubv.d */, Mips::MSUBV_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6636 /* msubv.h */, Mips::MSUBV_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6644 /* msubv.w */, Mips::MSUBV_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6652 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
  { 6652 /* mtc0 */, Mips::MTC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
  { 6652 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
  { 6652 /* mtc0 */, Mips::MTC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
  { 6657 /* mtc1 */, Mips::MTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
  { 6657 /* mtc1 */, Mips::MTC1_MMR6, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
  { 6657 /* mtc1 */, Mips::MTC1_MM, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
  { 6657 /* mtc1 */, Mips::MTC1_D64, Convert__FGR64AsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
  { 6662 /* mtc2 */, Mips::MTC2_MMR6, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
  { 6662 /* mtc2 */, Mips::MTC2, Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
  { 6662 /* mtc2 */, Mips::MTC2, Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
  { 6667 /* mtgc0 */, Mips::MTGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
  { 6667 /* mtgc0 */, Mips::MTGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
  { 6667 /* mtgc0 */, Mips::MTGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
  { 6667 /* mtgc0 */, Mips::MTGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
  { 6673 /* mthc0 */, Mips::MTHC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
  { 6673 /* mthc0 */, Mips::MTHC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
  { 6679 /* mthc1 */, Mips::MTHC1_D32, Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
  { 6679 /* mthc1 */, Mips::MTHC1_D32_MM, Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
  { 6679 /* mthc1 */, Mips::MTHC1_D64, Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
  { 6679 /* mthc1 */, Mips::MTHC1_D64_MM, Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
  { 6685 /* mthc2 */, Mips::MTHC2_MMR6, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
  { 6691 /* mthgc0 */, Mips::MTHGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
  { 6691 /* mthgc0 */, Mips::MTHGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
  { 6691 /* mthgc0 */, Mips::MTHGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
  { 6691 /* mthgc0 */, Mips::MTHGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
  { 6698 /* mthi */, Mips::MTHI, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 6698 /* mthi */, Mips::MTHI_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
  { 6698 /* mthi */, Mips::MTHI_DSP_MM, Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_HI32DSPAsmReg }, },
  { 6698 /* mthi */, Mips::MTHI_DSP, Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_HI32DSPAsmReg }, },
  { 6703 /* mthlip */, Mips::MTHLIP_MM, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
  { 6703 /* mthlip */, Mips::MTHLIP, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
  { 6710 /* mtlo */, Mips::MTLO, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 6710 /* mtlo */, Mips::MTLO_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
  { 6710 /* mtlo */, Mips::MTLO_DSP_MM, Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_LO32DSPAsmReg }, },
  { 6710 /* mtlo */, Mips::MTLO_DSP, Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_LO32DSPAsmReg }, },
  { 6715 /* mtm0 */, Mips::MTM0, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
  { 6720 /* mtm1 */, Mips::MTM1, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
  { 6725 /* mtm2 */, Mips::MTM2, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
  { 6730 /* mtp0 */, Mips::MTP0, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
  { 6735 /* mtp1 */, Mips::MTP1, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
  { 6740 /* mtp2 */, Mips::MTP2, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
  { 6745 /* mttacx */, Mips::MTTACX, Convert__regAC0__GPR32AsmReg1_0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 6745 /* mttacx */, Mips::MTTACX, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
  { 6752 /* mttc0 */, Mips::MTTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
  { 6752 /* mttc0 */, Mips::MTTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_HasMT, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
  { 6758 /* mttc1 */, Mips::MTTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
  { 6764 /* mttdsp */, Mips::MTTDSP, Convert__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg }, },
  { 6771 /* mttgpr */, Mips::MTTGPR, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6778 /* mtthc1 */, Mips::MTTHC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
  { 6785 /* mtthi */, Mips::MTTHI, Convert__regAC0__GPR32AsmReg1_0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 6785 /* mtthi */, Mips::MTTHI, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
  { 6791 /* mttlo */, Mips::MTTLO, Convert__regAC0__GPR32AsmReg1_0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 6791 /* mttlo */, Mips::MTTLO, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
  { 6797 /* mttr */, Mips::MTTR, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm1_0, MCK_ConstantUImm3_0, MCK_ConstantUImm1_0 }, },
  { 6802 /* muh */, Mips::MUH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6802 /* muh */, Mips::MUH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6802 /* muh */, Mips::MUH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6806 /* muhu */, Mips::MUHU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6806 /* muhu */, Mips::MUHU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6806 /* muhu */, Mips::MUHU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6811 /* mul */, Mips::MUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6811 /* mul */, Mips::MUL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6811 /* mul */, Mips::MUL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6811 /* mul */, Mips::MUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6811 /* mul */, Mips::MUL_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6811 /* mul */, Mips::MUL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6811 /* mul */, Mips::MUL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6811 /* mul */, Mips::MULImmMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 6815 /* mul.d */, Mips::FMUL_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 6815 /* mul.d */, Mips::FMUL_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 6815 /* mul.d */, Mips::FMUL_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 6815 /* mul.d */, Mips::FMUL_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 6821 /* mul.ph */, Mips::MUL_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6821 /* mul.ph */, Mips::MUL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6828 /* mul.s */, Mips::FMUL_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 6828 /* mul.s */, Mips::FMUL_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 6828 /* mul.s */, Mips::FMUL_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 6834 /* mul_q.h */, Mips::MUL_Q_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6842 /* mul_q.w */, Mips::MUL_Q_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6850 /* mul_s.ph */, Mips::MUL_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6850 /* mul_s.ph */, Mips::MUL_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6859 /* muleq_s.w.phl */, Mips::MULEQ_S_W_PHL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6859 /* muleq_s.w.phl */, Mips::MULEQ_S_W_PHL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6873 /* muleq_s.w.phr */, Mips::MULEQ_S_W_PHR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6873 /* muleq_s.w.phr */, Mips::MULEQ_S_W_PHR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6887 /* muleu_s.ph.qbl */, Mips::MULEU_S_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6887 /* muleu_s.ph.qbl */, Mips::MULEU_S_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6902 /* muleu_s.ph.qbr */, Mips::MULEU_S_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6902 /* muleu_s.ph.qbr */, Mips::MULEU_S_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6917 /* mulo */, Mips::MULOMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6917 /* mulo */, Mips::MULOMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6922 /* mulou */, Mips::MULOUMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6922 /* mulou */, Mips::MULOUMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6928 /* mulq_rs.ph */, Mips::MULQ_RS_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6928 /* mulq_rs.ph */, Mips::MULQ_RS_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6939 /* mulq_rs.w */, Mips::MULQ_RS_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6939 /* mulq_rs.w */, Mips::MULQ_RS_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6949 /* mulq_s.ph */, Mips::MULQ_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6949 /* mulq_s.ph */, Mips::MULQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6959 /* mulq_s.w */, Mips::MULQ_S_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6959 /* mulq_s.w */, Mips::MULQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6968 /* mulr_q.h */, Mips::MULR_Q_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6977 /* mulr_q.w */, Mips::MULR_Q_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 6986 /* mulsa.w.ph */, Mips::MULSA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6986 /* mulsa.w.ph */, Mips::MULSA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6997 /* mulsaq_s.w.ph */, Mips::MULSAQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 6997 /* mulsaq_s.w.ph */, Mips::MULSAQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7011 /* mult */, Mips::MULT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7011 /* mult */, Mips::MULT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7011 /* mult */, Mips::MULT_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7011 /* mult */, Mips::MULT_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7016 /* multu */, Mips::MULTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7016 /* multu */, Mips::MULTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7016 /* multu */, Mips::MULTU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7016 /* multu */, Mips::MULTU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7022 /* mulu */, Mips::MULU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7022 /* mulu */, Mips::MULU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7022 /* mulu */, Mips::MULU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7027 /* mulv.b */, Mips::MULV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 7034 /* mulv.d */, Mips::MULV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 7041 /* mulv.h */, Mips::MULV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 7048 /* mulv.w */, Mips::MULV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 7055 /* neg */, Mips::SUB, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 7055 /* neg */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
  { 7055 /* neg */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
  { 7055 /* neg */, Mips::NegRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
  { 7055 /* neg */, Mips::SUB, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7055 /* neg */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7055 /* neg */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7059 /* neg.d */, Mips::FNEG_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 7059 /* neg.d */, Mips::FNEG_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 7059 /* neg.d */, Mips::FNEG_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 7059 /* neg.d */, Mips::FNEG_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 7065 /* neg.s */, Mips::FNEG_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 7065 /* neg.s */, Mips::FNEG_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 7065 /* neg.s */, Mips::FNEG_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 7071 /* negu */, Mips::SUBu, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 7071 /* negu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
  { 7071 /* negu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
  { 7071 /* negu */, Mips::SUBu, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7071 /* negu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7071 /* negu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7076 /* nloc.b */, Mips::NLOC_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 7083 /* nloc.d */, Mips::NLOC_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 7090 /* nloc.h */, Mips::NLOC_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 7097 /* nloc.w */, Mips::NLOC_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 7104 /* nlzc.b */, Mips::NLZC_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 7111 /* nlzc.d */, Mips::NLZC_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 7118 /* nlzc.h */, Mips::NLZC_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 7125 /* nlzc.w */, Mips::NLZC_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 7132 /* nmadd.d */, Mips::NMADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 7132 /* nmadd.d */, Mips::NMADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 7132 /* nmadd.d */, Mips::NMADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 7140 /* nmadd.s */, Mips::NMADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 7140 /* nmadd.s */, Mips::NMADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 7148 /* nmsub.d */, Mips::NMSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 7148 /* nmsub.d */, Mips::NMSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 7148 /* nmsub.d */, Mips::NMSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 7156 /* nmsub.s */, Mips::NMSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 7156 /* nmsub.s */, Mips::NMSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 7164 /* nop */, Mips::SLL, Convert__regZERO__regZERO__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, {  }, },
  { 7164 /* nop */, Mips::SLL_MMR6, Convert__regZERO__regZERO__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, {  }, },
  { 7164 /* nop */, Mips::Move32R16, Convert__regZERO__regS0, Feature_InMips16Mode, {  }, },
  { 7164 /* nop */, Mips::SLL_MM, Convert__regZERO__regZERO__imm_95_0, Feature_InMicroMips, {  }, },
  { 7164 /* nop */, Mips::MOVE16_MM, Convert__regZERO__regZERO, Feature_InMicroMips, {  }, },
  { 7168 /* nor */, Mips::NORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_IsGP32bit, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 7168 /* nor */, Mips::NORImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
  { 7168 /* nor */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7168 /* nor */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7168 /* nor */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7168 /* nor */, Mips::NORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_IsGP32bit, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 7168 /* nor */, Mips::NORImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
  { 7172 /* nor.v */, Mips::NOR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 7178 /* nori.b */, Mips::NORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
  { 7185 /* not */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 7185 /* not */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
  { 7185 /* not */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
  { 7185 /* not */, Mips::NotRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
  { 7185 /* not */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7185 /* not */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7185 /* not */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7189 /* not16 */, Mips::NOT16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
  { 7189 /* not16 */, Mips::NOT16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
  { 7195 /* or */, Mips::OrRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
  { 7195 /* or */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7195 /* or */, Mips::OR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7195 /* or */, Mips::OR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7195 /* or */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 7195 /* or */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 7195 /* or */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 7195 /* or */, Mips::ORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
  { 7195 /* or */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7195 /* or */, Mips::OR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7195 /* or */, Mips::OR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7195 /* or */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 7195 /* or */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 7195 /* or */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 7195 /* or */, Mips::ORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
  { 7198 /* or.v */, Mips::OR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 7203 /* or16 */, Mips::OR16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
  { 7203 /* or16 */, Mips::OR16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
  { 7208 /* ori */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 7208 /* ori */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 7208 /* ori */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 7208 /* ori */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 7208 /* ori */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 7208 /* ori */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 7212 /* ori.b */, Mips::ORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
  { 7218 /* packrl.ph */, Mips::PACKRL_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7218 /* packrl.ph */, Mips::PACKRL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7228 /* pause */, Mips::PAUSE, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, {  }, },
  { 7228 /* pause */, Mips::PAUSE_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, {  }, },
  { 7228 /* pause */, Mips::PAUSE_MM, Convert_NoOperands, Feature_InMicroMips, {  }, },
  { 7234 /* pckev.b */, Mips::PCKEV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 7242 /* pckev.d */, Mips::PCKEV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 7250 /* pckev.h */, Mips::PCKEV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 7258 /* pckev.w */, Mips::PCKEV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 7266 /* pckod.b */, Mips::PCKOD_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 7274 /* pckod.d */, Mips::PCKOD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 7282 /* pckod.h */, Mips::PCKOD_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 7290 /* pckod.w */, Mips::PCKOD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 7298 /* pcnt.b */, Mips::PCNT_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 7305 /* pcnt.d */, Mips::PCNT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 7312 /* pcnt.h */, Mips::PCNT_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 7319 /* pcnt.w */, Mips::PCNT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 7326 /* pick.ph */, Mips::PICK_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7326 /* pick.ph */, Mips::PICK_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7334 /* pick.qb */, Mips::PICK_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7334 /* pick.qb */, Mips::PICK_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7342 /* pop */, Mips::POP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_HasCnMips, { MCK_GPR32AsmReg }, },
  { 7342 /* pop */, Mips::POP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7346 /* preceq.w.phl */, Mips::PRECEQ_W_PHL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7346 /* preceq.w.phl */, Mips::PRECEQ_W_PHL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7359 /* preceq.w.phr */, Mips::PRECEQ_W_PHR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7359 /* preceq.w.phr */, Mips::PRECEQ_W_PHR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7372 /* precequ.ph.qbl */, Mips::PRECEQU_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7372 /* precequ.ph.qbl */, Mips::PRECEQU_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7387 /* precequ.ph.qbla */, Mips::PRECEQU_PH_QBLA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7387 /* precequ.ph.qbla */, Mips::PRECEQU_PH_QBLA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7403 /* precequ.ph.qbr */, Mips::PRECEQU_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7403 /* precequ.ph.qbr */, Mips::PRECEQU_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7418 /* precequ.ph.qbra */, Mips::PRECEQU_PH_QBRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7418 /* precequ.ph.qbra */, Mips::PRECEQU_PH_QBRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7434 /* preceu.ph.qbl */, Mips::PRECEU_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7434 /* preceu.ph.qbl */, Mips::PRECEU_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7448 /* preceu.ph.qbla */, Mips::PRECEU_PH_QBLA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7448 /* preceu.ph.qbla */, Mips::PRECEU_PH_QBLA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7463 /* preceu.ph.qbr */, Mips::PRECEU_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7463 /* preceu.ph.qbr */, Mips::PRECEU_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7477 /* preceu.ph.qbra */, Mips::PRECEU_PH_QBRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7477 /* preceu.ph.qbra */, Mips::PRECEU_PH_QBRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7492 /* precr.qb.ph */, Mips::PRECR_QB_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7492 /* precr.qb.ph */, Mips::PRECR_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7504 /* precr_sra.ph.w */, Mips::PRECR_SRA_PH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 7504 /* precr_sra.ph.w */, Mips::PRECR_SRA_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 7519 /* precr_sra_r.ph.w */, Mips::PRECR_SRA_R_PH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 7519 /* precr_sra_r.ph.w */, Mips::PRECR_SRA_R_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 7536 /* precrq.ph.w */, Mips::PRECRQ_PH_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7536 /* precrq.ph.w */, Mips::PRECRQ_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7548 /* precrq.qb.ph */, Mips::PRECRQ_QB_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7548 /* precrq.qb.ph */, Mips::PRECRQ_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7561 /* precrq_rs.ph.w */, Mips::PRECRQ_RS_PH_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7561 /* precrq_rs.ph.w */, Mips::PRECRQ_RS_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7576 /* precrqu_s.qb.ph */, Mips::PRECRQU_S_QB_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7576 /* precrqu_s.qb.ph */, Mips::PRECRQU_S_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7592 /* pref */, Mips::PREF_R6, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
  { 7592 /* pref */, Mips::PREF, Convert__Mem2_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_Mem }, },
  { 7592 /* pref */, Mips::PREF_MM, Convert__Mem2_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
  { 7592 /* pref */, Mips::PREF_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
  { 7597 /* prefe */, Mips::PREFE, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
  { 7597 /* prefe */, Mips::PREFE_MM, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_HasEVA, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
  { 7603 /* prefx */, Mips::PREFX_MM, Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_ConstantUImm5_0, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
  { 7609 /* prepend */, Mips::PREPEND_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 7609 /* prepend */, Mips::PREPEND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 7617 /* raddu.w.qb */, Mips::RADDU_W_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7617 /* raddu.w.qb */, Mips::RADDU_W_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7628 /* rddsp */, Mips::RDDSP_MM, Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm7_0 }, },
  { 7628 /* rddsp */, Mips::RDDSP, Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
  { 7634 /* rdhwr */, Mips::RDHWR, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, },
  { 7634 /* rdhwr */, Mips::RDHWR_MM, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, },
  { 7634 /* rdhwr */, Mips::RDHWR_MMR6, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, },
  { 7634 /* rdhwr */, Mips::RDHWR_MMR6, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm3_0 }, },
  { 7634 /* rdhwr */, Mips::RDHWR, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm8_0 }, },
  { 7634 /* rdhwr */, Mips::RDHWR_MM, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm8_0 }, },
  { 7640 /* rdpgpr */, Mips::RDPGPR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7647 /* recip.d */, Mips::RECIP_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 7647 /* recip.d */, Mips::RECIP_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 7647 /* recip.d */, Mips::RECIP_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 7647 /* recip.d */, Mips::RECIP_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 7655 /* recip.s */, Mips::RECIP_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 7655 /* recip.s */, Mips::RECIP_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 7663 /* rem */, Mips::SRemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7663 /* rem */, Mips::SRemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 7663 /* rem */, Mips::SRemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7663 /* rem */, Mips::SRemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 7667 /* remu */, Mips::URemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7667 /* remu */, Mips::URemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 7667 /* remu */, Mips::URemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7667 /* remu */, Mips::URemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 7672 /* repl.ph */, Mips::REPL_PH_MM, Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantSImm10_0 }, },
  { 7672 /* repl.ph */, Mips::REPL_PH, Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantSImm10_0 }, },
  { 7680 /* repl.qb */, Mips::REPL_QB_MM, Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm8_0 }, },
  { 7680 /* repl.qb */, Mips::REPL_QB, Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm8_0 }, },
  { 7688 /* replv.ph */, Mips::REPLV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7688 /* replv.ph */, Mips::REPLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7697 /* replv.qb */, Mips::REPLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7697 /* replv.qb */, Mips::REPLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7706 /* rint.d */, Mips::RINT_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 7706 /* rint.d */, Mips::RINT_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 7713 /* rint.s */, Mips::RINT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 7713 /* rint.s */, Mips::RINT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 7720 /* rol */, Mips::ROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7720 /* rol */, Mips::ROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, 0, { MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 7720 /* rol */, Mips::ROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7720 /* rol */, Mips::ROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 7724 /* ror */, Mips::ROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7724 /* ror */, Mips::RORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, 0, { MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 7724 /* ror */, Mips::ROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7724 /* ror */, Mips::RORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 7728 /* rotr */, Mips::ROTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 7728 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 7728 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 7728 /* rotr */, Mips::ROTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 7728 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 7733 /* rotrv */, Mips::ROTRV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7733 /* rotrv */, Mips::ROTRV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7739 /* round.l.d */, Mips::ROUND_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 7739 /* round.l.d */, Mips::ROUND_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 7749 /* round.l.s */, Mips::ROUND_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
  { 7749 /* round.l.s */, Mips::ROUND_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
  { 7759 /* round.w.d */, Mips::ROUND_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
  { 7759 /* round.w.d */, Mips::ROUND_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
  { 7759 /* round.w.d */, Mips::ROUND_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
  { 7759 /* round.w.d */, Mips::ROUND_W_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 7769 /* round.w.s */, Mips::ROUND_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 7769 /* round.w.s */, Mips::ROUND_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 7769 /* round.w.s */, Mips::ROUND_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 7779 /* rsqrt.d */, Mips::RSQRT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 7779 /* rsqrt.d */, Mips::RSQRT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 7779 /* rsqrt.d */, Mips::RSQRT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 7779 /* rsqrt.d */, Mips::RSQRT_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 7787 /* rsqrt.s */, Mips::RSQRT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 7787 /* rsqrt.s */, Mips::RSQRT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotInMips16Mode|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 7795 /* s.d */, Mips::SDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, },
  { 7795 /* s.d */, Mips::SDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, },
  { 7799 /* s.s */, Mips::SWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, },
  { 7803 /* sat_s.b */, Mips::SAT_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
  { 7811 /* sat_s.d */, Mips::SAT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
  { 7819 /* sat_s.h */, Mips::SAT_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
  { 7827 /* sat_s.w */, Mips::SAT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 7835 /* sat_u.b */, Mips::SAT_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
  { 7843 /* sat_u.d */, Mips::SAT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
  { 7851 /* sat_u.h */, Mips::SAT_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
  { 7859 /* sat_u.w */, Mips::SAT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 7867 /* sb */, Mips::SB, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 7867 /* sb */, Mips::SB_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 7867 /* sb */, Mips::SB_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 7867 /* sb */, Mips::SbRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, },
  { 7870 /* sb16 */, Mips::SB16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
  { 7870 /* sb16 */, Mips::SB16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
  { 7875 /* sbe */, Mips::SBE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 7875 /* sbe */, Mips::SBE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 7879 /* sc */, Mips::SC64_R6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 7879 /* sc */, Mips::SC_R6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 7879 /* sc */, Mips::SC_MMR6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 7879 /* sc */, Mips::SC, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 7879 /* sc */, Mips::SC64, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 7879 /* sc */, Mips::SC_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 7882 /* scd */, Mips::SCD_R6, Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR64AsmReg, MCK_MemOffsetSimm9 }, },
  { 7882 /* scd */, Mips::SCD, Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
  { 7886 /* sce */, Mips::SCE, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 7886 /* sce */, Mips::SCE_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 7890 /* sd */, Mips::SDMacro, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotMips3, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
  { 7890 /* sd */, Mips::SD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, },
  { 7893 /* sdbbp */, Mips::SDBBP, Convert__imm_95_0, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, {  }, },
  { 7893 /* sdbbp */, Mips::SDBBP_R6, Convert__imm_95_0, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, {  }, },
  { 7893 /* sdbbp */, Mips::SDBBP_MMR6, Convert__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, {  }, },
  { 7893 /* sdbbp */, Mips::SDBBP_MM, Convert__ConstantUImm10_01_0, Feature_InMicroMips, { MCK_ConstantUImm10_0 }, },
  { 7893 /* sdbbp */, Mips::SDBBP, Convert__ConstantUImm20_01_0, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_ConstantUImm20_0 }, },
  { 7893 /* sdbbp */, Mips::SDBBP_R6, Convert__ConstantUImm20_01_0, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_ConstantUImm20_0 }, },
  { 7893 /* sdbbp */, Mips::SDBBP_MMR6, Convert__ConstantUImm20_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm20_0 }, },
  { 7899 /* sdbbp16 */, Mips::SDBBP16_MM, Convert__ConstantUImm4_01_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_ConstantUImm4_0 }, },
  { 7899 /* sdbbp16 */, Mips::SDBBP16_MMR6, Convert__ConstantUImm4_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm4_0 }, },
  { 7907 /* sdc1 */, Mips::SDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, },
  { 7907 /* sdc1 */, Mips::SDC1_MM, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, },
  { 7907 /* sdc1 */, Mips::SDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, },
  { 7907 /* sdc1 */, Mips::SDC1_D64_MMR6, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, },
  { 7912 /* sdc2 */, Mips::SDC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
  { 7912 /* sdc2 */, Mips::SDC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
  { 7912 /* sdc2 */, Mips::SDC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, },
  { 7917 /* sdc3 */, Mips::SDC3, Convert__COP3AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotCnMips|Feature_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
  { 7922 /* sdl */, Mips::SDL, Convert__GPR64AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
  { 7926 /* sdr */, Mips::SDR, Convert__GPR64AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
  { 7930 /* sdxc1 */, Mips::SDXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
  { 7930 /* sdxc1 */, Mips::SDXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
  { 7936 /* seb */, Mips::SebRx16, Convert__Reg1_0__Tie0_1_1, Feature_InMips16Mode, { MCK_CPU16Regs }, },
  { 7936 /* seb */, Mips::SEB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 7936 /* seb */, Mips::SEB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
  { 7936 /* seb */, Mips::SEB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7936 /* seb */, Mips::SEB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7940 /* seh */, Mips::SehRx16, Convert__Reg1_0__Tie0_1_1, Feature_InMips16Mode, { MCK_CPU16Regs }, },
  { 7940 /* seh */, Mips::SEH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 7940 /* seh */, Mips::SEH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
  { 7940 /* seh */, Mips::SEH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7940 /* seh */, Mips::SEH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7944 /* sel.d */, Mips::SEL_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 7944 /* sel.d */, Mips::SEL_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 7950 /* sel.s */, Mips::SEL_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 7950 /* sel.s */, Mips::SEL_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 7956 /* seleqz */, Mips::SELEQZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7956 /* seleqz */, Mips::SELEQZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7956 /* seleqz */, Mips::SELEQZ64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips32r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 7963 /* seleqz.d */, Mips::SELEQZ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 7963 /* seleqz.d */, Mips::SELEQZ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 7972 /* seleqz.s */, Mips::SELEQZ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 7972 /* seleqz.s */, Mips::SELEQZ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 7981 /* selnez */, Mips::SELNEZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7981 /* selnez */, Mips::SELNEZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 7981 /* selnez */, Mips::SELNEZ64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips32r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 7988 /* selnez.d */, Mips::SELNEZ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 7988 /* selnez.d */, Mips::SELNEZ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 7997 /* selnez.s */, Mips::SELNEZ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 7997 /* selnez.s */, Mips::SELNEZ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 8006 /* seq */, Mips::SEQMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8006 /* seq */, Mips::SEQIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, Feature_NotCnMips, { MCK_GPR32AsmReg, MCK_SImm32 }, },
  { 8006 /* seq */, Mips::SEQ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 8006 /* seq */, Mips::SEQMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8006 /* seq */, Mips::SEQIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 8006 /* seq */, Mips::SEQ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 8010 /* seqi */, Mips::SEQi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
  { 8010 /* seqi */, Mips::SEQi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
  { 8015 /* sgt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8015 /* sgt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8015 /* sgt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8015 /* sgt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8019 /* sgtu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8019 /* sgtu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8019 /* sgtu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8019 /* sgtu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8024 /* sh */, Mips::SH, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 8024 /* sh */, Mips::SH_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 8024 /* sh */, Mips::SH_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 8024 /* sh */, Mips::ShRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, },
  { 8027 /* sh16 */, Mips::SH16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
  { 8027 /* sh16 */, Mips::SH16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
  { 8032 /* she */, Mips::SHE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 8032 /* she */, Mips::SHE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 8036 /* shf.b */, Mips::SHF_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
  { 8042 /* shf.h */, Mips::SHF_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
  { 8048 /* shf.w */, Mips::SHF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
  { 8054 /* shilo */, Mips::SHILO_MM, Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_ConstantSImm6_0 }, },
  { 8054 /* shilo */, Mips::SHILO, Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_ConstantSImm6_0 }, },
  { 8060 /* shilov */, Mips::SHILOV_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
  { 8060 /* shilov */, Mips::SHILOV, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
  { 8067 /* shll.ph */, Mips::SHLL_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
  { 8067 /* shll.ph */, Mips::SHLL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
  { 8075 /* shll.qb */, Mips::SHLL_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
  { 8075 /* shll.qb */, Mips::SHLL_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
  { 8083 /* shll_s.ph */, Mips::SHLL_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
  { 8083 /* shll_s.ph */, Mips::SHLL_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
  { 8093 /* shll_s.w */, Mips::SHLL_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 8093 /* shll_s.w */, Mips::SHLL_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 8102 /* shllv.ph */, Mips::SHLLV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8102 /* shllv.ph */, Mips::SHLLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8111 /* shllv.qb */, Mips::SHLLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8111 /* shllv.qb */, Mips::SHLLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8120 /* shllv_s.ph */, Mips::SHLLV_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8120 /* shllv_s.ph */, Mips::SHLLV_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8131 /* shllv_s.w */, Mips::SHLLV_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8131 /* shllv_s.w */, Mips::SHLLV_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8141 /* shra.ph */, Mips::SHRA_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
  { 8141 /* shra.ph */, Mips::SHRA_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
  { 8149 /* shra.qb */, Mips::SHRA_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
  { 8149 /* shra.qb */, Mips::SHRA_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
  { 8157 /* shra_r.ph */, Mips::SHRA_R_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
  { 8157 /* shra_r.ph */, Mips::SHRA_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
  { 8167 /* shra_r.qb */, Mips::SHRA_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
  { 8167 /* shra_r.qb */, Mips::SHRA_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
  { 8177 /* shra_r.w */, Mips::SHRA_R_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 8177 /* shra_r.w */, Mips::SHRA_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 8186 /* shrav.ph */, Mips::SHRAV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8186 /* shrav.ph */, Mips::SHRAV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8195 /* shrav.qb */, Mips::SHRAV_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8195 /* shrav.qb */, Mips::SHRAV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8204 /* shrav_r.ph */, Mips::SHRAV_R_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8204 /* shrav_r.ph */, Mips::SHRAV_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8215 /* shrav_r.qb */, Mips::SHRAV_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8215 /* shrav_r.qb */, Mips::SHRAV_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8226 /* shrav_r.w */, Mips::SHRAV_R_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8226 /* shrav_r.w */, Mips::SHRAV_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8236 /* shrl.ph */, Mips::SHRL_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
  { 8236 /* shrl.ph */, Mips::SHRL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
  { 8244 /* shrl.qb */, Mips::SHRL_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
  { 8244 /* shrl.qb */, Mips::SHRL_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
  { 8252 /* shrlv.ph */, Mips::SHRLV_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8252 /* shrlv.ph */, Mips::SHRLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8261 /* shrlv.qb */, Mips::SHRLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8261 /* shrlv.qb */, Mips::SHRLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8270 /* sld.b */, Mips::SLD_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
  { 8276 /* sld.d */, Mips::SLD_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
  { 8282 /* sld.h */, Mips::SLD_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
  { 8288 /* sld.w */, Mips::SLD_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
  { 8294 /* sldi.b */, Mips::SLDI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
  { 8301 /* sldi.d */, Mips::SLDI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, },
  { 8308 /* sldi.h */, Mips::SLDI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
  { 8315 /* sldi.w */, Mips::SLDI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
  { 8322 /* sll */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8322 /* sll */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8322 /* sll */, Mips::SLL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 8322 /* sll */, Mips::SLL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 8322 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 8322 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 8322 /* sll */, Mips::SllX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, },
  { 8322 /* sll */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8322 /* sll */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8322 /* sll */, Mips::SLL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 8322 /* sll */, Mips::SLL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 8322 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 8326 /* sll.b */, Mips::SLL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8332 /* sll.d */, Mips::SLL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8338 /* sll.h */, Mips::SLL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8344 /* sll.w */, Mips::SLL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8350 /* sll16 */, Mips::SLL16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
  { 8350 /* sll16 */, Mips::SLL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
  { 8356 /* slli.b */, Mips::SLLI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
  { 8363 /* slli.d */, Mips::SLLI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
  { 8370 /* slli.h */, Mips::SLLI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
  { 8377 /* slli.w */, Mips::SLLI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 8384 /* sllv */, Mips::SllvRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
  { 8384 /* sllv */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8384 /* sllv */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8389 /* slt */, Mips::SltRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
  { 8389 /* slt */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 8389 /* slt */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 8389 /* slt */, Mips::SLTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
  { 8389 /* slt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8389 /* slt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8389 /* slt */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 8389 /* slt */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 8389 /* slt */, Mips::SLTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
  { 8393 /* slti */, Mips::SltiRxImmX16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
  { 8393 /* slti */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 8393 /* slti */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 8393 /* slti */, Mips::SltiRxImm16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
  { 8398 /* sltiu */, Mips::SltiuRxImmX16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
  { 8398 /* sltiu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 8398 /* sltiu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 8398 /* sltiu */, Mips::SltiuRxImm16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
  { 8404 /* sltu */, Mips::SltuRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
  { 8404 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 8404 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 8404 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
  { 8404 /* sltu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8404 /* sltu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8404 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 8404 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 8404 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
  { 8409 /* sne */, Mips::SNE, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 8409 /* sne */, Mips::SNE, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 8413 /* snei */, Mips::SNEi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
  { 8413 /* snei */, Mips::SNEi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
  { 8418 /* splat.b */, Mips::SPLAT_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
  { 8426 /* splat.d */, Mips::SPLAT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
  { 8434 /* splat.h */, Mips::SPLAT_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
  { 8442 /* splat.w */, Mips::SPLAT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
  { 8450 /* splati.b */, Mips::SPLATI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
  { 8459 /* splati.d */, Mips::SPLATI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, },
  { 8468 /* splati.h */, Mips::SPLATI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
  { 8477 /* splati.w */, Mips::SPLATI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
  { 8486 /* sqrt.d */, Mips::FSQRT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 8486 /* sqrt.d */, Mips::FSQRT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 8486 /* sqrt.d */, Mips::FSQRT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 8486 /* sqrt.d */, Mips::FSQRT_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 8493 /* sqrt.s */, Mips::FSQRT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 8493 /* sqrt.s */, Mips::FSQRT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 8500 /* sra */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8500 /* sra */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8500 /* sra */, Mips::SRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 8500 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 8500 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 8500 /* sra */, Mips::SraX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, },
  { 8500 /* sra */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8500 /* sra */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8500 /* sra */, Mips::SRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 8500 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 8504 /* sra.b */, Mips::SRA_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8510 /* sra.d */, Mips::SRA_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8516 /* sra.h */, Mips::SRA_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8522 /* sra.w */, Mips::SRA_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8528 /* srai.b */, Mips::SRAI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
  { 8535 /* srai.d */, Mips::SRAI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
  { 8542 /* srai.h */, Mips::SRAI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
  { 8549 /* srai.w */, Mips::SRAI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 8556 /* srar.b */, Mips::SRAR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8563 /* srar.d */, Mips::SRAR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8570 /* srar.h */, Mips::SRAR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8577 /* srar.w */, Mips::SRAR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8584 /* srari.b */, Mips::SRARI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
  { 8592 /* srari.d */, Mips::SRARI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
  { 8600 /* srari.h */, Mips::SRARI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
  { 8608 /* srari.w */, Mips::SRARI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 8616 /* srav */, Mips::SravRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
  { 8616 /* srav */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8616 /* srav */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8621 /* srl */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8621 /* srl */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8621 /* srl */, Mips::SRL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 8621 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 8621 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 8621 /* srl */, Mips::SrlX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, },
  { 8621 /* srl */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8621 /* srl */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8621 /* srl */, Mips::SRL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 8621 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
  { 8625 /* srl.b */, Mips::SRL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8631 /* srl.d */, Mips::SRL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8637 /* srl.h */, Mips::SRL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8643 /* srl.w */, Mips::SRL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8649 /* srl16 */, Mips::SRL16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
  { 8649 /* srl16 */, Mips::SRL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
  { 8655 /* srli.b */, Mips::SRLI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
  { 8662 /* srli.d */, Mips::SRLI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
  { 8669 /* srli.h */, Mips::SRLI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
  { 8676 /* srli.w */, Mips::SRLI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 8683 /* srlr.b */, Mips::SRLR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8690 /* srlr.d */, Mips::SRLR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8697 /* srlr.h */, Mips::SRLR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8704 /* srlr.w */, Mips::SRLR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8711 /* srlri.b */, Mips::SRLRI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
  { 8719 /* srlri.d */, Mips::SRLRI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
  { 8727 /* srlri.h */, Mips::SRLRI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
  { 8735 /* srlri.w */, Mips::SRLRI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 8743 /* srlv */, Mips::SrlvRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
  { 8743 /* srlv */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8743 /* srlv */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8748 /* ssnop */, Mips::SSNOP, Convert_NoOperands, Feature_HasStdEnc|Feature_NotInMicroMips, {  }, },
  { 8748 /* ssnop */, Mips::SSNOP_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, {  }, },
  { 8748 /* ssnop */, Mips::SSNOP_MM, Convert_NoOperands, Feature_InMicroMips, {  }, },
  { 8754 /* st.b */, Mips::ST_B, Convert__MSA128AsmReg1_0__MemOffsetSimm102_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10 }, },
  { 8759 /* st.d */, Mips::ST_D, Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_3 }, },
  { 8764 /* st.h */, Mips::ST_H, Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_1 }, },
  { 8769 /* st.w */, Mips::ST_W, Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_2 }, },
  { 8774 /* sub */, Mips::SUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8774 /* sub */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8774 /* sub */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8774 /* sub */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_InvNum }, },
  { 8774 /* sub */, Mips::SUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8774 /* sub */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8774 /* sub */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8774 /* sub */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_InvNum }, },
  { 8778 /* sub.d */, Mips::FSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 8778 /* sub.d */, Mips::FSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
  { 8778 /* sub.d */, Mips::FSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 8778 /* sub.d */, Mips::FSUB_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 8784 /* sub.s */, Mips::FSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 8784 /* sub.s */, Mips::FSUB_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 8784 /* sub.s */, Mips::FSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 8790 /* subq.ph */, Mips::SUBQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8790 /* subq.ph */, Mips::SUBQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8798 /* subq_s.ph */, Mips::SUBQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8798 /* subq_s.ph */, Mips::SUBQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8808 /* subq_s.w */, Mips::SUBQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8808 /* subq_s.w */, Mips::SUBQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8817 /* subqh.ph */, Mips::SUBQH_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8817 /* subqh.ph */, Mips::SUBQH_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8826 /* subqh.w */, Mips::SUBQH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8826 /* subqh.w */, Mips::SUBQH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8834 /* subqh_r.ph */, Mips::SUBQH_R_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8834 /* subqh_r.ph */, Mips::SUBQH_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8845 /* subqh_r.w */, Mips::SUBQH_R_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8845 /* subqh_r.w */, Mips::SUBQH_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 8855 /* subs_s.b */, Mips::SUBS_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8864 /* subs_s.d */, Mips::SUBS_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8873 /* subs_s.h */, Mips::SUBS_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8882 /* subs_s.w */, Mips::SUBS_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8891 /* subs_u.b */, Mips::SUBS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8900 /* subs_u.d */, Mips::SUBS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8909 /* subs_u.h */, Mips::SUBS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8918 /* subs_u.w */, Mips::SUBS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8927 /* subsus_u.b */, Mips::SUBSUS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8938 /* subsus_u.d */, Mips::SUBSUS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8949 /* subsus_u.h */, Mips::SUBSUS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8960 /* subsus_u.w */, Mips::SUBSUS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8971 /* subsuu_s.b */, Mips::SUBSUU_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8982 /* subsuu_s.d */, Mips::SUBSUU_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 8993 /* subsuu_s.h */, Mips::SUBSUU_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 9004 /* subsuu_s.w */, Mips::SUBSUU_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 9015 /* subu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9015 /* subu */, Mips::SUBu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9015 /* subu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9015 /* subu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, 0, { MCK_GPR32AsmReg, MCK_InvNum }, },
  { 9015 /* subu */, Mips::SubuRxRyRz16, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_CPU16Regs }, },
  { 9015 /* subu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9015 /* subu */, Mips::SUBu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9015 /* subu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9015 /* subu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_InvNum }, },
  { 9020 /* subu.ph */, Mips::SUBU_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9020 /* subu.ph */, Mips::SUBU_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9028 /* subu.qb */, Mips::SUBU_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9028 /* subu.qb */, Mips::SUBU_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9036 /* subu16 */, Mips::SUBU16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
  { 9036 /* subu16 */, Mips::SUBU16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
  { 9043 /* subu_s.ph */, Mips::SUBU_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9043 /* subu_s.ph */, Mips::SUBU_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9053 /* subu_s.qb */, Mips::SUBU_S_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9053 /* subu_s.qb */, Mips::SUBU_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9063 /* subuh.qb */, Mips::SUBUH_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9063 /* subuh.qb */, Mips::SUBUH_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9072 /* subuh_r.qb */, Mips::SUBUH_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9072 /* subuh_r.qb */, Mips::SUBUH_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9083 /* subv.b */, Mips::SUBV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 9090 /* subv.d */, Mips::SUBV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 9097 /* subv.h */, Mips::SUBV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 9104 /* subv.w */, Mips::SUBV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 9111 /* subvi.b */, Mips::SUBVI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 9119 /* subvi.d */, Mips::SUBVI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 9127 /* subvi.h */, Mips::SUBVI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 9135 /* subvi.w */, Mips::SUBVI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
  { 9143 /* suxc1 */, Mips::SUXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
  { 9143 /* suxc1 */, Mips::SUXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
  { 9143 /* suxc1 */, Mips::SUXC1_MM, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
  { 9149 /* sw */, Mips::SWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, },
  { 9149 /* sw */, Mips::SWSP_MMR6, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, },
  { 9149 /* sw */, Mips::SW, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 9149 /* sw */, Mips::SWDSP, Convert__GPR32AsmReg1_0__Mem2_1, Feature_NotInMips16Mode|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 9149 /* sw */, Mips::SWDSP_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 9149 /* sw */, Mips::SW_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 9149 /* sw */, Mips::SW_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 9149 /* sw */, Mips::SwRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, },
  { 9149 /* sw */, Mips::SwRxSpImmX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, },
  { 9152 /* sw16 */, Mips::SW16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
  { 9152 /* sw16 */, Mips::SW16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
  { 9157 /* swc1 */, Mips::SWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, },
  { 9157 /* swc1 */, Mips::SWC1_MM, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, },
  { 9162 /* swc2 */, Mips::SWC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
  { 9162 /* swc2 */, Mips::SWC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
  { 9162 /* swc2 */, Mips::SWC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, },
  { 9167 /* swc3 */, Mips::SWC3, Convert__COP3AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotCnMips|Feature_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
  { 9172 /* swe */, Mips::SWE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 9172 /* swe */, Mips::SWE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 9176 /* swl */, Mips::SWL, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 9176 /* swl */, Mips::SWL_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 9180 /* swle */, Mips::SWLE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 9180 /* swle */, Mips::SWLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 9185 /* swm */, Mips::SWM_MM, Convert__RegList1_0__Mem2_1, Feature_InMicroMips, { MCK_RegList, MCK_Mem }, },
  { 9189 /* swm16 */, Mips::SWM16_MM, Convert__RegList161_0__MemOffsetUimm42_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
  { 9189 /* swm16 */, Mips::SWM16_MMR6, Convert__RegList161_0__MemOffsetUimm42_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
  { 9195 /* swm32 */, Mips::SWM32_MM, Convert__RegList1_0__Mem2_1, Feature_InMicroMips, { MCK_RegList, MCK_Mem }, },
  { 9201 /* swp */, Mips::SWP_MM, ConvertCustom_ConvertXWPOperands, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12 }, },
  { 9205 /* swr */, Mips::SWR, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 9205 /* swr */, Mips::SWR_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 9209 /* swre */, Mips::SWRE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 9209 /* swre */, Mips::SWRE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
  { 9214 /* swxc1 */, Mips::SWXC1, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
  { 9214 /* swxc1 */, Mips::SWXC1_MM, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
  { 9220 /* sync */, Mips::SYNC, Convert__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, {  }, },
  { 9220 /* sync */, Mips::SYNC_MMR6, Convert__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, {  }, },
  { 9220 /* sync */, Mips::SYNC_MM, Convert__imm_95_0, Feature_InMicroMips, {  }, },
  { 9220 /* sync */, Mips::SYNC, Convert__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_ConstantUImm5_0 }, },
  { 9220 /* sync */, Mips::SYNC_MMR6, Convert__ConstantUImm5_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm5_0 }, },
  { 9220 /* sync */, Mips::SYNC_MM, Convert__ConstantUImm5_01_0, Feature_InMicroMips, { MCK_ConstantUImm5_0 }, },
  { 9225 /* synci */, Mips::SYNCI, Convert__MemOffsetSimm162_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_MemOffsetSimm16 }, },
  { 9225 /* synci */, Mips::SYNCI_MM, Convert__MemOffsetSimm162_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_MemOffsetSimm16 }, },
  { 9225 /* synci */, Mips::SYNCI_MMR6, Convert__MemOffsetSimm162_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_MemOffsetSimm16 }, },
  { 9231 /* synciobdma */, Mips::SYNC, Convert__imm_95_2, Feature_HasMips64|Feature_HasCnMips, {  }, },
  { 9242 /* syncs */, Mips::SYNC, Convert__imm_95_6, Feature_HasMips64|Feature_HasCnMips, {  }, },
  { 9248 /* syncw */, Mips::SYNC, Convert__imm_95_4, Feature_HasMips64|Feature_HasCnMips, {  }, },
  { 9254 /* syncws */, Mips::SYNC, Convert__imm_95_5, Feature_HasMips64|Feature_HasCnMips, {  }, },
  { 9261 /* syscall */, Mips::SYSCALL, Convert__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, {  }, },
  { 9261 /* syscall */, Mips::SYSCALL_MM, Convert__imm_95_0, Feature_InMicroMips, {  }, },
  { 9261 /* syscall */, Mips::SYSCALL_MM, Convert__ConstantUImm10_01_0, Feature_InMicroMips, { MCK_ConstantUImm10_0 }, },
  { 9261 /* syscall */, Mips::SYSCALL, Convert__ConstantUImm20_01_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_ConstantUImm20_0 }, },
  { 9269 /* teq */, Mips::TEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9269 /* teq */, Mips::TEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9269 /* teq */, Mips::TEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
  { 9269 /* teq */, Mips::TEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
  { 9273 /* teqi */, Mips::TEQI, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 9273 /* teqi */, Mips::TEQI_MM, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 9278 /* tge */, Mips::TGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9278 /* tge */, Mips::TGE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9278 /* tge */, Mips::TGE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
  { 9278 /* tge */, Mips::TGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
  { 9282 /* tgei */, Mips::TGEI, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 9282 /* tgei */, Mips::TGEI_MM, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 9287 /* tgeiu */, Mips::TGEIU, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 9287 /* tgeiu */, Mips::TGEIU_MM, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 9293 /* tgeu */, Mips::TGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9293 /* tgeu */, Mips::TGEU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9293 /* tgeu */, Mips::TGEU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
  { 9293 /* tgeu */, Mips::TGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
  { 9298 /* tlbginv */, Mips::TLBGINV, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, {  }, },
  { 9298 /* tlbginv */, Mips::TLBGINV_MM, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, {  }, },
  { 9306 /* tlbginvf */, Mips::TLBGINVF, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, {  }, },
  { 9306 /* tlbginvf */, Mips::TLBGINVF_MM, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, {  }, },
  { 9315 /* tlbgp */, Mips::TLBGP, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, {  }, },
  { 9315 /* tlbgp */, Mips::TLBGP_MM, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, {  }, },
  { 9321 /* tlbgr */, Mips::TLBGR, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, {  }, },
  { 9321 /* tlbgr */, Mips::TLBGR_MM, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, {  }, },
  { 9327 /* tlbgwi */, Mips::TLBGWI, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, {  }, },
  { 9327 /* tlbgwi */, Mips::TLBGWI_MM, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, {  }, },
  { 9334 /* tlbgwr */, Mips::TLBGWR, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, {  }, },
  { 9334 /* tlbgwr */, Mips::TLBGWR_MM, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, {  }, },
  { 9341 /* tlbinv */, Mips::TLBINV, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, {  }, },
  { 9341 /* tlbinv */, Mips::TLBINV_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, {  }, },
  { 9348 /* tlbinvf */, Mips::TLBINVF, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, {  }, },
  { 9348 /* tlbinvf */, Mips::TLBINVF_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, {  }, },
  { 9356 /* tlbp */, Mips::TLBP, Convert_NoOperands, Feature_HasStdEnc|Feature_NotInMicroMips, {  }, },
  { 9356 /* tlbp */, Mips::TLBP_MM, Convert_NoOperands, Feature_InMicroMips, {  }, },
  { 9361 /* tlbr */, Mips::TLBR, Convert_NoOperands, Feature_HasStdEnc|Feature_NotInMicroMips, {  }, },
  { 9361 /* tlbr */, Mips::TLBR_MM, Convert_NoOperands, Feature_InMicroMips, {  }, },
  { 9366 /* tlbwi */, Mips::TLBWI, Convert_NoOperands, Feature_HasStdEnc|Feature_NotInMicroMips, {  }, },
  { 9366 /* tlbwi */, Mips::TLBWI_MM, Convert_NoOperands, Feature_InMicroMips, {  }, },
  { 9372 /* tlbwr */, Mips::TLBWR, Convert_NoOperands, Feature_HasStdEnc|Feature_NotInMicroMips, {  }, },
  { 9372 /* tlbwr */, Mips::TLBWR_MM, Convert_NoOperands, Feature_InMicroMips, {  }, },
  { 9378 /* tlt */, Mips::TLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9378 /* tlt */, Mips::TLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9378 /* tlt */, Mips::TLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
  { 9378 /* tlt */, Mips::TLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
  { 9382 /* tlti */, Mips::TLTI, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 9382 /* tlti */, Mips::TLTI_MM, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 9387 /* tltiu */, Mips::TTLTIU, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 9387 /* tltiu */, Mips::TLTIU_MM, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 9393 /* tltu */, Mips::TLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9393 /* tltu */, Mips::TLTU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9393 /* tltu */, Mips::TLTU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
  { 9393 /* tltu */, Mips::TLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
  { 9398 /* tne */, Mips::TNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9398 /* tne */, Mips::TNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9398 /* tne */, Mips::TNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
  { 9398 /* tne */, Mips::TNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
  { 9402 /* tnei */, Mips::TNEI, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 9402 /* tnei */, Mips::TNEI_MM, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
  { 9407 /* trunc.l.d */, Mips::TRUNC_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 9407 /* trunc.l.d */, Mips::TRUNC_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
  { 9417 /* trunc.l.s */, Mips::TRUNC_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
  { 9417 /* trunc.l.s */, Mips::TRUNC_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
  { 9427 /* trunc.w.d */, Mips::TRUNC_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
  { 9427 /* trunc.w.d */, Mips::TRUNC_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
  { 9427 /* trunc.w.d */, Mips::TRUNC_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
  { 9427 /* trunc.w.d */, Mips::TRUNC_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
  { 9427 /* trunc.w.d */, Mips::PseudoTRUNC_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2, Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
  { 9427 /* trunc.w.d */, Mips::PseudoTRUNC_W_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2, Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, },
  { 9437 /* trunc.w.s */, Mips::TRUNC_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 9437 /* trunc.w.s */, Mips::TRUNC_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 9437 /* trunc.w.s */, Mips::TRUNC_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
  { 9437 /* trunc.w.s */, Mips::PseudoTRUNC_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2, 0, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
  { 9447 /* ulh */, Mips::Ulh, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 9451 /* ulhu */, Mips::Ulhu, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 9456 /* ulw */, Mips::Ulw, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 9460 /* ush */, Mips::Ush, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 9464 /* usw */, Mips::Usw, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, },
  { 9468 /* v3mulu */, Mips::V3MULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 9468 /* v3mulu */, Mips::V3MULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 9475 /* vmm0 */, Mips::VMM0, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 9475 /* vmm0 */, Mips::VMM0, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 9480 /* vmulu */, Mips::VMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 9480 /* vmulu */, Mips::VMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
  { 9486 /* vshf.b */, Mips::VSHF_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 9493 /* vshf.d */, Mips::VSHF_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 9500 /* vshf.h */, Mips::VSHF_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 9507 /* vshf.w */, Mips::VSHF_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 9514 /* wait */, Mips::WAIT, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotInMicroMips, {  }, },
  { 9514 /* wait */, Mips::WAIT_MM, Convert__imm_95_0, Feature_InMicroMips, {  }, },
  { 9514 /* wait */, Mips::WAIT_MMR6, Convert__ConstantUImm10_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm10_0 }, },
  { 9514 /* wait */, Mips::WAIT_MM, Convert__ConstantUImm10_01_0, Feature_InMicroMips, { MCK_ConstantUImm10_0 }, },
  { 9519 /* wrdsp */, Mips::WRDSP, Convert__GPR32AsmReg1_0__imm_95_31, Feature_HasDSP|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 9519 /* wrdsp */, Mips::WRDSP_MM, Convert__GPR32AsmReg1_0__imm_95_31, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg }, },
  { 9519 /* wrdsp */, Mips::WRDSP_MM, Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm7_0 }, },
  { 9519 /* wrdsp */, Mips::WRDSP, Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, Feature_HasDSP|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
  { 9525 /* wrpgpr */, Mips::WRPGPR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9532 /* wsbh */, Mips::WSBH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9532 /* wsbh */, Mips::WSBH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9532 /* wsbh */, Mips::WSBH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9537 /* xor */, Mips::XorRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
  { 9537 /* xor */, Mips::XOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9537 /* xor */, Mips::XOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9537 /* xor */, Mips::XOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9537 /* xor */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 9537 /* xor */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 9537 /* xor */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 9537 /* xor */, Mips::XORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
  { 9537 /* xor */, Mips::XOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9537 /* xor */, Mips::XOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9537 /* xor */, Mips::XOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
  { 9537 /* xor */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 9537 /* xor */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 9537 /* xor */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
  { 9537 /* xor */, Mips::XORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
  { 9541 /* xor.v */, Mips::XOR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
  { 9547 /* xor16 */, Mips::XOR16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
  { 9547 /* xor16 */, Mips::XOR16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
  { 9553 /* xori */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 9553 /* xori */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 9553 /* xori */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 9553 /* xori */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 9553 /* xori */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 9553 /* xori */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
  { 9558 /* xori.b */, Mips::XORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
  { 9565 /* yield */, Mips::YIELD, Convert__regZERO__GPR32AsmReg1_0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
  { 9565 /* yield */, Mips::YIELD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
};

#include "llvm/Support/Debug.h"
#include "llvm/Support/Format.h"

unsigned MipsAsmParser::
MatchInstructionImpl(const OperandVector &Operands,
                     MCInst &Inst,
                     uint64_t &ErrorInfo,
                     bool matchingInlineAsm, unsigned VariantID) {
  // Eliminate obvious mismatches.
  if (Operands.size() > 9) {
    ErrorInfo = 9;
    return Match_InvalidOperand;
  }

  // Get the current feature set.
  uint64_t AvailableFeatures = getAvailableFeatures();

  // Get the instruction mnemonic, which is the first token.
  StringRef Mnemonic = ((MipsOperand&)*Operands[0]).getToken();

  // Some state to try to produce better error messages.
  bool HadMatchOtherThanFeatures = false;
  bool HadMatchOtherThanPredicate = false;
  unsigned RetCode = Match_InvalidOperand;
  uint64_t MissingFeatures = ~0ULL;
  // Set ErrorInfo to the operand that mismatches if it is
  // wrong for all instances of the instruction.
  ErrorInfo = ~0ULL;
  // Find the appropriate table for this asm variant.
  const MatchEntry *Start, *End;
  switch (VariantID) {
  default: llvm_unreachable("invalid variant!");
  case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
  }
  // Search the table.
  auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());

  DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
  std::distance(MnemonicRange.first, MnemonicRange.second) << 
  " encodings with mnemonic '" << Mnemonic << "'\n");

  // Return a more specific error code if no mnemonics match.
  if (MnemonicRange.first == MnemonicRange.second)
    return Match_MnemonicFail;

  for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
       it != ie; ++it) {
    bool HasRequiredFeatures =
      (AvailableFeatures & it->RequiredFeatures) == it->RequiredFeatures;
    DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
                                          << MII.getName(it->Opcode) << "\n");
    // equal_range guarantees that instruction mnemonic matches.
    assert(Mnemonic == it->getMnemonic());
    bool OperandsValid = true;
    for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 8; ++FormalIdx) {
      auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
      DEBUG_WITH_TYPE("asm-matcher",
                      dbgs() << "  Matching formal operand class " << getMatchClassName(Formal)
                             << " against actual operand at index " << ActualIdx);
      if (ActualIdx < Operands.size())
        DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
                        Operands[ActualIdx]->print(dbgs()); dbgs() << "): ");
      else
        DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
      if (ActualIdx >= Operands.size()) {
        DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range ");
        OperandsValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass);
        if (!OperandsValid) ErrorInfo = ActualIdx;
        break;
      }
      MCParsedAsmOperand &Actual = *Operands[ActualIdx];
      unsigned Diag = validateOperandClass(Actual, Formal);
      if (Diag == Match_Success) {
        DEBUG_WITH_TYPE("asm-matcher",
                        dbgs() << "match success using generic matcher\n");
        ++ActualIdx;
        continue;
      }
      // If the generic handler indicates an invalid operand
      // failure, check for a special case.
      if (Diag != Match_Success) {
        unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
        if (TargetDiag == Match_Success) {
          DEBUG_WITH_TYPE("asm-matcher",
                          dbgs() << "match success using target matcher\n");
          ++ActualIdx;
          continue;
        }
        // If the target matcher returned a specific error code use
        // that, else use the one from the generic matcher.
        if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
          Diag = TargetDiag;
      }
      // If current formal operand wasn't matched and it is optional
      // then try to match next formal operand
      if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
        DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
        continue;
      }
      // If this operand is broken for all of the instances of this
      // mnemonic, keep track of it so we can report loc info.
      // If we already had a match that only failed due to a
      // target predicate, that diagnostic is preferred.
      if (!HadMatchOtherThanPredicate &&
          (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {
        if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand))
          RetCode = Diag;
        ErrorInfo = ActualIdx;
      }
      // Otherwise, just reject this instance of the mnemonic.
      OperandsValid = false;
      break;
    }

    if (!OperandsValid) {
      DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
                                               "operand mismatches, ignoring "
                                               "this opcode\n");
      continue;
    }
    if (!HasRequiredFeatures) {
      HadMatchOtherThanFeatures = true;
      uint64_t NewMissingFeatures = it->RequiredFeatures & ~AvailableFeatures;
      DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features: "
                                            << format_hex(NewMissingFeatures, 18)
                                            << "\n");
      if (countPopulation(NewMissingFeatures) <=
          countPopulation(MissingFeatures))
        MissingFeatures = NewMissingFeatures;
      continue;
    }

    Inst.clear();

    Inst.setOpcode(it->Opcode);
    // We have a potential match but have not rendered the operands.
    // Check the target predicate to handle any context sensitive
    // constraints.
    // For example, Ties that are referenced multiple times must be
    // checked here to ensure the input is the same for each match
    // constraints. If we leave it any later the ties will have been
    // canonicalized
    unsigned MatchResult;
    if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
      Inst.clear();
      DEBUG_WITH_TYPE(
          "asm-matcher",
          dbgs() << "Early target match predicate failed with diag code "
                 << MatchResult << "\n");
      RetCode = MatchResult;
      HadMatchOtherThanPredicate = true;
      continue;
    }

    if (matchingInlineAsm) {
      convertToMapAndConstraints(it->ConvertFn, Operands);
      if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo))
        return Match_InvalidTiedOperand;

      return Match_Success;
    }

    // We have selected a definite instruction, convert the parsed
    // operands into the appropriate MCInst.
    convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);

    // We have a potential match. Check the target predicate to
    // handle any context sensitive constraints.
    if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
      DEBUG_WITH_TYPE("asm-matcher",
                      dbgs() << "Target match predicate failed with diag code "
                             << MatchResult << "\n");
      Inst.clear();
      RetCode = MatchResult;
      HadMatchOtherThanPredicate = true;
      continue;
    }

    if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo))
      return Match_InvalidTiedOperand;

    DEBUG_WITH_TYPE(
        "asm-matcher",
        dbgs() << "Opcode result: complete match, selecting this opcode\n");
    return Match_Success;
  }

  // Okay, we had no match.  Try to return a useful error code.
  if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)
    return RetCode;

  // Missing feature matches return which features were missing
  ErrorInfo = MissingFeatures;
  return Match_MissingFeature;
}

namespace {
  struct OperandMatchEntry {
    uint64_t RequiredFeatures;
    uint16_t Mnemonic;
    uint8_t Class;
    uint8_t OperandMask;

    StringRef getMnemonic() const {
      return StringRef(MnemonicTable + Mnemonic + 1,
                       MnemonicTable[Mnemonic]);
    }
  };

  // Predicate for searching for an opcode.
  struct LessOpcodeOperand {
    bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
      return LHS.getMnemonic()  < RHS;
    }
    bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
      return LHS < RHS.getMnemonic();
    }
    bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
      return LHS.getMnemonic() < RHS.getMnemonic();
    }
  };
} // end anonymous namespace.

static const OperandMatchEntry OperandMatchTable[3237] = {
  /* Operand List Mask, Mnemonic, Operand Class, Features */
  { 0, 0 /* abs */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4 /* abs.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 4 /* abs.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4 /* abs.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 4 /* abs.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 10 /* abs.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 10 /* abs.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 16 /* absq_s.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 16 /* absq_s.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 26 /* absq_s.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSPR2, 26 /* absq_s.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 36 /* absq_s.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 36 /* absq_s.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 45 /* add */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 45 /* add */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 45 /* add */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 45 /* add */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 45 /* add */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 45 /* add */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 45 /* add */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 45 /* add */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 45 /* add */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 45 /* add */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 49 /* add.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 49 /* add.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 49 /* add.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 49 /* add.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 55 /* add.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 55 /* add.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 55 /* add.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 61 /* add_a.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 69 /* add_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 77 /* add_a.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 85 /* add_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 93 /* addi */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 93 /* addi */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 93 /* addi */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 93 /* addi */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 98 /* addiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 98 /* addiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 98 /* addiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 98 /* addiu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 98 /* addiu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 98 /* addiu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6, 104 /* addiupc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 104 /* addiupc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 104 /* addiupc */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 112 /* addiur1sp */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 122 /* addiur2 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 130 /* addius5 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 146 /* addq.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 146 /* addq.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 154 /* addq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 154 /* addq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 164 /* addq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 164 /* addq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 173 /* addqh.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 173 /* addqh.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 182 /* addqh.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 182 /* addqh.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 190 /* addqh_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 190 /* addqh_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 201 /* addqh_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 201 /* addqh_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 211 /* adds_a.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 220 /* adds_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 229 /* adds_a.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 238 /* adds_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 247 /* adds_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 256 /* adds_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 265 /* adds_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 274 /* adds_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 283 /* adds_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 292 /* adds_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 301 /* adds_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 310 /* adds_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 319 /* addsc */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 319 /* addsc */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 325 /* addu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 325 /* addu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 325 /* addu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 325 /* addu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 330 /* addu.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 330 /* addu.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 338 /* addu.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 338 /* addu.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 346 /* addu16 */, MCK_GPRMM16AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 346 /* addu16 */, MCK_GPRMM16AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 353 /* addu_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 353 /* addu_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 363 /* addu_s.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 363 /* addu_s.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 373 /* adduh.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 373 /* adduh.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 382 /* adduh_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 382 /* adduh_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 393 /* addv.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 400 /* addv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 407 /* addv.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 414 /* addv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 421 /* addvi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 429 /* addvi.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 437 /* addvi.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 445 /* addvi.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 453 /* addwc */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 453 /* addwc */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6, 459 /* align */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 459 /* align */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6, 465 /* aluipc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 465 /* aluipc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 472 /* and */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 472 /* and */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 472 /* and */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, 472 /* and */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 472 /* and */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 472 /* and */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 472 /* and */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, 472 /* and */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 476 /* and.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 482 /* and16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 482 /* and16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 488 /* andi */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 488 /* andi */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 488 /* andi */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 488 /* andi */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 488 /* andi */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 488 /* andi */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 493 /* andi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 500 /* andi16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 500 /* andi16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 507 /* append */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSPR2, 507 /* append */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 514 /* asub_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 523 /* asub_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 532 /* asub_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 541 /* asub_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 550 /* asub_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 559 /* asub_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 568 /* asub_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 577 /* asub_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6, 586 /* aui */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 586 /* aui */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6, 590 /* auipc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 590 /* auipc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 596 /* ave_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 604 /* ave_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 612 /* ave_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 620 /* ave_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 628 /* ave_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 636 /* ave_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 644 /* ave_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 652 /* ave_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 660 /* aver_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 669 /* aver_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 678 /* aver_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 687 /* aver_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 696 /* aver_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 705 /* aver_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 714 /* aver_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 723 /* aver_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 732 /* b */, MCK_JumpTarget, 1 /* 0 */ },
  { Feature_InMicroMips, 732 /* b */, MCK_JumpTarget, 1 /* 0 */ },
  { Feature_InMips16Mode, 732 /* b */, MCK_JumpTarget, 1 /* 0 */ },
  { 0, 732 /* b */, MCK_JumpTarget, 1 /* 0 */ },
  { Feature_InMips16Mode, 732 /* b */, MCK_JumpTarget, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 734 /* b16 */, MCK_JumpTarget, 1 /* 0 */ },
  { Feature_InMicroMips, 734 /* b16 */, MCK_JumpTarget, 1 /* 0 */ },
  { Feature_HasCnMips, 738 /* baddu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasCnMips, 738 /* baddu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 744 /* bal */, MCK_JumpTarget, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6, 744 /* bal */, MCK_JumpTarget, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 744 /* bal */, MCK_JumpTarget, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6, 748 /* balc */, MCK_JumpTarget, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 748 /* balc */, MCK_JumpTarget, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 753 /* balign */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSPR2, 753 /* balign */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasCnMips, 760 /* bbit0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasCnMips, 760 /* bbit0 */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasCnMips, 760 /* bbit0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasCnMips, 760 /* bbit0 */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasCnMips, 766 /* bbit032 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasCnMips, 766 /* bbit032 */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasCnMips, 774 /* bbit1 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasCnMips, 774 /* bbit1 */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasCnMips, 774 /* bbit1 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasCnMips, 774 /* bbit1 */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasCnMips, 780 /* bbit132 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasCnMips, 780 /* bbit132 */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 788 /* bc */, MCK_JumpTarget, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 788 /* bc */, MCK_JumpTarget, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 791 /* bc16 */, MCK_JumpTarget, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 796 /* bc1eqz */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 796 /* bc1eqz */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 803 /* bc1eqzc */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 803 /* bc1eqzc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 811 /* bc1f */, MCK_JumpTarget, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 811 /* bc1f */, MCK_JumpTarget, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 811 /* bc1f */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 811 /* bc1f */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 811 /* bc1f */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 811 /* bc1f */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 816 /* bc1fl */, MCK_JumpTarget, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 816 /* bc1fl */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 816 /* bc1fl */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 822 /* bc1nez */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 822 /* bc1nez */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 829 /* bc1nezc */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 829 /* bc1nezc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 837 /* bc1t */, MCK_JumpTarget, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 837 /* bc1t */, MCK_JumpTarget, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 837 /* bc1t */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 837 /* bc1t */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 837 /* bc1t */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 837 /* bc1t */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 842 /* bc1tl */, MCK_JumpTarget, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 842 /* bc1tl */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 842 /* bc1tl */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 848 /* bc2eqz */, MCK_COP2AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 848 /* bc2eqz */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 855 /* bc2eqzc */, MCK_COP2AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 855 /* bc2eqzc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 863 /* bc2nez */, MCK_COP2AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 863 /* bc2nez */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 870 /* bc2nezc */, MCK_COP2AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 870 /* bc2nezc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 878 /* bclr.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 885 /* bclr.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 892 /* bclr.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 899 /* bclr.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 906 /* bclri.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 914 /* bclri.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 922 /* bclri.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 930 /* bclri.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 938 /* beq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 938 /* beq */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 938 /* beq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 938 /* beq */, MCK_JumpTarget, 4 /* 2 */ },
  { 0, 938 /* beq */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { 0, 938 /* beq */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 942 /* beqc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 942 /* beqc */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 942 /* beqc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 942 /* beqc */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 942 /* beqc */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 942 /* beqc */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 947 /* beql */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 947 /* beql */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 947 /* beql */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 947 /* beql */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_InMips16Mode, 952 /* beqz */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 952 /* beqz */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 952 /* beqz */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips, 952 /* beqz */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 952 /* beqz */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMips16Mode, 952 /* beqz */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 957 /* beqz16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 957 /* beqz16 */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 957 /* beqz16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 957 /* beqz16 */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 964 /* beqzalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 964 /* beqzalc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 964 /* beqzalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 964 /* beqzalc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 972 /* beqzc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 972 /* beqzc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 972 /* beqzc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 972 /* beqzc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 972 /* beqzc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 972 /* beqzc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 972 /* beqzc */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 972 /* beqzc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 978 /* beqzc16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 978 /* beqzc16 */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 986 /* beqzl */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 986 /* beqzl */, MCK_JumpTarget, 2 /* 1 */ },
  { 0, 992 /* bge */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { 0, 992 /* bge */, MCK_JumpTarget, 4 /* 2 */ },
  { 0, 992 /* bge */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { 0, 992 /* bge */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 996 /* bgec */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 996 /* bgec */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 996 /* bgec */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 996 /* bgec */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 996 /* bgec */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 996 /* bgec */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1001 /* bgel */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1001 /* bgel */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1001 /* bgel */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1001 /* bgel */, MCK_JumpTarget, 4 /* 2 */ },
  { 0, 1006 /* bgeu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { 0, 1006 /* bgeu */, MCK_JumpTarget, 4 /* 2 */ },
  { 0, 1006 /* bgeu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { 0, 1006 /* bgeu */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1011 /* bgeuc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1011 /* bgeuc */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1011 /* bgeuc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1011 /* bgeuc */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1011 /* bgeuc */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1011 /* bgeuc */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1017 /* bgeul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1017 /* bgeul */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1017 /* bgeul */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1017 /* bgeul */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 1023 /* bgez */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 1023 /* bgez */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 1023 /* bgez */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 1023 /* bgez */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1028 /* bgezal */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1028 /* bgezal */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 1028 /* bgezal */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 1028 /* bgezal */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1035 /* bgezalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1035 /* bgezalc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1035 /* bgezalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1035 /* bgezalc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1043 /* bgezall */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1043 /* bgezall */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 1051 /* bgezals */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 1051 /* bgezals */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1059 /* bgezc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1059 /* bgezc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1059 /* bgezc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1059 /* bgezc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1059 /* bgezc */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1059 /* bgezc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1065 /* bgezl */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1065 /* bgezl */, MCK_JumpTarget, 2 /* 1 */ },
  { 0, 1071 /* bgt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { 0, 1071 /* bgt */, MCK_JumpTarget, 4 /* 2 */ },
  { 0, 1071 /* bgt */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { 0, 1071 /* bgt */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1075 /* bgtl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1075 /* bgtl */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1075 /* bgtl */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1075 /* bgtl */, MCK_JumpTarget, 4 /* 2 */ },
  { 0, 1080 /* bgtu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { 0, 1080 /* bgtu */, MCK_JumpTarget, 4 /* 2 */ },
  { 0, 1080 /* bgtu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { 0, 1080 /* bgtu */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1085 /* bgtul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1085 /* bgtul */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1085 /* bgtul */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1085 /* bgtul */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 1091 /* bgtz */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 1091 /* bgtz */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 1091 /* bgtz */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 1091 /* bgtz */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1096 /* bgtzalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1096 /* bgtzalc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1096 /* bgtzalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1096 /* bgtzalc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1104 /* bgtzc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1104 /* bgtzc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1104 /* bgtzc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1104 /* bgtzc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1104 /* bgtzc */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1104 /* bgtzc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1110 /* bgtzl */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1110 /* bgtzl */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1116 /* binsl.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1124 /* binsl.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1132 /* binsl.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1140 /* binsl.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1148 /* binsli.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1157 /* binsli.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1166 /* binsli.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1175 /* binsli.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1184 /* binsr.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1192 /* binsr.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1200 /* binsr.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1208 /* binsr.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1216 /* binsri.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1225 /* binsri.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1234 /* binsri.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1243 /* binsri.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 1252 /* bitrev */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 1252 /* bitrev */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6, 1259 /* bitswap */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1259 /* bitswap */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { 0, 1267 /* ble */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { 0, 1267 /* ble */, MCK_JumpTarget, 4 /* 2 */ },
  { 0, 1267 /* ble */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { 0, 1267 /* ble */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1271 /* blel */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1271 /* blel */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1271 /* blel */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1271 /* blel */, MCK_JumpTarget, 4 /* 2 */ },
  { 0, 1276 /* bleu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { 0, 1276 /* bleu */, MCK_JumpTarget, 4 /* 2 */ },
  { 0, 1276 /* bleu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { 0, 1276 /* bleu */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1281 /* bleul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1281 /* bleul */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1281 /* bleul */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1281 /* bleul */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 1287 /* blez */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 1287 /* blez */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 1287 /* blez */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 1287 /* blez */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1292 /* blezalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1292 /* blezalc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1292 /* blezalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1292 /* blezalc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1300 /* blezc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1300 /* blezc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1300 /* blezc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1300 /* blezc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1300 /* blezc */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1300 /* blezc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1306 /* blezl */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1306 /* blezl */, MCK_JumpTarget, 2 /* 1 */ },
  { 0, 1312 /* blt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { 0, 1312 /* blt */, MCK_JumpTarget, 4 /* 2 */ },
  { 0, 1312 /* blt */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { 0, 1312 /* blt */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1316 /* bltc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1316 /* bltc */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1316 /* bltc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1316 /* bltc */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1316 /* bltc */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1316 /* bltc */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1321 /* bltl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1321 /* bltl */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1321 /* bltl */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1321 /* bltl */, MCK_JumpTarget, 4 /* 2 */ },
  { 0, 1326 /* bltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { 0, 1326 /* bltu */, MCK_JumpTarget, 4 /* 2 */ },
  { 0, 1326 /* bltu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { 0, 1326 /* bltu */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1331 /* bltuc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1331 /* bltuc */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1331 /* bltuc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1331 /* bltuc */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1331 /* bltuc */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1331 /* bltuc */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1337 /* bltul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1337 /* bltul */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1337 /* bltul */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1337 /* bltul */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 1343 /* bltz */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 1343 /* bltz */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 1343 /* bltz */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 1343 /* bltz */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1348 /* bltzal */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1348 /* bltzal */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 1348 /* bltzal */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 1348 /* bltzal */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1355 /* bltzalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1355 /* bltzalc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1355 /* bltzalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1355 /* bltzalc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1363 /* bltzall */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1363 /* bltzall */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 1371 /* bltzals */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 1371 /* bltzals */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1379 /* bltzc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1379 /* bltzc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1379 /* bltzc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1379 /* bltzc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1379 /* bltzc */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1379 /* bltzc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1385 /* bltzl */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1385 /* bltzl */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1391 /* bmnz.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1398 /* bmnzi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1406 /* bmz.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1412 /* bmzi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 1419 /* bne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 1419 /* bne */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 1419 /* bne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 1419 /* bne */, MCK_JumpTarget, 4 /* 2 */ },
  { 0, 1419 /* bne */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { 0, 1419 /* bne */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1423 /* bnec */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1423 /* bnec */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1423 /* bnec */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1423 /* bnec */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1423 /* bnec */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1423 /* bnec */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1428 /* bneg.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1435 /* bneg.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1442 /* bneg.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1449 /* bneg.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1456 /* bnegi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1464 /* bnegi.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1472 /* bnegi.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1480 /* bnegi.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1488 /* bnel */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1488 /* bnel */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1488 /* bnel */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1488 /* bnel */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_InMips16Mode, 1493 /* bnez */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 1493 /* bnez */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 1493 /* bnez */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips, 1493 /* bnez */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 1493 /* bnez */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMips16Mode, 1493 /* bnez */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 1498 /* bnez16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 1498 /* bnez16 */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1498 /* bnez16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1498 /* bnez16 */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1505 /* bnezalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1505 /* bnezalc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1505 /* bnezalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1505 /* bnezalc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1513 /* bnezc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1513 /* bnezc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 1513 /* bnezc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 1513 /* bnezc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1513 /* bnezc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1513 /* bnezc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1513 /* bnezc */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1513 /* bnezc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1519 /* bnezc16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1519 /* bnezc16 */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 1527 /* bnezl */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 1527 /* bnezl */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1533 /* bnvc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1533 /* bnvc */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1533 /* bnvc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1533 /* bnvc */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1538 /* bnz.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1538 /* bnz.b */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1544 /* bnz.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1544 /* bnz.d */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1550 /* bnz.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1550 /* bnz.h */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1556 /* bnz.v */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1556 /* bnz.v */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1562 /* bnz.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1562 /* bnz.w */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1568 /* bovc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1568 /* bovc */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1568 /* bovc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1568 /* bovc */, MCK_JumpTarget, 4 /* 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasDSP, 1573 /* bposge32 */, MCK_JumpTarget, 1 /* 0 */ },
  { Feature_HasDSP|Feature_NotInMicroMips, 1573 /* bposge32 */, MCK_JumpTarget, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSPR3, 1582 /* bposge32c */, MCK_JumpTarget, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1606 /* bsel.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1613 /* bseli.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1621 /* bset.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1628 /* bset.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1635 /* bset.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1642 /* bset.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1649 /* bseti.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1657 /* bseti.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1665 /* bseti.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1673 /* bseti.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1693 /* bz.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1693 /* bz.b */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1698 /* bz.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1698 /* bz.d */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1703 /* bz.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1703 /* bz.h */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1708 /* bz.v */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1708 /* bz.v */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1713 /* bz.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 1713 /* bz.w */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1718 /* c.eq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1718 /* c.eq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1718 /* c.eq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1718 /* c.eq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1718 /* c.eq.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1718 /* c.eq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1718 /* c.eq.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1718 /* c.eq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1718 /* c.eq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1718 /* c.eq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1718 /* c.eq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1718 /* c.eq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1725 /* c.eq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1725 /* c.eq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1725 /* c.eq.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1725 /* c.eq.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1725 /* c.eq.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1725 /* c.eq.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1732 /* c.f.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1732 /* c.f.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1732 /* c.f.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1732 /* c.f.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1732 /* c.f.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1732 /* c.f.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1732 /* c.f.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1732 /* c.f.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1732 /* c.f.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1732 /* c.f.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1732 /* c.f.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1732 /* c.f.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1738 /* c.f.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1738 /* c.f.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1738 /* c.f.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1738 /* c.f.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1738 /* c.f.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1738 /* c.f.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1744 /* c.le.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1744 /* c.le.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1744 /* c.le.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1744 /* c.le.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1744 /* c.le.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1744 /* c.le.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1744 /* c.le.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1744 /* c.le.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1744 /* c.le.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1744 /* c.le.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1744 /* c.le.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1744 /* c.le.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1751 /* c.le.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1751 /* c.le.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1751 /* c.le.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1751 /* c.le.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1751 /* c.le.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1751 /* c.le.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1758 /* c.lt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1758 /* c.lt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1758 /* c.lt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1758 /* c.lt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1758 /* c.lt.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1758 /* c.lt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1758 /* c.lt.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1758 /* c.lt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1758 /* c.lt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1758 /* c.lt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1758 /* c.lt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1758 /* c.lt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1765 /* c.lt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1765 /* c.lt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1765 /* c.lt.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1765 /* c.lt.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1765 /* c.lt.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1765 /* c.lt.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1772 /* c.nge.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1772 /* c.nge.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1772 /* c.nge.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1772 /* c.nge.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1772 /* c.nge.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1772 /* c.nge.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1772 /* c.nge.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1772 /* c.nge.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1772 /* c.nge.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1772 /* c.nge.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1772 /* c.nge.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1772 /* c.nge.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1780 /* c.nge.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1780 /* c.nge.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1780 /* c.nge.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1780 /* c.nge.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1780 /* c.nge.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1780 /* c.nge.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1788 /* c.ngl.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1788 /* c.ngl.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1788 /* c.ngl.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1788 /* c.ngl.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1788 /* c.ngl.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1788 /* c.ngl.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1788 /* c.ngl.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1788 /* c.ngl.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1788 /* c.ngl.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1788 /* c.ngl.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1788 /* c.ngl.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1788 /* c.ngl.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1796 /* c.ngl.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1796 /* c.ngl.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1796 /* c.ngl.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1796 /* c.ngl.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1796 /* c.ngl.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1796 /* c.ngl.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1804 /* c.ngle.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1804 /* c.ngle.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1804 /* c.ngle.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1804 /* c.ngle.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1804 /* c.ngle.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1804 /* c.ngle.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1804 /* c.ngle.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1804 /* c.ngle.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1804 /* c.ngle.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1804 /* c.ngle.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1804 /* c.ngle.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1804 /* c.ngle.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1813 /* c.ngle.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1813 /* c.ngle.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1813 /* c.ngle.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1813 /* c.ngle.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1813 /* c.ngle.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1813 /* c.ngle.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1822 /* c.ngt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1822 /* c.ngt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1822 /* c.ngt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1822 /* c.ngt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1822 /* c.ngt.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1822 /* c.ngt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1822 /* c.ngt.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1822 /* c.ngt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1822 /* c.ngt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1822 /* c.ngt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1822 /* c.ngt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1822 /* c.ngt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1830 /* c.ngt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1830 /* c.ngt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1830 /* c.ngt.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1830 /* c.ngt.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1830 /* c.ngt.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1830 /* c.ngt.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1838 /* c.ole.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1838 /* c.ole.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1838 /* c.ole.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1838 /* c.ole.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1838 /* c.ole.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1838 /* c.ole.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1838 /* c.ole.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1838 /* c.ole.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1838 /* c.ole.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1838 /* c.ole.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1838 /* c.ole.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1838 /* c.ole.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1846 /* c.ole.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1846 /* c.ole.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1846 /* c.ole.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1846 /* c.ole.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1846 /* c.ole.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1846 /* c.ole.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1854 /* c.olt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1854 /* c.olt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1854 /* c.olt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1854 /* c.olt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1854 /* c.olt.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1854 /* c.olt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1854 /* c.olt.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1854 /* c.olt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1854 /* c.olt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1854 /* c.olt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1854 /* c.olt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1854 /* c.olt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1862 /* c.olt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1862 /* c.olt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1862 /* c.olt.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1862 /* c.olt.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1862 /* c.olt.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1862 /* c.olt.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1870 /* c.seq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1870 /* c.seq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1870 /* c.seq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1870 /* c.seq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1870 /* c.seq.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1870 /* c.seq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1870 /* c.seq.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1870 /* c.seq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1870 /* c.seq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1870 /* c.seq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1870 /* c.seq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1870 /* c.seq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1878 /* c.seq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1878 /* c.seq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1878 /* c.seq.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1878 /* c.seq.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1878 /* c.seq.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1878 /* c.seq.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1886 /* c.sf.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1886 /* c.sf.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1886 /* c.sf.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1886 /* c.sf.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1886 /* c.sf.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1886 /* c.sf.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1886 /* c.sf.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1886 /* c.sf.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1886 /* c.sf.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1886 /* c.sf.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1886 /* c.sf.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1886 /* c.sf.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1893 /* c.sf.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1893 /* c.sf.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1893 /* c.sf.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1893 /* c.sf.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1893 /* c.sf.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1893 /* c.sf.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1900 /* c.ueq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1900 /* c.ueq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1900 /* c.ueq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1900 /* c.ueq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1900 /* c.ueq.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1900 /* c.ueq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1900 /* c.ueq.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1900 /* c.ueq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1900 /* c.ueq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1900 /* c.ueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1900 /* c.ueq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1900 /* c.ueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1908 /* c.ueq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1908 /* c.ueq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1908 /* c.ueq.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1908 /* c.ueq.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1908 /* c.ueq.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1908 /* c.ueq.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1916 /* c.ule.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1916 /* c.ule.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1916 /* c.ule.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1916 /* c.ule.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1916 /* c.ule.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1916 /* c.ule.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1916 /* c.ule.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1916 /* c.ule.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1916 /* c.ule.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1916 /* c.ule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1916 /* c.ule.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1916 /* c.ule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1924 /* c.ule.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1924 /* c.ule.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1924 /* c.ule.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1924 /* c.ule.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1924 /* c.ule.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1924 /* c.ule.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1932 /* c.ult.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1932 /* c.ult.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1932 /* c.ult.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1932 /* c.ult.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1932 /* c.ult.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1932 /* c.ult.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1932 /* c.ult.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1932 /* c.ult.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1932 /* c.ult.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1932 /* c.ult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1932 /* c.ult.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1932 /* c.ult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1940 /* c.ult.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1940 /* c.ult.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1940 /* c.ult.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1940 /* c.ult.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1940 /* c.ult.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1940 /* c.ult.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1948 /* c.un.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1948 /* c.un.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1948 /* c.un.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1948 /* c.un.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1948 /* c.un.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1948 /* c.un.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1948 /* c.un.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1948 /* c.un.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1948 /* c.un.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1948 /* c.un.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1948 /* c.un.d */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1948 /* c.un.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1955 /* c.un.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1955 /* c.un.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1955 /* c.un.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1955 /* c.un.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1955 /* c.un.s */, MCK_FCCAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1955 /* c.un.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1962 /* cache */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1962 /* cache */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 1962 /* cache */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 1962 /* cache */, MCK_Mem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 1968 /* cachee */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasEVA, 1968 /* cachee */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1975 /* ceil.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 1975 /* ceil.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1984 /* ceil.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1984 /* ceil.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 1984 /* ceil.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 1984 /* ceil.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1993 /* ceil.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1993 /* ceil.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 1993 /* ceil.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 1993 /* ceil.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 1993 /* ceil.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 1993 /* ceil.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1993 /* ceil.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1993 /* ceil.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2002 /* ceil.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2002 /* ceil.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 2002 /* ceil.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2011 /* ceq.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2017 /* ceq.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2023 /* ceq.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2029 /* ceq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2035 /* ceqi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2042 /* ceqi.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2049 /* ceqi.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2056 /* ceqi.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2063 /* cfc1 */, MCK_CCRAsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2063 /* cfc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 2063 /* cfc1 */, MCK_CCRAsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 2063 /* cfc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 2068 /* cfc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips, 2068 /* cfc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2073 /* cfcmsa */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2073 /* cfcmsa */, MCK_MSACtrlAsmReg, 2 /* 1 */ },
  { Feature_HasMT, 2080 /* cftc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_HasMT, 2080 /* cftc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 2086 /* cins */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasMips64|Feature_HasCnMips, 2086 /* cins */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 2086 /* cins */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasMips64|Feature_HasCnMips, 2086 /* cins */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 2091 /* cins32 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 2091 /* cins32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2098 /* class.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 2098 /* class.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2106 /* class.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 2106 /* class.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2114 /* cle_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2122 /* cle_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2130 /* cle_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2138 /* cle_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2146 /* cle_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2154 /* cle_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2162 /* cle_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2170 /* cle_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2178 /* clei_s.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2187 /* clei_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2196 /* clei_s.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2205 /* clei_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2214 /* clei_u.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2223 /* clei_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2232 /* clei_u.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2241 /* clei_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 2250 /* clo */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 2250 /* clo */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6, 2250 /* clo */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 2250 /* clo */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2254 /* clt_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2262 /* clt_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2270 /* clt_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2278 /* clt_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2286 /* clt_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2294 /* clt_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2302 /* clt_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2310 /* clt_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2318 /* clti_s.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2327 /* clti_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2336 /* clti_s.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2345 /* clti_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2354 /* clti_u.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2363 /* clti_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2372 /* clti_u.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2381 /* clti_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 2390 /* clz */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 2390 /* clz */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6, 2390 /* clz */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 2390 /* clz */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2398 /* cmp.af.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2398 /* cmp.af.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2398 /* cmp.af.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2398 /* cmp.af.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2407 /* cmp.af.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2407 /* cmp.af.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2416 /* cmp.eq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2416 /* cmp.eq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2416 /* cmp.eq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2416 /* cmp.eq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 2425 /* cmp.eq.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 2425 /* cmp.eq.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2435 /* cmp.eq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2435 /* cmp.eq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2444 /* cmp.le.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2444 /* cmp.le.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2444 /* cmp.le.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2444 /* cmp.le.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 2453 /* cmp.le.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 2453 /* cmp.le.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2463 /* cmp.le.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2463 /* cmp.le.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2472 /* cmp.lt.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2472 /* cmp.lt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2472 /* cmp.lt.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2472 /* cmp.lt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 2481 /* cmp.lt.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 2481 /* cmp.lt.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2491 /* cmp.lt.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2491 /* cmp.lt.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2500 /* cmp.saf.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2500 /* cmp.saf.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2500 /* cmp.saf.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2500 /* cmp.saf.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2510 /* cmp.saf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2510 /* cmp.saf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2520 /* cmp.seq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2520 /* cmp.seq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2520 /* cmp.seq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2520 /* cmp.seq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2530 /* cmp.seq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2530 /* cmp.seq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2540 /* cmp.sle.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2540 /* cmp.sle.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2540 /* cmp.sle.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2540 /* cmp.sle.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2550 /* cmp.sle.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2550 /* cmp.sle.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2560 /* cmp.slt.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2560 /* cmp.slt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2560 /* cmp.slt.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2560 /* cmp.slt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2570 /* cmp.slt.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2570 /* cmp.slt.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2580 /* cmp.sueq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2580 /* cmp.sueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2580 /* cmp.sueq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2580 /* cmp.sueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2591 /* cmp.sueq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2591 /* cmp.sueq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2602 /* cmp.sule.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2602 /* cmp.sule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2602 /* cmp.sule.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2602 /* cmp.sule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2613 /* cmp.sule.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2613 /* cmp.sule.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2624 /* cmp.sult.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2624 /* cmp.sult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2624 /* cmp.sult.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2624 /* cmp.sult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2635 /* cmp.sult.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2635 /* cmp.sult.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2646 /* cmp.sun.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2646 /* cmp.sun.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2646 /* cmp.sun.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2646 /* cmp.sun.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2656 /* cmp.sun.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2656 /* cmp.sun.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2666 /* cmp.ueq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2666 /* cmp.ueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2666 /* cmp.ueq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2666 /* cmp.ueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2676 /* cmp.ueq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2676 /* cmp.ueq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2686 /* cmp.ule.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2686 /* cmp.ule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2686 /* cmp.ule.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2686 /* cmp.ule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2696 /* cmp.ule.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2696 /* cmp.ule.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2706 /* cmp.ult.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2706 /* cmp.ult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2706 /* cmp.ult.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2706 /* cmp.ult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2716 /* cmp.ult.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2716 /* cmp.ult.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2726 /* cmp.un.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2726 /* cmp.un.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2726 /* cmp.un.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2726 /* cmp.un.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2735 /* cmp.un.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2735 /* cmp.un.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 2744 /* cmpgdu.eq.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 2744 /* cmpgdu.eq.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 2757 /* cmpgdu.le.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 2757 /* cmpgdu.le.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 2770 /* cmpgdu.lt.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 2770 /* cmpgdu.lt.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 2783 /* cmpgu.eq.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 2783 /* cmpgu.eq.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 2795 /* cmpgu.le.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 2795 /* cmpgu.le.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 2807 /* cmpgu.lt.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 2807 /* cmpgu.lt.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 2824 /* cmpu.eq.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 2824 /* cmpu.eq.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 2835 /* cmpu.le.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 2835 /* cmpu.le.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 2846 /* cmpu.lt.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 2846 /* cmpu.lt.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2857 /* copy_s.b */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2857 /* copy_s.b */, MCK_MSA128AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 2866 /* copy_s.d */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 2866 /* copy_s.d */, MCK_MSA128AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2875 /* copy_s.h */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2875 /* copy_s.h */, MCK_MSA128AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2884 /* copy_s.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2884 /* copy_s.w */, MCK_MSA128AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2893 /* copy_u.b */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2893 /* copy_u.b */, MCK_MSA128AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2902 /* copy_u.h */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2902 /* copy_u.h */, MCK_MSA128AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 2911 /* copy_u.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 2911 /* copy_u.w */, MCK_MSA128AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, 2920 /* crc32b */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, 2927 /* crc32cb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips64r6|Feature_HasCRC|Feature_NotInMicroMips, 2935 /* crc32cd */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, 2943 /* crc32ch */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, 2951 /* crc32cw */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips64r6|Feature_HasCRC|Feature_NotInMicroMips, 2959 /* crc32d */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, 2966 /* crc32h */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, 2973 /* crc32w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2980 /* ctc1 */, MCK_CCRAsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2980 /* ctc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 2980 /* ctc1 */, MCK_CCRAsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 2980 /* ctc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 2985 /* ctc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips, 2985 /* ctc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2990 /* ctcmsa */, MCK_GPR32AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 2990 /* ctcmsa */, MCK_MSACtrlAsmReg, 1 /* 0 */ },
  { Feature_HasMT, 2997 /* cttc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_HasMT, 2997 /* cttc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3003 /* cvt.d.l */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3003 /* cvt.d.l */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3011 /* cvt.d.s */, MCK_AFGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3011 /* cvt.d.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3011 /* cvt.d.s */, MCK_AFGR64AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3011 /* cvt.d.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3011 /* cvt.d.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3011 /* cvt.d.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3011 /* cvt.d.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3011 /* cvt.d.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3019 /* cvt.d.w */, MCK_AFGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3019 /* cvt.d.w */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3019 /* cvt.d.w */, MCK_AFGR64AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3019 /* cvt.d.w */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3019 /* cvt.d.w */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3019 /* cvt.d.w */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3019 /* cvt.d.w */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3019 /* cvt.d.w */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3027 /* cvt.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3027 /* cvt.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3027 /* cvt.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3035 /* cvt.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3035 /* cvt.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3035 /* cvt.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3035 /* cvt.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3035 /* cvt.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3035 /* cvt.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3043 /* cvt.s.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3043 /* cvt.s.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3043 /* cvt.s.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3043 /* cvt.s.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3043 /* cvt.s.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3043 /* cvt.s.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3043 /* cvt.s.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3043 /* cvt.s.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3051 /* cvt.s.l */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3051 /* cvt.s.l */, MCK_FGR64AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3051 /* cvt.s.l */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3051 /* cvt.s.l */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3059 /* cvt.s.w */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3059 /* cvt.s.w */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 3059 /* cvt.s.w */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3067 /* cvt.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3067 /* cvt.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3067 /* cvt.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3067 /* cvt.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3067 /* cvt.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3067 /* cvt.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3067 /* cvt.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3067 /* cvt.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3075 /* cvt.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3075 /* cvt.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 3075 /* cvt.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3083 /* dadd */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3083 /* dadd */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3083 /* dadd */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3083 /* dadd */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3088 /* daddi */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3088 /* daddi */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3094 /* daddiu */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3094 /* daddiu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3101 /* daddu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3101 /* daddu */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3101 /* daddu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3101 /* daddu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3107 /* dahi */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3112 /* dalign */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3119 /* dati */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3124 /* daui */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3129 /* dbitswap */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64|Feature_NotMips64r6|Feature_NotInMicroMips, 3138 /* dclo */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3138 /* dclo */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64|Feature_NotMips64r6|Feature_NotInMicroMips, 3143 /* dclz */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3143 /* dclz */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3148 /* ddiv */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3148 /* ddiv */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3148 /* ddiv */, MCK_GPR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3148 /* ddiv */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3148 /* ddiv */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3148 /* ddiv */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3153 /* ddivu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3153 /* ddivu */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3153 /* ddivu */, MCK_GPR64AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3153 /* ddivu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3153 /* ddivu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3153 /* ddivu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3165 /* dext */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3165 /* dext */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3165 /* dext */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3170 /* dextm */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3176 /* dextu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 3182 /* di */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 3182 /* di */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 3182 /* di */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3185 /* dins */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3185 /* dins */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3185 /* dins */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3190 /* dinsm */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3196 /* dinsu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6, 3202 /* div */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3202 /* div */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3202 /* div */, MCK_GPR32AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3202 /* div */, MCK_GPR32NonZeroAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3202 /* div */, MCK_GPR32AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3202 /* div */, MCK_GPR32ZeroAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3202 /* div */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 3202 /* div */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 3202 /* div */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 3202 /* div */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3202 /* div */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3202 /* div */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3202 /* div */, MCK_GPR32NonZeroAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3206 /* div.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3206 /* div.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3206 /* div.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3206 /* div.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3212 /* div.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3212 /* div.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 3212 /* div.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 3218 /* div_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 3226 /* div_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 3234 /* div_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 3242 /* div_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 3250 /* div_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 3258 /* div_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 3266 /* div_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 3274 /* div_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6, 3282 /* divu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3282 /* divu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3282 /* divu */, MCK_GPR32AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3282 /* divu */, MCK_GPR32NonZeroAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3282 /* divu */, MCK_GPR32AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3282 /* divu */, MCK_GPR32ZeroAsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3282 /* divu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 3282 /* divu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3282 /* divu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 3282 /* divu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 3282 /* divu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3282 /* divu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { 0, 3287 /* dla */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { 0, 3287 /* dla */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { 0, 3287 /* dla */, MCK_Mem, 2 /* 1 */ },
  { 0, 3291 /* dli */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 3295 /* dlsa */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3295 /* dlsa */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_NotInMicroMips, 3300 /* dmfc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_NotInMicroMips, 3300 /* dmfc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasMips64, 3300 /* dmfc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_HasMips64, 3300 /* dmfc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3306 /* dmfc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3306 /* dmfc1 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { 0, 3312 /* dmfc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
  { 0, 3312 /* dmfc2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasCnMips, 3312 /* dmfc2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasMips64, 3312 /* dmfc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
  { Feature_HasMips64, 3312 /* dmfc2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt|Feature_NotInMicroMips, 3318 /* dmfgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt|Feature_NotInMicroMips, 3318 /* dmfgc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt, 3318 /* dmfgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt, 3318 /* dmfgc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3325 /* dmod */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3330 /* dmodu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 3336 /* dmt */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_NotInMicroMips, 3340 /* dmtc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_NotInMicroMips, 3340 /* dmtc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasMips64, 3340 /* dmtc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_HasMips64, 3340 /* dmtc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3346 /* dmtc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3346 /* dmtc1 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { 0, 3352 /* dmtc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
  { 0, 3352 /* dmtc2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasCnMips, 3352 /* dmtc2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasMips64, 3352 /* dmtc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
  { Feature_HasMips64, 3352 /* dmtc2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt|Feature_NotInMicroMips, 3358 /* dmtgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt|Feature_NotInMicroMips, 3358 /* dmtgc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt, 3358 /* dmtgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt, 3358 /* dmtgc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3365 /* dmuh */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3370 /* dmuhu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasCnMips, 3376 /* dmul */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasMips3|Feature_NotMips64r6|Feature_NotCnMips, 3376 /* dmul */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3376 /* dmul */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasCnMips, 3376 /* dmul */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3376 /* dmul */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3381 /* dmulo */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3387 /* dmulou */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3394 /* dmult */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3400 /* dmultu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3407 /* dmulu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3413 /* dneg */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3413 /* dneg */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3418 /* dnegu */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3418 /* dnegu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 3424 /* dotp_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 3433 /* dotp_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 3442 /* dotp_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 3451 /* dotp_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 3460 /* dotp_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 3469 /* dotp_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 3478 /* dpa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 3478 /* dpa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSPR2, 3478 /* dpa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSPR2, 3478 /* dpa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 3487 /* dpadd_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 3497 /* dpadd_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 3507 /* dpadd_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 3517 /* dpadd_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 3527 /* dpadd_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 3537 /* dpadd_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3547 /* dpaq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3547 /* dpaq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSP, 3547 /* dpaq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 3547 /* dpaq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3559 /* dpaq_sa.l.w */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3559 /* dpaq_sa.l.w */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSP, 3559 /* dpaq_sa.l.w */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 3559 /* dpaq_sa.l.w */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 3571 /* dpaqx_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 3571 /* dpaqx_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSPR2, 3571 /* dpaqx_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSPR2, 3571 /* dpaqx_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 3584 /* dpaqx_sa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 3584 /* dpaqx_sa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSPR2, 3584 /* dpaqx_sa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSPR2, 3584 /* dpaqx_sa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3598 /* dpau.h.qbl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3598 /* dpau.h.qbl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSP, 3598 /* dpau.h.qbl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 3598 /* dpau.h.qbl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3609 /* dpau.h.qbr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3609 /* dpau.h.qbr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSP, 3609 /* dpau.h.qbr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 3609 /* dpau.h.qbr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 3620 /* dpax.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 3620 /* dpax.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSPR2, 3620 /* dpax.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSPR2, 3620 /* dpax.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasCnMips, 3630 /* dpop */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasCnMips, 3630 /* dpop */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 3635 /* dps.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 3635 /* dps.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSPR2, 3635 /* dps.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSPR2, 3635 /* dps.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3644 /* dpsq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3644 /* dpsq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSP, 3644 /* dpsq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 3644 /* dpsq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3656 /* dpsq_sa.l.w */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3656 /* dpsq_sa.l.w */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSP, 3656 /* dpsq_sa.l.w */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 3656 /* dpsq_sa.l.w */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 3668 /* dpsqx_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 3668 /* dpsqx_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSPR2, 3668 /* dpsqx_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSPR2, 3668 /* dpsqx_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 3681 /* dpsqx_sa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 3681 /* dpsqx_sa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSPR2, 3681 /* dpsqx_sa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSPR2, 3681 /* dpsqx_sa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3695 /* dpsu.h.qbl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3695 /* dpsu.h.qbl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSP, 3695 /* dpsu.h.qbl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 3695 /* dpsu.h.qbl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3706 /* dpsu.h.qbr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3706 /* dpsu.h.qbr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSP, 3706 /* dpsu.h.qbr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 3706 /* dpsu.h.qbr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 3717 /* dpsub_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 3727 /* dpsub_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 3737 /* dpsub_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 3747 /* dpsub_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 3757 /* dpsub_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 3767 /* dpsub_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 3777 /* dpsx.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 3777 /* dpsx.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSPR2, 3777 /* dpsx.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSPR2, 3777 /* dpsx.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3787 /* drem */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3787 /* drem */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3787 /* drem */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3787 /* drem */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3792 /* dremu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3792 /* dremu */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3792 /* dremu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3792 /* dremu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64, 3798 /* drol */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64, 3798 /* drol */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips64, 3798 /* drol */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips64, 3798 /* drol */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64, 3803 /* dror */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64, 3803 /* dror */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips64, 3803 /* dror */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips64, 3803 /* dror */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3808 /* drotr */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3808 /* drotr */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3814 /* drotr32 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3814 /* drotr32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3822 /* drotrv */, MCK_GPR32AsmReg, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3822 /* drotrv */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3829 /* dsbh */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3834 /* dshd */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3839 /* dsll */, MCK_GPR32AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3839 /* dsll */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3839 /* dsll */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3839 /* dsll */, MCK_GPR32AsmReg, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3839 /* dsll */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3839 /* dsll */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3844 /* dsll32 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3844 /* dsll32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3851 /* dsllv */, MCK_GPR32AsmReg, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3851 /* dsllv */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3857 /* dsra */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3, 3857 /* dsra */, MCK_GPR32AsmReg, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips3, 3857 /* dsra */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3857 /* dsra */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3862 /* dsra32 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3862 /* dsra32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3869 /* dsrav */, MCK_GPR32AsmReg, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3869 /* dsrav */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3875 /* dsrl */, MCK_GPR32AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3875 /* dsrl */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3875 /* dsrl */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3875 /* dsrl */, MCK_GPR32AsmReg, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3875 /* dsrl */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3875 /* dsrl */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3880 /* dsrl32 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3880 /* dsrl32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3887 /* dsrlv */, MCK_GPR32AsmReg, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3887 /* dsrlv */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3893 /* dsub */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3893 /* dsub */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3893 /* dsub */, MCK_InvNum, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3893 /* dsub */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3893 /* dsub */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3893 /* dsub */, MCK_InvNum, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3898 /* dsubi */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3898 /* dsubi */, MCK_InvNum, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3898 /* dsubi */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3898 /* dsubi */, MCK_InvNum, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3904 /* dsubu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3904 /* dsubu */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3904 /* dsubu */, MCK_InvNum, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3904 /* dsubu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3904 /* dsubu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3904 /* dsubu */, MCK_InvNum, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6, 3910 /* dvp */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 3910 /* dvp */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 3914 /* dvpe */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 3923 /* ei */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 3923 /* ei */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 3923 /* ei */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 3926 /* emt */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6, 3942 /* evp */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 3942 /* evp */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 3946 /* evpe */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 3951 /* ext */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 3951 /* ext */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 3951 /* ext */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3955 /* extp */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3955 /* extp */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 3955 /* extp */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_HasDSP, 3955 /* extp */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3960 /* extpdp */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3960 /* extpdp */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 3960 /* extpdp */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_HasDSP, 3960 /* extpdp */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3967 /* extpdpv */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3967 /* extpdpv */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
  { Feature_HasDSP, 3967 /* extpdpv */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_HasDSP, 3967 /* extpdpv */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3975 /* extpv */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3975 /* extpv */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
  { Feature_HasDSP, 3975 /* extpv */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_HasDSP, 3975 /* extpv */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3981 /* extr.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3981 /* extr.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 3981 /* extr.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_HasDSP, 3981 /* extr.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3988 /* extr_r.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3988 /* extr_r.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 3988 /* extr_r.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_HasDSP, 3988 /* extr_r.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3997 /* extr_rs.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 3997 /* extr_rs.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 3997 /* extr_rs.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_HasDSP, 3997 /* extr_rs.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 4007 /* extr_s.h */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 4007 /* extr_s.h */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 4007 /* extr_s.h */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_HasDSP, 4007 /* extr_s.h */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 4016 /* extrv.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 4016 /* extrv.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
  { Feature_HasDSP, 4016 /* extrv.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_HasDSP, 4016 /* extrv.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 4024 /* extrv_r.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 4024 /* extrv_r.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
  { Feature_HasDSP, 4024 /* extrv_r.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_HasDSP, 4024 /* extrv_r.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 4034 /* extrv_rs.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 4034 /* extrv_rs.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
  { Feature_HasDSP, 4034 /* extrv_rs.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_HasDSP, 4034 /* extrv_rs.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 4045 /* extrv_s.h */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 4045 /* extrv_s.h */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
  { Feature_HasDSP, 4045 /* extrv_s.h */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_HasDSP, 4045 /* extrv_s.h */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
  { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 4055 /* exts */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasMips64|Feature_HasCnMips, 4055 /* exts */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 4055 /* exts */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasMips64|Feature_HasCnMips, 4055 /* exts */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 4060 /* exts32 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 4060 /* exts32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4067 /* fadd.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4074 /* fadd.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4081 /* fcaf.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4088 /* fcaf.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4095 /* fceq.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4102 /* fceq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4109 /* fclass.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4118 /* fclass.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4127 /* fcle.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4134 /* fcle.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4141 /* fclt.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4148 /* fclt.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4155 /* fcne.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4162 /* fcne.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4169 /* fcor.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4176 /* fcor.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4183 /* fcueq.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4191 /* fcueq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4199 /* fcule.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4207 /* fcule.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4215 /* fcult.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4223 /* fcult.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4231 /* fcun.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4238 /* fcun.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4245 /* fcune.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4253 /* fcune.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4261 /* fdiv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4268 /* fdiv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4275 /* fexdo.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4283 /* fexdo.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4291 /* fexp2.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4299 /* fexp2.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4307 /* fexupl.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4316 /* fexupl.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4325 /* fexupr.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4334 /* fexupr.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4343 /* ffint_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4353 /* ffint_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4363 /* ffint_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4373 /* ffint_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4383 /* ffql.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4390 /* ffql.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4397 /* ffqr.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4404 /* ffqr.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4411 /* fill.b */, MCK_GPR32AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4411 /* fill.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 4418 /* fill.d */, MCK_GPR64AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 4418 /* fill.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4425 /* fill.h */, MCK_GPR32AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4425 /* fill.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4432 /* fill.w */, MCK_GPR32AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4432 /* fill.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4439 /* flog2.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4447 /* flog2.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4455 /* floor.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 4455 /* floor.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4465 /* floor.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4465 /* floor.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 4465 /* floor.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 4465 /* floor.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4475 /* floor.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4475 /* floor.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 4475 /* floor.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 4475 /* floor.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 4475 /* floor.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 4475 /* floor.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4475 /* floor.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4475 /* floor.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4485 /* floor.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 4485 /* floor.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 4485 /* floor.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4495 /* fmadd.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4503 /* fmadd.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4511 /* fmax.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4518 /* fmax.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4525 /* fmax_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4534 /* fmax_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4543 /* fmin.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4550 /* fmin.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4557 /* fmin_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4566 /* fmin_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4575 /* fmsub.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4583 /* fmsub.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4591 /* fmul.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4598 /* fmul.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 4605 /* fork */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4610 /* frcp.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4617 /* frcp.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4624 /* frint.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4632 /* frint.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4640 /* frsqrt.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4649 /* frsqrt.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4658 /* fsaf.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4665 /* fsaf.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4672 /* fseq.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4679 /* fseq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4686 /* fsle.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4693 /* fsle.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4700 /* fslt.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4707 /* fslt.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4714 /* fsne.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4721 /* fsne.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4728 /* fsor.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4735 /* fsor.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4742 /* fsqrt.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4750 /* fsqrt.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4758 /* fsub.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4765 /* fsub.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4772 /* fsueq.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4780 /* fsueq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4788 /* fsule.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4796 /* fsule.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4804 /* fsult.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4812 /* fsult.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4820 /* fsun.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4827 /* fsun.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4834 /* fsune.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4842 /* fsune.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4850 /* ftint_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4860 /* ftint_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4870 /* ftint_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4880 /* ftint_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4890 /* ftq.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4896 /* ftq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4902 /* ftrunc_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4913 /* ftrunc_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4924 /* ftrunc_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4935 /* ftrunc_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasGINV|Feature_NotInMicroMips, 4946 /* ginvi */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_HasGINV, 4946 /* ginvi */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasGINV|Feature_NotInMicroMips, 4952 /* ginvt */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_HasGINV, 4952 /* ginvt */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4958 /* hadd_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4967 /* hadd_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4976 /* hadd_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4985 /* hadd_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 4994 /* hadd_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5003 /* hadd_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5012 /* hsub_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5021 /* hsub_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5030 /* hsub_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5039 /* hsub_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5048 /* hsub_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5057 /* hsub_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5074 /* ilvev.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5082 /* ilvev.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5090 /* ilvev.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5098 /* ilvev.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5106 /* ilvl.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5113 /* ilvl.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5120 /* ilvl.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5127 /* ilvl.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5134 /* ilvod.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5142 /* ilvod.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5150 /* ilvod.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5158 /* ilvod.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5166 /* ilvr.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5173 /* ilvr.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5180 /* ilvr.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5187 /* ilvr.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 5194 /* ins */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 5194 /* ins */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5194 /* ins */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5198 /* insert.b */, MCK_GPR32AsmReg, 16 /* 4 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5198 /* insert.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 5207 /* insert.d */, MCK_GPR64AsmReg, 16 /* 4 */ },
  { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 5207 /* insert.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5216 /* insert.h */, MCK_GPR32AsmReg, 16 /* 4 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5216 /* insert.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5225 /* insert.w */, MCK_GPR32AsmReg, 16 /* 4 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5225 /* insert.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 5234 /* insv */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 5234 /* insv */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5239 /* insve.b */, MCK_MSA128AsmReg, 17 /* 0, 4 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5247 /* insve.d */, MCK_MSA128AsmReg, 17 /* 0, 4 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5255 /* insve.h */, MCK_MSA128AsmReg, 17 /* 0, 4 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5263 /* insve.w */, MCK_MSA128AsmReg, 17 /* 0, 4 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 5271 /* j */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 5271 /* j */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 5271 /* j */, MCK_JumpTarget, 1 /* 0 */ },
  { 0, 5273 /* jal */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 5273 /* jal */, MCK_JumpTarget, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5273 /* jal */, MCK_JumpTarget, 1 /* 0 */ },
  { 0, 5273 /* jal */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 5277 /* jalr */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5277 /* jalr */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_NotInMicroMips, 5277 /* jalr */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips|Feature_NoIndirectJumpGuards, 5277 /* jalr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 5277 /* jalr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_NotInMips16Mode, 5277 /* jalr */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32|Feature_NotInMicroMips, 5282 /* jalr.hb */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips64|Feature_NotInMicroMips, 5282 /* jalr.hb */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32, 5282 /* jalr.hb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 5282 /* jalr.hb */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 5290 /* jalrc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5290 /* jalrc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips64r6, 5290 /* jalrc */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5290 /* jalrc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5296 /* jalrc.hb */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5296 /* jalrc.hb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 5305 /* jalrs */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 5311 /* jalrs16 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5324 /* jalx */, MCK_JumpTarget, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 5324 /* jalx */, MCK_JumpTarget, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6, 5329 /* jialc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6, 5329 /* jialc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5329 /* jialc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5329 /* jialc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 5329 /* jialc */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 5329 /* jialc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6, 5335 /* jic */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6, 5335 /* jic */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5335 /* jic */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5335 /* jic */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 5335 /* jic */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 5335 /* jic */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5339 /* jr */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 5339 /* jr */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 5339 /* jr */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_NotInMips16Mode|Feature_IsPTR64bit|Feature_NotInMicroMips, 5339 /* jr */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips64r6, 5339 /* jr */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6, 5342 /* jr.hb */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6, 5342 /* jr.hb */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5342 /* jr.hb */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6, 5342 /* jr.hb */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 5348 /* jr16 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6, 5363 /* jrc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 5363 /* jrc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips64r6, 5363 /* jrc */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5367 /* jrc16 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 5384 /* l.d */, MCK_AFGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 5384 /* l.d */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 5384 /* l.d */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 5384 /* l.d */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, 5388 /* l.s */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, 5388 /* l.s */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { 0, 5392 /* la */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { 0, 5392 /* la */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { 0, 5392 /* la */, MCK_Mem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6, 5395 /* lapc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5395 /* lapc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5400 /* lb */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5400 /* lb */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_InMicroMips, 5400 /* lb */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 5400 /* lb */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 5400 /* lb */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 5400 /* lb */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5403 /* lbe */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5403 /* lbe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasEVA, 5403 /* lbe */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasEVA, 5403 /* lbe */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5407 /* lbu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5407 /* lbu */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_InMicroMips, 5407 /* lbu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 5407 /* lbu */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 5407 /* lbu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 5407 /* lbu */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
  { Feature_InMicroMips, 5411 /* lbu16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 5411 /* lbu16 */, MCK_MicroMipsMem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5417 /* lbue */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5417 /* lbue */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasEVA, 5417 /* lbue */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasEVA, 5417 /* lbue */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 5422 /* lbux */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
  { Feature_HasDSP, 5422 /* lbux */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
  { Feature_HasStdEnc|Feature_NotMips3, 5427 /* ld */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips3, 5427 /* ld */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 5427 /* ld */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 5427 /* ld */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5430 /* ld.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5430 /* ld.b */, MCK_MemOffsetSimm10, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5435 /* ld.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5435 /* ld.d */, MCK_MemOffsetSimm10_3, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5440 /* ld.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5440 /* ld.h */, MCK_MemOffsetSimm10_1, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5445 /* ld.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5445 /* ld.w */, MCK_MemOffsetSimm10_2, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5450 /* ldc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5450 /* ldc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 5450 /* ldc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 5450 /* ldc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5450 /* ldc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5450 /* ldc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5450 /* ldc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5450 /* ldc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 5455 /* ldc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 5455 /* ldc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5455 /* ldc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5455 /* ldc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5455 /* ldc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5455 /* ldc2 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotCnMips|Feature_NotInMicroMips, 5460 /* ldc3 */, MCK_COP3AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotCnMips|Feature_NotInMicroMips, 5460 /* ldc3 */, MCK_Mem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5465 /* ldi.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5471 /* ldi.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5477 /* ldi.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5483 /* ldi.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 5489 /* ldl */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 5489 /* ldl */, MCK_Mem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r6, 5493 /* ldpc */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips64r6, 5493 /* ldpc */, MCK_JumpTarget, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 5498 /* ldr */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 5498 /* ldr */, MCK_Mem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5502 /* ldxc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5502 /* ldxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5502 /* ldxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5502 /* ldxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 5508 /* lh */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 5508 /* lh */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
  { Feature_InMicroMips, 5508 /* lh */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 5508 /* lh */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5511 /* lhe */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5511 /* lhe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasEVA, 5511 /* lhe */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasEVA, 5511 /* lhe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 5515 /* lhu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 5515 /* lhu */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
  { Feature_InMicroMips, 5515 /* lhu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 5515 /* lhu */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
  { Feature_InMicroMips, 5519 /* lhu16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 5519 /* lhu16 */, MCK_MicroMipsMem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5525 /* lhue */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5525 /* lhue */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasEVA, 5525 /* lhue */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasEVA, 5525 /* lhue */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 5530 /* lhx */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
  { Feature_HasDSP, 5530 /* lhx */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
  { 0, 5534 /* li */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { 0, 5537 /* li.d */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_NotFP64bit|Feature_IsNotSoftFloat, 5537 /* li.d */, MCK_StrictlyAFGR64AsmReg, 1 /* 0 */ },
  { Feature_IsFP64bit|Feature_IsNotSoftFloat, 5537 /* li.d */, MCK_StrictlyFGR64AsmReg, 1 /* 0 */ },
  { 0, 5542 /* li.s */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_IsNotSoftFloat, 5542 /* li.s */, MCK_StrictlyFGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 5547 /* li16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5547 /* li16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips64r6|Feature_NotInMicroMips, 5552 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips64r6|Feature_NotInMicroMips, 5552 /* ll */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 5552 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 5552 /* ll */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5552 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5552 /* ll */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5552 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5552 /* ll */, MCK_Mem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5552 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5552 /* ll */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 5552 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 5552 /* ll */, MCK_Mem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5555 /* lld */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5555 /* lld */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 5555 /* lld */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 5555 /* lld */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5559 /* lle */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5559 /* lle */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasEVA, 5559 /* lle */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasEVA, 5559 /* lle */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5563 /* lsa */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5563 /* lsa */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6, 5563 /* lsa */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5567 /* lui */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 5567 /* lui */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 5567 /* lui */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5571 /* luxc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5571 /* luxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5571 /* luxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5571 /* luxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 5571 /* luxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 5571 /* luxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
  { Feature_InMicroMips, 5577 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 5577 /* lw */, MCK_MicroMipsMemSP, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 5577 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 5577 /* lw */, MCK_Mem, 2 /* 1 */ },
  { Feature_NotInMips16Mode|Feature_HasDSP, 5577 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_NotInMips16Mode|Feature_HasDSP, 5577 /* lw */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 5577 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 5577 /* lw */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5577 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5577 /* lw */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips, 5577 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 5577 /* lw */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips, 5577 /* lw */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 5577 /* lw */, MCK_MicroMipsMemGP, 2 /* 1 */ },
  { Feature_InMicroMips, 5580 /* lw16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 5580 /* lw16 */, MCK_MicroMipsMem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5585 /* lwc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5585 /* lwc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 5585 /* lwc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 5585 /* lwc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 5590 /* lwc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 5590 /* lwc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5590 /* lwc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5590 /* lwc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5590 /* lwc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5590 /* lwc2 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotCnMips|Feature_NotInMicroMips, 5595 /* lwc3 */, MCK_COP3AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotCnMips|Feature_NotInMicroMips, 5595 /* lwc3 */, MCK_Mem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5600 /* lwe */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5600 /* lwe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasEVA, 5600 /* lwe */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasEVA, 5600 /* lwe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5604 /* lwl */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5604 /* lwl */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 5604 /* lwl */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 5604 /* lwl */, MCK_Mem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 5608 /* lwle */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 5608 /* lwle */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 5608 /* lwle */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 5608 /* lwle */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_InMicroMips, 5613 /* lwm */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips, 5613 /* lwm */, MCK_RegList, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 5617 /* lwm16 */, MCK_MemOffsetUimm4, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 5617 /* lwm16 */, MCK_RegList16, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5617 /* lwm16 */, MCK_MemOffsetUimm4, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5617 /* lwm16 */, MCK_RegList16, 1 /* 0 */ },
  { Feature_InMicroMips, 5623 /* lwm32 */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips, 5623 /* lwm32 */, MCK_RegList, 1 /* 0 */ },
  { Feature_InMicroMips, 5629 /* lwp */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 5629 /* lwp */, MCK_MemOffsetSimm12, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6, 5633 /* lwpc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 5633 /* lwpc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5638 /* lwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5638 /* lwr */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 5638 /* lwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 5638 /* lwr */, MCK_Mem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 5642 /* lwre */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 5642 /* lwre */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 5642 /* lwre */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 5642 /* lwre */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 5647 /* lwu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 5647 /* lwu */, MCK_MemOffsetSimm12, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 5647 /* lwu */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 5647 /* lwu */, MCK_Mem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 5651 /* lwupc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 5657 /* lwx */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
  { Feature_HasDSP, 5657 /* lwx */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
  { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5661 /* lwxc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5661 /* lwxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 5661 /* lwxc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 5661 /* lwxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
  { Feature_InMicroMips, 5667 /* lwxs */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
  { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5672 /* madd */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 5672 /* madd */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 5672 /* madd */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 5672 /* madd */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSP, 5672 /* madd */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 5672 /* madd */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, 5677 /* madd.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 5677 /* madd.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, 5677 /* madd.d */, MCK_FGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
  { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, 5684 /* madd.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 5684 /* madd.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5691 /* madd_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5700 /* madd_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5709 /* maddf.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5709 /* maddf.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5717 /* maddf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5717 /* maddf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5725 /* maddr_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5735 /* maddr_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5745 /* maddu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 5745 /* maddu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 5745 /* maddu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 5745 /* maddu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSP, 5745 /* maddu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 5745 /* maddu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5751 /* maddv.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5759 /* maddv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5767 /* maddv.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5775 /* maddv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 5783 /* maq_s.w.phl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 5783 /* maq_s.w.phl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSP, 5783 /* maq_s.w.phl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 5783 /* maq_s.w.phl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 5795 /* maq_s.w.phr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 5795 /* maq_s.w.phr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSP, 5795 /* maq_s.w.phr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 5795 /* maq_s.w.phr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 5807 /* maq_sa.w.phl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 5807 /* maq_sa.w.phl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSP, 5807 /* maq_sa.w.phl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 5807 /* maq_sa.w.phl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 5820 /* maq_sa.w.phr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 5820 /* maq_sa.w.phr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSP, 5820 /* maq_sa.w.phr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 5820 /* maq_sa.w.phr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5833 /* max.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5833 /* max.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5839 /* max.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5839 /* max.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5845 /* max_a.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5853 /* max_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5861 /* max_a.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5869 /* max_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5877 /* max_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5885 /* max_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5893 /* max_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5901 /* max_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5909 /* max_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5917 /* max_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5925 /* max_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5933 /* max_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5941 /* maxa.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5941 /* maxa.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5948 /* maxa.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5948 /* maxa.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5955 /* maxi_s.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5964 /* maxi_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5973 /* maxi_s.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5982 /* maxi_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 5991 /* maxi_u.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6000 /* maxi_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6009 /* maxi_u.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6018 /* maxi_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 6027 /* mfc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 6027 /* mfc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6027 /* mfc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6027 /* mfc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 6027 /* mfc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 6027 /* mfc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6027 /* mfc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6027 /* mfc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6032 /* mfc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6032 /* mfc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6032 /* mfc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6032 /* mfc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 6032 /* mfc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 6032 /* mfc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6032 /* mfc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6032 /* mfc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6037 /* mfc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6037 /* mfc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 6037 /* mfc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 6037 /* mfc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 6037 /* mfc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 6037 /* mfc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6042 /* mfgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6042 /* mfgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6042 /* mfgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6042 /* mfgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6042 /* mfgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6042 /* mfgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6042 /* mfgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6042 /* mfgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6048 /* mfhc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6048 /* mfhc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6048 /* mfhc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6048 /* mfhc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6054 /* mfhc1 */, MCK_AFGR64AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6054 /* mfhc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6054 /* mfhc1 */, MCK_AFGR64AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6054 /* mfhc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6054 /* mfhc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6054 /* mfhc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6054 /* mfhc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6054 /* mfhc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6060 /* mfhc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6060 /* mfhc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6066 /* mfhgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6066 /* mfhgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6066 /* mfhgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6066 /* mfhgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6066 /* mfhgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6066 /* mfhgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6066 /* mfhgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6066 /* mfhgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6073 /* mfhi */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 6073 /* mfhi */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 6073 /* mfhi */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 6073 /* mfhi */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 6073 /* mfhi */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_HasDSP, 6073 /* mfhi */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 6078 /* mfhi16 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6085 /* mflo */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 6085 /* mflo */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 6085 /* mflo */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 6085 /* mflo */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 6085 /* mflo */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_HasDSP, 6085 /* mflo */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 6090 /* mflo16 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasMT|Feature_NotInMicroMips, 6097 /* mftacx */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasMT, 6097 /* mftacx */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_HasMT, 6097 /* mftacx */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasMT|Feature_NotInMicroMips, 6104 /* mftc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_HasMT|Feature_NotInMicroMips, 6104 /* mftc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasMT, 6104 /* mftc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_HasMT, 6104 /* mftc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasMT, 6110 /* mftc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_HasMT, 6110 /* mftc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasMT, 6116 /* mftdsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasMT, 6123 /* mftgpr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasMT, 6130 /* mfthc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_HasMT, 6130 /* mfthc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasMT|Feature_NotInMicroMips, 6137 /* mfthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasMT, 6137 /* mfthi */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_HasMT, 6137 /* mfthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasMT|Feature_NotInMicroMips, 6143 /* mftlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasMT, 6143 /* mftlo */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_HasMT, 6143 /* mftlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 6149 /* mftr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6154 /* min.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6154 /* min.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6160 /* min.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6160 /* min.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6166 /* min_a.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6174 /* min_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6182 /* min_a.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6190 /* min_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6198 /* min_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6206 /* min_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6214 /* min_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6222 /* min_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6230 /* min_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6238 /* min_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6246 /* min_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6254 /* min_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6262 /* mina.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6262 /* mina.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6269 /* mina.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6269 /* mina.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6276 /* mini_s.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6285 /* mini_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6294 /* mini_s.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6303 /* mini_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6312 /* mini_u.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6321 /* mini_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6330 /* mini_u.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6339 /* mini_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 6348 /* mod */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6348 /* mod */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6352 /* mod_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6360 /* mod_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6368 /* mod_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6376 /* mod_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6384 /* mod_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6392 /* mod_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6400 /* mod_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6408 /* mod_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 6416 /* modsub */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 6416 /* modsub */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 6423 /* modu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6423 /* modu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6428 /* mov.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6428 /* mov.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6428 /* mov.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6428 /* mov.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6434 /* mov.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6434 /* mov.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 6434 /* mov.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 6440 /* move */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 6440 /* move */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 6440 /* move */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_IsGP64bit|Feature_NotInMicroMips, 6440 /* move */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_IsGP64bit|Feature_NotInMicroMips, 6440 /* move */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6445 /* move.v */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6452 /* move16 */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 6459 /* movep */, MCK_GPRMM16AsmRegMoveP, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 6459 /* movep */, MCK_MovePRegPair, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6459 /* movep */, MCK_GPRMM16AsmRegMoveP, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6459 /* movep */, MCK_MovePRegPair, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6465 /* movf */, MCK_FCCAsmReg, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6465 /* movf */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6465 /* movf */, MCK_FCCAsmReg, 4 /* 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6465 /* movf */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6470 /* movf.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6470 /* movf.d */, MCK_FCCAsmReg, 4 /* 2 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6470 /* movf.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6470 /* movf.d */, MCK_FCCAsmReg, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6470 /* movf.d */, MCK_FCCAsmReg, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6470 /* movf.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6477 /* movf.s */, MCK_FCCAsmReg, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6477 /* movf.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6477 /* movf.s */, MCK_FCCAsmReg, 4 /* 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6477 /* movf.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6484 /* movn */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 6484 /* movn */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6489 /* movn.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6489 /* movn.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6489 /* movn.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6489 /* movn.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6489 /* movn.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6489 /* movn.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6496 /* movn.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6496 /* movn.s */, MCK_GPR32AsmReg, 4 /* 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6496 /* movn.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6496 /* movn.s */, MCK_GPR32AsmReg, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6503 /* movt */, MCK_FCCAsmReg, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6503 /* movt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6503 /* movt */, MCK_FCCAsmReg, 4 /* 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6503 /* movt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6508 /* movt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6508 /* movt.d */, MCK_FCCAsmReg, 4 /* 2 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6508 /* movt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6508 /* movt.d */, MCK_FCCAsmReg, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6508 /* movt.d */, MCK_FCCAsmReg, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6508 /* movt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6515 /* movt.s */, MCK_FCCAsmReg, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6515 /* movt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6515 /* movt.s */, MCK_FCCAsmReg, 4 /* 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6515 /* movt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6522 /* movz */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 6522 /* movz */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6527 /* movz.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6527 /* movz.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6527 /* movz.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6527 /* movz.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6527 /* movz.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6527 /* movz.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6534 /* movz.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6534 /* movz.s */, MCK_GPR32AsmReg, 4 /* 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6534 /* movz.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6534 /* movz.s */, MCK_GPR32AsmReg, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6541 /* msub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 6541 /* msub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 6541 /* msub */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 6541 /* msub */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSP, 6541 /* msub */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 6541 /* msub */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, 6546 /* msub.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 6546 /* msub.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, 6546 /* msub.d */, MCK_FGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
  { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, 6553 /* msub.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 6553 /* msub.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6560 /* msub_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6569 /* msub_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6578 /* msubf.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6578 /* msubf.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6586 /* msubf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6586 /* msubf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6594 /* msubr_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6604 /* msubr_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6614 /* msubu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 6614 /* msubu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 6614 /* msubu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 6614 /* msubu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSP, 6614 /* msubu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 6614 /* msubu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6620 /* msubv.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6628 /* msubv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6636 /* msubv.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6644 /* msubv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 6652 /* mtc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 6652 /* mtc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6652 /* mtc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6652 /* mtc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 6652 /* mtc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 6652 /* mtc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6652 /* mtc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6652 /* mtc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6657 /* mtc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6657 /* mtc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6657 /* mtc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6657 /* mtc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 6657 /* mtc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 6657 /* mtc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6657 /* mtc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6657 /* mtc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6662 /* mtc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6662 /* mtc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 6662 /* mtc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 6662 /* mtc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 6662 /* mtc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 6662 /* mtc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6667 /* mtgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6667 /* mtgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6667 /* mtgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6667 /* mtgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6667 /* mtgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6667 /* mtgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6667 /* mtgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6667 /* mtgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6673 /* mthc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6673 /* mthc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6673 /* mthc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6673 /* mthc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6679 /* mthc1 */, MCK_AFGR64AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6679 /* mthc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6679 /* mthc1 */, MCK_AFGR64AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6679 /* mthc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6679 /* mthc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6679 /* mthc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6679 /* mthc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6679 /* mthc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6685 /* mthc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6685 /* mthc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6691 /* mthgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6691 /* mthgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6691 /* mthgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6691 /* mthgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6691 /* mthgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6691 /* mthgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6691 /* mthgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6691 /* mthgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6698 /* mthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 6698 /* mthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 6698 /* mthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 6698 /* mthi */, MCK_HI32DSPAsmReg, 2 /* 1 */ },
  { Feature_HasDSP, 6698 /* mthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 6698 /* mthi */, MCK_HI32DSPAsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 6703 /* mthlip */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 6703 /* mthlip */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 6703 /* mthlip */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_HasDSP, 6703 /* mthlip */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6710 /* mtlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 6710 /* mtlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 6710 /* mtlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 6710 /* mtlo */, MCK_LO32DSPAsmReg, 2 /* 1 */ },
  { Feature_HasDSP, 6710 /* mtlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 6710 /* mtlo */, MCK_LO32DSPAsmReg, 2 /* 1 */ },
  { Feature_HasCnMips, 6715 /* mtm0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasCnMips, 6720 /* mtm1 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasCnMips, 6725 /* mtm2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasCnMips, 6730 /* mtp0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasCnMips, 6735 /* mtp1 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasCnMips, 6740 /* mtp2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasMT|Feature_NotInMicroMips, 6745 /* mttacx */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasMT, 6745 /* mttacx */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_HasMT, 6745 /* mttacx */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasMT|Feature_NotInMicroMips, 6752 /* mttc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_HasMT|Feature_NotInMicroMips, 6752 /* mttc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasMT, 6752 /* mttc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
  { Feature_HasMT, 6752 /* mttc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasMT, 6758 /* mttc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_HasMT, 6758 /* mttc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasMT, 6764 /* mttdsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasMT, 6771 /* mttgpr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasMT, 6778 /* mtthc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_HasMT, 6778 /* mtthc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasMT|Feature_NotInMicroMips, 6785 /* mtthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasMT, 6785 /* mtthi */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_HasMT, 6785 /* mtthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasMT|Feature_NotInMicroMips, 6791 /* mttlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasMT, 6791 /* mttlo */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
  { Feature_HasMT, 6791 /* mttlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 6797 /* mttr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6802 /* muh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 6802 /* muh */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6802 /* muh */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6806 /* muhu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 6806 /* muhu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6806 /* muhu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6811 /* mul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 6811 /* mul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6811 /* mul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6811 /* mul */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 6811 /* mul */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 6811 /* mul */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 6811 /* mul */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 6811 /* mul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6815 /* mul.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6815 /* mul.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6815 /* mul.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6815 /* mul.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 6821 /* mul.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 6821 /* mul.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6828 /* mul.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6828 /* mul.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 6828 /* mul.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6834 /* mul_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6842 /* mul_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 6850 /* mul_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 6850 /* mul_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 6859 /* muleq_s.w.phl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 6859 /* muleq_s.w.phl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 6873 /* muleq_s.w.phr */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 6873 /* muleq_s.w.phr */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 6887 /* muleu_s.ph.qbl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 6887 /* muleu_s.ph.qbl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 6902 /* muleu_s.ph.qbr */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 6902 /* muleu_s.ph.qbr */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 6917 /* mulo */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 6917 /* mulo */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 6922 /* mulou */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 6922 /* mulou */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 6928 /* mulq_rs.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 6928 /* mulq_rs.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 6939 /* mulq_rs.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 6939 /* mulq_rs.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 6949 /* mulq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 6949 /* mulq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 6959 /* mulq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 6959 /* mulq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6968 /* mulr_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 6977 /* mulr_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 6986 /* mulsa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 6986 /* mulsa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSPR2, 6986 /* mulsa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSPR2, 6986 /* mulsa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 6997 /* mulsaq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 6997 /* mulsaq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSP, 6997 /* mulsaq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 6997 /* mulsaq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7011 /* mult */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 7011 /* mult */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7011 /* mult */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7011 /* mult */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSP, 7011 /* mult */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 7011 /* mult */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7016 /* multu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 7016 /* multu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7016 /* multu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7016 /* multu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_HasDSP, 7016 /* multu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 7016 /* multu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7022 /* mulu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 7022 /* mulu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7022 /* mulu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7027 /* mulv.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7034 /* mulv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7041 /* mulv.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7048 /* mulv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 7055 /* neg */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 7055 /* neg */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7055 /* neg */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 7055 /* neg */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 7055 /* neg */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7055 /* neg */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7059 /* neg.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7059 /* neg.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7059 /* neg.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 7059 /* neg.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7065 /* neg.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsNotSoftFloat, 7065 /* neg.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 7065 /* neg.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 7071 /* negu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 7071 /* negu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7071 /* negu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 7071 /* negu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 7071 /* negu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7071 /* negu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7076 /* nloc.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7083 /* nloc.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7090 /* nloc.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7097 /* nloc.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7104 /* nlzc.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7111 /* nlzc.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7118 /* nlzc.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7125 /* nlzc.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, 7132 /* nmadd.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 7132 /* nmadd.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, 7132 /* nmadd.d */, MCK_FGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
  { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, 7140 /* nmadd.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 7140 /* nmadd.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, 7148 /* nmsub.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 7148 /* nmsub.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, 7148 /* nmsub.d */, MCK_FGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
  { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, 7156 /* nmsub.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 7156 /* nmsub.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
  { Feature_IsGP32bit, 7168 /* nor */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_IsGP64bit, 7168 /* nor */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 7168 /* nor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 7168 /* nor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7168 /* nor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_IsGP32bit, 7168 /* nor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_IsGP64bit, 7168 /* nor */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7172 /* nor.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7178 /* nori.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 7185 /* not */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 7185 /* not */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7185 /* not */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 7185 /* not */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 7185 /* not */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7185 /* not */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 7189 /* not16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7189 /* not16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 7195 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 7195 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7195 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7195 /* or */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 7195 /* or */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 7195 /* or */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, 7195 /* or */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 7195 /* or */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 7195 /* or */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7195 /* or */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7195 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 7195 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 7195 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, 7195 /* or */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7198 /* or.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 7203 /* or16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7203 /* or16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7208 /* ori */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 7208 /* ori */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 7208 /* ori */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7208 /* ori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 7208 /* ori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 7208 /* ori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7212 /* ori.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7218 /* packrl.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 7218 /* packrl.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7234 /* pckev.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7242 /* pckev.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7250 /* pckev.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7258 /* pckev.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7266 /* pckod.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7274 /* pckod.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7282 /* pckod.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7290 /* pckod.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7298 /* pcnt.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7305 /* pcnt.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7312 /* pcnt.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7319 /* pcnt.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7326 /* pick.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 7326 /* pick.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7334 /* pick.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 7334 /* pick.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasCnMips, 7342 /* pop */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasCnMips, 7342 /* pop */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7346 /* preceq.w.phl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 7346 /* preceq.w.phl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7359 /* preceq.w.phr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 7359 /* preceq.w.phr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7372 /* precequ.ph.qbl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 7372 /* precequ.ph.qbl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7387 /* precequ.ph.qbla */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 7387 /* precequ.ph.qbla */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7403 /* precequ.ph.qbr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 7403 /* precequ.ph.qbr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7418 /* precequ.ph.qbra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 7418 /* precequ.ph.qbra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7434 /* preceu.ph.qbl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 7434 /* preceu.ph.qbl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7448 /* preceu.ph.qbla */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 7448 /* preceu.ph.qbla */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7463 /* preceu.ph.qbr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 7463 /* preceu.ph.qbr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7477 /* preceu.ph.qbra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 7477 /* preceu.ph.qbra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 7492 /* precr.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 7492 /* precr.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 7504 /* precr_sra.ph.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSPR2, 7504 /* precr_sra.ph.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 7519 /* precr_sra_r.ph.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSPR2, 7519 /* precr_sra_r.ph.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7536 /* precrq.ph.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 7536 /* precrq.ph.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7548 /* precrq.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 7548 /* precrq.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7561 /* precrq_rs.ph.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 7561 /* precrq_rs.ph.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7576 /* precrqu_s.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 7576 /* precrqu_s.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 7592 /* pref */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7592 /* pref */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 7592 /* pref */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7592 /* pref */, MCK_Mem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 7597 /* prefe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasEVA, 7597 /* prefe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 7603 /* prefx */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 7609 /* prepend */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSPR2, 7609 /* prepend */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7617 /* raddu.w.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 7617 /* raddu.w.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7628 /* rddsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 7628 /* rddsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 7634 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 7634 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 7634 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 7634 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7634 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7634 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7634 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7634 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 7634 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 7634 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 7634 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 7634 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7640 /* rdpgpr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7647 /* recip.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7647 /* recip.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7647 /* recip.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 7647 /* recip.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7655 /* recip.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 7655 /* recip.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7663 /* rem */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7663 /* rem */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7663 /* rem */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7663 /* rem */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7667 /* remu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7667 /* remu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7667 /* remu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7667 /* remu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7672 /* repl.ph */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 7672 /* repl.ph */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7680 /* repl.qb */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 7680 /* repl.qb */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7688 /* replv.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 7688 /* replv.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 7697 /* replv.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 7697 /* replv.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7706 /* rint.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7706 /* rint.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7713 /* rint.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7713 /* rint.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { 0, 7720 /* rol */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { 0, 7720 /* rol */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { 0, 7720 /* rol */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { 0, 7720 /* rol */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { 0, 7724 /* ror */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { 0, 7724 /* ror */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { 0, 7724 /* ror */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { 0, 7724 /* ror */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7728 /* rotr */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 7728 /* rotr */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 7728 /* rotr */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7728 /* rotr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 7728 /* rotr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7733 /* rotrv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips, 7733 /* rotrv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7739 /* round.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7739 /* round.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7749 /* round.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7749 /* round.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7749 /* round.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7749 /* round.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7759 /* round.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7759 /* round.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7759 /* round.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7759 /* round.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7759 /* round.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7759 /* round.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7759 /* round.w.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7769 /* round.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7769 /* round.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 7769 /* round.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7779 /* rsqrt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7779 /* rsqrt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7779 /* rsqrt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 7779 /* rsqrt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7787 /* rsqrt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_NotInMips16Mode|Feature_IsNotSoftFloat, 7787 /* rsqrt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 7795 /* s.d */, MCK_AFGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 7795 /* s.d */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 7795 /* s.d */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 7795 /* s.d */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, 7799 /* s.s */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, 7799 /* s.s */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7803 /* sat_s.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7811 /* sat_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7819 /* sat_s.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7827 /* sat_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7835 /* sat_u.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7843 /* sat_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7851 /* sat_u.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 7859 /* sat_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 7867 /* sb */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 7867 /* sb */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7867 /* sb */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7867 /* sb */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips, 7867 /* sb */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 7867 /* sb */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 7870 /* sb16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 7870 /* sb16 */, MCK_MicroMipsMem, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7870 /* sb16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7870 /* sb16 */, MCK_MicroMipsMem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 7875 /* sbe */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 7875 /* sbe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasEVA, 7875 /* sbe */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasEVA, 7875 /* sbe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips64r6|Feature_NotInMicroMips, 7879 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips64r6|Feature_NotInMicroMips, 7879 /* sc */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 7879 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 7879 /* sc */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7879 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7879 /* sc */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7879 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7879 /* sc */, MCK_Mem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7879 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7879 /* sc */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 7879 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 7879 /* sc */, MCK_Mem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6, 7882 /* scd */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6, 7882 /* scd */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7882 /* scd */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7882 /* scd */, MCK_Mem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 7886 /* sce */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 7886 /* sce */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasEVA, 7886 /* sce */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasEVA, 7886 /* sce */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotMips3, 7890 /* sd */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips3, 7890 /* sd */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 7890 /* sd */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 7890 /* sd */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7907 /* sdc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7907 /* sdc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7907 /* sdc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7907 /* sdc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7907 /* sdc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7907 /* sdc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7907 /* sdc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7907 /* sdc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 7912 /* sdc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 7912 /* sdc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7912 /* sdc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7912 /* sdc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7912 /* sdc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7912 /* sdc2 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotCnMips|Feature_NotInMicroMips, 7917 /* sdc3 */, MCK_COP3AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotCnMips|Feature_NotInMicroMips, 7917 /* sdc3 */, MCK_Mem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7922 /* sdl */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7922 /* sdl */, MCK_Mem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7926 /* sdr */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7926 /* sdr */, MCK_Mem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7930 /* sdxc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7930 /* sdxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 7930 /* sdxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 7930 /* sdxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7936 /* seb */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 7936 /* seb */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7936 /* seb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 7936 /* seb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7940 /* seh */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 7940 /* seh */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7940 /* seh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 7940 /* seh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7944 /* sel.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7944 /* sel.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7950 /* sel.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7950 /* sel.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 7956 /* seleqz */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7956 /* seleqz */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips32r6, 7956 /* seleqz */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7963 /* seleqz.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7963 /* seleqz.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7972 /* seleqz.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7972 /* seleqz.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 7981 /* selnez */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7981 /* selnez */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips32r6, 7981 /* selnez */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7988 /* selnez.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7988 /* selnez.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7997 /* selnez.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 7997 /* selnez.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_NotCnMips, 8006 /* seq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_NotCnMips, 8006 /* seq */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasCnMips, 8006 /* seq */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_NotCnMips, 8006 /* seq */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_NotCnMips, 8006 /* seq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasCnMips, 8006 /* seq */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasCnMips, 8010 /* seqi */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasCnMips, 8010 /* seqi */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 8015 /* sgt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 8015 /* sgt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 8015 /* sgt */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips, 8015 /* sgt */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 8019 /* sgtu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 8019 /* sgtu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 8019 /* sgtu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips, 8019 /* sgtu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 8024 /* sh */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 8024 /* sh */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 8024 /* sh */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 8024 /* sh */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips, 8024 /* sh */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 8024 /* sh */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 8027 /* sh16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 8027 /* sh16 */, MCK_MicroMipsMem, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 8027 /* sh16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 8027 /* sh16 */, MCK_MicroMipsMem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 8032 /* she */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 8032 /* she */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasEVA, 8032 /* she */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasEVA, 8032 /* she */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8036 /* shf.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8042 /* shf.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8048 /* shf.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 8054 /* shilo */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 8054 /* shilo */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 8060 /* shilov */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 8060 /* shilov */, MCK_GPR32AsmReg, 2 /* 1 */ },
  { Feature_HasDSP, 8060 /* shilov */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
  { Feature_HasDSP, 8060 /* shilov */, MCK_GPR32AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 8067 /* shll.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 8067 /* shll.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 8075 /* shll.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 8075 /* shll.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 8083 /* shll_s.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 8083 /* shll_s.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 8093 /* shll_s.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 8093 /* shll_s.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 8102 /* shllv.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 8102 /* shllv.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 8111 /* shllv.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 8111 /* shllv.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 8120 /* shllv_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 8120 /* shllv_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 8131 /* shllv_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 8131 /* shllv_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 8141 /* shra.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 8141 /* shra.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 8149 /* shra.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSPR2, 8149 /* shra.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 8157 /* shra_r.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 8157 /* shra_r.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 8167 /* shra_r.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSPR2, 8167 /* shra_r.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 8177 /* shra_r.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 8177 /* shra_r.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 8186 /* shrav.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 8186 /* shrav.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 8195 /* shrav.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 8195 /* shrav.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 8204 /* shrav_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 8204 /* shrav_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 8215 /* shrav_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 8215 /* shrav_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 8226 /* shrav_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 8226 /* shrav_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 8236 /* shrl.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSPR2, 8236 /* shrl.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 8244 /* shrl.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasDSP, 8244 /* shrl.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 8252 /* shrlv.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 8252 /* shrlv.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 8261 /* shrlv.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 8261 /* shrlv.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8270 /* sld.b */, MCK_GPR32AsmReg, 8 /* 3 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8270 /* sld.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8276 /* sld.d */, MCK_GPR32AsmReg, 8 /* 3 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8276 /* sld.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8282 /* sld.h */, MCK_GPR32AsmReg, 8 /* 3 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8282 /* sld.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8288 /* sld.w */, MCK_GPR32AsmReg, 8 /* 3 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8288 /* sld.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8294 /* sldi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8301 /* sldi.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8308 /* sldi.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8315 /* sldi.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_NotInMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 8322 /* sll */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_NotInMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 8322 /* sll */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8326 /* sll.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8332 /* sll.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8338 /* sll.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8344 /* sll.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 8350 /* sll16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 8350 /* sll16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8356 /* slli.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8363 /* slli.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8370 /* slli.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8377 /* slli.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 8384 /* sllv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips, 8384 /* sllv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 8389 /* slt */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 8389 /* slt */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_IsGP64bit, 8389 /* slt */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 8389 /* slt */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips, 8389 /* slt */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 8389 /* slt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 8389 /* slt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_IsGP64bit, 8389 /* slt */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 8393 /* slti */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 8393 /* slti */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 8398 /* sltiu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 8398 /* sltiu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 8404 /* sltu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 8404 /* sltu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_IsGP64bit, 8404 /* sltu */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 8404 /* sltu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips, 8404 /* sltu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 8404 /* sltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 8404 /* sltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_IsGP64bit, 8404 /* sltu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasCnMips, 8409 /* sne */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasCnMips, 8409 /* sne */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasCnMips, 8413 /* snei */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasCnMips, 8413 /* snei */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8418 /* splat.b */, MCK_GPR32AsmReg, 8 /* 3 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8418 /* splat.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8426 /* splat.d */, MCK_GPR32AsmReg, 8 /* 3 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8426 /* splat.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8434 /* splat.h */, MCK_GPR32AsmReg, 8 /* 3 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8434 /* splat.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8442 /* splat.w */, MCK_GPR32AsmReg, 8 /* 3 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8442 /* splat.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8450 /* splati.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8459 /* splati.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8468 /* splati.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8477 /* splati.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8486 /* sqrt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 8486 /* sqrt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8486 /* sqrt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 8486 /* sqrt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8493 /* sqrt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 8493 /* sqrt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_NotInMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_NotInMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8504 /* sra.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8510 /* sra.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8516 /* sra.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8522 /* sra.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8528 /* srai.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8535 /* srai.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8542 /* srai.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8549 /* srai.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8556 /* srar.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8563 /* srar.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8570 /* srar.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8577 /* srar.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8584 /* srari.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8592 /* srari.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8600 /* srari.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8608 /* srari.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 8616 /* srav */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips, 8616 /* srav */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_NotInMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_NotInMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8625 /* srl.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8631 /* srl.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8637 /* srl.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8643 /* srl.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 8649 /* srl16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 8649 /* srl16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8655 /* srli.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8662 /* srli.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8669 /* srli.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8676 /* srli.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8683 /* srlr.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8690 /* srlr.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8697 /* srlr.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8704 /* srlr.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8711 /* srlri.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8719 /* srlri.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8727 /* srlri.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8735 /* srlri.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 8743 /* srlv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips, 8743 /* srlv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8754 /* st.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8754 /* st.b */, MCK_MemOffsetSimm10, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8759 /* st.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8759 /* st.d */, MCK_MemOffsetSimm10_3, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8764 /* st.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8764 /* st.h */, MCK_MemOffsetSimm10_1, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8769 /* st.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8769 /* st.w */, MCK_MemOffsetSimm10_2, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 8774 /* sub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 8774 /* sub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 8774 /* sub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 8774 /* sub */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 8774 /* sub */, MCK_InvNum, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 8774 /* sub */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 8774 /* sub */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 8774 /* sub */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 8774 /* sub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 8774 /* sub */, MCK_InvNum, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8778 /* sub.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 8778 /* sub.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8778 /* sub.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 8778 /* sub.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8784 /* sub.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 8784 /* sub.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 8784 /* sub.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 8790 /* subq.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 8790 /* subq.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 8798 /* subq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 8798 /* subq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 8808 /* subq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 8808 /* subq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 8817 /* subqh.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 8817 /* subqh.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 8826 /* subqh.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 8826 /* subqh.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 8834 /* subqh_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 8834 /* subqh_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 8845 /* subqh_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 8845 /* subqh_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8855 /* subs_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8864 /* subs_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8873 /* subs_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8882 /* subs_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8891 /* subs_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8900 /* subs_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8909 /* subs_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8918 /* subs_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8927 /* subsus_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8938 /* subsus_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8949 /* subsus_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8960 /* subsus_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8971 /* subsuu_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8982 /* subsuu_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 8993 /* subsuu_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 9004 /* subsuu_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 9015 /* subu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 9015 /* subu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 9015 /* subu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { 0, 9015 /* subu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { 0, 9015 /* subu */, MCK_InvNum, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 9015 /* subu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 9015 /* subu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 9015 /* subu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { 0, 9015 /* subu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { 0, 9015 /* subu */, MCK_InvNum, 4 /* 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 9020 /* subu.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 9020 /* subu.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 9028 /* subu.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 9028 /* subu.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 9036 /* subu16 */, MCK_GPRMM16AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 9036 /* subu16 */, MCK_GPRMM16AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 9043 /* subu_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 9043 /* subu_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSP, 9053 /* subu_s.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP, 9053 /* subu_s.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 9063 /* subuh.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 9063 /* subuh.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasDSPR2, 9072 /* subuh_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSPR2, 9072 /* subuh_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 9083 /* subv.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 9090 /* subv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 9097 /* subv.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 9104 /* subv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 9111 /* subvi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 9119 /* subvi.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 9127 /* subvi.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 9135 /* subvi.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9143 /* suxc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9143 /* suxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9143 /* suxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9143 /* suxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 9143 /* suxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 9143 /* suxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 9149 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 9149 /* sw */, MCK_MicroMipsMemSP, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 9149 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 9149 /* sw */, MCK_MicroMipsMemSP, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 9149 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 9149 /* sw */, MCK_Mem, 2 /* 1 */ },
  { Feature_NotInMips16Mode|Feature_HasDSP, 9149 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_NotInMips16Mode|Feature_HasDSP, 9149 /* sw */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasDSP, 9149 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 9149 /* sw */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 9149 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 9149 /* sw */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips, 9149 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 9149 /* sw */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 9152 /* sw16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 9152 /* sw16 */, MCK_MicroMipsMem, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 9152 /* sw16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 9152 /* sw16 */, MCK_MicroMipsMem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9157 /* swc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9157 /* swc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 9157 /* swc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 9157 /* swc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 9162 /* swc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 9162 /* swc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 9162 /* swc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 9162 /* swc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9162 /* swc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9162 /* swc2 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotCnMips|Feature_NotInMicroMips, 9167 /* swc3 */, MCK_COP3AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotCnMips|Feature_NotInMicroMips, 9167 /* swc3 */, MCK_Mem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 9172 /* swe */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 9172 /* swe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasEVA, 9172 /* swe */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasEVA, 9172 /* swe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9176 /* swl */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9176 /* swl */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 9176 /* swl */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 9176 /* swl */, MCK_Mem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 9180 /* swle */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 9180 /* swle */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 9180 /* swle */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 9180 /* swle */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_InMicroMips, 9185 /* swm */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips, 9185 /* swm */, MCK_RegList, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 9189 /* swm16 */, MCK_MemOffsetUimm4, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 9189 /* swm16 */, MCK_RegList16, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 9189 /* swm16 */, MCK_MemOffsetUimm4, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 9189 /* swm16 */, MCK_RegList16, 1 /* 0 */ },
  { Feature_InMicroMips, 9195 /* swm32 */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips, 9195 /* swm32 */, MCK_RegList, 1 /* 0 */ },
  { Feature_InMicroMips, 9201 /* swp */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 9201 /* swp */, MCK_MemOffsetSimm12, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9205 /* swr */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9205 /* swr */, MCK_Mem, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 9205 /* swr */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 9205 /* swr */, MCK_Mem, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 9209 /* swre */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 9209 /* swre */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 9209 /* swre */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 9209 /* swre */, MCK_MemOffsetSimm9, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 9214 /* swxc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 9214 /* swxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 9214 /* swxc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 9214 /* swxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 9225 /* synci */, MCK_MemOffsetSimm16, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 9225 /* synci */, MCK_MemOffsetSimm16, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 9225 /* synci */, MCK_MemOffsetSimm16, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9269 /* teq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 9269 /* teq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 9269 /* teq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9269 /* teq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9273 /* teqi */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 9273 /* teqi */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9278 /* tge */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 9278 /* tge */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 9278 /* tge */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9278 /* tge */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9282 /* tgei */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 9282 /* tgei */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9287 /* tgeiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 9287 /* tgeiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9293 /* tgeu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 9293 /* tgeu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 9293 /* tgeu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9293 /* tgeu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9378 /* tlt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 9378 /* tlt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 9378 /* tlt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9378 /* tlt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9382 /* tlti */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 9382 /* tlti */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9387 /* tltiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 9387 /* tltiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9393 /* tltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 9393 /* tltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 9393 /* tltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9393 /* tltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9398 /* tne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 9398 /* tne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 9398 /* tne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9398 /* tne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9402 /* tnei */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 9402 /* tnei */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9407 /* trunc.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 9407 /* trunc.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9417 /* trunc.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9417 /* trunc.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 9417 /* trunc.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 9417 /* trunc.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9427 /* trunc.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
  { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9427 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
  { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9427 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9427 /* trunc.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
  { Feature_NotFP64bit|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
  { Feature_NotFP64bit|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_NotFP64bit|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
  { Feature_IsFP64bit|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
  { Feature_IsFP64bit|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
  { Feature_IsFP64bit|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
  { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9437 /* trunc.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 9437 /* trunc.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_IsNotSoftFloat, 9437 /* trunc.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { 0, 9437 /* trunc.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
  { 0, 9437 /* trunc.w.s */, MCK_GPR32AsmReg, 4 /* 2 */ },
  { 0, 9447 /* ulh */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { 0, 9447 /* ulh */, MCK_Mem, 2 /* 1 */ },
  { 0, 9451 /* ulhu */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { 0, 9451 /* ulhu */, MCK_Mem, 2 /* 1 */ },
  { 0, 9456 /* ulw */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { 0, 9456 /* ulw */, MCK_Mem, 2 /* 1 */ },
  { 0, 9460 /* ush */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { 0, 9460 /* ush */, MCK_Mem, 2 /* 1 */ },
  { 0, 9464 /* usw */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { 0, 9464 /* usw */, MCK_Mem, 2 /* 1 */ },
  { Feature_HasCnMips, 9468 /* v3mulu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasCnMips, 9468 /* v3mulu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasCnMips, 9475 /* vmm0 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasCnMips, 9475 /* vmm0 */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasCnMips, 9480 /* vmulu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasCnMips, 9480 /* vmulu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 9486 /* vshf.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 9493 /* vshf.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 9500 /* vshf.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 9507 /* vshf.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_HasDSP|Feature_NotInMicroMips, 9519 /* wrdsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasDSP|Feature_InMicroMips, 9519 /* wrdsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasDSP, 9519 /* wrdsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasDSP|Feature_NotInMicroMips, 9519 /* wrdsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 9525 /* wrpgpr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 9532 /* wsbh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 9532 /* wsbh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 9532 /* wsbh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 9537 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 9537 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 9537 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 9537 /* xor */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 9537 /* xor */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips, 9537 /* xor */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, 9537 /* xor */, MCK_GPR64AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 9537 /* xor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 9537 /* xor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 9537 /* xor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 9537 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 9537 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips, 9537 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, 9537 /* xor */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 9541 /* xor.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 9547 /* xor16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 9547 /* xor16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 9553 /* xori */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 9553 /* xori */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 9553 /* xori */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_InMicroMips|Feature_HasMips32r6, 9553 /* xori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_NotInMicroMips, 9553 /* xori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_InMicroMips|Feature_NotMips32r6, 9553 /* xori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
  { Feature_HasStdEnc|Feature_HasMSA, 9558 /* xori.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
  { Feature_HasMT|Feature_NotInMicroMips, 9565 /* yield */, MCK_GPR32AsmReg, 1 /* 0 */ },
  { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 9565 /* yield */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
};

OperandMatchResultTy MipsAsmParser::
tryCustomParseOperand(OperandVector &Operands,
                      unsigned MCK) {

  switch(MCK) {
  case MCK_ACC64DSPAsmReg:
    return parseAnyRegister(Operands);
  case MCK_AFGR64AsmReg:
    return parseAnyRegister(Operands);
  case MCK_CCRAsmReg:
    return parseAnyRegister(Operands);
  case MCK_COP0AsmReg:
    return parseAnyRegister(Operands);
  case MCK_COP2AsmReg:
    return parseAnyRegister(Operands);
  case MCK_COP3AsmReg:
    return parseAnyRegister(Operands);
  case MCK_FCCAsmReg:
    return parseAnyRegister(Operands);
  case MCK_FGR32AsmReg:
    return parseAnyRegister(Operands);
  case MCK_FGR64AsmReg:
    return parseAnyRegister(Operands);
  case MCK_FGRH32AsmReg:
    return parseAnyRegister(Operands);
  case MCK_GPR32AsmReg:
    return parseAnyRegister(Operands);
  case MCK_GPR32NonZeroAsmReg:
    return parseAnyRegister(Operands);
  case MCK_GPR32ZeroAsmReg:
    return parseAnyRegister(Operands);
  case MCK_GPR64AsmReg:
    return parseAnyRegister(Operands);
  case MCK_GPRMM16AsmReg:
    return parseAnyRegister(Operands);
  case MCK_GPRMM16AsmRegMoveP:
    return parseAnyRegister(Operands);
  case MCK_GPRMM16AsmRegZero:
    return parseAnyRegister(Operands);
  case MCK_HI32DSPAsmReg:
    return parseAnyRegister(Operands);
  case MCK_HWRegsAsmReg:
    return parseAnyRegister(Operands);
  case MCK_LO32DSPAsmReg:
    return parseAnyRegister(Operands);
  case MCK_MSA128AsmReg:
    return parseAnyRegister(Operands);
  case MCK_MSACtrlAsmReg:
    return parseAnyRegister(Operands);
  case MCK_MicroMipsMemGP:
    return parseMemOperand(Operands);
  case MCK_MicroMipsMem:
    return parseMemOperand(Operands);
  case MCK_MicroMipsMemSP:
    return parseMemOperand(Operands);
  case MCK_InvNum:
    return parseInvNum(Operands);
  case MCK_JumpTarget:
    return parseJumpTarget(Operands);
  case MCK_MemOffsetSimm10:
    return parseMemOperand(Operands);
  case MCK_MemOffsetSimm10_1:
    return parseMemOperand(Operands);
  case MCK_MemOffsetSimm10_2:
    return parseMemOperand(Operands);
  case MCK_MemOffsetSimm10_3:
    return parseMemOperand(Operands);
  case MCK_MemOffsetSimm11:
    return parseMemOperand(Operands);
  case MCK_MemOffsetSimm12:
    return parseMemOperand(Operands);
  case MCK_MemOffsetSimm16:
    return parseMemOperand(Operands);
  case MCK_MemOffsetSimm9:
    return parseMemOperand(Operands);
  case MCK_MemOffsetSimmPtr:
    return parseMemOperand(Operands);
  case MCK_MemOffsetUimm4:
    return parseMemOperand(Operands);
  case MCK_Mem:
    return parseMemOperand(Operands);
  case MCK_MovePRegPair:
    return parseMovePRegPair(Operands);
  case MCK_RegList16:
    return parseRegisterList(Operands);
  case MCK_RegList:
    return parseRegisterList(Operands);
  case MCK_StrictlyAFGR64AsmReg:
    return parseAnyRegister(Operands);
  case MCK_StrictlyFGR32AsmReg:
    return parseAnyRegister(Operands);
  case MCK_StrictlyFGR64AsmReg:
    return parseAnyRegister(Operands);
  default:
    return MatchOperand_NoMatch;
  }
  return MatchOperand_NoMatch;
}

OperandMatchResultTy MipsAsmParser::
MatchOperandParserImpl(OperandVector &Operands,
                       StringRef Mnemonic,
                       bool ParseForAllFeatures) {
  // Get the current feature set.
  uint64_t AvailableFeatures = getAvailableFeatures();

  // Get the next operand index.
  unsigned NextOpNum = Operands.size() - 1;
  // Search the table.
  auto MnemonicRange =
    std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
                     Mnemonic, LessOpcodeOperand());

  if (MnemonicRange.first == MnemonicRange.second)
    return MatchOperand_NoMatch;

  for (const OperandMatchEntry *it = MnemonicRange.first,
       *ie = MnemonicRange.second; it != ie; ++it) {
    // equal_range guarantees that instruction mnemonic matches.
    assert(Mnemonic == it->getMnemonic());

    // check if the available features match
    if (!ParseForAllFeatures && (AvailableFeatures & it->RequiredFeatures) != it->RequiredFeatures)
        continue;

    // check if the operand in question has a custom parser.
    if (!(it->OperandMask & (1 << NextOpNum)))
      continue;

    // call custom parse method to handle the operand
    OperandMatchResultTy Result = tryCustomParseOperand(Operands, it->Class);
    if (Result != MatchOperand_NoMatch)
      return Result;
  }

  // Okay, we had no match.
  return MatchOperand_NoMatch;
}

#endif // GET_MATCHER_IMPLEMENTATION


#ifdef GET_MNEMONIC_SPELL_CHECKER
#undef GET_MNEMONIC_SPELL_CHECKER

static std::string MipsMnemonicSpellCheck(StringRef S, uint64_t FBS, unsigned VariantID) {
  const unsigned MaxEditDist = 2;
  std::vector<StringRef> Candidates;
  StringRef Prev = "";

  // Find the appropriate table for this asm variant.
  const MatchEntry *Start, *End;
  switch (VariantID) {
  default: llvm_unreachable("invalid variant!");
  case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
  }

  for (auto I = Start; I < End; I++) {
    // Ignore unsupported instructions.
    if ((FBS & I->RequiredFeatures) != I->RequiredFeatures)
      continue;

    StringRef T = I->getMnemonic();
    // Avoid recomputing the edit distance for the same string.
    if (T.equals(Prev))
      continue;

    Prev = T;
    unsigned Dist = S.edit_distance(T, false, MaxEditDist);
    if (Dist <= MaxEditDist)
      Candidates.push_back(T);
  }

  if (Candidates.empty())
    return "";

  std::string Res = ", did you mean: ";
  unsigned i = 0;
  for( ; i < Candidates.size() - 1; i++)
    Res += Candidates[i].str() + ", ";
  return Res + Candidates[i].str() + "?";
}

#endif // GET_MNEMONIC_SPELL_CHECKER