Handle ARM "ret void" and function alignment with proper padding.
Modify run-pnacl-sz to pass in the correct assembler/disasembler flags
for ARM when not using the integrated assembler.
Model the "ret" pseudo instruction (special form of
"bx" inst). Separate from "bx" to allow epilogue
insertion to find the terminator.
Add a flag "--skip-unimplemented" to skip through all of the
"Not yet implemented" assertions, and use that in the test.
Set up a stack trace printer when ALLOW_DUMP so that the
UnimplementedError prints out some useful information of
*which* case is unimplemented.
Change the .type ...,@function from @function to %function.
ARM assembler seems to only like %function because
"@" is a comment character.
BUG= https://code.google.com/p/nativeclient/issues/detail?id=4076
R=stichnot@chromium.org
Review URL: https://codereview.chromium.org/1136793002
diff --git a/src/IceTargetLoweringARM32.h b/src/IceTargetLoweringARM32.h
index e973652..c1862d5 100644
--- a/src/IceTargetLoweringARM32.h
+++ b/src/IceTargetLoweringARM32.h
@@ -16,6 +16,7 @@
#define SUBZERO_SRC_ICETARGETLOWERINGARM32_H
#include "IceDefs.h"
+#include "IceInstARM32.h"
#include "IceRegistersARM32.h"
#include "IceTargetLowering.h"
@@ -91,6 +92,14 @@
static Type stackSlotType();
+ // The following are helpers that insert lowered ARM32 instructions
+ // with minimal syntactic overhead, so that the lowering code can
+ // look as close to assembly as practical.
+
+ void _ret(Variable *LR, Variable *Src0 = nullptr) {
+ Context.insert(InstARM32Ret::create(Func, LR, Src0));
+ }
+
bool UsesFramePointer;
bool NeedsStackAlignment;
llvm::SmallBitVector TypeToRegisterSet[IceType_NUM];
