Subzero: switch from llvm-objdump to objdump for lit tests (for LLVM merge)
After the next LLVM merge, llvm-objdump is going to lose the "--symbolize"
flag. It also sounds like llvm-objdump may at some point converge to the
objdump-style of output.
So, rather than keep updating test expectations, switch to objdump,
assuming objdump will be more stable than llvm-objdump.
Also stash the assembler/disassembler commandlines in
the run-llvm2ice.py script. In theory this will let us
tweak the commandlines more easily (one place).
In practice the test expectatations will probably need
to be adjusted if the base commandlines change though.
Bulk edit the test expectations to match objdump now.
Some of this is assisted by a python script.
Example script: https://codereview.chromium.org/928663002/
BUG= https://code.google.com/p/nativeclient/issues/detail?id=4026
R=kschimpf@google.com, stichnot@chromium.org
Review URL: https://codereview.chromium.org/914263005
diff --git a/tests_lit/assembler/x86/immediate_encodings.ll b/tests_lit/assembler/x86/immediate_encodings.ll
index 28180c0..2dc7710 100644
--- a/tests_lit/assembler/x86/immediate_encodings.ll
+++ b/tests_lit/assembler/x86/immediate_encodings.ll
@@ -2,9 +2,8 @@
; For example, the encoding is shorter for 8-bit immediates or when using EAX.
; This assumes that EAX is chosen as the first free register in O2 mode.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
+; RUN: | FileCheck %s
define internal i32 @testXor8Imm8(i32 %arg) {
entry:
@@ -14,7 +13,7 @@
ret i32 %result
}
; CHECK-LABEL: testXor8Imm8
-; CHECK: 34 7f xor al, 127
+; CHECK: 34 7f xor al
define internal i32 @testXor8Imm8Neg(i32 %arg) {
entry:
@@ -24,7 +23,7 @@
ret i32 %result
}
; CHECK-LABEL: testXor8Imm8Neg
-; CHECK: 34 80 xor al, -128
+; CHECK: 34 80 xor al
define internal i32 @testXor8Imm8NotEAX(i32 %arg, i32 %arg2, i32 %arg3) {
entry:
@@ -40,7 +39,7 @@
ret i32 %result
}
; CHECK-LABEL: testXor8Imm8NotEAX
-; CHECK: 80 f{{[1-3]}} 7f xor {{[^a]}}l, 127
+; CHECK: 80 f{{[1-3]}} 7f xor {{[^a]}}l
define internal i32 @testXor16Imm8(i32 %arg) {
entry:
@@ -50,7 +49,7 @@
ret i32 %result
}
; CHECK-LABEL: testXor16Imm8
-; CHECK: 66 83 f0 7f xor ax, 127
+; CHECK: 66 83 f0 7f xor ax
define internal i32 @testXor16Imm8Neg(i32 %arg) {
entry:
@@ -60,7 +59,7 @@
ret i32 %result
}
; CHECK-LABEL: testXor16Imm8Neg
-; CHECK: 66 83 f0 80 xor ax, -128
+; CHECK: 66 83 f0 80 xor ax
define internal i32 @testXor16Imm16Eax(i32 %arg) {
entry:
@@ -71,8 +70,8 @@
ret i32 %result
}
; CHECK-LABEL: testXor16Imm16Eax
-; CHECK: 66 35 00 04 xor ax, 1024
-; CHECK-NEXT: add ax, 1
+; CHECK: 66 35 00 04 xor ax
+; CHECK-NEXT: add ax,0x1
define internal i32 @testXor16Imm16NegEax(i32 %arg) {
entry:
@@ -83,8 +82,8 @@
ret i32 %result
}
; CHECK-LABEL: testXor16Imm16NegEax
-; CHECK: 66 35 00 ff xor ax, 65280
-; CHECK-NEXT: add ax, 1
+; CHECK: 66 35 00 ff xor ax
+; CHECK-NEXT: add ax,0x1
define internal i32 @testXor16Imm16NotEAX(i32 %arg_i32, i32 %arg2_i32, i32 %arg3_i32) {
entry:
@@ -100,8 +99,8 @@
ret i32 %result
}
; CHECK-LABEL: testXor16Imm16NotEAX
-; CHECK: 66 81 f{{[1-3]}} ff 7f xor {{[^a]}}x, 32767
-; CHECK-NEXT: 66 81 f{{[1-3]}} ff 7f xor {{[^a]}}x, 32767
+; CHECK: 66 81 f{{[1-3]}} ff 7f xor {{[^a]}}x
+; CHECK-NEXT: 66 81 f{{[1-3]}} ff 7f xor {{[^a]}}x
define internal i32 @testXor32Imm8(i32 %arg) {
entry:
@@ -109,7 +108,7 @@
ret i32 %result
}
; CHECK-LABEL: testXor32Imm8
-; CHECK: 83 f0 7f xor eax, 127
+; CHECK: 83 f0 7f xor eax
define internal i32 @testXor32Imm8Neg(i32 %arg) {
entry:
@@ -117,7 +116,7 @@
ret i32 %result
}
; CHECK-LABEL: testXor32Imm8Neg
-; CHECK: 83 f0 80 xor eax, -128
+; CHECK: 83 f0 80 xor eax
define internal i32 @testXor32Imm32Eax(i32 %arg) {
entry:
@@ -125,7 +124,7 @@
ret i32 %result
}
; CHECK-LABEL: testXor32Imm32Eax
-; CHECK: 35 00 00 00 01 xor eax, 16777216
+; CHECK: 35 00 00 00 01 xor eax
define internal i32 @testXor32Imm32NegEax(i32 %arg) {
entry:
@@ -133,7 +132,7 @@
ret i32 %result
}
; CHECK-LABEL: testXor32Imm32NegEax
-; CHECK: 35 00 ff ff ff xor eax, 4294967040
+; CHECK: 35 00 ff ff ff xor eax
define internal i32 @testXor32Imm32NotEAX(i32 %arg, i32 %arg2, i32 %arg3) {
entry:
@@ -145,7 +144,7 @@
ret i32 %add2
}
; CHECK-LABEL: testXor32Imm32NotEAX
-; CHECK: 81 f{{[1-3]}} ff 7f 00 00 xor e{{[^a]}}x, 32767
+; CHECK: 81 f{{[1-3]}} ff 7f 00 00 xor e{{[^a]}}x,
; Should be similar for add, sub, etc., so sample a few.
@@ -157,7 +156,7 @@
ret i32 %result
}
; CHECK-LABEL: testAdd8Imm8
-; CHECK: 04 7e add al, 126
+; CHECK: 04 7e add al
define internal i32 @testSub8Imm8(i32 %arg) {
entry:
@@ -167,7 +166,7 @@
ret i32 %result
}
; CHECK-LABEL: testSub8Imm8
-; CHECK: 2c 7d sub al, 125
+; CHECK: 2c 7d sub al
; imul has some shorter 8-bit immediate encodings.
; It also has a shorter encoding for eax, but we don't do that yet.
@@ -181,8 +180,8 @@
ret i32 %result
}
; CHECK-LABEL: testMul16Imm8
-; CHECK: 66 6b c0 63 imul ax, ax, 99
-; CHECK-NEXT: add ax, 1
+; CHECK: 66 6b c0 63 imul ax,ax
+; CHECK-NEXT: add ax,0x1
define internal i32 @testMul16Imm8Neg(i32 %arg) {
entry:
@@ -193,8 +192,8 @@
ret i32 %result
}
; CHECK-LABEL: testMul16Imm8Neg
-; CHECK: 66 6b c0 91 imul ax, ax, -111
-; CHECK-NEXT: add ax, 1
+; CHECK: 66 6b c0 91 imul ax,ax
+; CHECK-NEXT: add ax,0x1
define internal i32 @testMul16Imm16(i32 %arg) {
entry:
@@ -205,8 +204,8 @@
ret i32 %result
}
; CHECK-LABEL: testMul16Imm16
-; CHECK: 66 69 c0 00 04 imul ax, ax, 1024
-; CHECK-NEXT: add ax, 1
+; CHECK: 66 69 c0 00 04 imul ax,ax
+; CHECK-NEXT: add ax,0x1
define internal i32 @testMul16Imm16Neg(i32 %arg) {
entry:
@@ -217,8 +216,8 @@
ret i32 %result
}
; CHECK-LABEL: testMul16Imm16Neg
-; CHECK: 66 69 c0 00 ff imul ax, ax, 65280
-; CHECK-NEXT: add ax, 1
+; CHECK: 66 69 c0 00 ff imul ax,ax
+; CHECK-NEXT: add ax,0x1
define internal i32 @testMul32Imm8(i32 %arg) {
entry:
@@ -226,7 +225,7 @@
ret i32 %result
}
; CHECK-LABEL: testMul32Imm8
-; CHECK: 6b c0 63 imul eax, eax, 99
+; CHECK: 6b c0 63 imul eax,eax
define internal i32 @testMul32Imm8Neg(i32 %arg) {
entry:
@@ -234,7 +233,7 @@
ret i32 %result
}
; CHECK-LABEL: testMul32Imm8Neg
-; CHECK: 6b c0 91 imul eax, eax, -111
+; CHECK: 6b c0 91 imul eax,eax
define internal i32 @testMul32Imm16(i32 %arg) {
entry:
@@ -242,7 +241,7 @@
ret i32 %result
}
; CHECK-LABEL: testMul32Imm16
-; CHECK: 69 c0 00 04 00 00 imul eax, eax, 1024
+; CHECK: 69 c0 00 04 00 00 imul eax,eax
define internal i32 @testMul32Imm16Neg(i32 %arg) {
entry:
@@ -250,7 +249,7 @@
ret i32 %result
}
; CHECK-LABEL: testMul32Imm16Neg
-; CHECK: 69 c0 00 ff ff ff imul eax, eax, 4294967040
+; CHECK: 69 c0 00 ff ff ff imul eax,eax
; The GPR shift instructions either allow an 8-bit immediate or
; have a special encoding for "1".
@@ -262,7 +261,7 @@
ret i32 %result
}
; CHECK-LABEL: testShl16Imm8
-; CHECK: 66 c1 e0 0d shl ax, 13
+; CHECK: 66 c1 e0 0d shl ax,0xd
define internal i32 @testShl16Imm1(i32 %arg) {
entry:
@@ -286,9 +285,9 @@
ret i64 %shl
}
; CHECK-LABEL: test_via_shl64Bit
-; CHECK: 0f a5 c2 shld edx, eax, cl
-; CHECK: d3 e0 shl eax, cl
-; CHECK: f6 c1 20 test cl, 32
+; CHECK: 0f a5 c2 shld edx,eax,cl
+; CHECK: d3 e0 shl eax,cl
+; CHECK: f6 c1 20 test cl,0x20
; Test a few register encodings of "test".
declare i64 @llvm.ctlz.i64(i64, i1)
@@ -305,6 +304,6 @@
ret i64 %res
}
; CHECK-LABEL: test_via_ctlz_64
-; CHECK-DAG: 85 c0 test eax, eax
-; CHECK-DAG: 85 db test ebx, ebx
-; CHECK-DAG: 85 f6 test esi, esi
+; CHECK-DAG: 85 c0 test eax,eax
+; CHECK-DAG: 85 db test ebx,ebx
+; CHECK-DAG: 85 f6 test esi,esi
diff --git a/tests_lit/assembler/x86/jump_encodings.ll b/tests_lit/assembler/x86/jump_encodings.ll
index f8607cb..d594ae9 100644
--- a/tests_lit/assembler/x86/jump_encodings.ll
+++ b/tests_lit/assembler/x86/jump_encodings.ll
@@ -2,9 +2,8 @@
; forward vs backward, using CFG labels, or local labels).
; Use -ffunction-sections so that the offsets reset for each function.
-; RUN: %p2i -i %s --args -O2 --verbose none -ffunction-sections \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
+; RUN: -ffunction-sections | FileCheck %s
; Use atomic ops as filler, which shouldn't get optimized out.
declare void @llvm.nacl.atomic.store.i32(i32, i32*, i32)
@@ -25,15 +24,13 @@
}
; CHECK-LABEL: test_near_backward
-; CHECK: 8: {{.*}} mov dword ptr
+; CHECK: 8: {{.*}} mov DWORD PTR
; CHECK-NEXT: a: {{.*}} mfence
-; CHECK-NEXT: d: {{.*}} mov dword ptr
+; CHECK-NEXT: d: {{.*}} mov DWORD PTR
; CHECK-NEXT: f: {{.*}} mfence
; CHECK-NEXT: 12: {{.*}} cmp
-; (0x15 + 2) - 10 == 0xd
-; CHECK-NEXT: 15: 72 f6 jb -10
-; (0x17 + 2) - 17 == 0x8
-; CHECK-NEXT: 17: eb ef jmp -17
+; CHECK-NEXT: 15: 72 f6 jb d
+; CHECK-NEXT: 17: eb ef jmp 8
; Test one of the backward branches being too large for 8 bits
; and one being just okay.
@@ -74,13 +71,11 @@
}
; CHECK-LABEL: test_far_backward1
-; CHECK: 8: {{.*}} mov {{.*}}, dword ptr [e{{[^s]}}
-; CHECK-NEXT: a: {{.*}} mov dword ptr
+; CHECK: 8: {{.*}} mov {{.*}},DWORD PTR [e{{[^s]}}
+; CHECK-NEXT: a: {{.*}} mov DWORD PTR
; CHECK-NEXT: c: {{.*}} mfence
-; (0x85 + 2) - 125 == 0xa
-; CHECK: 85: 77 83 ja -125
-; (0x87 + 5) - 132 == 0x8
-; CHECK-NEXT: 87: e9 7c ff ff ff jmp -132
+; CHECK: 85: 77 83 ja a
+; CHECK-NEXT: 87: e9 7c ff ff ff jmp 8
; Same as test_far_backward1, but with the conditional branch being
; the one that is too far.
@@ -124,14 +119,12 @@
}
; CHECK-LABEL: test_far_backward2
-; CHECK: c: {{.*}} mov {{.*}}, dword ptr [e{{[^s]}}
-; CHECK: 14: {{.*}} mov {{.*}}, dword ptr
-; CHECK-NEXT: 16: {{.*}} mov dword ptr
+; CHECK: c: {{.*}} mov {{.*}},DWORD PTR [e{{[^s]}}
+; CHECK: 14: {{.*}} mov {{.*}},DWORD PTR
+; CHECK-NEXT: 16: {{.*}} mov DWORD PTR
; CHECK-NEXT: 18: {{.*}} mfence
-; (0x8c + 6) - 134 == 0xc
-; CHECK: 8c: 0f 8e 7a ff ff ff jle -134
-; (0x92 + 2) - 126 == 0x16
-; CHECK-NEXT: 92: eb 82 jmp -126
+; CHECK: 8c: 0f 8e 7a ff ff ff jle c
+; CHECK-NEXT: 92: eb 82 jmp 16
define void @test_near_forward(i32 %iptr, i32 %val) {
entry:
@@ -151,14 +144,11 @@
; form to avoid needing a relaxation pass.
; CHECK-LABEL: test_near_forward
; CHECK: 8: {{.*}} cmp
-; CHECK-NEXT: b: 0f 82 05 00 00 00 jb 5
-; CHECK-NEXT: 11: {{.*}} mov dword ptr
+; CHECK-NEXT: b: 0f 82 05 00 00 00 jb 16
+; CHECK-NEXT: 11: {{.*}} mov DWORD PTR
; CHECK-NEXT: 13: {{.*}} mfence
-; Forward branch is 5 bytes ahead to here.
-; CHECK-NEXT: 16: {{.*}} mov dword ptr
-; Jumps back to (0x1b + 2) - 21 == 0x8 (to before the forward branch,
-; therefore knowing that the forward branch was indeed 6 bytes).
-; CHECK: 1b: eb eb jmp -21
+; CHECK-NEXT: 16: {{.*}} mov DWORD PTR
+; CHECK: 1b: eb eb jmp 8
; Unlike forward branches to cfg nodes, "local" forward branches
@@ -179,15 +169,13 @@
br i1 %cmp, label %next, label %next2
}
; CHECK-LABEL: test_local_forward_then_back
-; CHECK: 14: {{.*}} mov dword ptr
+; CHECK: 14: {{.*}} mov DWORD PTR
; CHECK-NEXT: 16: {{.*}} mfence
-; CHECK-NEXT: 19: {{.*}} mov dword ptr {{.*}}, 1
+; CHECK-NEXT: 19: {{.*}} mov DWORD PTR {{.*}},0x1
; CHECK-NEXT: 20: {{.*}} cmp
-; CHECK-NEXT: 23: {{.*}} jb 14
-; (0x37 + 2) - 37 == 0x14
-; CHECK: 37: {{.*}} jne -37
-; (0x39 + 2) - 34 == 0x19
-; CHECK: 39: {{.*}} jmp -34
+; CHECK-NEXT: 23: {{.*}} jb 33
+; CHECK: 37: {{.*}} jne 14
+; CHECK: 39: {{.*}} jmp 19
; Test that backward local branches also work and are small.
@@ -204,12 +192,9 @@
br i1 %success, label %next, label %next2
}
; CHECK-LABEL: test_local_backward
-; CHECK: 9: {{.*}} mov {{.*}}, dword
+; CHECK: 9: {{.*}} mov {{.*}},DWORD
; CHECK: b: {{.*}} mov
; CHECK-NEXT: d: {{.*}} xor
-; CHECK-NEXT: f: {{.*}} lock
-; CHECK-NEXT: 10: {{.*}} cmpxchg
-; (0x13 + 2) - 10 == 0xb
-; CHECK-NEXT: 13: 75 f6 jne -10
-; (0x1c + 2) - 21 == 0x9
-; CHECK: 1c: 74 eb je -21
+; CHECK-NEXT: f: {{.*}} lock cmpxchg
+; CHECK-NEXT: 13: 75 f6 jne b
+; CHECK: 1c: 74 eb je 9
diff --git a/tests_lit/assembler/x86/opcode_register_encodings.ll b/tests_lit/assembler/x86/opcode_register_encodings.ll
index 122347c..642e034 100644
--- a/tests_lit/assembler/x86/opcode_register_encodings.ll
+++ b/tests_lit/assembler/x86/opcode_register_encodings.ll
@@ -2,16 +2,15 @@
; those for pmull vary more wildly depending on operand size (rather than
; follow a usual pattern).
-; RUN: %p2i -i %s --args -O2 -mattr=sse4.1 -sandbox --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args -O2 -mattr=sse4.1 -sandbox \
+; RUN: --verbose none | FileCheck %s
define <8 x i16> @test_mul_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
entry:
%res = mul <8 x i16> %arg0, %arg1
ret <8 x i16> %res
; CHECK-LABEL: test_mul_v8i16
-; CHECK: 66 0f d5 c1 pmullw xmm0, xmm1
+; CHECK: 66 0f d5 c1 pmullw xmm0,xmm1
}
; Test register and address mode encoding.
@@ -34,14 +33,14 @@
%res = select <8 x i1> %cond, <8 x i16> %res_acc1_3, <8 x i16> %res_acc2_4
ret <8 x i16> %res
; CHECK-LABEL: test_mul_v8i16_more_regs
-; CHECK-DAG: 66 0f d5 c2 pmullw xmm0, xmm2
-; CHECK-DAG: 66 0f d5 c3 pmullw xmm0, xmm3
-; CHECK-DAG: 66 0f d5 c4 pmullw xmm0, xmm4
-; CHECK-DAG: 66 0f d5 c5 pmullw xmm0, xmm5
-; CHECK-DAG: 66 0f d5 c6 pmullw xmm0, xmm6
-; CHECK-DAG: 66 0f d5 c7 pmullw xmm0, xmm7
-; CHECK-DAG: 66 0f d5 44 24 70 pmullw xmm0, xmmword ptr [esp + 112]
-; CHECK-DAG: 66 0f d5 8c 24 80 00 00 00 pmullw xmm1, xmmword ptr [esp + 128]
+; CHECK-DAG: 66 0f d5 c2 pmullw xmm0,xmm2
+; CHECK-DAG: 66 0f d5 c3 pmullw xmm0,xmm3
+; CHECK-DAG: 66 0f d5 c4 pmullw xmm0,xmm4
+; CHECK-DAG: 66 0f d5 c5 pmullw xmm0,xmm5
+; CHECK-DAG: 66 0f d5 c6 pmullw xmm0,xmm6
+; CHECK-DAG: 66 0f d5 c7 pmullw xmm0,xmm7
+; CHECK-DAG: 66 0f d5 44 24 70 pmullw xmm0,XMMWORD PTR [esp
+; CHECK-DAG: 66 0f d5 8c 24 80 00 00 00 pmullw xmm1,XMMWORD PTR [esp
}
define <4 x i32> @test_mul_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
@@ -49,7 +48,7 @@
%res = mul <4 x i32> %arg0, %arg1
ret <4 x i32> %res
; CHECK-LABEL: test_mul_v4i32
-; CHECK: 66 0f 38 40 c1 pmulld xmm0, xmm1
+; CHECK: 66 0f 38 40 c1 pmulld xmm0,xmm1
}
define <4 x i32> @test_mul_v4i32_more_regs(<4 x i1> %cond, <4 x i32> %arg0, <4 x i32> %arg1, <4 x i32> %arg2, <4 x i32> %arg3, <4 x i32> %arg4, <4 x i32> %arg5, <4 x i32> %arg6, <4 x i32> %arg7, <4 x i32> %arg8) {
@@ -71,14 +70,14 @@
%res = select <4 x i1> %cond, <4 x i32> %res_acc1_3, <4 x i32> %res_acc2_4
ret <4 x i32> %res
; CHECK-LABEL: test_mul_v4i32_more_regs
-; CHECK-DAG: 66 0f 38 40 c2 pmulld xmm0, xmm2
-; CHECK-DAG: 66 0f 38 40 c3 pmulld xmm0, xmm3
-; CHECK-DAG: 66 0f 38 40 c4 pmulld xmm0, xmm4
-; CHECK-DAG: 66 0f 38 40 c5 pmulld xmm0, xmm5
-; CHECK-DAG: 66 0f 38 40 c6 pmulld xmm0, xmm6
-; CHECK-DAG: 66 0f 38 40 c7 pmulld xmm0, xmm7
-; CHECK-DAG: 66 0f 38 40 44 24 70 pmulld xmm0, xmmword ptr [esp + 112]
-; CHECK-DAG: 66 0f 38 40 8c 24 80 00 00 00 pmulld xmm1, xmmword ptr [esp + 128]
+; CHECK-DAG: 66 0f 38 40 c2 pmulld xmm0,xmm2
+; CHECK-DAG: 66 0f 38 40 c3 pmulld xmm0,xmm3
+; CHECK-DAG: 66 0f 38 40 c4 pmulld xmm0,xmm4
+; CHECK-DAG: 66 0f 38 40 c5 pmulld xmm0,xmm5
+; CHECK-DAG: 66 0f 38 40 c6 pmulld xmm0,xmm6
+; CHECK-DAG: 66 0f 38 40 c7 pmulld xmm0,xmm7
+; CHECK-DAG: 66 0f 38 40 44 24 70 pmulld xmm0,XMMWORD PTR [esp
+; CHECK-DAG: 66 0f 38 40 8c 24 80 00 00 00 pmulld xmm1,XMMWORD PTR [esp
}
; Test movq, which is used by atomic stores.
@@ -95,9 +94,9 @@
ret void
}
; CHECK-LABEL: test_atomic_store_64
-; CHECK-DAG: f3 0f 7e 04 24 movq xmm0, qword ptr [esp]
-; CHECK-DAG: f3 0f 7e 44 24 08 movq xmm0, qword ptr [esp + 8]
-; CHECK-DAG: 66 0f d6 0{{.*}} movq qword ptr [e{{.*}}], xmm0
+; CHECK-DAG: f3 0f 7e 04 24 movq xmm0,QWORD PTR [esp]
+; CHECK-DAG: f3 0f 7e 44 24 08 movq xmm0,QWORD PTR [esp
+; CHECK-DAG: 66 0f d6 0{{.*}} movq QWORD PTR [e{{.*}}],xmm0
; Test "movups" via vector stores and loads.
define void @store_v16xI8(i32 %addr, i32 %addr2, i32 %addr3, <16 x i8> %v) {
@@ -110,7 +109,7 @@
ret void
}
; CHECK-LABEL: store_v16xI8
-; CHECK: 0f 11 0{{.*}} movups xmmword ptr [e{{.*}}], xmm0
+; CHECK: 0f 11 0{{.*}} movups XMMWORD PTR [e{{.*}}],xmm0
define <16 x i8> @load_v16xI8(i32 %addr, i32 %addr2, i32 %addr3) {
%addr_v16xI8 = inttoptr i32 %addr to <16 x i8>*
@@ -124,7 +123,7 @@
ret <16 x i8> %res123
}
; CHECK-LABEL: load_v16xI8
-; CHECK: 0f 10 0{{.*}} movups xmm0, xmmword ptr [e{{.*}}]
+; CHECK: 0f 10 0{{.*}} movups xmm0,XMMWORD PTR [e{{.*}}]
; Test segment override prefix. This happens w/ nacl.read.tp.
declare i8* @llvm.nacl.read.tp()
@@ -154,11 +153,11 @@
ret i32 %v
}
; CHECK-LABEL: test_nacl_read_tp_more_addressing
-; CHECK: 65 8b 05 00 00 00 00 mov eax, dword ptr gs:[0]
-; CHECK: 8b 04 00 mov eax, dword ptr [eax + eax]
-; CHECK: 65 8b 0d 00 00 00 00 mov ecx, dword ptr gs:[0]
-; CHECK: 89 51 80 mov dword ptr [ecx - 128], edx
-; CHECK: 89 91 00 01 00 00 mov dword ptr [ecx + 256], edx
+; CHECK: 65 8b 05 00 00 00 00 mov eax,DWORD PTR gs:0x0
+; CHECK: 8b 04 00 mov eax,DWORD PTR [eax+eax*1]
+; CHECK: 65 8b 0d 00 00 00 00 mov ecx,DWORD PTR gs:0x0
+; CHECK: 89 51 80 mov DWORD PTR [ecx-0x80],edx
+; CHECK: 89 91 00 01 00 00 mov DWORD PTR [ecx+0x100],edx
; The 16-bit pinsrw/pextrw (SSE2) are quite different from
; the pinsr{b,d}/pextr{b,d} (SSE4.1).
@@ -172,10 +171,10 @@
%res3 = insertelement <4 x i32> %res2, i32 %elt1, i32 3
ret <4 x i32> %res3
}
-; CHECK-LABEL: test_pinsrd:
-; CHECK-DAG: 66 0f 3a 22 c{{.*}} 01 pinsrd xmm0, e{{.*}}, 1
-; CHECK-DAG: 66 0f 3a 22 c{{.*}} 02 pinsrd xmm0, e{{.*}}, 2
-; CHECK-DAG: 66 0f 3a 22 c{{.*}} 03 pinsrd xmm0, e{{.*}}, 3
+; CHECK-LABEL: test_pinsrd
+; CHECK-DAG: 66 0f 3a 22 c{{.*}} 01 pinsrd xmm0,e{{.*}}
+; CHECK-DAG: 66 0f 3a 22 c{{.*}} 02 pinsrd xmm0,e{{.*}}
+; CHECK-DAG: 66 0f 3a 22 c{{.*}} 03 pinsrd xmm0,e{{.*}}
define <16 x i8> @test_pinsrb(<16 x i8> %vec, i32 %elt1_w, i32 %elt2_w, i32 %elt3_w, i32 %elt4_w) {
entry:
@@ -190,10 +189,10 @@
%res3 = insertelement <16 x i8> %res2, i8 %elt1, i32 15
ret <16 x i8> %res3
}
-; CHECK-LABEL: test_pinsrb:
-; CHECK-DAG: 66 0f 3a 20 c{{.*}} 01 pinsrb xmm0, e{{.*}}, 1
-; CHECK-DAG: 66 0f 3a 20 c{{.*}} 07 pinsrb xmm0, e{{.*}}, 7
-; CHECK-DAG: 66 0f 3a 20 {{.*}} 0f pinsrb xmm0, byte ptr {{.*}}, 15
+; CHECK-LABEL: test_pinsrb
+; CHECK-DAG: 66 0f 3a 20 c{{.*}} 01 pinsrb xmm0,e{{.*}}
+; CHECK-DAG: 66 0f 3a 20 c{{.*}} 07 pinsrb xmm0,e{{.*}}
+; CHECK-DAG: 66 0f 3a 20 {{.*}} 0f pinsrb xmm0,BYTE PTR {{.*}}
define <8 x i16> @test_pinsrw(<8 x i16> %vec, i32 %elt1_w, i32 %elt2_w, i32 %elt3_w, i32 %elt4_w) {
entry:
@@ -208,10 +207,10 @@
%res3 = insertelement <8 x i16> %res2, i16 %elt1, i32 7
ret <8 x i16> %res3
}
-; CHECK-LABEL: test_pinsrw:
-; CHECK-DAG: 66 0f c4 c{{.*}} 01 pinsrw xmm0, e{{.*}}, 1
-; CHECK-DAG: 66 0f c4 c{{.*}} 04 pinsrw xmm0, e{{.*}}, 4
-; CHECK-DAG: 66 0f c4 c{{.*}} 07 pinsrw xmm0, e{{.*}}, 7
+; CHECK-LABEL: test_pinsrw
+; CHECK-DAG: 66 0f c4 c{{.*}} 01 pinsrw xmm0,e{{.*}}
+; CHECK-DAG: 66 0f c4 c{{.*}} 04 pinsrw xmm0,e{{.*}}
+; CHECK-DAG: 66 0f c4 c{{.*}} 07 pinsrw xmm0,e{{.*}}
define i32 @test_pextrd(i32 %c, <4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32> %vec4) {
entry:
@@ -232,10 +231,10 @@
ret i32 %res3
}
; CHECK-LABEL: test_pextrd
-; CHECK-DAG: 66 0f 3a 16 c0 00 pextrd eax, xmm0, 0
-; CHECK-DAG: 66 0f 3a 16 c8 01 pextrd eax, xmm1, 1
-; CHECK-DAG: 66 0f 3a 16 d0 02 pextrd eax, xmm2, 2
-; CHECK-DAG: 66 0f 3a 16 d8 03 pextrd eax, xmm3, 3
+; CHECK-DAG: 66 0f 3a 16 c0 00 pextrd eax,xmm0
+; CHECK-DAG: 66 0f 3a 16 c8 01 pextrd eax,xmm1
+; CHECK-DAG: 66 0f 3a 16 d0 02 pextrd eax,xmm2
+; CHECK-DAG: 66 0f 3a 16 d8 03 pextrd eax,xmm3
define i32 @test_pextrb(i32 %c, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3, <16 x i8> %vec4) {
entry:
@@ -260,10 +259,10 @@
ret i32 %res3_ext
}
; CHECK-LABEL: test_pextrb
-; CHECK-DAG: 66 0f 3a 14 c0 00 pextrb eax, xmm0, 0
-; CHECK-DAG: 66 0f 3a 14 c8 06 pextrb eax, xmm1, 6
-; CHECK-DAG: 66 0f 3a 14 d0 0c pextrb eax, xmm2, 12
-; CHECK-DAG: 66 0f 3a 14 d8 0f pextrb eax, xmm3, 15
+; CHECK-DAG: 66 0f 3a 14 c0 00 pextrb eax,xmm0
+; CHECK-DAG: 66 0f 3a 14 c8 06 pextrb eax,xmm1
+; CHECK-DAG: 66 0f 3a 14 d0 0c pextrb eax,xmm2
+; CHECK-DAG: 66 0f 3a 14 d8 0f pextrb eax,xmm3
define i32 @test_pextrw(i32 %c, <8 x i16> %vec1, <8 x i16> %vec2, <8 x i16> %vec3, <8 x i16> %vec4) {
entry:
@@ -288,7 +287,7 @@
ret i32 %res3_ext
}
; CHECK-LABEL: test_pextrw
-; CHECK-DAG: 66 0f c5 c0 00 pextrw eax, xmm0, 0
-; CHECK-DAG: 66 0f c5 c1 02 pextrw eax, xmm1, 2
-; CHECK-DAG: 66 0f c5 c2 05 pextrw eax, xmm2, 5
-; CHECK-DAG: 66 0f c5 c3 07 pextrw eax, xmm3, 7
+; CHECK-DAG: 66 0f c5 c0 00 pextrw eax,xmm0
+; CHECK-DAG: 66 0f c5 c1 02 pextrw eax,xmm1
+; CHECK-DAG: 66 0f c5 c2 05 pextrw eax,xmm2
+; CHECK-DAG: 66 0f c5 c3 07 pextrw eax,xmm3
diff --git a/tests_lit/lit.cfg b/tests_lit/lit.cfg
index b8bde4e..3817ebb 100644
--- a/tests_lit/lit.cfg
+++ b/tests_lit/lit.cfg
@@ -62,10 +62,13 @@
pydir = os.path.join(bin_root, 'pydir')
-# Finding LLVM binary tools. All tools used in the tests must be listed in
-# the llvmbintools list.
+# Finding LLVM binary tools. Tools used in the tests must be listed in
+# the llvmbintools list or binutilsbintools.
llvmbinpath = os.path.abspath(os.environ.get('LLVM_BIN_PATH'))
+# Find binutils tools. This is used for objdump.
+binutilsbinpath = os.path.abspath(os.environ.get('BINUTILS_BIN_PATH'))
+
# Define the location of the llvm2ice tool.
llvm2icetool = os.path.join(bin_root, 'llvm2ice')
llvm2iceatts = shellcmd(' '.join([llvm2icetool, '--build-atts']),
@@ -88,7 +91,8 @@
# Base command for running llvm2ice
llvm2ice_cmd = [os.path.join(pydir, 'run-llvm2ice.py'),
'--llvm2ice', llvm2icetool,
- '--llvm-bin-path', llvmbinpath]
+ '--llvm-bin-path', llvmbinpath,
+ '--binutils-bin-path', binutilsbinpath]
# Run commands only if corresponding build attributes apply, including
# for each compiler setup.
@@ -109,7 +113,6 @@
llvmbintools = [r"\bFileCheck\b",
r"\bllvm-as\b",
r"\bllvm-mc\b",
- r"\bllvm-objdump\b",
r"\bllvm-readobj\b",
r"\bnot\b",
r"\bpnacl-freeze\b",
@@ -126,6 +129,16 @@
tool)
config.substitutions.append((tool, substitution))
+binutilsbintools = [r"\bobjdump\b",]
+
+for tool in binutilsbintools:
+ # The re.sub() line is adapted from one of LLVM's lit.cfg files.
+ # Similar to the llvmbintools.
+ substitution = re.sub(r"^(\\)?((\| )?)\W+b([0-9A-Za-z-_]+)\\b\W*$",
+ r"\2" + binutilsbinpath + "/" + r"\4",
+ tool)
+ config.substitutions.append((tool, substitution))
+
# Add a feature to detect the Python version.
config.available_features.add("python%d.%d" % (sys.version_info[0],
sys.version_info[1]))
@@ -136,4 +149,5 @@
dbg('bin_root = %s' % bin_root)
dbg('llvmbinpath = %s' % llvmbinpath)
+dbg('binutilsbinpath = %s' % binutilsbinpath)
dbg("Build attributes = %s" % llvm2iceatts)
diff --git a/tests_lit/llvm2ice_tests/64bit.pnacl.ll b/tests_lit/llvm2ice_tests/64bit.pnacl.ll
index d6d6afc..e4f4cb0 100644
--- a/tests_lit/llvm2ice_tests/64bit.pnacl.ll
+++ b/tests_lit/llvm2ice_tests/64bit.pnacl.ll
@@ -2,12 +2,9 @@
; particular the patterns for lowering i64 operations into constituent
; i32 operations on x86-32.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args -Om1 --verbose none \
; RUN: | FileCheck --check-prefix=OPTM1 %s
@__init_array_start = internal constant [0 x i8] zeroinitializer, align 4
@@ -31,49 +28,49 @@
}
; CHECK-LABEL: pass64BitArg
; CHECK: sub esp
-; CHECK: mov dword ptr [esp + 4]
-; CHECK: mov dword ptr [esp]
-; CHECK: mov dword ptr [esp + 8], 123
-; CHECK: mov dword ptr [esp + 16]
-; CHECK: mov dword ptr [esp + 12]
-; CHECK: call ignore64BitArgNoInline
+; CHECK: mov DWORD PTR [esp+0x4]
+; CHECK: mov DWORD PTR [esp]
+; CHECK: mov DWORD PTR [esp+0x8],0x7b
+; CHECK: mov DWORD PTR [esp+0x10]
+; CHECK: mov DWORD PTR [esp+0xc]
+; CHECK: call {{.*}} R_{{.*}} ignore64BitArgNoInline
; CHECK: sub esp
-; CHECK: mov dword ptr [esp + 4]
-; CHECK: mov dword ptr [esp]
-; CHECK: mov dword ptr [esp + 8], 123
-; CHECK: mov dword ptr [esp + 16]
-; CHECK: mov dword ptr [esp + 12]
-; CHECK: call ignore64BitArgNoInline
+; CHECK: mov DWORD PTR [esp+0x4]
+; CHECK: mov DWORD PTR [esp]
+; CHECK: mov DWORD PTR [esp+0x8],0x7b
+; CHECK: mov DWORD PTR [esp+0x10]
+; CHECK: mov DWORD PTR [esp+0xc]
+; CHECK: call {{.*}} R_{{.*}} ignore64BitArgNoInline
; CHECK: sub esp
-; CHECK: mov dword ptr [esp + 4]
-; CHECK: mov dword ptr [esp]
-; CHECK: mov dword ptr [esp + 8], 123
-; CHECK: mov dword ptr [esp + 16]
-; CHECK: mov dword ptr [esp + 12]
-; CHECK: call ignore64BitArgNoInline
+; CHECK: mov DWORD PTR [esp+0x4]
+; CHECK: mov DWORD PTR [esp]
+; CHECK: mov DWORD PTR [esp+0x8],0x7b
+; CHECK: mov DWORD PTR [esp+0x10]
+; CHECK: mov DWORD PTR [esp+0xc]
+; CHECK: call {{.*}} R_{{.*}} ignore64BitArgNoInline
;
; OPTM1-LABEL: pass64BitArg
; OPTM1: sub esp
-; OPTM1: mov dword ptr [esp + 4]
-; OPTM1: mov dword ptr [esp]
-; OPTM1: mov dword ptr [esp + 8], 123
-; OPTM1: mov dword ptr [esp + 16]
-; OPTM1: mov dword ptr [esp + 12]
-; OPTM1: call ignore64BitArgNoInline
+; OPTM1: mov DWORD PTR [esp+0x4]
+; OPTM1: mov DWORD PTR [esp]
+; OPTM1: mov DWORD PTR [esp+0x8],0x7b
+; OPTM1: mov DWORD PTR [esp+0x10]
+; OPTM1: mov DWORD PTR [esp+0xc]
+; OPTM1: call {{.*}} R_{{.*}} ignore64BitArgNoInline
; OPTM1: sub esp
-; OPTM1: mov dword ptr [esp + 4]
-; OPTM1: mov dword ptr [esp]
-; OPTM1: mov dword ptr [esp + 8], 123
-; OPTM1: mov dword ptr [esp + 16]
-; OPTM1: mov dword ptr [esp + 12]
-; OPTM1: call ignore64BitArgNoInline
+; OPTM1: mov DWORD PTR [esp+0x4]
+; OPTM1: mov DWORD PTR [esp]
+; OPTM1: mov DWORD PTR [esp+0x8],0x7b
+; OPTM1: mov DWORD PTR [esp+0x10]
+; OPTM1: mov DWORD PTR [esp+0xc]
+; OPTM1: call {{.*}} R_{{.*}} ignore64BitArgNoInline
; OPTM1: sub esp
-; OPTM1: mov dword ptr [esp + 4]
-; OPTM1: mov dword ptr [esp]
-; OPTM1: mov dword ptr [esp + 8], 123
-; OPTM1: mov dword ptr [esp + 16]
-; OPTM1: mov dword ptr [esp + 12]
-; OPTM1: call ignore64BitArgNoInline
+; OPTM1: mov DWORD PTR [esp+0x4]
+; OPTM1: mov DWORD PTR [esp]
+; OPTM1: mov DWORD PTR [esp+0x8],0x7b
+; OPTM1: mov DWORD PTR [esp+0x10]
+; OPTM1: mov DWORD PTR [esp+0xc]
+; OPTM1: call {{.*}} R_{{.*}} ignore64BitArgNoInline
declare i32 @ignore64BitArgNoInline(i64, i32, i64)
@@ -84,50 +81,50 @@
}
; CHECK-LABEL: pass64BitConstArg
; CHECK: sub esp
-; CHECK: mov dword ptr [esp + 4]
-; CHECK-NEXT: mov dword ptr [esp]
-; CHECK-NEXT: mov dword ptr [esp + 8], 123
+; CHECK: mov DWORD PTR [esp+0x4]
+; CHECK-NEXT: mov DWORD PTR [esp]
+; CHECK-NEXT: mov DWORD PTR [esp+0x8],0x7b
; Bundle padding might be added (so not using -NEXT).
-; CHECK: mov dword ptr [esp + 16], 3735928559
-; CHECK-NEXT: mov dword ptr [esp + 12], 305419896
+; CHECK: mov DWORD PTR [esp+0x10],0xdeadbeef
+; CHECK-NEXT: mov DWORD PTR [esp+0xc],0x12345678
; Bundle padding will push the call down.
; CHECK-NOT: mov
-; CHECK: call ignore64BitArgNoInline
+; CHECK: call {{.*}} R_{{.*}} ignore64BitArgNoInline
;
; OPTM1-LABEL: pass64BitConstArg
; OPTM1: sub esp
-; OPTM1: mov dword ptr [esp + 4]
-; OPTM1-NEXT: mov dword ptr [esp]
-; OPTM1-NEXT: mov dword ptr [esp + 8], 123
+; OPTM1: mov DWORD PTR [esp+0x4]
+; OPTM1-NEXT: mov DWORD PTR [esp]
+; OPTM1-NEXT: mov DWORD PTR [esp+0x8],0x7b
; Bundle padding might be added (so not using -NEXT).
-; OPTM1: mov dword ptr [esp + 16], 3735928559
-; OPTM1-NEXT: mov dword ptr [esp + 12], 305419896
+; OPTM1: mov DWORD PTR [esp+0x10],0xdeadbeef
+; OPTM1-NEXT: mov DWORD PTR [esp+0xc],0x12345678
; OPTM1-NOT: mov
-; OPTM1: call ignore64BitArgNoInline
+; OPTM1: call {{.*}} R_{{.*}} ignore64BitArgNoInline
define internal i64 @return64BitArg(i64 %a) {
entry:
ret i64 %a
}
; CHECK-LABEL: return64BitArg
-; CHECK: mov {{.*}}, dword ptr [esp + 4]
-; CHECK: mov {{.*}}, dword ptr [esp + 8]
+; CHECK: mov {{.*}},DWORD PTR [esp+0x4]
+; CHECK: mov {{.*}},DWORD PTR [esp+0x8]
;
; OPTM1-LABEL: return64BitArg
-; OPTM1: mov {{.*}}, dword ptr [esp + 4]
-; OPTM1: mov {{.*}}, dword ptr [esp + 8]
+; OPTM1: mov {{.*}},DWORD PTR [esp+0x4]
+; OPTM1: mov {{.*}},DWORD PTR [esp+0x8]
define internal i64 @return64BitConst() {
entry:
ret i64 -2401053092306725256
}
; CHECK-LABEL: return64BitConst
-; CHECK: mov eax, 305419896
-; CHECK: mov edx, 3735928559
+; CHECK: mov eax,0x12345678
+; CHECK: mov edx,0xdeadbeef
;
; OPTM1-LABEL: return64BitConst
-; OPTM1: mov eax, 305419896
-; OPTM1: mov edx, 3735928559
+; OPTM1: mov eax,0x12345678
+; OPTM1: mov edx,0xdeadbeef
define internal i64 @add64BitSigned(i64 %a, i64 %b) {
entry:
@@ -225,10 +222,10 @@
ret i64 %div
}
; CHECK-LABEL: div64BitSigned
-; CHECK: call __divdi3
+; CHECK: call {{.*}} R_{{.*}} __divdi3
; OPTM1-LABEL: div64BitSigned
-; OPTM1: call __divdi3
+; OPTM1: call {{.*}} R_{{.*}} __divdi3
define internal i64 @div64BitSignedConst(i64 %a) {
entry:
@@ -236,14 +233,14 @@
ret i64 %div
}
; CHECK-LABEL: div64BitSignedConst
-; CHECK: mov dword ptr [esp + 12], 2874
-; CHECK: mov dword ptr [esp + 8], 1942892530
-; CHECK: call __divdi3
+; CHECK: mov DWORD PTR [esp+0xc],0xb3a
+; CHECK: mov DWORD PTR [esp+0x8],0x73ce2ff2
+; CHECK: call {{.*}} R_{{.*}} __divdi3
;
; OPTM1-LABEL: div64BitSignedConst
-; OPTM1: mov dword ptr [esp + 12], 2874
-; OPTM1: mov dword ptr [esp + 8], 1942892530
-; OPTM1: call __divdi3
+; OPTM1: mov DWORD PTR [esp+0xc],0xb3a
+; OPTM1: mov DWORD PTR [esp+0x8],0x73ce2ff2
+; OPTM1: call {{.*}} R_{{.*}} __divdi3
define internal i64 @div64BitUnsigned(i64 %a, i64 %b) {
entry:
@@ -251,10 +248,10 @@
ret i64 %div
}
; CHECK-LABEL: div64BitUnsigned
-; CHECK: call __udivdi3
+; CHECK: call {{.*}} R_{{.*}} __udivdi3
;
; OPTM1-LABEL: div64BitUnsigned
-; OPTM1: call __udivdi3
+; OPTM1: call {{.*}} R_{{.*}} __udivdi3
define internal i64 @rem64BitSigned(i64 %a, i64 %b) {
entry:
@@ -262,10 +259,10 @@
ret i64 %rem
}
; CHECK-LABEL: rem64BitSigned
-; CHECK: call __moddi3
+; CHECK: call {{.*}} R_{{.*}} __moddi3
;
; OPTM1-LABEL: rem64BitSigned
-; OPTM1: call __moddi3
+; OPTM1: call {{.*}} R_{{.*}} __moddi3
define internal i64 @rem64BitUnsigned(i64 %a, i64 %b) {
entry:
@@ -273,10 +270,10 @@
ret i64 %rem
}
; CHECK-LABEL: rem64BitUnsigned
-; CHECK: call __umoddi3
+; CHECK: call {{.*}} R_{{.*}} __umoddi3
;
; OPTM1-LABEL: rem64BitUnsigned
-; OPTM1: call __umoddi3
+; OPTM1: call {{.*}} R_{{.*}} __umoddi3
define internal i64 @shl64BitSigned(i64 %a, i64 %b) {
entry:
@@ -286,13 +283,13 @@
; CHECK-LABEL: shl64BitSigned
; CHECK: shld
; CHECK: shl e
-; CHECK: test {{.*}}, 32
+; CHECK: test {{.*}},0x20
; CHECK: je
;
; OPTM1-LABEL: shl64BitSigned
; OPTM1: shld
; OPTM1: shl e
-; OPTM1: test {{.*}}, 32
+; OPTM1: test {{.*}},0x20
; OPTM1: je
define internal i32 @shl64BitSignedTrunc(i64 %a, i64 %b) {
@@ -304,13 +301,13 @@
; CHECK-LABEL: shl64BitSignedTrunc
; CHECK: mov
; CHECK: shl e
-; CHECK: test {{.*}}, 32
+; CHECK: test {{.*}},0x20
; CHECK: je
;
; OPTM1-LABEL: shl64BitSignedTrunc
; OPTM1: shld
; OPTM1: shl e
-; OPTM1: test {{.*}}, 32
+; OPTM1: test {{.*}},0x20
; OPTM1: je
define internal i64 @shl64BitUnsigned(i64 %a, i64 %b) {
@@ -321,13 +318,13 @@
; CHECK-LABEL: shl64BitUnsigned
; CHECK: shld
; CHECK: shl e
-; CHECK: test {{.*}}, 32
+; CHECK: test {{.*}},0x20
; CHECK: je
;
; OPTM1-LABEL: shl64BitUnsigned
; OPTM1: shld
; OPTM1: shl e
-; OPTM1: test {{.*}}, 32
+; OPTM1: test {{.*}},0x20
; OPTM1: je
define internal i64 @shr64BitSigned(i64 %a, i64 %b) {
@@ -338,16 +335,16 @@
; CHECK-LABEL: shr64BitSigned
; CHECK: shrd
; CHECK: sar
-; CHECK: test {{.*}}, 32
+; CHECK: test {{.*}},0x20
; CHECK: je
-; CHECK: sar {{.*}}, 31
+; CHECK: sar {{.*}},0x1f
;
; OPTM1-LABEL: shr64BitSigned
; OPTM1: shrd
; OPTM1: sar
-; OPTM1: test {{.*}}, 32
+; OPTM1: test {{.*}},0x20
; OPTM1: je
-; OPTM1: sar {{.*}}, 31
+; OPTM1: sar {{.*}},0x1f
define internal i32 @shr64BitSignedTrunc(i64 %a, i64 %b) {
entry:
@@ -358,15 +355,15 @@
; CHECK-LABEL: shr64BitSignedTrunc
; CHECK: shrd
; CHECK: sar
-; CHECK: test {{.*}}, 32
+; CHECK: test {{.*}},0x20
; CHECK: je
;
; OPTM1-LABEL: shr64BitSignedTrunc
; OPTM1: shrd
; OPTM1: sar
-; OPTM1: test {{.*}}, 32
+; OPTM1: test {{.*}},0x20
; OPTM1: je
-; OPTM1: sar {{.*}}, 31
+; OPTM1: sar {{.*}},0x1f
define internal i64 @shr64BitUnsigned(i64 %a, i64 %b) {
entry:
@@ -376,13 +373,13 @@
; CHECK-LABEL: shr64BitUnsigned
; CHECK: shrd
; CHECK: shr
-; CHECK: test {{.*}}, 32
+; CHECK: test {{.*}},0x20
; CHECK: je
;
; OPTM1-LABEL: shr64BitUnsigned
; OPTM1: shrd
; OPTM1: shr
-; OPTM1: test {{.*}}, 32
+; OPTM1: test {{.*}},0x20
; OPTM1: je
define internal i32 @shr64BitUnsignedTrunc(i64 %a, i64 %b) {
@@ -394,13 +391,13 @@
; CHECK-LABEL: shr64BitUnsignedTrunc
; CHECK: shrd
; CHECK: shr
-; CHECK: test {{.*}}, 32
+; CHECK: test {{.*}},0x20
; CHECK: je
;
; OPTM1-LABEL: shr64BitUnsignedTrunc
; OPTM1: shrd
; OPTM1: shr
-; OPTM1: test {{.*}}, 32
+; OPTM1: test {{.*}},0x20
; OPTM1: je
define internal i64 @and64BitSigned(i64 %a, i64 %b) {
@@ -487,10 +484,10 @@
ret i32 %conv
}
; CHECK-LABEL: trunc64To32Signed
-; CHECK: mov eax, dword ptr [esp + 4]
+; CHECK: mov eax,DWORD PTR [esp+0x4]
;
; OPTM1-LABEL: trunc64To32Signed
-; OPTM1: mov eax, dword ptr [esp +
+; OPTM1: mov eax,DWORD PTR [esp+
define internal i32 @trunc64To16Signed(i64 %a) {
entry:
@@ -499,11 +496,11 @@
ret i32 %conv.ret_ext
}
; CHECK-LABEL: trunc64To16Signed
-; CHECK: mov eax, dword ptr [esp + 4]
-; CHECK-NEXT: movsx eax, ax
+; CHECK: mov eax,DWORD PTR [esp+0x4]
+; CHECK-NEXT: movsx eax,ax
;
; OPTM1-LABEL: trunc64To16Signed
-; OPTM1: mov eax, dword ptr [esp +
+; OPTM1: mov eax,DWORD PTR [esp+
; OPTM1: movsx eax,
define internal i32 @trunc64To8Signed(i64 %a) {
@@ -513,11 +510,11 @@
ret i32 %conv.ret_ext
}
; CHECK-LABEL: trunc64To8Signed
-; CHECK: mov eax, dword ptr [esp + 4]
-; CHECK-NEXT: movsx eax, al
+; CHECK: mov eax,DWORD PTR [esp+0x4]
+; CHECK-NEXT: movsx eax,al
;
; OPTM1-LABEL: trunc64To8Signed
-; OPTM1: mov eax, dword ptr [esp +
+; OPTM1: mov eax,DWORD PTR [esp+
; OPTM1: movsx eax,
define internal i32 @trunc64To32SignedConst() {
@@ -526,10 +523,10 @@
ret i32 %conv
}
; CHECK-LABEL: trunc64To32SignedConst
-; CHECK: mov eax, 1942892530
+; CHECK: mov eax,0x73ce2ff2
;
; OPTM1-LABEL: trunc64To32SignedConst
-; OPTM1: mov eax, 1942892530
+; OPTM1: mov eax,0x73ce2ff2
define internal i32 @trunc64To16SignedConst() {
entry:
@@ -538,11 +535,11 @@
ret i32 %conv.ret_ext
}
; CHECK-LABEL: trunc64To16SignedConst
-; CHECK: mov eax, 1942892530
-; CHECK: movsx eax, ax
+; CHECK: mov eax,0x73ce2ff2
+; CHECK: movsx eax,ax
;
; OPTM1-LABEL: trunc64To16SignedConst
-; OPTM1: mov eax, 1942892530
+; OPTM1: mov eax,0x73ce2ff2
; OPTM1: movsx eax,
define internal i32 @trunc64To32Unsigned(i64 %a) {
@@ -551,10 +548,10 @@
ret i32 %conv
}
; CHECK-LABEL: trunc64To32Unsigned
-; CHECK: mov eax, dword ptr [esp + 4]
+; CHECK: mov eax,DWORD PTR [esp+0x4]
;
; OPTM1-LABEL: trunc64To32Unsigned
-; OPTM1: mov eax, dword ptr [esp +
+; OPTM1: mov eax,DWORD PTR [esp+
define internal i32 @trunc64To16Unsigned(i64 %a) {
entry:
@@ -563,11 +560,11 @@
ret i32 %conv.ret_ext
}
; CHECK-LABEL: trunc64To16Unsigned
-; CHECK: mov eax, dword ptr [esp + 4]
-; CHECK-NEXT: movzx eax, ax
+; CHECK: mov eax,DWORD PTR [esp+0x4]
+; CHECK-NEXT: movzx eax,ax
;
; OPTM1-LABEL: trunc64To16Unsigned
-; OPTM1: mov eax, dword ptr [esp +
+; OPTM1: mov eax,DWORD PTR [esp+
; OPTM1: movzx eax,
define internal i32 @trunc64To8Unsigned(i64 %a) {
@@ -577,11 +574,11 @@
ret i32 %conv.ret_ext
}
; CHECK-LABEL: trunc64To8Unsigned
-; CHECK: mov eax, dword ptr [esp + 4]
-; CHECK-NEXT: movzx eax, al
+; CHECK: mov eax,DWORD PTR [esp+0x4]
+; CHECK-NEXT: movzx eax,al
;
; OPTM1-LABEL: trunc64To8Unsigned
-; OPTM1: mov eax, dword ptr [esp +
+; OPTM1: mov eax,DWORD PTR [esp+
; OPTM1: movzx eax,
define internal i32 @trunc64To1(i64 %a) {
@@ -592,14 +589,14 @@
ret i32 %tobool.ret_ext
}
; CHECK-LABEL: trunc64To1
-; CHECK: mov eax, dword ptr [esp + 4]
-; CHECK: and eax, 1
-; CHECK: and eax, 1
+; CHECK: mov eax,DWORD PTR [esp+0x4]
+; CHECK: and eax,0x1
+; CHECK: and eax,0x1
;
; OPTM1-LABEL: trunc64To1
-; OPTM1: mov eax, dword ptr [esp +
-; OPTM1: and eax, 1
-; OPTM1: and eax, 1
+; OPTM1: mov eax,DWORD PTR [esp+
+; OPTM1: and eax,0x1
+; OPTM1: and eax,0x1
define internal i64 @sext32To64(i32 %a) {
entry:
@@ -608,11 +605,11 @@
}
; CHECK-LABEL: sext32To64
; CHECK: mov
-; CHECK: sar {{.*}}, 31
+; CHECK: sar {{.*}},0x1f
;
; OPTM1-LABEL: sext32To64
; OPTM1: mov
-; OPTM1: sar {{.*}}, 31
+; OPTM1: sar {{.*}},0x1f
define internal i64 @sext16To64(i32 %a) {
entry:
@@ -622,11 +619,11 @@
}
; CHECK-LABEL: sext16To64
; CHECK: movsx
-; CHECK: sar {{.*}}, 31
+; CHECK: sar {{.*}},0x1f
;
; OPTM1-LABEL: sext16To64
; OPTM1: movsx
-; OPTM1: sar {{.*}}, 31
+; OPTM1: sar {{.*}},0x1f
define internal i64 @sext8To64(i32 %a) {
entry:
@@ -636,11 +633,11 @@
}
; CHECK-LABEL: sext8To64
; CHECK: movsx
-; CHECK: sar {{.*}}, 31
+; CHECK: sar {{.*}},0x1f
;
; OPTM1-LABEL: sext8To64
; OPTM1: movsx
-; OPTM1: sar {{.*}}, 31
+; OPTM1: sar {{.*}},0x1f
define internal i64 @sext1To64(i32 %a) {
entry:
@@ -650,13 +647,13 @@
}
; CHECK-LABEL: sext1To64
; CHECK: mov
-; CHECK: shl {{.*}}, 31
-; CHECK: sar {{.*}}, 31
+; CHECK: shl {{.*}},0x1f
+; CHECK: sar {{.*}},0x1f
;
; OPTM1-LABEL: sext1To64
; OPTM1: mov
-; OPTM1: shl {{.*}}, 31
-; OPTM1: sar {{.*}}, 31
+; OPTM1: shl {{.*}},0x1f
+; OPTM1: sar {{.*}},0x1f
define internal i64 @zext32To64(i32 %a) {
entry:
@@ -665,11 +662,11 @@
}
; CHECK-LABEL: zext32To64
; CHECK: mov
-; CHECK: mov {{.*}}, 0
+; CHECK: mov {{.*}},0x0
;
; OPTM1-LABEL: zext32To64
; OPTM1: mov
-; OPTM1: mov {{.*}}, 0
+; OPTM1: mov {{.*}},0x0
define internal i64 @zext16To64(i32 %a) {
entry:
@@ -679,11 +676,11 @@
}
; CHECK-LABEL: zext16To64
; CHECK: movzx
-; CHECK: mov {{.*}}, 0
+; CHECK: mov {{.*}},0x0
;
; OPTM1-LABEL: zext16To64
; OPTM1: movzx
-; OPTM1: mov {{.*}}, 0
+; OPTM1: mov {{.*}},0x0
define internal i64 @zext8To64(i32 %a) {
entry:
@@ -693,11 +690,11 @@
}
; CHECK-LABEL: zext8To64
; CHECK: movzx
-; CHECK: mov {{.*}}, 0
+; CHECK: mov {{.*}},0x0
;
; OPTM1-LABEL: zext8To64
; OPTM1: movzx
-; OPTM1: mov {{.*}}, 0
+; OPTM1: mov {{.*}},0x0
define internal i64 @zext1To64(i32 %a) {
entry:
@@ -706,12 +703,12 @@
ret i64 %conv
}
; CHECK-LABEL: zext1To64
-; CHECK: and {{.*}}, 1
-; CHECK: mov {{.*}}, 0
+; CHECK: and {{.*}},0x1
+; CHECK: mov {{.*}},0x0
;
; OPTM1-LABEL: zext1To64
-; OPTM1: and {{.*}}, 1
-; OPTM1: mov {{.*}}, 0
+; OPTM1: and {{.*}},0x1
+; OPTM1: mov {{.*}},0x0
define internal void @icmpEq64(i64 %a, i64 %b, i64 %c, i64 %d) {
entry:
@@ -1142,13 +1139,13 @@
ret i64 %v0
}
; CHECK-LABEL: load64
-; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp + 4]
-; CHECK-NEXT: mov {{.*}}, dword ptr [e[[REGISTER]]]
-; CHECK-NEXT: mov {{.*}}, dword ptr [e[[REGISTER]] + 4]
+; CHECK: mov e[[REGISTER:[a-z]+]],DWORD PTR [esp+0x4]
+; CHECK-NEXT: mov {{.*}},DWORD PTR [e[[REGISTER]]]
+; CHECK-NEXT: mov {{.*}},DWORD PTR [e[[REGISTER]]+0x4]
;
; OPTM1-LABEL: load64
-; OPTM1: mov e{{..}}, dword ptr [e{{..}}]
-; OPTM1: mov e{{..}}, dword ptr [e{{..}} + 4]
+; OPTM1: mov e{{..}},DWORD PTR [e{{..}}]
+; OPTM1: mov e{{..}},DWORD PTR [e{{..}}+0x4]
define internal void @store64(i32 %a, i64 %value) {
entry:
@@ -1157,13 +1154,13 @@
ret void
}
; CHECK-LABEL: store64
-; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp + 4]
-; CHECK: mov dword ptr [e[[REGISTER]] + 4],
-; CHECK: mov dword ptr [e[[REGISTER]]],
+; CHECK: mov e[[REGISTER:[a-z]+]],DWORD PTR [esp+0x4]
+; CHECK: mov DWORD PTR [e[[REGISTER]]+0x4],
+; CHECK: mov DWORD PTR [e[[REGISTER]]],
;
; OPTM1-LABEL: store64
-; OPTM1: mov dword ptr [e[[REGISTER:[a-z]+]] + 4],
-; OPTM1: mov dword ptr [e[[REGISTER]]],
+; OPTM1: mov DWORD PTR [e[[REGISTER:[a-z]+]]+0x4],
+; OPTM1: mov DWORD PTR [e[[REGISTER]]],
define internal void @store64Const(i32 %a) {
entry:
@@ -1172,13 +1169,13 @@
ret void
}
; CHECK-LABEL: store64Const
-; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp + 4]
-; CHECK: mov dword ptr [e[[REGISTER]] + 4], 3735928559
-; CHECK: mov dword ptr [e[[REGISTER]]], 305419896
+; CHECK: mov e[[REGISTER:[a-z]+]],DWORD PTR [esp+0x4]
+; CHECK: mov DWORD PTR [e[[REGISTER]]+0x4],0xdeadbeef
+; CHECK: mov DWORD PTR [e[[REGISTER]]],0x12345678
;
; OPTM1-LABEL: store64Const
-; OPTM1: mov dword ptr [e[[REGISTER:[a-z]+]] + 4], 3735928559
-; OPTM1: mov dword ptr [e[[REGISTER]]], 305419896
+; OPTM1: mov DWORD PTR [e[[REGISTER:[a-z]+]]+0x4],0xdeadbeef
+; OPTM1: mov DWORD PTR [e[[REGISTER]]],0x12345678
define internal i64 @select64VarVar(i64 %a, i64 %b) {
entry:
@@ -1275,9 +1272,9 @@
; The following checks are not strictly necessary since one of the RUN
; lines actually runs the output through the assembler.
; CHECK-LABEL: icmpEq64Imm
-; CHECK-NOT: cmp {{[0-9]+}},
+; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
; OPTM1-LABEL: icmpEq64Imm
-; OPTM1-LABEL-NOT: cmp {{[0-9]+}},
+; OPTM1-LABEL-NOT: cmp 0x{{[0-9a-f]+}},
define internal void @icmpLt64Imm() {
entry:
@@ -1302,6 +1299,6 @@
; The following checks are not strictly necessary since one of the RUN
; lines actually runs the output through the assembler.
; CHECK-LABEL: icmpLt64Imm
-; CHECK-NOT: cmp {{[0-9]+}},
+; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
; OPTM1-LABEL: icmpLt64Imm
-; OPTM1-NOT: cmp {{[0-9]+}},
+; OPTM1-NOT: cmp 0x{{[0-9a-f]+}},
diff --git a/tests_lit/llvm2ice_tests/8bit.pnacl.ll b/tests_lit/llvm2ice_tests/8bit.pnacl.ll
index 319e684..a60512d 100644
--- a/tests_lit/llvm2ice_tests/8bit.pnacl.ll
+++ b/tests_lit/llvm2ice_tests/8bit.pnacl.ll
@@ -1,11 +1,9 @@
; This tries to be a comprehensive test of i8 operations.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args -Om1 --verbose none \
+; RUN: | FileCheck %s
define internal i32 @add8Bit(i32 %a, i32 %b) {
entry:
@@ -58,7 +56,7 @@
ret i32 %ret
}
; CHECK-LABEL: mul8Bit
-; CHECK: mul {{[abcd]l|byte ptr}}
+; CHECK: mul {{[abcd]l|BYTE PTR}}
define internal i32 @mul8BitConst(i32 %a) {
entry:
@@ -69,8 +67,8 @@
}
; CHECK-LABEL: mul8BitConst
; 8-bit imul only accepts r/m, not imm
-; CHECK: mov {{.*}}, 56
-; CHECK: mul {{[abcd]l|byte ptr}}
+; CHECK: mov {{.*}},0x38
+; CHECK: mul {{[abcd]l|BYTE PTR}}
define internal i32 @udiv8Bit(i32 %a, i32 %b) {
entry:
@@ -81,7 +79,7 @@
ret i32 %ret
}
; CHECK-LABEL: udiv8Bit
-; CHECK: div {{[abcd]l|byte ptr}}
+; CHECK: div {{[abcd]l|BYTE PTR}}
define internal i32 @udiv8BitConst(i32 %a) {
entry:
@@ -91,7 +89,7 @@
ret i32 %ret
}
; CHECK-LABEL: udiv8BitConst
-; CHECK: div {{[abcd]l|byte ptr}}
+; CHECK: div {{[abcd]l|BYTE PTR}}
define internal i32 @urem8Bit(i32 %a, i32 %b) {
entry:
@@ -102,7 +100,7 @@
ret i32 %ret
}
; CHECK-LABEL: urem8Bit
-; CHECK: div {{[abcd]l|byte ptr}}
+; CHECK: div {{[abcd]l|BYTE PTR}}
define internal i32 @urem8BitConst(i32 %a) {
entry:
@@ -112,7 +110,7 @@
ret i32 %ret
}
; CHECK-LABEL: urem8BitConst
-; CHECK: div {{[abcd]l|byte ptr}}
+; CHECK: div {{[abcd]l|BYTE PTR}}
define internal i32 @sdiv8Bit(i32 %a, i32 %b) {
@@ -124,7 +122,7 @@
ret i32 %ret
}
; CHECK-LABEL: sdiv8Bit
-; CHECK: idiv {{[abcd]l|byte ptr}}
+; CHECK: idiv {{[abcd]l|BYTE PTR}}
define internal i32 @sdiv8BitConst(i32 %a) {
entry:
@@ -134,7 +132,7 @@
ret i32 %ret
}
; CHECK-LABEL: sdiv8BitConst
-; CHECK: idiv {{[abcd]l|byte ptr}}
+; CHECK: idiv {{[abcd]l|BYTE PTR}}
define internal i32 @srem8Bit(i32 %a, i32 %b) {
entry:
@@ -145,7 +143,7 @@
ret i32 %ret
}
; CHECK-LABEL: srem8Bit
-; CHECK: idiv {{[abcd]l|byte ptr}}
+; CHECK: idiv {{[abcd]l|BYTE PTR}}
define internal i32 @srem8BitConst(i32 %a) {
entry:
@@ -155,7 +153,7 @@
ret i32 %ret
}
; CHECK-LABEL: srem8BitConst
-; CHECK: idiv {{[abcd]l|byte ptr}}
+; CHECK: idiv {{[abcd]l|BYTE PTR}}
define internal i32 @shl8Bit(i32 %a, i32 %b) {
entry:
@@ -166,7 +164,7 @@
ret i32 %ret
}
; CHECK-LABEL: shl8Bit
-; CHECK: shl {{[abd]l|byte ptr}}, cl
+; CHECK: shl {{[abd]l|BYTE PTR}},cl
define internal i32 @shl8BitConst(i32 %a, i32 %b) {
entry:
@@ -176,7 +174,7 @@
ret i32 %ret
}
; CHECK-LABEL: shl8BitConst
-; CHECK: shl {{[abcd]l|byte ptr}}, 6
+; CHECK: shl {{[abcd]l|BYTE PTR}},0x6
define internal i32 @lshr8Bit(i32 %a, i32 %b) {
entry:
@@ -187,7 +185,7 @@
ret i32 %ret
}
; CHECK-LABEL: lshr8Bit
-; CHECK: shr {{[abd]l|byte ptr}}, cl
+; CHECK: shr {{[abd]l|BYTE PTR}},cl
define internal i32 @lshr8BitConst(i32 %a, i32 %b) {
entry:
@@ -197,7 +195,7 @@
ret i32 %ret
}
; CHECK-LABEL: lshr8BitConst
-; CHECK: shr {{[abcd]l|byte ptr}}, 6
+; CHECK: shr {{[abcd]l|BYTE PTR}},0x6
define internal i32 @ashr8Bit(i32 %a, i32 %b) {
entry:
@@ -208,7 +206,7 @@
ret i32 %ret
}
; CHECK-LABEL: ashr8Bit
-; CHECK: sar {{[abd]l|byte ptr}}, cl
+; CHECK: sar {{[abd]l|BYTE PTR}},cl
define internal i32 @ashr8BitConst(i32 %a, i32 %b) {
entry:
@@ -218,7 +216,7 @@
ret i32 %ret
}
; CHECK-LABEL: ashr8BitConst
-; CHECK: sar {{[abcd]l|byte ptr}}, 6
+; CHECK: sar {{[abcd]l|BYTE PTR}},0x6
define internal i32 @icmp8Bit(i32 %a, i32 %b) {
entry:
@@ -229,7 +227,7 @@
ret i32 %ret
}
; CHECK-LABEL: icmp8Bit
-; CHECK: cmp {{[abcd]l|byte ptr}}
+; CHECK: cmp {{[abcd]l|BYTE PTR}}
define internal i32 @icmp8BitConst(i32 %a) {
entry:
@@ -239,7 +237,7 @@
ret i32 %ret
}
; CHECK-LABEL: icmp8BitConst
-; CHECK: cmp {{[abcd]l|byte ptr}}
+; CHECK: cmp {{[abcd]l|BYTE PTR}}
define internal i32 @icmp8BitConstSwapped(i32 %a) {
entry:
@@ -249,7 +247,7 @@
ret i32 %ret
}
; CHECK-LABEL: icmp8BitConstSwapped
-; CHECK: cmp {{[abcd]l|byte ptr}}
+; CHECK: cmp {{[abcd]l|BYTE PTR}}
define internal i32 @icmp8BitMem(i32 %a, i32 %b_iptr) {
entry:
@@ -261,7 +259,7 @@
ret i32 %ret
}
; CHECK-LABEL: icmp8BitMem
-; CHECK: cmp {{[abcd]l|byte ptr}}
+; CHECK: cmp {{[abcd]l|BYTE PTR}}
define internal i32 @icmp8BitMemSwapped(i32 %a, i32 %b_iptr) {
entry:
@@ -273,7 +271,7 @@
ret i32 %ret
}
; CHECK-LABEL: icmp8BitMemSwapped
-; CHECK: cmp {{[abcd]l|byte ptr}}
+; CHECK: cmp {{[abcd]l|BYTE PTR}}
define internal i32 @selectI8Var(i32 %a, i32 %b) {
entry:
@@ -324,9 +322,9 @@
}
; CHECK-LABEL: testPhi8
; This assumes there will be some copy from an 8-bit register / stack slot.
-; CHECK-DAG: mov {{.*}}, {{[a-d]}}l
-; CHECK-DAG: mov {{.*}}, byte ptr
-; CHECK-DAG: mov byte ptr {{.*}}
+; CHECK-DAG: mov {{.*}},{{[a-d]}}l
+; CHECK-DAG: mov {{.*}},BYTE PTR
+; CHECK-DAG: mov BYTE PTR {{.*}}
@global8 = internal global [1 x i8] c"\01", align 4
@@ -338,7 +336,7 @@
ret i32 %ret_ext
}
; CHECK-LABEL: load_i8
-; CHECK: mov {{[a-d]l}}, byte ptr
+; CHECK: mov {{[a-d]l}},BYTE PTR
define i32 @load_i8_global(i32 %addr_arg) {
entry:
@@ -348,7 +346,7 @@
ret i32 %ret_ext
}
; CHECK-LABEL: load_i8_global
-; CHECK: mov {{[a-d]l}}, byte ptr
+; CHECK: mov {{[a-d]l}},BYTE PTR
define void @store_i8(i32 %addr_arg, i32 %val) {
entry:
@@ -358,7 +356,7 @@
ret void
}
; CHECK-LABEL: store_i8
-; CHECK: mov byte ptr {{.*}}, {{[a-d]l}}
+; CHECK: mov BYTE PTR {{.*}},{{[a-d]l}}
define void @store_i8_const(i32 %addr_arg) {
entry:
@@ -367,4 +365,4 @@
ret void
}
; CHECK-LABEL: store_i8_const
-; CHECK: mov byte ptr {{.*}}, 123
+; CHECK: mov BYTE PTR {{.*}},0x7b
diff --git a/tests_lit/llvm2ice_tests/address-mode-opt.ll b/tests_lit/llvm2ice_tests/address-mode-opt.ll
index 321945f..6b40f26 100644
--- a/tests_lit/llvm2ice_tests/address-mode-opt.ll
+++ b/tests_lit/llvm2ice_tests/address-mode-opt.ll
@@ -1,12 +1,9 @@
; This file checks support for address mode optimization.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -O2 -mattr=sse4.1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
-; RUN: | FileCheck --check-prefix=SSE41 %s
+; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args -O2 -mattr=sse4.1 \
+; RUN: --verbose none | FileCheck --check-prefix=SSE41 %s
define float @load_arg_plus_200000(float* %arg) {
entry:
@@ -15,8 +12,8 @@
%addr.ptr = inttoptr i32 %addr.int to float*
%addr.load = load float* %addr.ptr, align 4
ret float %addr.load
-; CHECK-LABEL: load_arg_plus_200000:
-; CHECK: movss xmm0, dword ptr [eax + 200000]
+; CHECK-LABEL: load_arg_plus_200000
+; CHECK: movss xmm0,DWORD PTR [eax+0x30d40]
}
define float @load_200000_plus_arg(float* %arg) {
@@ -26,8 +23,8 @@
%addr.ptr = inttoptr i32 %addr.int to float*
%addr.load = load float* %addr.ptr, align 4
ret float %addr.load
-; CHECK-LABEL: load_200000_plus_arg:
-; CHECK: movss xmm0, dword ptr [eax + 200000]
+; CHECK-LABEL: load_200000_plus_arg
+; CHECK: movss xmm0,DWORD PTR [eax+0x30d40]
}
define float @load_arg_minus_200000(float* %arg) {
@@ -37,8 +34,8 @@
%addr.ptr = inttoptr i32 %addr.int to float*
%addr.load = load float* %addr.ptr, align 4
ret float %addr.load
-; CHECK-LABEL: load_arg_minus_200000:
-; CHECK: movss xmm0, dword ptr [eax - 200000]
+; CHECK-LABEL: load_arg_minus_200000
+; CHECK: movss xmm0,DWORD PTR [eax-0x30d40]
}
define float @load_200000_minus_arg(float* %arg) {
@@ -48,8 +45,8 @@
%addr.ptr = inttoptr i32 %addr.int to float*
%addr.load = load float* %addr.ptr, align 4
ret float %addr.load
-; CHECK-LABEL: load_200000_minus_arg:
-; CHECK: movss xmm0, dword ptr [e{{..}}]
+; CHECK-LABEL: load_200000_minus_arg
+; CHECK: movss xmm0,DWORD PTR [e{{..}}]
}
define <8 x i16> @load_mul_v8i16_mem(<8 x i16> %arg0, i32 %arg1_iptr) {
@@ -59,8 +56,8 @@
%arg1 = load <8 x i16>* %addr_ptr, align 2
%res_vec = mul <8 x i16> %arg0, %arg1
ret <8 x i16> %res_vec
-; CHECK-LABEL: load_mul_v8i16_mem:
-; CHECK: pmullw xmm{{.*}}, xmmword ptr [e{{.*}} - 200000]
+; CHECK-LABEL: load_mul_v8i16_mem
+; CHECK: pmullw xmm{{.*}},XMMWORD PTR [e{{.*}}-0x30d40]
}
define <4 x i32> @load_mul_v4i32_mem(<4 x i32> %arg0, i32 %arg1_iptr) {
@@ -70,12 +67,12 @@
%arg1 = load <4 x i32>* %addr_ptr, align 4
%res = mul <4 x i32> %arg0, %arg1
ret <4 x i32> %res
-; CHECK-LABEL: load_mul_v4i32_mem:
-; CHECK: pmuludq xmm{{.*}}, xmmword ptr [e{{.*}} - 200000]
+; CHECK-LABEL: load_mul_v4i32_mem
+; CHECK: pmuludq xmm{{.*}},XMMWORD PTR [e{{.*}}-0x30d40]
; CHECK: pmuludq
;
-; SSE41-LABEL: load_mul_v4i32_mem:
-; SSE41: pmulld xmm{{.*}}, xmmword ptr [e{{.*}} - 200000]
+; SSE41-LABEL: load_mul_v4i32_mem
+; SSE41: pmulld xmm{{.*}},XMMWORD PTR [e{{.*}}-0x30d40]
}
define float @address_mode_opt_chaining(float* %arg) {
@@ -86,8 +83,8 @@
%addr2.ptr = inttoptr i32 %addr2.int to float*
%addr2.load = load float* %addr2.ptr, align 4
ret float %addr2.load
-; CHECK-LABEL: address_mode_opt_chaining:
-; CHECK: movss xmm0, dword ptr [eax + 8]
+; CHECK-LABEL: address_mode_opt_chaining
+; CHECK: movss xmm0,DWORD PTR [eax+0x8]
}
define float @address_mode_opt_chaining_overflow(float* %arg) {
@@ -98,9 +95,9 @@
%addr2.ptr = inttoptr i32 %addr2.int to float*
%addr2.load = load float* %addr2.ptr, align 4
ret float %addr2.load
-; CHECK-LABEL: address_mode_opt_chaining_overflow:
-; CHECK: 2147483640
-; CHECK: movss xmm0, dword ptr [{{.*}} + 2147483643]
+; CHECK-LABEL: address_mode_opt_chaining_overflow
+; CHECK: 0x7ffffff8
+; CHECK: movss xmm0,DWORD PTR [{{.*}}+0x7ffffffb]
}
define float @address_mode_opt_chaining_overflow_sub(float* %arg) {
@@ -111,9 +108,9 @@
%addr2.ptr = inttoptr i32 %addr2.int to float*
%addr2.load = load float* %addr2.ptr, align 4
ret float %addr2.load
-; CHECK-LABEL: address_mode_opt_chaining_overflow_sub:
-; CHECK: 2147483640
-; CHECK: movss xmm0, dword ptr [{{.*}} - 2147483643]
+; CHECK-LABEL: address_mode_opt_chaining_overflow_sub
+; CHECK: 0x7ffffff8
+; CHECK: movss xmm0,DWORD PTR [{{.*}}-0x7ffffffb]
}
define float @address_mode_opt_chaining_no_overflow(float* %arg) {
@@ -124,8 +121,8 @@
%addr2.ptr = inttoptr i32 %addr2.int to float*
%addr2.load = load float* %addr2.ptr, align 4
ret float %addr2.load
-; CHECK-LABEL: address_mode_opt_chaining_no_overflow:
-; CHECK: movss xmm0, dword ptr [{{.*}} + 3]
+; CHECK-LABEL: address_mode_opt_chaining_no_overflow
+; CHECK: movss xmm0,DWORD PTR [{{.*}}+0x3]
}
define float @address_mode_opt_add_pos_min_int(float* %arg) {
@@ -135,8 +132,8 @@
%addr1.ptr = inttoptr i32 %addr1.int to float*
%addr1.load = load float* %addr1.ptr, align 4
ret float %addr1.load
-; CHECK-LABEL: address_mode_opt_add_pos_min_int:
-; CHECK: movss xmm0, dword ptr [{{.*}} - 2147483648]
+; CHECK-LABEL: address_mode_opt_add_pos_min_int
+; CHECK: movss xmm0,DWORD PTR [{{.*}}-0x80000000]
}
define float @address_mode_opt_sub_min_int(float* %arg) {
@@ -146,6 +143,6 @@
%addr1.ptr = inttoptr i32 %addr1.int to float*
%addr1.load = load float* %addr1.ptr, align 4
ret float %addr1.load
-; CHECK-LABEL: address_mode_opt_sub_min_int:
-; CHECK: movss xmm0, dword ptr [{{.*}} - 2147483648]
+; CHECK-LABEL: address_mode_opt_sub_min_int
+; CHECK: movss xmm0,DWORD PTR [{{.*}}-0x80000000]
}
diff --git a/tests_lit/llvm2ice_tests/align-spill-locations.ll b/tests_lit/llvm2ice_tests/align-spill-locations.ll
index fc7ac2b..9092596 100644
--- a/tests_lit/llvm2ice_tests/align-spill-locations.ll
+++ b/tests_lit/llvm2ice_tests/align-spill-locations.ll
@@ -1,11 +1,9 @@
; This checks to ensure that Subzero aligns spill slots.
-; RUN: %p2i -i %s --args --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
+; RUN: | FileCheck %s
; The location of the stack slot for a variable is inferred from the
; return sequence.
@@ -21,9 +19,9 @@
block:
call void @ForceXmmSpills()
ret <4 x i32> %vec.global
-; CHECK-LABEL: align_global_vector:
-; CHECK: movups xmm0, xmmword ptr [esp]
-; CHECK-NEXT: add esp, 28
+; CHECK-LABEL: align_global_vector
+; CHECK: movups xmm0,XMMWORD PTR [esp]
+; CHECK-NEXT: add esp,0x1c
; CHECK-NEXT: ret
}
@@ -34,9 +32,9 @@
%vec.local = insertelement <4 x i32> undef, i32 %arg, i32 0
call void @ForceXmmSpills()
ret <4 x i32> %vec.local
-; CHECK-LABEL: align_local_vector:
-; CHECK: movups xmm0, xmmword ptr [esp]
-; CHECK-NEXT: add esp, 28
+; CHECK-LABEL: align_local_vector
+; CHECK: movups xmm0,XMMWORD PTR [esp]
+; CHECK-NEXT: add esp,0x1c
; CHECK-NEXT: ret
}
@@ -50,9 +48,9 @@
block:
call void @ForceXmmSpillsAndUseAlloca(i8* %alloc)
ret <4 x i32> %vec.global
-; CHECK-LABEL: align_global_vector_ebp_based:
-; CHECK: movups xmm0, xmmword ptr [ebp - 24]
-; CHECK-NEXT: mov esp, ebp
+; CHECK-LABEL: align_global_vector_ebp_based
+; CHECK: movups xmm0,XMMWORD PTR [ebp-0x18]
+; CHECK-NEXT: mov esp,ebp
; CHECK-NEXT: pop ebp
; CHECK: ret
}
@@ -63,9 +61,9 @@
%vec.local = insertelement <4 x i32> undef, i32 %arg, i32 0
call void @ForceXmmSpillsAndUseAlloca(i8* %alloc)
ret <4 x i32> %vec.local
-; CHECK-LABEL: align_local_vector_ebp_based:
-; CHECK: movups xmm0, xmmword ptr [ebp - 24]
-; CHECK-NEXT: mov esp, ebp
+; CHECK-LABEL: align_local_vector_ebp_based
+; CHECK: movups xmm0,XMMWORD PTR [ebp-0x18]
+; CHECK-NEXT: mov esp,ebp
; CHECK-NEXT: pop ebp
; CHECK: ret
}
@@ -79,11 +77,11 @@
%vec.local = insertelement <4 x i32> undef, i32 undef, i32 0
call void @ForceXmmSpillsAndUseFloat(float %float.global)
ret <4 x i32> %vec.local
-; CHECK-LABEL: align_local_vector_and_global_float:
-; CHECK: cvtsi2ss xmm0, eax
-; CHECK-NEXT: movss dword ptr [esp + {{12|28}}], xmm0
-; CHECK: movups xmm0, xmmword ptr [{{esp|esp \+ 16}}]
-; CHECK-NEXT: add esp, 44
+; CHECK-LABEL: align_local_vector_and_global_float
+; CHECK: cvtsi2ss xmm0,eax
+; CHECK-NEXT: movss DWORD PTR [esp+{{0xc|0x1c}}],xmm0
+; CHECK: movups xmm0,XMMWORD PTR [{{esp|esp\+0x10}}]
+; CHECK-NEXT: add esp,0x2c
; CHECK-NEXT: ret
}
diff --git a/tests_lit/llvm2ice_tests/alloc.ll b/tests_lit/llvm2ice_tests/alloc.ll
index 28f617a..bf9dfde 100644
--- a/tests_lit/llvm2ice_tests/alloc.ll
+++ b/tests_lit/llvm2ice_tests/alloc.ll
@@ -1,11 +1,9 @@
; This is a basic test of the alloca instruction.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args -Om1 --verbose none \
+; RUN: | FileCheck %s
define void @fixed_416_align_16(i32 %n) {
entry:
@@ -14,11 +12,11 @@
call void @f1(i32 %__2)
ret void
}
-; CHECK-LABEL: fixed_416_align_16:
-; CHECK: sub esp, 416
-; CHECK: sub esp, 16
-; CHECK: mov dword ptr [esp], eax
-; CHECK: call f1
+; CHECK-LABEL: fixed_416_align_16
+; CHECK: sub esp,0x1a0
+; CHECK: sub esp,0x10
+; CHECK: mov DWORD PTR [esp],eax
+; CHECK: call {{.*}} R_{{.*}} f1
define void @fixed_416_align_32(i32 %n) {
entry:
@@ -27,12 +25,12 @@
call void @f1(i32 %__2)
ret void
}
-; CHECK-LABEL: fixed_416_align_32:
-; CHECK: and esp, -32
-; CHECK: sub esp, 416
-; CHECK: sub esp, 16
-; CHECK: mov dword ptr [esp], eax
-; CHECK: call f1
+; CHECK-LABEL: fixed_416_align_32
+; CHECK: and esp,0xffffffe0
+; CHECK: sub esp,0x1a0
+; CHECK: sub esp,0x10
+; CHECK: mov DWORD PTR [esp],eax
+; CHECK: call {{.*}} R_{{.*}} f1
define void @fixed_351_align_16(i32 %n) {
entry:
@@ -41,11 +39,11 @@
call void @f1(i32 %__2)
ret void
}
-; CHECK-LABEL: fixed_351_align_16:
-; CHECK: sub esp, 352
-; CHECK: sub esp, 16
-; CHECK: mov dword ptr [esp], eax
-; CHECK: call f1
+; CHECK-LABEL: fixed_351_align_16
+; CHECK: sub esp,0x160
+; CHECK: sub esp,0x10
+; CHECK: mov DWORD PTR [esp],eax
+; CHECK: call {{.*}} R_{{.*}} f1
define void @fixed_351_align_32(i32 %n) {
entry:
@@ -54,17 +52,14 @@
call void @f1(i32 %__2)
ret void
}
-; CHECK-LABEL: fixed_351_align_32:
-; CHECK: and esp, -32
-; CHECK: sub esp, 352
-; CHECK: sub esp, 16
-; CHECK: mov dword ptr [esp], eax
-; CHECK: call f1
+; CHECK-LABEL: fixed_351_align_32
+; CHECK: and esp,0xffffffe0
+; CHECK: sub esp,0x160
+; CHECK: sub esp,0x10
+; CHECK: mov DWORD PTR [esp],eax
+; CHECK: call {{.*}} R_{{.*}} f1
-define void @f1(i32 %ignored) {
-entry:
- ret void
-}
+declare void @f1(i32 %ignored)
define void @variable_n_align_16(i32 %n) {
entry:
@@ -73,14 +68,14 @@
call void @f2(i32 %__2)
ret void
}
-; CHECK-LABEL: variable_n_align_16:
-; CHECK: mov eax, dword ptr [ebp + 8]
-; CHECK: add eax, 15
-; CHECK: and eax, -16
-; CHECK: sub esp, eax
-; CHECK: sub esp, 16
-; CHECK: mov dword ptr [esp], eax
-; CHECK: call f2
+; CHECK-LABEL: variable_n_align_16
+; CHECK: mov eax,DWORD PTR [ebp+0x8]
+; CHECK: add eax,0xf
+; CHECK: and eax,0xfffffff0
+; CHECK: sub esp,eax
+; CHECK: sub esp,0x10
+; CHECK: mov DWORD PTR [esp],eax
+; CHECK: call {{.*}} R_{{.*}} f2
define void @variable_n_align_32(i32 %n) {
entry:
@@ -90,15 +85,15 @@
ret void
}
; In -O2, the order of the CHECK-DAG lines in the output is switched.
-; CHECK-LABEL: variable_n_align_32:
-; CHECK-DAG: and esp, -32
-; CHECK-DAG: mov eax, dword ptr [ebp + 8]
-; CHECK: add eax, 31
-; CHECK: and eax, -32
-; CHECK: sub esp, eax
-; CHECK: sub esp, 16
-; CHECK: mov dword ptr [esp], eax
-; CHECK: call f2
+; CHECK-LABEL: variable_n_align_32
+; CHECK-DAG: and esp,0xffffffe0
+; CHECK-DAG: mov eax,DWORD PTR [ebp+0x8]
+; CHECK: add eax,0x1f
+; CHECK: and eax,0xffffffe0
+; CHECK: sub esp,eax
+; CHECK: sub esp,0x10
+; CHECK: mov DWORD PTR [esp],eax
+; CHECK: call {{.*}} R_{{.*}} f2
; Test alloca with default (0) alignment.
define void @align0(i32 %n) {
@@ -109,11 +104,8 @@
ret void
}
; CHECK-LABEL: align0
-; CHECK: add [[REG:.*]], 15
-; CHECK: and [[REG]], -16
-; CHECK: sub esp, [[REG]]
+; CHECK: add [[REG:.*]],0xf
+; CHECK: and [[REG]],0xfffffff0
+; CHECK: sub esp,[[REG]]
-define void @f2(i32 %ignored) {
-entry:
- ret void
-}
+declare void @f2(i32 %ignored)
\ No newline at end of file
diff --git a/tests_lit/llvm2ice_tests/bitcast.ll b/tests_lit/llvm2ice_tests/bitcast.ll
index 379d19b..2a1e4cd 100644
--- a/tests_lit/llvm2ice_tests/bitcast.ll
+++ b/tests_lit/llvm2ice_tests/bitcast.ll
@@ -1,11 +1,9 @@
; Trivial smoke test of bitcast between integer and FP types.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args -Om1 --verbose none \
+; RUN: | FileCheck %s
define internal i32 @cast_f2i(float %f) {
entry:
@@ -22,7 +20,7 @@
ret float %v0
}
; CHECK-LABEL: cast_i2f
-; CHECK: fld dword ptr
+; CHECK: fld DWORD PTR
; CHECK: ret
define internal i64 @cast_d2ll(double %d) {
@@ -40,7 +38,7 @@
ret i64 %v0
}
; CHECK-LABEL: cast_d2ll_const
-; CHECK: movsd xmm{{.*}}, qword ptr
+; CHECK: movsd xmm{{.*}},QWORD PTR
; CHECK: mov edx
; CHECK: ret
@@ -50,7 +48,7 @@
ret double %v0
}
; CHECK-LABEL: cast_ll2d
-; CHECK: fld qword ptr
+; CHECK: fld QWORD PTR
; CHECK: ret
define internal double @cast_ll2d_const() {
@@ -59,7 +57,7 @@
ret double %v0
}
; CHECK-LABEL: cast_ll2d_const
-; CHECK: mov {{.*}}, 1942892530
-; CHECK: mov {{.*}}, 2874
-; CHECK: fld qword ptr
+; CHECK: mov {{.*}},0x73ce2ff2
+; CHECK: mov {{.*}},0xb3a
+; CHECK: fld QWORD PTR
; CHECK: ret
diff --git a/tests_lit/llvm2ice_tests/branch-opt.ll b/tests_lit/llvm2ice_tests/branch-opt.ll
index a0407ec..ad8ea9a 100644
--- a/tests_lit/llvm2ice_tests/branch-opt.ll
+++ b/tests_lit/llvm2ice_tests/branch-opt.ll
@@ -1,13 +1,9 @@
; Tests the branch optimizations under O2 (against a lack of
; optimizations under Om1).
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d -symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
; RUN: | FileCheck --check-prefix=O2 %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d -symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i --assemble --disassemble -i %s --args -Om1 --verbose none \
; RUN: | FileCheck --check-prefix=OM1 %s
declare void @dummy()
@@ -47,7 +43,7 @@
ret void
}
; O2-LABEL: testCondFallthroughToNextBlock
-; O2: cmp {{.*}}, 123
+; O2: cmp {{.*}},0x7b
; O2-NEXT: jge
; O2-NOT: j
; O2: call
@@ -56,7 +52,7 @@
; O2: ret
; OM1-LABEL: testCondFallthroughToNextBlock
-; OM1: cmp {{.*}}, 123
+; OM1: cmp {{.*}},0x7b
; OM1: jge
; OM1: cmp
; OM1: jne
@@ -82,7 +78,7 @@
ret void
}
; O2-LABEL: testCondTargetNextBlock
-; O2: cmp {{.*}}, 123
+; O2: cmp {{.*}},0x7b
; O2-NEXT: jl
; O2-NOT: j
; O2: call
@@ -91,7 +87,7 @@
; O2: ret
; OM1-LABEL: testCondTargetNextBlock
-; OM1: cmp {{.*}}, 123
+; OM1: cmp {{.*}},0x7b
; OM1: jge
; OM1: cmp
; OM1: jne
diff --git a/tests_lit/llvm2ice_tests/callindirect.pnacl.ll b/tests_lit/llvm2ice_tests/callindirect.pnacl.ll
index 1524f63..b6c70ed 100644
--- a/tests_lit/llvm2ice_tests/callindirect.pnacl.ll
+++ b/tests_lit/llvm2ice_tests/callindirect.pnacl.ll
@@ -2,12 +2,9 @@
; should be to the same operand, whether it's in a register or on the
; stack.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args -Om1 --verbose none \
; RUN: | FileCheck --check-prefix=OPTM1 %s
@__init_array_start = internal constant [0 x i8] zeroinitializer, align 4
diff --git a/tests_lit/llvm2ice_tests/cmp-opt.ll b/tests_lit/llvm2ice_tests/cmp-opt.ll
index 163d7af..339d2f8 100644
--- a/tests_lit/llvm2ice_tests/cmp-opt.ll
+++ b/tests_lit/llvm2ice_tests/cmp-opt.ll
@@ -1,11 +1,8 @@
; Simple test of non-fused compare/branch.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args -Om1 --verbose none \
; RUN: | FileCheck --check-prefix=OPTM1 %s
define void @testBool(i32 %a, i32 %b) {
diff --git a/tests_lit/llvm2ice_tests/convert.ll b/tests_lit/llvm2ice_tests/convert.ll
index 922b4d4..86d69eb 100644
--- a/tests_lit/llvm2ice_tests/convert.ll
+++ b/tests_lit/llvm2ice_tests/convert.ll
@@ -1,14 +1,9 @@
; Simple test of signed and unsigned integer conversions.
-; TODO(jvoung): llvm-objdump doesn't symbolize global symbols well, so we
-; have [0] == i8v, [2] == i16v, [4] == i32v, [8] == i64v, etc.
-
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args -Om1 --verbose none \
+; RUN: | FileCheck %s
@i8v = internal global [1 x i8] zeroinitializer, align 1
@i16v = internal global [2 x i8] zeroinitializer, align 2
@@ -35,16 +30,16 @@
ret void
}
; CHECK-LABEL: from_int8
-; CHECK: mov {{.*}}, byte ptr [
-; CHECK: movsx e{{.*}}, {{[a-d]l|byte ptr}}
-; CHECK: mov word ptr [
+; CHECK: mov {{.*}},BYTE PTR
+; CHECK: movsx e{{.*}},{{[a-d]l|BYTE PTR}}
+; CHECK: mov WORD PTR
; CHECK: movsx
-; CHECK: mov dword ptr [
+; CHECK: mov DWORD PTR
; CHECK: movsx
-; CHECK: sar {{.*}}, 31
+; CHECK: sar {{.*}},0x1f
; This appears to be a bug in llvm-mc. It should be i64v and i64+4.
-; CHECK-DAG: [.bss]
-; CHECK-DAG: [.bss]
+; CHECK-DAG: .bss
+; CHECK-DAG: .bss
define void @from_int16() {
entry:
@@ -62,13 +57,13 @@
ret void
}
; CHECK-LABEL: from_int16
-; CHECK: mov {{.*}}, word ptr [
-; CHECK: [.bss]
-; CHECK: movsx e{{.*}}, {{.*x|[ds]i|bp|word ptr}}
-; CHECK: [.bss]
-; CHECK: movsx e{{.*}}, {{.*x|[ds]i|bp|word ptr}}
-; CHECK: sar {{.*}}, 31
-; CHECK: [.bss]
+; CHECK: mov {{.*}},WORD PTR
+; CHECK: .bss
+; CHECK: movsx e{{.*}},{{.*x|[ds]i|bp|WORD PTR}}
+; CHECK: .bss
+; CHECK: movsx e{{.*}},{{.*x|[ds]i|bp|WORD PTR}}
+; CHECK: sar {{.*}},0x1f
+; CHECK: .bss
define void @from_int32() {
entry:
@@ -86,11 +81,11 @@
ret void
}
; CHECK-LABEL: from_int32
-; CHECK: [.bss]
-; CHECK: [.bss]
-; CHECK: [.bss]
-; CHECK: sar {{.*}}, 31
-; CHECK: [.bss]
+; CHECK: .bss
+; CHECK: .bss
+; CHECK: .bss
+; CHECK: sar {{.*}},0x1f
+; CHECK: .bss
define void @from_int64() {
entry:
@@ -108,10 +103,10 @@
ret void
}
; CHECK-LABEL: from_int64
-; CHECK: [.bss]
-; CHECK: [.bss]
-; CHECK: [.bss]
-; CHECK: [.bss]
+; CHECK: .bss
+; CHECK: .bss
+; CHECK: .bss
+; CHECK: .bss
define void @from_uint8() {
@@ -130,14 +125,14 @@
ret void
}
; CHECK-LABEL: from_uint8
-; CHECK: [.bss]
-; CHECK: movzx e{{.*}}, {{[a-d]l|byte ptr}}
-; CHECK: [.bss]
+; CHECK: .bss
+; CHECK: movzx e{{.*}},{{[a-d]l|BYTE PTR}}
+; CHECK: .bss
; CHECK: movzx
-; CHECK: [.bss]
+; CHECK: .bss
; CHECK: movzx
-; CHECK: mov {{.*}}, 0
-; CHECK: [.bss]
+; CHECK: mov {{.*}},0x0
+; CHECK: .bss
define void @from_uint16() {
entry:
@@ -155,13 +150,13 @@
ret void
}
; CHECK-LABEL: from_uint16
-; CHECK: [.bss]
-; CHECK: [.bss]
-; CHECK: movzx e{{.*}}, {{.*x|[ds]i|bp|word ptr}}
-; CHECK: [.bss]
-; CHECK: movzx e{{.*}}, {{.*x|[ds]i|bp|word ptr}}
-; CHECK: mov {{.*}}, 0
-; CHECK: [.bss]
+; CHECK: .bss
+; CHECK: .bss
+; CHECK: movzx e{{.*}},{{.*x|[ds]i|bp|WORD PTR}}
+; CHECK: .bss
+; CHECK: movzx e{{.*}},{{.*x|[ds]i|bp|WORD PTR}}
+; CHECK: mov {{.*}},0x0
+; CHECK: .bss
define void @from_uint32() {
entry:
@@ -179,11 +174,11 @@
ret void
}
; CHECK-LABEL: from_uint32
-; CHECK: [.bss]
-; CHECK: [.bss]
-; CHECK: [.bss]
-; CHECK: mov {{.*}}, 0
-; CHECK: [.bss]
+; CHECK: .bss
+; CHECK: .bss
+; CHECK: .bss
+; CHECK: mov {{.*}},0x0
+; CHECK: .bss
define void @from_uint64() {
entry:
@@ -201,7 +196,7 @@
ret void
}
; CHECK-LABEL: from_uint64
-; CHECK: [.bss]
-; CHECK: [.bss]
-; CHECK: [.bss]
-; CHECK: [.bss]
+; CHECK: .bss
+; CHECK: .bss
+; CHECK: .bss
+; CHECK: .bss
diff --git a/tests_lit/llvm2ice_tests/div_legalization.ll b/tests_lit/llvm2ice_tests/div_legalization.ll
index 603f797..9e1f774 100644
--- a/tests_lit/llvm2ice_tests/div_legalization.ll
+++ b/tests_lit/llvm2ice_tests/div_legalization.ll
@@ -1,19 +1,17 @@
; This is a regression test that idiv and div operands are legalized
; (they cannot be constants and can only be reg/mem for x86).
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args -Om1 --verbose none \
+; RUN: | FileCheck %s
define i32 @Sdiv_const8_b(i8 %a) {
; CHECK-LABEL: Sdiv_const8_b
entry:
%div = sdiv i8 %a, 12
-; CHECK: mov {{.*}}, 12
-; CHECK-NOT: idiv 12
+; CHECK: mov {{.*}},0xc
+; CHECK-NOT: idiv 0xc
%div_ext = sext i8 %div to i32
ret i32 %div_ext
}
@@ -22,8 +20,8 @@
; CHECK-LABEL: Sdiv_const16_b
entry:
%div = sdiv i16 %a, 1234
-; CHECK: mov {{.*}}, 1234
-; CHECK-NOT: idiv 1234
+; CHECK: mov {{.*}},0x4d2
+; CHECK-NOT: idiv 0x4d2
%div_ext = sext i16 %div to i32
ret i32 %div_ext
}
@@ -32,8 +30,8 @@
; CHECK-LABEL: Sdiv_const32_b
entry:
%div = sdiv i32 %a, 1234
-; CHECK: mov {{.*}}, 1234
-; CHECK-NOT: idiv 1234
+; CHECK: mov {{.*}},0x4d2
+; CHECK-NOT: idiv 0x4d2
ret i32 %div
}
@@ -41,8 +39,8 @@
; CHECK-LABEL: Srem_const_b
entry:
%rem = srem i32 %a, 2345
-; CHECK: mov {{.*}}, 2345
-; CHECK-NOT: idiv 2345
+; CHECK: mov {{.*}},0x929
+; CHECK-NOT: idiv 0x929
ret i32 %rem
}
@@ -50,8 +48,8 @@
; CHECK-LABEL: Udiv_const_b
entry:
%div = udiv i32 %a, 3456
-; CHECK: mov {{.*}}, 3456
-; CHECK-NOT: div 3456
+; CHECK: mov {{.*}},0xd80
+; CHECK-NOT: div 0xd80
ret i32 %div
}
@@ -59,7 +57,7 @@
; CHECK-LABEL: Urem_const_b
entry:
%rem = urem i32 %a, 4567
-; CHECK: mov {{.*}}, 4567
-; CHECK-NOT: div 4567
+; CHECK: mov {{.*}},0x11d7
+; CHECK-NOT: div 0x11d7
ret i32 %rem
}
diff --git a/tests_lit/llvm2ice_tests/ebp_args.ll b/tests_lit/llvm2ice_tests/ebp_args.ll
index 03959bb..6533fbb 100644
--- a/tests_lit/llvm2ice_tests/ebp_args.ll
+++ b/tests_lit/llvm2ice_tests/ebp_args.ll
@@ -3,9 +3,8 @@
; adjustment was incorrectly added to the stack/frame offset for
; ebp-based frames.
-; RUN: %p2i -i %s --args -Om1 --target=x8632 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args -Om1 --verbose none \
+; RUN: | FileCheck %s
declare i32 @memcpy_helper2(i32 %buf, i32 %buf2, i32 %n)
@@ -13,9 +12,9 @@
entry:
%buf2 = alloca i8, i32 128, align 4
%n.arg_trunc = trunc i32 %n to i8
- %arg_ext = zext i8 %n.arg_trunc to i32
+ %arg.ext = zext i8 %n.arg_trunc to i32
%buf2.asint = ptrtoint i8* %buf2 to i32
- %call = call i32 @memcpy_helper2(i32 %buf, i32 %buf2.asint, i32 %arg_ext)
+ %call = call i32 @memcpy_helper2(i32 %buf, i32 %buf2.asint, i32 %arg.ext)
ret i32 %call
}
@@ -23,21 +22,21 @@
; and stack slot assignment code, and may need to be relaxed if the
; lowering code changes.
-; CHECK-LABEL: memcpy_helper:
+; CHECK-LABEL: memcpy_helper
; CHECK: push ebp
-; CHECK: mov ebp, esp
-; CHECK: sub esp, 24
-; CHECK: sub esp, 128
-; CHECK: mov dword ptr [ebp - 4], esp
-; CHECK: mov eax, dword ptr [ebp + 12]
-; CHECK: mov dword ptr [ebp - 8], eax
-; CHECK: movzx eax, byte ptr [ebp - 8]
-; CHECK: mov dword ptr [ebp - 12], eax
-; CHECK: sub esp, 16
-; CHECK: mov eax, dword ptr [ebp + 8]
-; CHECK: mov dword ptr [esp], eax
-; CHECK: mov eax, dword ptr [ebp - 4]
-; CHECK: mov dword ptr [esp + 4], eax
-; CHECK: mov eax, dword ptr [ebp - 12]
-; CHECK: mov dword ptr [esp + 8], eax
-; CHECK: call memcpy_helper2
+; CHECK: mov ebp,esp
+; CHECK: sub esp,0x18
+; CHECK: sub esp,0x80
+; CHECK: mov DWORD PTR [ebp-0x4],esp
+; CHECK: mov eax,DWORD PTR [ebp+0xc]
+; CHECK: mov DWORD PTR [ebp-0x8],eax
+; CHECK: movzx eax,BYTE PTR [ebp-0x8]
+; CHECK: mov DWORD PTR [ebp-0xc],eax
+; CHECK: sub esp,0x10
+; CHECK: mov eax,DWORD PTR [ebp+0x8]
+; CHECK: mov DWORD PTR [esp],eax
+; CHECK: mov eax,DWORD PTR [ebp-0x4]
+; CHECK: mov DWORD PTR [esp+0x4],eax
+; CHECK: mov eax,DWORD PTR [ebp-0xc]
+; CHECK: mov DWORD PTR [esp+0x8],eax
+; CHECK: call {{.*}} R_{{.*}} memcpy_helper2
diff --git a/tests_lit/llvm2ice_tests/elf_container.ll b/tests_lit/llvm2ice_tests/elf_container.ll
index 6e1c7b3..994f1a4 100644
--- a/tests_lit/llvm2ice_tests/elf_container.ll
+++ b/tests_lit/llvm2ice_tests/elf_container.ll
@@ -14,7 +14,7 @@
; Add a run that shows relocations in code inline.
; RUN: %p2i -i %s --args -O2 --verbose none -filetype=obj -o %t \
-; RUN: && llvm-objdump -d -r -x86-asm-syntax=intel %t \
+; RUN: && objdump -w -d -r -Mintel %t \
; RUN: | FileCheck --check-prefix=TEXT-RELOCS %s
; Use intrinsics to test external calls.
@@ -53,10 +53,8 @@
ret float %f
}
; TEXT-RELOCS-LABEL: returnFloatConst
-; TEXT-RELOCS: movss
-; TEXT-RELOCS-NEXT: R_386_32 .L$float$0
-; TEXT-RELOCS: addss
-; TEXT-RELOCS-NEXT: R_386_32 .L$float$1
+; TEXT-RELOCS: movss {{.*}} R_386_32 .L$float$0
+; TEXT-RELOCS: addss {{.*}} R_386_32 .L$float$1
define internal double @returnDoubleConst() {
entry:
@@ -65,12 +63,9 @@
ret double %d2
}
; TEXT-RELOCS-LABEL: returnDoubleConst
-; TEXT-RELOCS: movsd
-; TEXT-RELOCS-NEXT: R_386_32 .L$double$0
-; TEXT-RELOCS: addsd
-; TEXT-RELOCS-NEXT: R_386_32 .L$double$1
-; TEXT-RELOCS: addsd
-; TEXT-RELOCS-NEXT: R_386_32 .L$double$2
+; TEXT-RELOCS: movsd {{.*}} R_386_32 .L$double$0
+; TEXT-RELOCS: addsd {{.*}} R_386_32 .L$double$1
+; TEXT-RELOCS: addsd {{.*}} R_386_32 .L$double$2
; Test intrinsics that call out to external functions.
define internal void @test_memcpy(i32 %iptr_dst, i32 %len) {
@@ -82,8 +77,7 @@
ret void
}
; TEXT-RELOCS-LABEL: test_memcpy
-; TEXT-RELOCS: mov
-; TEXT-RELOCS: R_386_32 bytes
+; TEXT-RELOCS: mov {{.*}} R_386_32 bytes
define internal void @test_memset(i32 %iptr_dst, i32 %wide_val, i32 %len) {
entry:
@@ -114,16 +108,14 @@
ret i32 %r
}
; TEXT-RELOCS-LABEL: test_ret_fp
-; TEXT-RELOCS-NEXT: mov
-; TEXT-RELOCS-NEXT: R_386_32 returnFloatConst
+; TEXT-RELOCS-NEXT: mov {{.*}} R_386_32 returnFloatConst
define internal i32 @test_ret_global_pointer() {
%r = ptrtoint [7 x i8]* @bytes to i32
ret i32 %r
}
; TEXT-RELOCS-LABEL: test_ret_global_pointer
-; TEXT-RELOCS-NEXT: mov
-; TEXT-RELOCS-NEXT: R_386_32 bytes
+; TEXT-RELOCS-NEXT: mov {{.*}} R_386_32 bytes
; Test defining a non-internal function.
define void @_start(i32) {
diff --git a/tests_lit/llvm2ice_tests/fp.pnacl.ll b/tests_lit/llvm2ice_tests/fp.pnacl.ll
index 0987b7f..1beb3eb 100644
--- a/tests_lit/llvm2ice_tests/fp.pnacl.ll
+++ b/tests_lit/llvm2ice_tests/fp.pnacl.ll
@@ -3,12 +3,10 @@
; that should be present regardless of the optimization level, so
; there are no special OPTM1 match lines.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args -Om1 --verbose none \
+; RUN: | FileCheck %s
@__init_array_start = internal constant [0 x i8] zeroinitializer, align 4
@__fini_array_start = internal constant [0 x i8] zeroinitializer, align 4
@@ -20,7 +18,7 @@
ret i32 %b
}
; CHECK-LABEL: doubleArgs
-; CHECK: mov eax, dword ptr [esp + 12]
+; CHECK: mov eax,DWORD PTR [esp+0xc]
; CHECK-NEXT: ret
define internal i32 @floatArgs(float %a, i32 %b, float %c) {
@@ -28,7 +26,7 @@
ret i32 %b
}
; CHECK-LABEL: floatArgs
-; CHECK: mov eax, dword ptr [esp + 8]
+; CHECK: mov eax,DWORD PTR [esp+0x8]
; CHECK-NEXT: ret
define internal i32 @passFpArgs(float %a, double %b, float %c, double %d, float %e, double %f) {
@@ -41,12 +39,12 @@
ret i32 %add3
}
; CHECK-LABEL: passFpArgs
-; CHECK: mov dword ptr [esp + 4], 123
-; CHECK: call ignoreFpArgsNoInline
-; CHECK: mov dword ptr [esp + 4], 123
-; CHECK: call ignoreFpArgsNoInline
-; CHECK: mov dword ptr [esp + 4], 123
-; CHECK: call ignoreFpArgsNoInline
+; CHECK: mov DWORD PTR [esp+0x4],0x7b
+; CHECK: call {{.*}} R_{{.*}} ignoreFpArgsNoInline
+; CHECK: mov DWORD PTR [esp+0x4],0x7b
+; CHECK: call {{.*}} R_{{.*}} ignoreFpArgsNoInline
+; CHECK: mov DWORD PTR [esp+0x4],0x7b
+; CHECK: call {{.*}} R_{{.*}} ignoreFpArgsNoInline
declare i32 @ignoreFpArgsNoInline(float %x, i32 %y, double %z)
@@ -56,8 +54,8 @@
ret i32 %call
}
; CHECK-LABEL: passFpConstArg
-; CHECK: mov dword ptr [esp + 4], 123
-; CHECK: call ignoreFpArgsNoInline
+; CHECK: mov DWORD PTR [esp+0x4],0x7b
+; CHECK: call {{.*}} R_{{.*}} ignoreFpArgsNoInline
define internal i32 @passFp32ConstArg(float %a) {
entry:
@@ -65,28 +63,25 @@
ret i32 %call
}
; CHECK-LABEL: passFp32ConstArg
-; CHECK: mov dword ptr [esp + 4], 123
-; CHECK: movss dword ptr [esp + 8]
-; CHECK: call ignoreFp32ArgsNoInline
+; CHECK: mov DWORD PTR [esp+0x4],0x7b
+; CHECK: movss DWORD PTR [esp+0x8]
+; CHECK: call {{.*}} R_{{.*}} ignoreFp32ArgsNoInline
-define i32 @ignoreFp32ArgsNoInline(float %x, i32 %y, float %z) {
-entry:
- ret i32 %y
-}
+declare i32 @ignoreFp32ArgsNoInline(float %x, i32 %y, float %z)
define internal float @returnFloatArg(float %a) {
entry:
ret float %a
}
; CHECK-LABEL: returnFloatArg
-; CHECK: fld dword ptr [esp
+; CHECK: fld DWORD PTR [esp
define internal double @returnDoubleArg(double %a) {
entry:
ret double %a
}
; CHECK-LABEL: returnDoubleArg
-; CHECK: fld qword ptr [esp
+; CHECK: fld QWORD PTR [esp
define internal float @returnFloatConst() {
entry:
@@ -180,7 +175,7 @@
ret float %div
}
; CHECK-LABEL: remFloat
-; CHECK: call fmodf
+; CHECK: call {{.*}} R_{{.*}} fmodf
define internal double @remDouble(double %a, double %b) {
entry:
@@ -188,7 +183,7 @@
ret double %div
}
; CHECK-LABEL: remDouble
-; CHECK: call fmod
+; CHECK: call {{.*}} R_{{.*}} fmod
define internal float @fptrunc(double %a) {
entry:
@@ -214,7 +209,7 @@
ret i64 %conv
}
; CHECK-LABEL: doubleToSigned64
-; CHECK: call cvtdtosi64
+; CHECK: call {{.*}} R_{{.*}} cvtdtosi64
define internal i64 @floatToSigned64(float %a) {
entry:
@@ -222,7 +217,7 @@
ret i64 %conv
}
; CHECK-LABEL: floatToSigned64
-; CHECK: call cvtftosi64
+; CHECK: call {{.*}} R_{{.*}} cvtftosi64
define internal i64 @doubleToUnsigned64(double %a) {
entry:
@@ -230,7 +225,7 @@
ret i64 %conv
}
; CHECK-LABEL: doubleToUnsigned64
-; CHECK: call cvtdtoui64
+; CHECK: call {{.*}} R_{{.*}} cvtdtoui64
define internal i64 @floatToUnsigned64(float %a) {
entry:
@@ -238,7 +233,7 @@
ret i64 %conv
}
; CHECK-LABEL: floatToUnsigned64
-; CHECK: call cvtftoui64
+; CHECK: call {{.*}} R_{{.*}} cvtftoui64
define internal i32 @doubleToSigned32(double %a) {
entry:
@@ -270,7 +265,7 @@
ret i32 %conv
}
; CHECK-LABEL: doubleToUnsigned32
-; CHECK: call cvtdtoui32
+; CHECK: call {{.*}} R_{{.*}} cvtdtoui32
define internal i32 @floatToUnsigned32(float %a) {
entry:
@@ -278,8 +273,7 @@
ret i32 %conv
}
; CHECK-LABEL: floatToUnsigned32
-; CHECK: call cvtftoui32
-
+; CHECK: call {{.*}} R_{{.*}} cvtftoui32
define internal i32 @doubleToSigned16(double %a) {
entry:
@@ -369,7 +363,7 @@
}
; CHECK-LABEL: doubleToUnsigned1
; CHECK: cvttsd2si
-; CHECK: and eax, 1
+; CHECK: and eax,0x1
define internal i32 @floatToUnsigned1(float %a) {
entry:
@@ -379,7 +373,7 @@
}
; CHECK-LABEL: floatToUnsigned1
; CHECK: cvttss2si
-; CHECK: and eax, 1
+; CHECK: and eax,0x1
define internal double @signed64ToDouble(i64 %a) {
entry:
@@ -387,8 +381,8 @@
ret double %conv
}
; CHECK-LABEL: signed64ToDouble
-; CHECK: call cvtsi64tod
-; CHECK: fstp qword
+; CHECK: call {{.*}} R_{{.*}} cvtsi64tod
+; CHECK: fstp QWORD
define internal float @signed64ToFloat(i64 %a) {
entry:
@@ -396,8 +390,8 @@
ret float %conv
}
; CHECK-LABEL: signed64ToFloat
-; CHECK: call cvtsi64tof
-; CHECK: fstp dword
+; CHECK: call {{.*}} R_{{.*}} cvtsi64tof
+; CHECK: fstp DWORD
define internal double @unsigned64ToDouble(i64 %a) {
entry:
@@ -405,7 +399,7 @@
ret double %conv
}
; CHECK-LABEL: unsigned64ToDouble
-; CHECK: call cvtui64tod
+; CHECK: call {{.*}} R_{{.*}} cvtui64tod
; CHECK: fstp
define internal float @unsigned64ToFloat(i64 %a) {
@@ -414,7 +408,7 @@
ret float %conv
}
; CHECK-LABEL: unsigned64ToFloat
-; CHECK: call cvtui64tof
+; CHECK: call {{.*}} R_{{.*}} cvtui64tof
; CHECK: fstp
define internal double @unsigned64ToDoubleConst() {
@@ -423,9 +417,9 @@
ret double %conv
}
; CHECK-LABEL: unsigned64ToDouble
-; CHECK: mov dword ptr [esp + 4], 2874
-; CHECK: mov dword ptr [esp], 1942892530
-; CHECK: call cvtui64tod
+; CHECK: mov DWORD PTR [esp+0x4],0xb3a
+; CHECK: mov DWORD PTR [esp],0x73ce2ff2
+; CHECK: call {{.*}} R_{{.*}} cvtui64tod
; CHECK: fstp
define internal double @signed32ToDouble(i32 %a) {
@@ -461,8 +455,8 @@
ret double %conv
}
; CHECK-LABEL: unsigned32ToDouble
-; CHECK: call cvtui32tod
-; CHECK: fstp qword
+; CHECK: call {{.*}} R_{{.*}} cvtui32tod
+; CHECK: fstp QWORD
define internal float @unsigned32ToFloat(i32 %a) {
entry:
@@ -470,8 +464,8 @@
ret float %conv
}
; CHECK-LABEL: unsigned32ToFloat
-; CHECK: call cvtui32tof
-; CHECK: fstp dword
+; CHECK: call {{.*}} R_{{.*}} cvtui32tof
+; CHECK: fstp DWORD
define internal double @signed16ToDouble(i32 %a) {
entry:
@@ -481,7 +475,7 @@
}
; CHECK-LABEL: signed16ToDouble
; CHECK: cvtsi2sd
-; CHECK: fld qword
+; CHECK: fld QWORD
define internal float @signed16ToFloat(i32 %a) {
entry:
@@ -491,7 +485,7 @@
}
; CHECK-LABEL: signed16ToFloat
; CHECK: cvtsi2ss
-; CHECK: fld dword
+; CHECK: fld DWORD
define internal double @unsigned16ToDouble(i32 %a) {
entry:
@@ -636,18 +630,15 @@
}
; CHECK-LABEL: fcmpEq
; CHECK: ucomiss
-; CHECK: jne {{[0-9]}}
-; CHECK-NEXT: jp {{[0-9]}}
-; CHECK: call func
+; CHECK: jne
+; CHECK-NEXT: jp
+; CHECK: call {{.*}} R_{{.*}} func
; CHECK: ucomisd
-; CHECK: jne {{[0-9]}}
-; CHECK-NEXT: jp {{[0-9]}}
-; CHECK: call func
+; CHECK: jne
+; CHECK-NEXT: jp
+; CHECK: call {{.*}} R_{{.*}} func
-define void @func() {
-entry:
- ret void
-}
+declare void @func()
define internal void @fcmpNe(float %a, float %b, double %c, double %d) {
entry:
@@ -671,13 +662,13 @@
}
; CHECK-LABEL: fcmpNe
; CHECK: ucomiss
-; CHECK: jne {{[0-9]}}
-; CHECK-NEXT: jp {{[0-9]}}
-; CHECK: call func
+; CHECK: jne
+; CHECK-NEXT: jp
+; CHECK: call {{.*}} R_{{.*}} func
; CHECK: ucomisd
-; CHECK: jne {{[0-9]}}
-; CHECK-NEXT: jp {{[0-9]}}
-; CHECK: call func
+; CHECK: jne
+; CHECK-NEXT: jp
+; CHECK: call {{.*}} R_{{.*}} func
define internal void @fcmpGt(float %a, float %b, double %c, double %d) {
entry:
@@ -701,11 +692,11 @@
}
; CHECK-LABEL: fcmpGt
; CHECK: ucomiss
-; CHECK: ja {{[0-9]}}
-; CHECK: call func
+; CHECK: ja
+; CHECK: call {{.*}} R_{{.*}} func
; CHECK: ucomisd
-; CHECK: ja {{[0-9]}}
-; CHECK: call func
+; CHECK: ja
+; CHECK: call {{.*}} R_{{.*}} func
define internal void @fcmpGe(float %a, float %b, double %c, double %d) {
entry:
@@ -729,11 +720,11 @@
}
; CHECK-LABEL: fcmpGe
; CHECK: ucomiss
-; CHECK: jb {{[0-9]}}
-; CHECK: call func
+; CHECK: jb
+; CHECK: call {{.*}} R_{{.*}} func
; CHECK: ucomisd
-; CHECK: jb {{[0-9]}}
-; CHECK: call func
+; CHECK: jb
+; CHECK: call {{.*}} R_{{.*}} func
define internal void @fcmpLt(float %a, float %b, double %c, double %d) {
entry:
@@ -757,11 +748,11 @@
}
; CHECK-LABEL: fcmpLt
; CHECK: ucomiss
-; CHECK: ja {{[0-9]}}
-; CHECK: call func
+; CHECK: ja
+; CHECK: call {{.*}} R_{{.*}} func
; CHECK: ucomisd
-; CHECK: ja {{[0-9]}}
-; CHECK: call func
+; CHECK: ja
+; CHECK: call {{.*}} R_{{.*}} func
define internal void @fcmpLe(float %a, float %b, double %c, double %d) {
entry:
@@ -785,11 +776,11 @@
}
; CHECK-LABEL: fcmpLe
; CHECK: ucomiss
-; CHECK: jb {{[0-9]}}
-; CHECK: call func
+; CHECK: jb
+; CHECK: call {{.*}} R_{{.*}} func
; CHECK: ucomisd
-; CHECK: jb {{[0-9]}}
-; CHECK: call func
+; CHECK: jb
+; CHECK: call {{.*}} R_{{.*}} func
define internal i32 @fcmpFalseFloat(float %a, float %b) {
entry:
@@ -798,7 +789,7 @@
ret i32 %cmp.ret_ext
}
; CHECK-LABEL: fcmpFalseFloat
-; CHECK: mov {{.*}}, 0
+; CHECK: mov {{.*}},0x0
define internal i32 @fcmpFalseDouble(double %a, double %b) {
entry:
@@ -807,7 +798,7 @@
ret i32 %cmp.ret_ext
}
; CHECK-LABEL: fcmpFalseDouble
-; CHECK: mov {{.*}}, 0
+; CHECK: mov {{.*}},0x0
define internal i32 @fcmpOeqFloat(float %a, float %b) {
entry:
@@ -817,8 +808,8 @@
}
; CHECK-LABEL: fcmpOeqFloat
; CHECK: ucomiss
-; CHECK: jne {{[0-9]}}
-; CHECK: jp {{[0-9]}}
+; CHECK: jne
+; CHECK: jp
define internal i32 @fcmpOeqDouble(double %a, double %b) {
entry:
@@ -828,8 +819,8 @@
}
; CHECK-LABEL: fcmpOeqDouble
; CHECK: ucomisd
-; CHECK: jne {{[0-9]}}
-; CHECK: jp {{[0-9]}}
+; CHECK: jne
+; CHECK: jp
define internal i32 @fcmpOgtFloat(float %a, float %b) {
entry:
@@ -839,7 +830,7 @@
}
; CHECK-LABEL: fcmpOgtFloat
; CHECK: ucomiss
-; CHECK: ja {{[0-9]}}
+; CHECK: ja
define internal i32 @fcmpOgtDouble(double %a, double %b) {
entry:
@@ -849,7 +840,7 @@
}
; CHECK-LABEL: fcmpOgtDouble
; CHECK: ucomisd
-; CHECK: ja {{[0-9]}}
+; CHECK: ja
define internal i32 @fcmpOgeFloat(float %a, float %b) {
entry:
@@ -859,7 +850,7 @@
}
; CHECK-LABEL: fcmpOgeFloat
; CHECK: ucomiss
-; CHECK: jae {{[0-9]}}
+; CHECK: jae
define internal i32 @fcmpOgeDouble(double %a, double %b) {
entry:
@@ -869,7 +860,7 @@
}
; CHECK-LABEL: fcmpOgeDouble
; CHECK: ucomisd
-; CHECK: jae {{[0-9]}}
+; CHECK: jae
define internal i32 @fcmpOltFloat(float %a, float %b) {
entry:
@@ -879,7 +870,7 @@
}
; CHECK-LABEL: fcmpOltFloat
; CHECK: ucomiss
-; CHECK: ja {{[0-9]}}
+; CHECK: ja
define internal i32 @fcmpOltDouble(double %a, double %b) {
entry:
@@ -889,7 +880,7 @@
}
; CHECK-LABEL: fcmpOltDouble
; CHECK: ucomisd
-; CHECK: ja {{[0-9]}}
+; CHECK: ja
define internal i32 @fcmpOleFloat(float %a, float %b) {
entry:
@@ -899,7 +890,7 @@
}
; CHECK-LABEL: fcmpOleFloat
; CHECK: ucomiss
-; CHECK: jae {{[0-9]}}
+; CHECK: jae
define internal i32 @fcmpOleDouble(double %a, double %b) {
entry:
@@ -909,7 +900,7 @@
}
; CHECK-LABEL: fcmpOleDouble
; CHECK: ucomisd
-; CHECK: jae {{[0-9]}}
+; CHECK: jae
define internal i32 @fcmpOneFloat(float %a, float %b) {
entry:
@@ -919,7 +910,7 @@
}
; CHECK-LABEL: fcmpOneFloat
; CHECK: ucomiss
-; CHECK: jne {{[0-9]}}
+; CHECK: jne
define internal i32 @fcmpOneDouble(double %a, double %b) {
entry:
@@ -929,7 +920,7 @@
}
; CHECK-LABEL: fcmpOneDouble
; CHECK: ucomisd
-; CHECK: jne {{[0-9]}}
+; CHECK: jne
define internal i32 @fcmpOrdFloat(float %a, float %b) {
entry:
@@ -939,7 +930,7 @@
}
; CHECK-LABEL: fcmpOrdFloat
; CHECK: ucomiss
-; CHECK: jnp {{[0-9]}}
+; CHECK: jnp
define internal i32 @fcmpOrdDouble(double %a, double %b) {
entry:
@@ -949,7 +940,7 @@
}
; CHECK-LABEL: fcmpOrdDouble
; CHECK: ucomisd
-; CHECK: jnp {{[0-9]}}
+; CHECK: jnp
define internal i32 @fcmpUeqFloat(float %a, float %b) {
entry:
@@ -959,7 +950,7 @@
}
; CHECK-LABEL: fcmpUeqFloat
; CHECK: ucomiss
-; CHECK: je {{[0-9]}}
+; CHECK: je
define internal i32 @fcmpUeqDouble(double %a, double %b) {
entry:
@@ -969,7 +960,7 @@
}
; CHECK-LABEL: fcmpUeqDouble
; CHECK: ucomisd
-; CHECK: je {{[0-9]}}
+; CHECK: je
define internal i32 @fcmpUgtFloat(float %a, float %b) {
entry:
@@ -979,7 +970,7 @@
}
; CHECK-LABEL: fcmpUgtFloat
; CHECK: ucomiss
-; CHECK: jb {{[0-9]}}
+; CHECK: jb
define internal i32 @fcmpUgtDouble(double %a, double %b) {
entry:
@@ -989,7 +980,7 @@
}
; CHECK-LABEL: fcmpUgtDouble
; CHECK: ucomisd
-; CHECK: jb {{[0-9]}}
+; CHECK: jb
define internal i32 @fcmpUgeFloat(float %a, float %b) {
entry:
@@ -999,7 +990,7 @@
}
; CHECK-LABEL: fcmpUgeFloat
; CHECK: ucomiss
-; CHECK: jbe {{[0-9]}}
+; CHECK: jbe
define internal i32 @fcmpUgeDouble(double %a, double %b) {
entry:
@@ -1009,7 +1000,7 @@
}
; CHECK-LABEL: fcmpUgeDouble
; CHECK: ucomisd
-; CHECK: jbe {{[0-9]}}
+; CHECK: jbe
define internal i32 @fcmpUltFloat(float %a, float %b) {
entry:
@@ -1019,7 +1010,7 @@
}
; CHECK-LABEL: fcmpUltFloat
; CHECK: ucomiss
-; CHECK: jb {{[0-9]}}
+; CHECK: jb
define internal i32 @fcmpUltDouble(double %a, double %b) {
entry:
@@ -1029,7 +1020,7 @@
}
; CHECK-LABEL: fcmpUltDouble
; CHECK: ucomisd
-; CHECK: jb {{[0-9]}}
+; CHECK: jb
define internal i32 @fcmpUleFloat(float %a, float %b) {
entry:
@@ -1039,7 +1030,7 @@
}
; CHECK-LABEL: fcmpUleFloat
; CHECK: ucomiss
-; CHECK: jbe {{[0-9]}}
+; CHECK: jbe
define internal i32 @fcmpUleDouble(double %a, double %b) {
entry:
@@ -1049,7 +1040,7 @@
}
; CHECK-LABEL: fcmpUleDouble
; CHECK: ucomisd
-; CHECK: jbe {{[0-9]}}
+; CHECK: jbe
define internal i32 @fcmpUneFloat(float %a, float %b) {
entry:
@@ -1059,8 +1050,8 @@
}
; CHECK-LABEL: fcmpUneFloat
; CHECK: ucomiss
-; CHECK: jne {{[0-9]}}
-; CHECK: jp {{[0-9]}}
+; CHECK: jne
+; CHECK: jp
define internal i32 @fcmpUneDouble(double %a, double %b) {
entry:
@@ -1070,8 +1061,8 @@
}
; CHECK-LABEL: fcmpUneDouble
; CHECK: ucomisd
-; CHECK: jne {{[0-9]}}
-; CHECK: jp {{[0-9]}}
+; CHECK: jne
+; CHECK: jp
define internal i32 @fcmpUnoFloat(float %a, float %b) {
entry:
@@ -1081,7 +1072,7 @@
}
; CHECK-LABEL: fcmpUnoFloat
; CHECK: ucomiss
-; CHECK: jp {{[0-9]}}
+; CHECK: jp
define internal i32 @fcmpUnoDouble(double %a, double %b) {
entry:
@@ -1091,7 +1082,7 @@
}
; CHECK-LABEL: fcmpUnoDouble
; CHECK: ucomisd
-; CHECK: jp {{[0-9]}}
+; CHECK: jp
define internal i32 @fcmpTrueFloat(float %a, float %b) {
entry:
@@ -1100,7 +1091,7 @@
ret i32 %cmp.ret_ext
}
; CHECK-LABEL: fcmpTrueFloat
-; CHECK: mov {{.*}}, 1
+; CHECK: mov {{.*}},0x1
define internal i32 @fcmpTrueDouble(double %a, double %b) {
entry:
@@ -1109,7 +1100,7 @@
ret i32 %cmp.ret_ext
}
; CHECK-LABEL: fcmpTrueDouble
-; CHECK: mov {{.*}}, 1
+; CHECK: mov {{.*}},0x1
define internal float @loadFloat(i32 %a) {
entry:
@@ -1137,7 +1128,7 @@
store float %value, float* %__2, align 4
ret void
}
-; CHECK-LABEL: storeFloat:
+; CHECK-LABEL: storeFloat
; CHECK: movss
; CHECK: movss
@@ -1147,7 +1138,7 @@
store double %value, double* %__2, align 8
ret void
}
-; CHECK-LABEL: storeDouble:
+; CHECK-LABEL: storeDouble
; CHECK: movsd
; CHECK: movsd
@@ -1179,7 +1170,7 @@
}
; CHECK-LABEL: selectFloatVarVar
; CHECK: ucomiss
-; CHECK: ja {{[0-9]}}
+; CHECK: ja
; CHECK: fld
define internal double @selectDoubleVarVar(double %a, double %b) {
@@ -1190,5 +1181,5 @@
}
; CHECK-LABEL: selectDoubleVarVar
; CHECK: ucomisd
-; CHECK: ja {{[0-9]}}
+; CHECK: ja
; CHECK: fld
diff --git a/tests_lit/llvm2ice_tests/fpcall.ll b/tests_lit/llvm2ice_tests/fpcall.ll
index 91fa575..5f737ae 100644
--- a/tests_lit/llvm2ice_tests/fpcall.ll
+++ b/tests_lit/llvm2ice_tests/fpcall.ll
@@ -3,18 +3,12 @@
; particular, the top-of-stack must be popped regardless of whether
; its value is used.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args -Om1 --verbose none \
+; RUN: | FileCheck %s
-define float @dummy() {
-entry:
- ret float 0.000000e+00
-}
-; CHECK-LABEL: dummy
+declare float @dummy()
; The call is ignored, but the top of the FP stack still needs to be
; popped.
@@ -24,7 +18,7 @@
ret i32 0
}
; CHECK-LABEL: ignored_fp_call
-; CHECK: call dummy
+; CHECK: call {{.*}} R_{{.*}} dummy
; CHECK: fstp
; The top of the FP stack is popped and subsequently used.
@@ -35,7 +29,7 @@
ret i32 %ret
}
; CHECK-LABEL: converted_fp_call
-; CHECK: call dummy
+; CHECK: call {{.*}} R_{{.*}} dummy
; CHECK: fstp
; CHECK: cvttss2si
@@ -48,6 +42,6 @@
ret float %fp
}
; CHECK-LABEL: returned_fp_call
-; CHECK: call dummy
+; CHECK: call {{.*}} R_{{.*}} dummy
; CHECK: fstp
; CHECK: fld
diff --git a/tests_lit/llvm2ice_tests/fpconst.pnacl.ll b/tests_lit/llvm2ice_tests/fpconst.pnacl.ll
index 7591387..5716ed6 100644
--- a/tests_lit/llvm2ice_tests/fpconst.pnacl.ll
+++ b/tests_lit/llvm2ice_tests/fpconst.pnacl.ll
@@ -6,12 +6,10 @@
; number in a reasonable number of digits". See
; http://llvm.org/docs/LangRef.html#simple-constants .
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -s -d -symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -s -d -symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i --assemble --disassemble --dis-flags=-s -i %s --args -O2 \
+; RUN: --verbose none | FileCheck %s
+; RUN: %p2i --assemble --disassemble --dis-flags=-s -i %s --args -Om1 \
+; RUN: --verbose none | FileCheck %s
@__init_array_start = internal constant [0 x i8] zeroinitializer, align 4
@__fini_array_start = internal constant [0 x i8] zeroinitializer, align 4
@@ -549,4 +547,4 @@
; CHECK-LABEL: .rodata.cst8
; CHECK: 00000000 0000e03f
; CHECK-NOT: 00000000 0000e03f
-; CHECK-LABEL: .shstrtab
+; CHECK-LABEL: .text
diff --git a/tests_lit/llvm2ice_tests/function_aligned.ll b/tests_lit/llvm2ice_tests/function_aligned.ll
index 819646e..44bdf08 100644
--- a/tests_lit/llvm2ice_tests/function_aligned.ll
+++ b/tests_lit/llvm2ice_tests/function_aligned.ll
@@ -3,9 +3,8 @@
; but typically you want to align functions anyway.
; Also, we are currently using hlts for non-executable padding.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i --assemble --disassemble -i %s --args -O2 --verbose none \
+; RUN: | FileCheck %s
define void @foo() {
ret void
diff --git a/tests_lit/llvm2ice_tests/globalinit.pnacl.ll b/tests_lit/llvm2ice_tests/globalinit.pnacl.ll
index 2d5e5ce..c61b0b9 100644
--- a/tests_lit/llvm2ice_tests/globalinit.pnacl.ll
+++ b/tests_lit/llvm2ice_tests/globalinit.pnacl.ll
@@ -8,14 +8,10 @@
; Test -filetype=iasm and try to cross reference instructions w/ the
; symbol table.
-; RUN: %p2i -i %s --args --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d -r --symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i --assemble --disassemble -i %s --args --verbose none \
; RUN: | FileCheck --check-prefix=IAS %s
-; RUN: %p2i -i %s --args --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d -t --symbolize -x86-asm-syntax=intel - \
-; RUN: | FileCheck --check-prefix=SYMTAB %s
+; RUN: %p2i --assemble --disassemble --dis-flags=-t -i %s --args \
+; RUN: --verbose none | FileCheck --check-prefix=SYMTAB %s
@PrimitiveInit = internal global [4 x i8] c"\1B\00\00\00", align 4
; CHECK: .type PrimitiveInit,@object
@@ -121,46 +117,39 @@
; CHECK: movl $ArrayInitPartial,
; CHECK: movl $ArrayUninit,
-; llvm-objdump does not indicate what symbol the mov/relocation applies to
-; so we grep for "mov {{.*}}, OFFSET", along with "OFFSET {{.*}} symbol" in
-; the symbol table as a sanity check. NOTE: The symbol table sorting has no
-; relation to the code's references.
+; objdump does not indicate what symbol the mov/relocation applies to
+; so we grep for "mov {{.*}}, OFFSET, sec", along with
+; "OFFSET {{.*}} sec {{.*}} symbol" in the symbol table as a sanity check.
+; NOTE: The symbol table sorting has no relation to the code's references.
; IAS-LABEL: main
; SYMTAB-LABEL: SYMBOL TABLE
; SYMTAB-DAG: 00000000 {{.*}} .data {{.*}} PrimitiveInit
-; IAS: mov {{.*}}, .data
-; IAS-NEXT: R_386_32
+; IAS: mov {{.*}},0x0 {{.*}} .data
; IAS: call
; SYMTAB-DAG: 00000000 {{.*}} .rodata {{.*}} PrimitiveInitConst
-; IAS: mov {{.*}}, .rodata
-; IAS-NEXT: R_386_32
+; IAS: mov {{.*}},0x0 {{.*}} .rodata
; IAS: call
; SYMTAB-DAG: 00000000 {{.*}} .bss {{.*}} PrimitiveInitStatic
-; IAS: mov {{.*}}, .bss
-; IAS-NEXT: R_386_32
+; IAS: mov {{.*}},0x0 {{.*}} .bss
; IAS: call
; SYMTAB-DAG: 00000004 {{.*}} .bss {{.*}} PrimitiveUninit
-; IAS: mov {{.*}}, .bss
-; IAS-NEXT: R_386_32
+; IAS: mov {{.*}},0x4 {{.*}} .bss
; IAS: call
; SYMTAB-DAG: 00000004{{.*}}.data{{.*}}ArrayInit
-; IAS: mov {{.*}}, .data
-; IAS-NEXT: R_386_32
+; IAS: mov {{.*}},0x4 {{.*}} .data
; IAS: call
; SYMTAB-DAG: 00000018 {{.*}} .data {{.*}} ArrayInitPartial
-; IAS: mov {{.*}}, .data
-; IAS-NEXT: R_386_32
+; IAS: mov {{.*}},0x18 {{.*}} .data
; IAS: call
; SYMTAB-DAG: 00000008 {{.*}} .bss {{.*}} ArrayUninit
-; IAS: mov {{.*}}, .bss
-; IAS-NEXT: R_386_32
+; IAS: mov {{.*}},0x8 {{.*}} .bss
; IAS: call
diff --git a/tests_lit/llvm2ice_tests/mangle.ll b/tests_lit/llvm2ice_tests/mangle.ll
index 2d4384e..cae1d1f 100644
--- a/tests_lit/llvm2ice_tests/mangle.ll
+++ b/tests_lit/llvm2ice_tests/mangle.ll
@@ -4,10 +4,10 @@
; REQUIRES: allow_dump
; RUN: %p2i -i %s --args --verbose none -ffunction-sections | FileCheck %s
; TODO(stichnot): The following line causes this test to fail.
-; RUIN: %p2i -i %s --args --verbose none \
-; RUIN: | llvm-mc -triple=i686-none-nacl -filetype=obj
+; RUIN: %p2i --assemble --disassemble -i %s --args --verbose none \
+; RUIN: | FileCheck %s
; RUN: %p2i -i %s --args --verbose none --prefix Subzero -ffunction-sections \
-; RUN: | FileCheck --check-prefix=MANGLE %s
+; RUN: | FileCheck --check-prefix=MANGLE %s
define internal void @FuncC(i32 %i) {
entry:
diff --git a/tests_lit/llvm2ice_tests/nacl-atomic-cmpxchg-optimization.ll b/tests_lit/llvm2ice_tests/nacl-atomic-cmpxchg-optimization.ll
index e13fb9b..9cadd21 100644
--- a/tests_lit/llvm2ice_tests/nacl-atomic-cmpxchg-optimization.ll
+++ b/tests_lit/llvm2ice_tests/nacl-atomic-cmpxchg-optimization.ll
@@ -1,12 +1,8 @@
; This tests the optimization of atomic cmpxchg w/ following cmp + branches.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d -symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
; RUN: | FileCheck --check-prefix=O2 %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d -symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
; RUN: | FileCheck --check-prefix=OM1 %s
declare i32 @llvm.nacl.atomic.cmpxchg.i32(i32*, i32, i32, i32, i32)
@@ -36,16 +32,14 @@
ret i32 %succeeded_first_try
}
; O2-LABEL: test_atomic_cmpxchg_loop
-; O2: lock
-; O2-NEXT: cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
+; O2: lock cmpxchg DWORD PTR [e{{[^a].}}],e{{[^a]}}
; O2-NEXT: j{{e|ne}}
; Make sure the call isn't accidentally deleted.
; O2: call
;
; Check that the unopt version does have a cmp
; OM1-LABEL: test_atomic_cmpxchg_loop
-; OM1: lock
-; OM1-NEXT: cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
+; OM1: lock cmpxchg DWORD PTR [e{{[^a].}}],e{{[^a]}}
; OM1: cmp
; OM1: je
; OM1: call
@@ -67,8 +61,7 @@
ret i32 %old
}
; O2-LABEL: test_atomic_cmpxchg_loop2
-; O2: lock
-; O2-NEXT: cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
+; O2: lock cmpxchg DWORD PTR [e{{[^a].}}],e{{[^a]}}
; O2-NOT: cmp
; O2: jne
@@ -90,8 +83,7 @@
ret i32 %succeeded_first_try
}
; O2-LABEL: test_atomic_cmpxchg_loop_const
-; O2: lock
-; O2-NEXT: cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
+; O2: lock cmpxchg DWORD PTR [e{{[^a].}}],e{{[^a]}}
; O2-NEXT: j{{e|ne}}
; This is a case where the flags cannot be reused (compare is for some
@@ -112,8 +104,7 @@
ret i32 %old
}
; O2-LABEL: test_atomic_cmpxchg_no_opt
-; O2: lock
-; O2-NEXT: cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
+; O2: lock cmpxchg DWORD PTR [e{{[^a].}}],e{{[^a]}}
; O2: cmp
; O2: jle
@@ -136,8 +127,7 @@
ret i32 %r
}
; O2-LABEL: test_atomic_cmpxchg_no_opt2
-; O2: lock
-; O2-NEXT: cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
+; O2: lock cmpxchg DWORD PTR [e{{[^a].}}],e{{[^a]}}
; O2: mov {{.*}}
; O2: cmp
; O2: je
diff --git a/tests_lit/llvm2ice_tests/nacl-atomic-fence-all.ll b/tests_lit/llvm2ice_tests/nacl-atomic-fence-all.ll
index 28b1e4c..0b9b5b7 100644
--- a/tests_lit/llvm2ice_tests/nacl-atomic-fence-all.ll
+++ b/tests_lit/llvm2ice_tests/nacl-atomic-fence-all.ll
@@ -3,12 +3,8 @@
; (unlike the non-"all" variety of nacl.atomic.fence, which only
; applies to atomic load/stores).
;
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d -r -symbolize -x86-asm-syntax=intel - | FileCheck %s
-
-; TODO(jvoung): llvm-objdump doesn't symbolize global symbols well, so we
-; have 0 == g32_a, 4 == g32_b, 8 == g32_c, 12 == g32_d
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
+; RUN: | FileCheck %s
declare void @llvm.nacl.atomic.fence.all()
declare i32 @llvm.nacl.atomic.load.i32(i32*, i32)
@@ -45,21 +41,18 @@
}
; CHECK-LABEL: test_fused_load_add_a
; alloca store
-; CHECK: mov {{.*}}, esp
-; CHECK: mov dword ptr {{.*}}, 999
+; CHECK: mov {{.*}},esp
+; CHECK: mov DWORD PTR {{.*}},0x3e7
; atomic store (w/ its own mfence)
; The load + add are optimized into one everywhere.
-; CHECK: add {{.*}}, dword ptr [.bss]
-; CHECK-NEXT: R_386_32
-; CHECK: mov dword ptr
+; CHECK: add {{.*}},DWORD PTR {{.*}}.bss
+; CHECK: mov DWORD PTR
; CHECK: mfence
-; CHECK: add {{.*}}, dword ptr [.bss]
-; CHECK-NEXT: R_386_32
-; CHECK: mov dword ptr
-; CHECK: add {{.*}}, dword ptr [.bss]
-; CHECK-NEXT: R_386_32
+; CHECK: add {{.*}},DWORD PTR {{.*}}.bss
+; CHECK: mov DWORD PTR
+; CHECK: add {{.*}},DWORD PTR {{.*}}.bss
; CHECK: mfence
-; CHECK: mov dword ptr
+; CHECK: mov DWORD PTR
; Test with the fence moved up a bit.
define i32 @test_fused_load_add_b() {
@@ -88,22 +81,19 @@
}
; CHECK-LABEL: test_fused_load_add_b
; alloca store
-; CHECK: mov {{.*}}, esp
-; CHECK: mov dword ptr {{.*}}, 999
+; CHECK: mov {{.*}},esp
+; CHECK: mov DWORD PTR {{.*}},0x3e7
; atomic store (w/ its own mfence)
-; CHECK: add {{.*}}, dword ptr [.bss]
-; CHECK-NEXT: R_386_32
-; CHECK: mov dword ptr
+; CHECK: add {{.*}},DWORD PTR {{.*}}.bss
+; CHECK: mov DWORD PTR
; CHECK: mfence
-; CHECK: add {{.*}}, dword ptr [.bss]
-; CHECK-NEXT: R_386_32
-; CHECK: mov dword ptr
+; CHECK: add {{.*}},DWORD PTR {{.*}}.bss
+; CHECK: mov DWORD PTR
; CHECK: mfence
; Load + add can still be optimized into one instruction
; because it is not separated by a fence.
-; CHECK: add {{.*}}, dword ptr [.bss]
-; CHECK-NEXT: R_386_32
-; CHECK: mov dword ptr
+; CHECK: add {{.*}},DWORD PTR {{.*}}.bss
+; CHECK: mov DWORD PTR
; Test with the fence splitting a load/add.
define i32 @test_fused_load_add_c() {
@@ -132,24 +122,21 @@
}
; CHECK-LABEL: test_fused_load_add_c
; alloca store
-; CHECK: mov {{.*}}, esp
-; CHECK: mov dword ptr {{.*}}, 999
+; CHECK: mov {{.*}},esp
+; CHECK: mov DWORD PTR {{.*}},0x3e7
; atomic store (w/ its own mfence)
-; CHECK: add {{.*}}, dword ptr [.bss]
-; CHECK-NEXT: R_386_32
-; CHECK: mov dword ptr
+; CHECK: add {{.*}},DWORD PTR {{.*}}.bss
+; CHECK: mov DWORD PTR
; CHECK: mfence
; This load + add are no longer optimized into one,
; though perhaps it should be legal as long as
; the load stays on the same side of the fence.
-; CHECK: mov {{.*}}, dword ptr [.bss]
-; CHECK-NEXT: R_386_32
+; CHECK: mov {{.*}},DWORD PTR {{.*}}.bss
; CHECK: mfence
-; CHECK: add {{.*}}, 1
-; CHECK: mov dword ptr
-; CHECK: add {{.*}}, dword ptr [.bss]
-; CHECK-NEXT: R_386_32
-; CHECK: mov dword ptr
+; CHECK: add {{.*}},0x1
+; CHECK: mov DWORD PTR
+; CHECK: add {{.*}},DWORD PTR {{.*}}.bss
+; CHECK: mov DWORD PTR
; Test where a bunch of i8 loads could have been fused into one
@@ -187,12 +174,11 @@
ret i32 %b1234
}
; CHECK-LABEL: could_have_fused_loads
-; CHECK: mov {{.*}}, byte ptr
-; CHECK-NEXT: R_386_32
-; CHECK: mov {{.*}}, byte ptr
-; CHECK: mov {{.*}}, byte ptr
+; CHECK: mov {{.*}},BYTE PTR
+; CHECK: mov {{.*}},BYTE PTR
+; CHECK: mov {{.*}},BYTE PTR
; CHECK: mfence
-; CHECK: mov {{.*}}, byte ptr
+; CHECK: mov {{.*}},BYTE PTR
; Test where an identical load from two branches could have been hoisted
@@ -212,10 +198,8 @@
}
; CHECK-LABEL: could_have_hoisted_loads
; CHECK: jne {{.*}}
-; CHECK: mov {{.*}}, dword ptr [.bss]
-; CHECK-NEXT: R_386_32
+; CHECK: mov {{.*}},DWORD PTR {{.*}}.bss
; CHECK: ret
; CHECK: mfence
-; CHECK: mov {{.*}}, dword ptr [.bss]
-; CHECK-NEXT: R_386_32
+; CHECK: mov {{.*}},DWORD PTR {{.*}}.bss
; CHECK: ret
diff --git a/tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll b/tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll
index c16f7c0..fdd1d65 100644
--- a/tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll
+++ b/tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll
@@ -1,17 +1,11 @@
; This tests each of the supported NaCl atomic instructions for every
; size allowed.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
; RUN: | FileCheck %s
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
-; RUN: | FileCheck --check-prefix=CHECKO2 %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
+; RUN: | FileCheck --check-prefix=O2 %s
+; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
; RUN: | FileCheck %s
declare i8 @llvm.nacl.atomic.load.i8(i8*, i32)
@@ -53,8 +47,8 @@
ret i32 %r
}
; CHECK-LABEL: test_atomic_load_8
-; CHECK: mov {{.*}}, dword
-; CHECK: mov {{.*}}, byte
+; CHECK: mov {{.*}},DWORD
+; CHECK: mov {{.*}},BYTE
define i32 @test_atomic_load_16(i32 %iptr) {
entry:
@@ -64,8 +58,8 @@
ret i32 %r
}
; CHECK-LABEL: test_atomic_load_16
-; CHECK: mov {{.*}}, dword
-; CHECK: mov {{.*}}, word
+; CHECK: mov {{.*}},DWORD
+; CHECK: mov {{.*}},WORD
define i32 @test_atomic_load_32(i32 %iptr) {
entry:
@@ -74,8 +68,8 @@
ret i32 %r
}
; CHECK-LABEL: test_atomic_load_32
-; CHECK: mov {{.*}}, dword
-; CHECK: mov {{.*}}, dword
+; CHECK: mov {{.*}},DWORD
+; CHECK: mov {{.*}},DWORD
define i64 @test_atomic_load_64(i32 %iptr) {
entry:
@@ -84,8 +78,8 @@
ret i64 %r
}
; CHECK-LABEL: test_atomic_load_64
-; CHECK: movq x{{.*}}, qword
-; CHECK: movq qword {{.*}}, x{{.*}}
+; CHECK: movq x{{.*}},QWORD
+; CHECK: movq QWORD {{.*}},x{{.*}}
define i32 @test_atomic_load_32_with_arith(i32 %iptr) {
entry:
@@ -98,13 +92,13 @@
ret i32 %r2
}
; CHECK-LABEL: test_atomic_load_32_with_arith
-; CHECK: mov {{.*}}, dword
+; CHECK: mov {{.*}},DWORD
; The next instruction may be a separate load or folded into an add.
;
; In O2 mode, we know that the load and add are going to be fused.
-; CHECKO2-LABEL: test_atomic_load_32_with_arith
-; CHECKO2: mov {{.*}}, dword
-; CHECKO2: add {{.*}}, dword
+; O2-LABEL: test_atomic_load_32_with_arith
+; O2: mov {{.*}},DWORD
+; O2: add {{.*}},DWORD
define i32 @test_atomic_load_32_ignored(i32 %iptr) {
entry:
@@ -113,11 +107,11 @@
ret i32 0
}
; CHECK-LABEL: test_atomic_load_32_ignored
-; CHECK: mov {{.*}}, dword
-; CHECK: mov {{.*}}, dword
-; CHECKO2-LABEL: test_atomic_load_32_ignored
-; CHECKO2: mov {{.*}}, dword
-; CHECKO2: mov {{.*}}, dword
+; CHECK: mov {{.*}},DWORD
+; CHECK: mov {{.*}},DWORD
+; O2-LABEL: test_atomic_load_32_ignored
+; O2: mov {{.*}},DWORD
+; O2: mov {{.*}},DWORD
define i64 @test_atomic_load_64_ignored(i32 %iptr) {
entry:
@@ -126,8 +120,8 @@
ret i64 0
}
; CHECK-LABEL: test_atomic_load_64_ignored
-; CHECK: movq x{{.*}}, qword
-; CHECK: movq qword {{.*}}, x{{.*}}
+; CHECK: movq x{{.*}},QWORD
+; CHECK: movq QWORD {{.*}},x{{.*}}
;;; Store
@@ -139,7 +133,7 @@
ret void
}
; CHECK-LABEL: test_atomic_store_8
-; CHECK: mov byte
+; CHECK: mov BYTE
; CHECK: mfence
define void @test_atomic_store_16(i32 %iptr, i32 %v) {
@@ -150,7 +144,7 @@
ret void
}
; CHECK-LABEL: test_atomic_store_16
-; CHECK: mov word
+; CHECK: mov WORD
; CHECK: mfence
define void @test_atomic_store_32(i32 %iptr, i32 %v) {
@@ -160,7 +154,7 @@
ret void
}
; CHECK-LABEL: test_atomic_store_32
-; CHECK: mov dword
+; CHECK: mov DWORD
; CHECK: mfence
define void @test_atomic_store_64(i32 %iptr, i64 %v) {
@@ -170,8 +164,8 @@
ret void
}
; CHECK-LABEL: test_atomic_store_64
-; CHECK: movq x{{.*}}, qword
-; CHECK: movq qword {{.*}}, x{{.*}}
+; CHECK: movq x{{.*}},QWORD
+; CHECK: movq QWORD {{.*}},x{{.*}}
; CHECK: mfence
define void @test_atomic_store_64_const(i32 %iptr) {
@@ -181,10 +175,10 @@
ret void
}
; CHECK-LABEL: test_atomic_store_64_const
-; CHECK: mov {{.*}}, 1942892530
-; CHECK: mov {{.*}}, 2874
-; CHECK: movq x{{.*}}, qword
-; CHECK: movq qword {{.*}}, x{{.*}}
+; CHECK: mov {{.*}},0x73ce2ff2
+; CHECK: mov {{.*}},0xb3a
+; CHECK: movq x{{.*}},QWORD
+; CHECK: movq QWORD {{.*}},x{{.*}}
; CHECK: mfence
@@ -202,9 +196,8 @@
ret i32 %a_ext
}
; CHECK-LABEL: test_atomic_rmw_add_8
-; CHECK: lock
-; CHECK-NEXT: xadd byte {{.*}}, [[REG:.*]]
-; CHECK: {{mov|movzx}} {{.*}}, [[REG]]
+; CHECK: lock xadd BYTE {{.*}},[[REG:.*]]
+; CHECK: {{mov|movzx}} {{.*}},[[REG]]
define i32 @test_atomic_rmw_add_16(i32 %iptr, i32 %v) {
entry:
@@ -215,9 +208,8 @@
ret i32 %a_ext
}
; CHECK-LABEL: test_atomic_rmw_add_16
-; CHECK: lock
-; CHECK-NEXT: xadd word {{.*}}, [[REG:.*]]
-; CHECK: {{mov|movzx}} {{.*}}, [[REG]]
+; CHECK: lock xadd WORD {{.*}},[[REG:.*]]
+; CHECK: {{mov|movzx}} {{.*}},[[REG]]
define i32 @test_atomic_rmw_add_32(i32 %iptr, i32 %v) {
entry:
@@ -226,9 +218,8 @@
ret i32 %a
}
; CHECK-LABEL: test_atomic_rmw_add_32
-; CHECK: lock
-; CHECK-NEXT: xadd dword {{.*}}, [[REG:.*]]
-; CHECK: mov {{.*}}, [[REG]]
+; CHECK: lock xadd DWORD {{.*}},[[REG:.*]]
+; CHECK: mov {{.*}},[[REG]]
define i64 @test_atomic_rmw_add_64(i32 %iptr, i64 %v) {
entry:
@@ -238,27 +229,23 @@
}
; CHECK-LABEL: test_atomic_rmw_add_64
; CHECK: push ebx
-; CHECK: mov eax, dword ptr [{{.*}}]
-; CHECK: mov edx, dword ptr [{{.*}} + 4]
-; CHECK: mov ebx, eax
+; CHECK: mov eax,DWORD PTR [{{.*}}]
+; CHECK: mov edx,DWORD PTR [{{.*}}+0x4]
+; CHECK: [[LABEL:[^ ]*]]: {{.*}} mov ebx,eax
; RHS of add cannot be any of the e[abcd]x regs because they are
; clobbered in the loop, and the RHS needs to be remain live.
-; CHECK: add ebx, {{.*e.[^x]}}
-; CHECK: mov ecx, edx
-; CHECK: adc ecx, {{.*e.[^x]}}
+; CHECK: add ebx,{{.*e.[^x]}}
+; CHECK: mov ecx,edx
+; CHECK: adc ecx,{{.*e.[^x]}}
; Ptr cannot be eax, ebx, ecx, or edx (used up for the expected and desired).
; It can be esi, edi, or ebp though, for example (so we need to be careful
; about rejecting eb* and ed*.)
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
+; CHECK: jne [[LABEL]]
; Test with some more register pressure. When we have an alloca, ebp is
; used to manage the stack frame, so it cannot be used as a register either.
-define void @use_ptr(i32 %iptr) {
-entry:
- ret void
-}
+declare void @use_ptr(i32 %iptr)
define i64 @test_atomic_rmw_add_64_alloca(i32 %iptr, i64 %v) {
entry:
@@ -284,9 +271,8 @@
; not esp, since that's the stack pointer and mucking with it will break
; the later use_ptr function call.
; That pretty much leaves esi, or edi as the only viable registers.
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{[ds]}}i]
-; CHECK: call use_ptr
+; CHECK: lock cmpxchg8b QWORD PTR [e{{[ds]}}i]
+; CHECK: call {{.*}} R_{{.*}} use_ptr
define i32 @test_atomic_rmw_add_32_ignored(i32 %iptr, i32 %v) {
entry:
@@ -297,8 +283,7 @@
; Technically this could use "lock add" instead of "lock xadd", if liveness
; tells us that the destination variable is dead.
; CHECK-LABEL: test_atomic_rmw_add_32_ignored
-; CHECK: lock
-; CHECK-NEXT: xadd dword {{.*}}, [[REG:.*]]
+; CHECK: lock xadd DWORD {{.*}},[[REG:.*]]
; Atomic RMW 64 needs to be expanded into its own loop.
; Make sure that works w/ non-trivial function bodies.
@@ -322,15 +307,14 @@
}
; CHECK-LABEL: test_atomic_rmw_add_64_loop
; CHECK: push ebx
-; CHECK: mov eax, dword ptr [{{.*}}]
-; CHECK: mov edx, dword ptr [{{.*}} + 4]
-; CHECK: mov ebx, eax
-; CHECK: add ebx, {{.*e.[^x]}}
-; CHECK: mov ecx, edx
-; CHECK: adc ecx, {{.*e.[^x]}}
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK: mov eax,DWORD PTR [{{.*}}]
+; CHECK: mov edx,DWORD PTR [{{.*}}+0x4]
+; CHECK: [[LABEL:[^ ]*]]: {{.*}} mov ebx,eax
+; CHECK: add ebx,{{.*e.[^x]}}
+; CHECK: mov ecx,edx
+; CHECK: adc ecx,{{.*e.[^x]}}
+; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}+0x0]
+; CHECK: jne [[LABEL]]
;; sub
@@ -344,9 +328,8 @@
}
; CHECK-LABEL: test_atomic_rmw_sub_8
; CHECK: neg [[REG:.*]]
-; CHECK: lock
-; CHECK-NEXT: xadd byte {{.*}}, [[REG]]
-; CHECK: {{mov|movzx}} {{.*}}, [[REG]]
+; CHECK: lock xadd BYTE {{.*}},[[REG]]
+; CHECK: {{mov|movzx}} {{.*}},[[REG]]
define i32 @test_atomic_rmw_sub_16(i32 %iptr, i32 %v) {
entry:
@@ -358,9 +341,8 @@
}
; CHECK-LABEL: test_atomic_rmw_sub_16
; CHECK: neg [[REG:.*]]
-; CHECK: lock
-; CHECK-NEXT: xadd word {{.*}}, [[REG]]
-; CHECK: {{mov|movzx}} {{.*}}, [[REG]]
+; CHECK: lock xadd WORD {{.*}},[[REG]]
+; CHECK: {{mov|movzx}} {{.*}},[[REG]]
define i32 @test_atomic_rmw_sub_32(i32 %iptr, i32 %v) {
entry:
@@ -370,9 +352,8 @@
}
; CHECK-LABEL: test_atomic_rmw_sub_32
; CHECK: neg [[REG:.*]]
-; CHECK: lock
-; CHECK-NEXT: xadd dword {{.*}}, [[REG]]
-; CHECK: mov {{.*}}, [[REG]]
+; CHECK: lock xadd DWORD {{.*}},[[REG]]
+; CHECK: mov {{.*}},[[REG]]
define i64 @test_atomic_rmw_sub_64(i32 %iptr, i64 %v) {
entry:
@@ -382,15 +363,14 @@
}
; CHECK-LABEL: test_atomic_rmw_sub_64
; CHECK: push ebx
-; CHECK: mov eax, dword ptr [{{.*}}]
-; CHECK: mov edx, dword ptr [{{.*}} + 4]
-; CHECK: mov ebx, eax
-; CHECK: sub ebx, {{.*e.[^x]}}
-; CHECK: mov ecx, edx
-; CHECK: sbb ecx, {{.*e.[^x]}}
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK: mov eax,DWORD PTR [{{.*}}]
+; CHECK: mov edx,DWORD PTR [{{.*}}+0x4]
+; CHECK: [[LABEL:[^ ]*]]: {{.*}} mov ebx,eax
+; CHECK: sub ebx,{{.*e.[^x]}}
+; CHECK: mov ecx,edx
+; CHECK: sbb ecx,{{.*e.[^x]}}
+; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
+; CHECK: jne [[LABEL]]
define i32 @test_atomic_rmw_sub_32_ignored(i32 %iptr, i32 %v) {
@@ -402,8 +382,7 @@
; Could use "lock sub" instead of "neg; lock xadd"
; CHECK-LABEL: test_atomic_rmw_sub_32_ignored
; CHECK: neg [[REG:.*]]
-; CHECK: lock
-; CHECK-NEXT: xadd dword {{.*}}, [[REG]]
+; CHECK: lock xadd DWORD {{.*}},[[REG]]
;; or
@@ -416,13 +395,12 @@
ret i32 %a_ext
}
; CHECK-LABEL: test_atomic_rmw_or_8
-; CHECK: mov al, byte ptr
+; CHECK: mov al,BYTE PTR
; Dest cannot be eax here, because eax is used for the old value. Also want
; to make sure that cmpxchg's source is the same register.
; CHECK: or [[REG:[^a].]]
-; CHECK: lock
-; CHECK-NEXT: cmpxchg byte ptr [e{{[^a].}}], [[REG]]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg BYTE PTR [e{{[^a].}}],[[REG]]
+; CHECK: jne
define i32 @test_atomic_rmw_or_16(i32 %iptr, i32 %v) {
entry:
@@ -433,11 +411,10 @@
ret i32 %a_ext
}
; CHECK-LABEL: test_atomic_rmw_or_16
-; CHECK: mov ax, word ptr
+; CHECK: mov ax,WORD PTR
; CHECK: or [[REG:[^a].]]
-; CHECK: lock
-; CHECK-NEXT: cmpxchg word ptr [e{{[^a].}}], [[REG]]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg WORD PTR [e{{[^a].}}],[[REG]]
+; CHECK: jne
define i32 @test_atomic_rmw_or_32(i32 %iptr, i32 %v) {
entry:
@@ -446,11 +423,10 @@
ret i32 %a
}
; CHECK-LABEL: test_atomic_rmw_or_32
-; CHECK: mov eax, dword ptr
+; CHECK: mov eax,DWORD PTR
; CHECK: or [[REG:e[^a].]]
-; CHECK: lock
-; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}], [[REG]]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}],[[REG]]
+; CHECK: jne
define i64 @test_atomic_rmw_or_64(i32 %iptr, i64 %v) {
entry:
@@ -460,15 +436,14 @@
}
; CHECK-LABEL: test_atomic_rmw_or_64
; CHECK: push ebx
-; CHECK: mov eax, dword ptr [{{.*}}]
-; CHECK: mov edx, dword ptr [{{.*}} + 4]
-; CHECK: mov ebx, eax
-; CHECK: or ebx, {{.*e.[^x]}}
-; CHECK: mov ecx, edx
-; CHECK: or ecx, {{.*e.[^x]}}
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK: mov eax,DWORD PTR [{{.*}}]
+; CHECK: mov edx,DWORD PTR [{{.*}}+0x4]
+; CHECK: [[LABEL:[^ ]*]]: {{.*}} mov ebx,eax
+; CHECK: or ebx,{{.*e.[^x]}}
+; CHECK: mov ecx,edx
+; CHECK: or ecx,{{.*e.[^x]}}
+; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
+; CHECK: jne [[LABEL]]
define i32 @test_atomic_rmw_or_32_ignored(i32 %iptr, i32 %v) {
entry:
@@ -480,11 +455,10 @@
; Could just "lock or", if we inspect the liveness information first.
; Would also need a way to introduce "lock"'edness to binary
; operators without introducing overhead on the more common binary ops.
-; CHECK: mov eax, dword ptr
+; CHECK: mov eax,DWORD PTR
; CHECK: or [[REG:e[^a].]]
-; CHECK: lock
-; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}], [[REG]]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}],[[REG]]
+; CHECK: jne
;; and
@@ -497,11 +471,10 @@
ret i32 %a_ext
}
; CHECK-LABEL: test_atomic_rmw_and_8
-; CHECK: mov al, byte ptr
+; CHECK: mov al,BYTE PTR
; CHECK: and [[REG:[^a].]]
-; CHECK: lock
-; CHECK-NEXT: cmpxchg byte ptr [e{{[^a].}}], [[REG]]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg BYTE PTR [e{{[^a].}}],[[REG]]
+; CHECK: jne
define i32 @test_atomic_rmw_and_16(i32 %iptr, i32 %v) {
entry:
@@ -512,11 +485,10 @@
ret i32 %a_ext
}
; CHECK-LABEL: test_atomic_rmw_and_16
-; CHECK: mov ax, word ptr
+; CHECK: mov ax,WORD PTR
; CHECK: and
-; CHECK: lock
-; CHECK-NEXT: cmpxchg word ptr [e{{[^a].}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg WORD PTR [e{{[^a].}}]
+; CHECK: jne
define i32 @test_atomic_rmw_and_32(i32 %iptr, i32 %v) {
entry:
@@ -525,11 +497,10 @@
ret i32 %a
}
; CHECK-LABEL: test_atomic_rmw_and_32
-; CHECK: mov eax, dword ptr
+; CHECK: mov eax,DWORD PTR
; CHECK: and
-; CHECK: lock
-; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}]
+; CHECK: jne
define i64 @test_atomic_rmw_and_64(i32 %iptr, i64 %v) {
entry:
@@ -539,15 +510,14 @@
}
; CHECK-LABEL: test_atomic_rmw_and_64
; CHECK: push ebx
-; CHECK: mov eax, dword ptr [{{.*}}]
-; CHECK: mov edx, dword ptr [{{.*}} + 4]
-; CHECK: mov ebx, eax
-; CHECK: and ebx, {{.*e.[^x]}}
-; CHECK: mov ecx, edx
-; CHECK: and ecx, {{.*e.[^x]}}
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK: mov eax,DWORD PTR [{{.*}}]
+; CHECK: mov edx,DWORD PTR [{{.*}}+0x4]
+; CHECK: [[LABEL:[^ ]*]]: {{.*}} mov ebx,eax
+; CHECK: and ebx,{{.*e.[^x]}}
+; CHECK: mov ecx,edx
+; CHECK: and ecx,{{.*e.[^x]}}
+; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
+; CHECK: jne [[LABEL]]
define i32 @test_atomic_rmw_and_32_ignored(i32 %iptr, i32 %v) {
entry:
@@ -557,11 +527,10 @@
}
; CHECK-LABEL: test_atomic_rmw_and_32_ignored
; Could just "lock and"
-; CHECK: mov eax, dword ptr
+; CHECK: mov eax,DWORD PTR
; CHECK: and
-; CHECK: lock
-; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}]
+; CHECK: jne
;; xor
@@ -574,11 +543,10 @@
ret i32 %a_ext
}
; CHECK-LABEL: test_atomic_rmw_xor_8
-; CHECK: mov al, byte ptr
+; CHECK: mov al,BYTE PTR
; CHECK: xor [[REG:[^a].]]
-; CHECK: lock
-; CHECK-NEXT: cmpxchg byte ptr [e{{[^a].}}], [[REG]]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg BYTE PTR [e{{[^a].}}],[[REG]]
+; CHECK: jne
define i32 @test_atomic_rmw_xor_16(i32 %iptr, i32 %v) {
entry:
@@ -589,11 +557,10 @@
ret i32 %a_ext
}
; CHECK-LABEL: test_atomic_rmw_xor_16
-; CHECK: mov ax, word ptr
+; CHECK: mov ax,WORD PTR
; CHECK: xor
-; CHECK: lock
-; CHECK-NEXT: cmpxchg word ptr [e{{[^a].}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg WORD PTR [e{{[^a].}}]
+; CHECK: jne
define i32 @test_atomic_rmw_xor_32(i32 %iptr, i32 %v) {
@@ -603,11 +570,10 @@
ret i32 %a
}
; CHECK-LABEL: test_atomic_rmw_xor_32
-; CHECK: mov eax, dword ptr
+; CHECK: mov eax,DWORD PTR
; CHECK: xor
-; CHECK: lock
-; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}]
+; CHECK: jne
define i64 @test_atomic_rmw_xor_64(i32 %iptr, i64 %v) {
entry:
@@ -617,15 +583,14 @@
}
; CHECK-LABEL: test_atomic_rmw_xor_64
; CHECK: push ebx
-; CHECK: mov eax, dword ptr [{{.*}}]
-; CHECK: mov edx, dword ptr [{{.*}} + 4]
-; CHECK: mov ebx, eax
-; CHECK: or ebx, {{.*e.[^x]}}
-; CHECK: mov ecx, edx
-; CHECK: or ecx, {{.*e.[^x]}}
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK: mov eax,DWORD PTR [{{.*}}]
+; CHECK: mov edx,DWORD PTR [{{.*}}+0x4]
+; CHECK: mov ebx,eax
+; CHECK: or ebx,{{.*e.[^x]}}
+; CHECK: mov ecx,edx
+; CHECK: or ecx,{{.*e.[^x]}}
+; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
+; CHECK: jne
define i32 @test_atomic_rmw_xor_32_ignored(i32 %iptr, i32 %v) {
entry:
@@ -634,11 +599,10 @@
ret i32 %v
}
; CHECK-LABEL: test_atomic_rmw_xor_32_ignored
-; CHECK: mov eax, dword ptr
+; CHECK: mov eax,DWORD PTR
; CHECK: xor
-; CHECK: lock
-; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}]
+; CHECK: jne
;; exchange
@@ -651,7 +615,7 @@
ret i32 %a_ext
}
; CHECK-LABEL: test_atomic_rmw_xchg_8
-; CHECK: xchg byte ptr {{.*}}, [[REG:.*]]
+; CHECK: xchg BYTE PTR {{.*}},[[REG:.*]]
define i32 @test_atomic_rmw_xchg_16(i32 %iptr, i32 %v) {
entry:
@@ -662,7 +626,7 @@
ret i32 %a_ext
}
; CHECK-LABEL: test_atomic_rmw_xchg_16
-; CHECK: xchg word ptr {{.*}}, [[REG:.*]]
+; CHECK: xchg WORD PTR {{.*}},[[REG:.*]]
define i32 @test_atomic_rmw_xchg_32(i32 %iptr, i32 %v) {
entry:
@@ -671,7 +635,7 @@
ret i32 %a
}
; CHECK-LABEL: test_atomic_rmw_xchg_32
-; CHECK: xchg dword ptr {{.*}}, [[REG:.*]]
+; CHECK: xchg DWORD PTR {{.*}},[[REG:.*]]
define i64 @test_atomic_rmw_xchg_64(i32 %iptr, i64 %v) {
entry:
@@ -685,9 +649,8 @@
; CHECK-DAG: mov eax
; CHECK-DAG: mov ecx
; CHECK-DAG: mov ebx
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [{{e.[^x]}}]
-; CHECK: jne -{{[0-9]}}
+; CHECK: lock cmpxchg8b QWORD PTR [{{e.[^x]}}
+; CHECK: jne
define i32 @test_atomic_rmw_xchg_32_ignored(i32 %iptr, i32 %v) {
entry:
@@ -698,7 +661,7 @@
; In this case, ignoring the return value doesn't help. The xchg is
; used to do an atomic store.
; CHECK-LABEL: test_atomic_rmw_xchg_32_ignored
-; CHECK: xchg dword ptr {{.*}}, [[REG:.*]]
+; CHECK: xchg DWORD PTR {{.*}},[[REG:.*]]
;;;; Cmpxchg
@@ -713,11 +676,10 @@
ret i32 %old_ext
}
; CHECK-LABEL: test_atomic_cmpxchg_8
-; CHECK: mov eax, {{.*}}
+; CHECK: mov eax,{{.*}}
; Need to check that eax isn't used as the address register or the desired.
; since it is already used as the *expected* register.
-; CHECK: lock
-; CHECK-NEXT: cmpxchg byte ptr [e{{[^a].}}], {{[^a]}}l
+; CHECK: lock cmpxchg BYTE PTR [e{{[^a].}}],{{[^a]}}l
define i32 @test_atomic_cmpxchg_16(i32 %iptr, i32 %expected, i32 %desired) {
entry:
@@ -730,9 +692,8 @@
ret i32 %old_ext
}
; CHECK-LABEL: test_atomic_cmpxchg_16
-; CHECK: mov eax, {{.*}}
-; CHECK: lock
-; CHECK-NEXT: cmpxchg word ptr [e{{[^a].}}], {{[^a]}}x
+; CHECK: mov eax,{{.*}}
+; CHECK: lock cmpxchg WORD PTR [e{{[^a].}}],{{[^a]}}x
define i32 @test_atomic_cmpxchg_32(i32 %iptr, i32 %expected, i32 %desired) {
entry:
@@ -742,9 +703,8 @@
ret i32 %old
}
; CHECK-LABEL: test_atomic_cmpxchg_32
-; CHECK: mov eax, {{.*}}
-; CHECK: lock
-; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}], e{{[^a]}}
+; CHECK: mov eax,{{.*}}
+; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}],e{{[^a]}}
define i64 @test_atomic_cmpxchg_64(i32 %iptr, i64 %expected, i64 %desired) {
entry:
@@ -759,8 +719,7 @@
; CHECK-DAG: mov eax
; CHECK-DAG: mov ecx
; CHECK-DAG: mov ebx
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
+; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}+0x0]
; edx and eax are already the return registers, so they don't actually
; need to be reshuffled via movs. The next test stores the result
; somewhere, so in that case they do need to be mov'ed.
@@ -781,10 +740,9 @@
; CHECK-DAG: mov eax
; CHECK-DAG: mov ecx
; CHECK-DAG: mov ebx
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
-; CHECK-DAG: mov {{.*}}, edx
-; CHECK-DAG: mov {{.*}}, eax
+; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
+; CHECK-DAG: mov {{.*}},edx
+; CHECK-DAG: mov {{.*}},eax
; Test with some more register pressure. When we have an alloca, ebp is
; used to manage the stack frame, so it cannot be used as a register either.
@@ -813,9 +771,8 @@
; not esp, since that's the stack pointer and mucking with it will break
; the later use_ptr function call.
; That pretty much leaves esi, or edi as the only viable registers.
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{[ds]}}i]
-; CHECK: call use_ptr
+; CHECK: lock cmpxchg8b QWORD PTR [e{{[ds]}}i]
+; CHECK: call {{.*}} R_{{.*}} use_ptr
define i32 @test_atomic_cmpxchg_32_ignored(i32 %iptr, i32 %expected, i32 %desired) {
entry:
@@ -825,9 +782,8 @@
ret i32 0
}
; CHECK-LABEL: test_atomic_cmpxchg_32_ignored
-; CHECK: mov eax, {{.*}}
-; CHECK: lock
-; CHECK-NEXT: cmpxchg dword ptr [e{{[^a].}}]
+; CHECK: mov eax,{{.*}}
+; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}]
define i64 @test_atomic_cmpxchg_64_ignored(i32 %iptr, i64 %expected, i64 %desired) {
entry:
@@ -842,8 +798,7 @@
; CHECK-DAG: mov eax
; CHECK-DAG: mov ecx
; CHECK-DAG: mov ebx
-; CHECK: lock
-; CHECK-NEXT: cmpxchg8b qword ptr [e{{.[^x]}}]
+; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}+0x0]
;;;; Fence and is-lock-free.
@@ -871,7 +826,7 @@
ret i32 %r
}
; CHECK-LABEL: test_atomic_is_lock_free
-; CHECK: mov {{.*}}, 1
+; CHECK: mov {{.*}},0x1
define i32 @test_not_lock_free(i32 %iptr) {
entry:
@@ -881,7 +836,7 @@
ret i32 %r
}
; CHECK-LABEL: test_not_lock_free
-; CHECK: mov {{.*}}, 0
+; CHECK: mov {{.*}},0x0
define i32 @test_atomic_is_lock_free_ignored(i32 %iptr) {
entry:
@@ -890,11 +845,11 @@
ret i32 0
}
; CHECK-LABEL: test_atomic_is_lock_free_ignored
-; CHECK: mov {{.*}}, 0
+; CHECK: mov {{.*}},0x0
; This can get optimized out, because it's side-effect-free.
-; CHECKO2-LABEL: test_atomic_is_lock_free_ignored
-; CHECKO2-NOT: mov {{.*}}, 1
-; CHECKO2: mov {{.*}}, 0
+; O2-LABEL: test_atomic_is_lock_free_ignored
+; O2-NOT: mov {{.*}}, 1
+; O2: mov {{.*}},0x0
; TODO(jvoung): at some point we can take advantage of the
; fact that nacl.atomic.is.lock.free will resolve to a constant
@@ -915,7 +870,7 @@
ret i32 %z
}
; CHECK-LABEL: test_atomic_is_lock_free_can_dce
-; CHECK: mov {{.*}}, 1
+; CHECK: mov {{.*}},0x1
; CHECK: ret
; CHECK: add
; CHECK: ret
diff --git a/tests_lit/llvm2ice_tests/nacl-other-intrinsics.ll b/tests_lit/llvm2ice_tests/nacl-other-intrinsics.ll
index 29e8def..98373ee 100644
--- a/tests_lit/llvm2ice_tests/nacl-other-intrinsics.ll
+++ b/tests_lit/llvm2ice_tests/nacl-other-intrinsics.ll
@@ -1,26 +1,20 @@
; This tests the NaCl intrinsics not related to atomic operations.
-; RUN: %p2i -i %s --args -O2 --verbose none -sandbox \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose none -sandbox \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none -sandbox \
+; RUN: | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none -sandbox \
+; RUN: | FileCheck %s
; Do another run w/ O2 and a different check-prefix (otherwise O2 and Om1
; share the same "CHECK" prefix). This separate run helps check that
; some code is optimized out.
-; RUN: %p2i -i %s --args -O2 --verbose none -sandbox \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none -sandbox \
; RUN: | FileCheck --check-prefix=CHECKO2REM %s
; Do O2 runs without -sandbox to make sure llvm.nacl.read.tp gets
-; lowered to __nacl_read_tp instead of gs:[0x0].
+; lowered to __nacl_read_tp instead of gs:0x0.
; We also know that because it's O2, it'll have the O2REM optimizations.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
; RUN: | FileCheck --check-prefix=CHECKO2UNSANDBOXEDREM %s
declare i8* @llvm.nacl.read.tp()
@@ -51,11 +45,11 @@
ret i32 %__1
}
; CHECK-LABEL: test_nacl_read_tp
-; CHECK: mov e{{.*}}, dword ptr gs:[0]
+; CHECK: mov e{{.*}},DWORD PTR gs:0x0
; CHECKO2REM-LABEL: test_nacl_read_tp
-; CHECKO2REM: mov e{{.*}}, dword ptr gs:[0]
+; CHECKO2REM: mov e{{.*}},DWORD PTR gs:0x0
; CHECKO2UNSANDBOXEDREM-LABEL: test_nacl_read_tp
-; CHECKO2UNSANDBOXEDREM: call __nacl_read_tp
+; CHECKO2UNSANDBOXEDREM: call {{.*}} R_{{.*}} __nacl_read_tp
define i32 @test_nacl_read_tp_more_addressing() {
entry:
@@ -75,14 +69,14 @@
ret i32 %v
}
; CHECK-LABEL: test_nacl_read_tp_more_addressing
-; CHECK: mov e{{.*}}, dword ptr gs:[0]
-; CHECK: mov e{{.*}}, dword ptr gs:[0]
+; CHECK: mov e{{.*}},DWORD PTR gs:0x0
+; CHECK: mov e{{.*}},DWORD PTR gs:0x0
; CHECKO2REM-LABEL: test_nacl_read_tp_more_addressing
-; CHECKO2REM: mov e{{.*}}, dword ptr gs:[0]
-; CHECKO2REM: mov e{{.*}}, dword ptr gs:[0]
+; CHECKO2REM: mov e{{.*}},DWORD PTR gs:0x0
+; CHECKO2REM: mov e{{.*}},DWORD PTR gs:0x0
; CHECKO2UNSANDBOXEDREM-LABEL: test_nacl_read_tp_more_addressing
-; CHECKO2UNSANDBOXEDREM: call __nacl_read_tp
-; CHECKO2UNSANDBOXEDREM: call __nacl_read_tp
+; CHECKO2UNSANDBOXEDREM: call {{.*}} R_{{.*}} __nacl_read_tp
+; CHECKO2UNSANDBOXEDREM: call {{.*}} R_{{.*}} __nacl_read_tp
define i32 @test_nacl_read_tp_dead(i32 %a) {
entry:
@@ -93,9 +87,9 @@
}
; Consider nacl.read.tp side-effect free, so it can be eliminated.
; CHECKO2REM-LABEL: test_nacl_read_tp_dead
-; CHECKO2REM-NOT: mov e{{.*}}, dword ptr gs:[0]
+; CHECKO2REM-NOT: mov e{{.*}}, DWORD PTR gs:0x0
; CHECKO2UNSANDBOXEDREM-LABEL: test_nacl_read_tp_dead
-; CHECKO2UNSANDBOXEDREM-NOT: call __nacl_read_tp
+; CHECKO2UNSANDBOXEDREM-NOT: call {{.*}} R_{{.*}} __nacl_read_tp
define void @test_memcpy(i32 %iptr_dst, i32 %iptr_src, i32 %len) {
entry:
@@ -106,7 +100,7 @@
ret void
}
; CHECK-LABEL: test_memcpy
-; CHECK: call memcpy
+; CHECK: call {{.*}} R_{{.*}} memcpy
; CHECKO2REM-LABEL: test_memcpy
; CHECKO2UNSANDBOXEDREM-LABEL: test_memcpy
@@ -121,7 +115,7 @@
ret void
}
; CHECK-LABEL: test_memcpy_const_len_align
-; CHECK: call memcpy
+; CHECK: call {{.*}} R_{{.*}} memcpy
define void @test_memmove(i32 %iptr_dst, i32 %iptr_src, i32 %len) {
entry:
@@ -132,7 +126,7 @@
ret void
}
; CHECK-LABEL: test_memmove
-; CHECK: call memmove
+; CHECK: call {{.*}} R_{{.*}} memmove
define void @test_memmove_const_len_align(i32 %iptr_dst, i32 %iptr_src) {
entry:
@@ -143,7 +137,7 @@
ret void
}
; CHECK-LABEL: test_memmove_const_len_align
-; CHECK: call memmove
+; CHECK: call {{.*}} R_{{.*}} memmove
define void @test_memset(i32 %iptr_dst, i32 %wide_val, i32 %len) {
entry:
@@ -155,7 +149,7 @@
}
; CHECK-LABEL: test_memset
; CHECK: movzx
-; CHECK: call memset
+; CHECK: call {{.*}} R_{{.*}} memset
define void @test_memset_const_len_align(i32 %iptr_dst, i32 %wide_val) {
entry:
@@ -167,7 +161,7 @@
}
; CHECK-LABEL: test_memset_const_len_align
; CHECK: movzx
-; CHECK: call memset
+; CHECK: call {{.*}} R_{{.*}} memset
define void @test_memset_const_val(i32 %iptr_dst, i32 %len) {
entry:
@@ -177,8 +171,8 @@
}
; CHECK-LABEL: test_memset_const_val
; Make sure the argument is legalized (can't movzx reg, 0).
-; CHECK: movzx {{.*}}, {{[^0]}}
-; CHECK: call memset
+; CHECK: movzx {{.*}},{{[^0]}}
+; CHECK: call {{.*}} R_{{.*}} memset
define i32 @test_setjmplongjmp(i32 %iptr_env) {
@@ -196,11 +190,11 @@
ret i32 1
}
; CHECK-LABEL: test_setjmplongjmp
-; CHECK: call setjmp
-; CHECK: call longjmp
+; CHECK: call {{.*}} R_{{.*}} setjmp
+; CHECK: call {{.*}} R_{{.*}} longjmp
; CHECKO2REM-LABEL: test_setjmplongjmp
-; CHECKO2REM: call setjmp
-; CHECKO2REM: call longjmp
+; CHECKO2REM: call {{.*}} R_{{.*}} setjmp
+; CHECKO2REM: call {{.*}} R_{{.*}} longjmp
define i32 @test_setjmp_unused(i32 %iptr_env, i32 %i_other) {
entry:
@@ -211,7 +205,7 @@
; Don't consider setjmp side-effect free, so it's not eliminated if
; result unused.
; CHECKO2REM-LABEL: test_setjmp_unused
-; CHECKO2REM: call setjmp
+; CHECKO2REM: call {{.*}} R_{{.*}} setjmp
define float @test_sqrt_float(float %x, i32 %iptr) {
entry:
@@ -224,7 +218,7 @@
; CHECK-LABEL: test_sqrt_float
; CHECK: sqrtss xmm{{.*}}
; CHECK: sqrtss xmm{{.*}}
-; CHECK: sqrtss xmm{{.*}}, dword ptr
+; CHECK: sqrtss xmm{{.*}},DWORD PTR
define float @test_sqrt_float_mergeable_load(float %x, i32 %iptr) {
entry:
@@ -251,7 +245,7 @@
; CHECK-LABEL: test_sqrt_double
; CHECK: sqrtsd xmm{{.*}}
; CHECK: sqrtsd xmm{{.*}}
-; CHECK: sqrtsd xmm{{.*}}, qword ptr
+; CHECK: sqrtsd xmm{{.*}},QWORD PTR
define double @test_sqrt_double_mergeable_load(double %x, i32 %iptr) {
entry:
@@ -297,7 +291,7 @@
; CHECK-LABEL: test_bswap_16
; Make sure this is the right operand size so that the most significant bit
; to least significant bit rotation happens at the right boundary.
-; CHECK: rol {{[abcd]x|si|di|bp|word ptr}}, 8
+; CHECK: rol {{[abcd]x|si|di|bp|word ptr}},0x8
define i32 @test_bswap_32(i32 %x) {
entry:
@@ -325,10 +319,10 @@
; TODO(jvoung): If we detect that LZCNT is supported, then use that
; and avoid the need to do the cmovne and xor stuff to guarantee that
; the result is well-defined w/ input == 0.
-; CHECK: bsr [[REG_TMP:e.*]], {{.*}}
-; CHECK: mov [[REG_RES:e.*]], 63
-; CHECK: cmovne [[REG_RES]], [[REG_TMP]]
-; CHECK: xor [[REG_RES]], 31
+; CHECK: bsr [[REG_TMP:e.*]],{{.*}}
+; CHECK: mov [[REG_RES:e.*]],0x3f
+; CHECK: cmovne [[REG_RES]],[[REG_TMP]]
+; CHECK: xor [[REG_RES]],0x1f
define i32 @test_ctlz_32_const() {
entry:
@@ -339,7 +333,7 @@
; The dest operand must be a register and the source operand must be a register
; or memory.
; CHECK-LABEL: test_ctlz_32_const
-; CHECK: bsr e{{.*}}, {{.*}}e{{.*}}
+; CHECK: bsr e{{.*}},{{.*}}e{{.*}}
define i32 @test_ctlz_32_ignored(i32 %x) {
entry:
@@ -356,16 +350,16 @@
}
; CHECKO2REM-LABEL: test_ctlz_64
; CHECK-LABEL: test_ctlz_64
-; CHECK: bsr [[REG_TMP1:e.*]], {{.*}}
-; CHECK: mov [[REG_RES1:e.*]], 63
-; CHECK: cmovne [[REG_RES1]], [[REG_TMP1]]
-; CHECK: xor [[REG_RES1]], 31
-; CHECK: add [[REG_RES1]], 32
-; CHECK: bsr [[REG_RES2:e.*]], {{.*}}
-; CHECK: xor [[REG_RES2]], 31
-; CHECK: test [[REG_UPPER:.*]], [[REG_UPPER]]
-; CHECK: cmove [[REG_RES2]], [[REG_RES1]]
-; CHECK: mov {{.*}}, 0
+; CHECK: bsr [[REG_TMP1:e.*]],{{.*}}
+; CHECK: mov [[REG_RES1:e.*]],0x3f
+; CHECK: cmovne [[REG_RES1]],[[REG_TMP1]]
+; CHECK: xor [[REG_RES1]],0x1f
+; CHECK: add [[REG_RES1]],0x20
+; CHECK: bsr [[REG_RES2:e.*]],{{.*}}
+; CHECK: xor [[REG_RES2]],0x1f
+; CHECK: test [[REG_UPPER:.*]],[[REG_UPPER]]
+; CHECK: cmove [[REG_RES2]],[[REG_RES1]]
+; CHECK: mov {{.*}},0x0
define i32 @test_ctlz_64_const(i64 %x) {
entry:
@@ -374,8 +368,8 @@
ret i32 %r2
}
; CHECK-LABEL: test_ctlz_64_const
-; CHECK: bsr e{{.*}}, {{.*}}e{{.*}}
-; CHECK: bsr e{{.*}}, {{.*}}e{{.*}}
+; CHECK: bsr e{{.*}},{{.*}}e{{.*}}
+; CHECK: bsr e{{.*}},{{.*}}e{{.*}}
define i32 @test_ctlz_64_ignored(i64 %x) {
@@ -392,9 +386,9 @@
ret i32 %r
}
; CHECK-LABEL: test_cttz_32
-; CHECK: bsf [[REG_IF_NOTZERO:e.*]], {{.*}}
-; CHECK: mov [[REG_IF_ZERO:e.*]], 32
-; CHECK: cmovne [[REG_IF_ZERO]], [[REG_IF_NOTZERO]]
+; CHECK: bsf [[REG_IF_NOTZERO:e.*]],{{.*}}
+; CHECK: mov [[REG_IF_ZERO:e.*]],0x20
+; CHECK: cmovne [[REG_IF_ZERO]],[[REG_IF_NOTZERO]]
define i64 @test_cttz_64(i64 %x) {
entry:
@@ -402,14 +396,14 @@
ret i64 %r
}
; CHECK-LABEL: test_cttz_64
-; CHECK: bsf [[REG_IF_NOTZERO:e.*]], {{.*}}
-; CHECK: mov [[REG_RES1:e.*]], 32
-; CHECK: cmovne [[REG_RES1]], [[REG_IF_NOTZERO]]
-; CHECK: add [[REG_RES1]], 32
-; CHECK: bsf [[REG_RES2:e.*]], [[REG_LOWER:.*]]
-; CHECK: test [[REG_LOWER]], [[REG_LOWER]]
-; CHECK: cmove [[REG_RES2]], [[REG_RES1]]
-; CHECK: mov {{.*}}, 0
+; CHECK: bsf [[REG_IF_NOTZERO:e.*]],{{.*}}
+; CHECK: mov [[REG_RES1:e.*]],0x20
+; CHECK: cmovne [[REG_RES1]],[[REG_IF_NOTZERO]]
+; CHECK: add [[REG_RES1]],0x20
+; CHECK: bsf [[REG_RES2:e.*]],[[REG_LOWER:.*]]
+; CHECK: test [[REG_LOWER]],[[REG_LOWER]]
+; CHECK: cmove [[REG_RES2]],[[REG_RES1]]
+; CHECK: mov {{.*}},0x0
define i32 @test_popcount_32(i32 %x) {
entry:
@@ -417,7 +411,7 @@
ret i32 %r
}
; CHECK-LABEL: test_popcount_32
-; CHECK: call __popcountsi2
+; CHECK: call {{.*}} R_{{.*}} __popcountsi2
define i64 @test_popcount_64(i64 %x) {
entry:
@@ -425,10 +419,10 @@
ret i64 %r
}
; CHECK-LABEL: test_popcount_64
-; CHECK: call __popcountdi2
+; CHECK: call {{.*}} R_{{.*}} __popcountdi2
; __popcountdi2 only returns a 32-bit result, so clear the upper bits of
; the return value just in case.
-; CHECK: mov {{.*}}, 0
+; CHECK: mov {{.*}},0x0
define i32 @test_popcount_64_ret_i32(i64 %x) {
@@ -439,7 +433,7 @@
}
; If there is a trunc, then the mov {{.*}}, 0 is dead and gets optimized out.
; CHECKO2REM-LABEL: test_popcount_64_ret_i32
-; CHECKO2REM: call __popcountdi2
+; CHECKO2REM: call {{.*}} R_{{.*}} __popcountdi2
; CHECKO2REM-NOT: mov {{.*}}, 0
define void @test_stacksave_noalloca() {
@@ -449,8 +443,8 @@
ret void
}
; CHECK-LABEL: test_stacksave_noalloca
-; CHECK: mov {{.*}}, esp
-; CHECK: mov esp, {{.*}}
+; CHECK: mov {{.*}},esp
+; CHECK: mov esp,{{.*}}
declare i32 @foo(i32 %x)
@@ -482,7 +476,7 @@
}
; CHECK-LABEL: test_stacksave_multiple
; At least 3 copies of esp, but probably more from having to do the allocas.
-; CHECK: mov {{.*}}, esp
-; CHECK: mov {{.*}}, esp
-; CHECK: mov {{.*}}, esp
-; CHECK: mov esp, {{.*}}
+; CHECK: mov {{.*}},esp
+; CHECK: mov {{.*}},esp
+; CHECK: mov {{.*}},esp
+; CHECK: mov esp,{{.*}}
diff --git a/tests_lit/llvm2ice_tests/nop-insertion.ll b/tests_lit/llvm2ice_tests/nop-insertion.ll
index 8189b1e..8feeb77 100644
--- a/tests_lit/llvm2ice_tests/nop-insertion.ll
+++ b/tests_lit/llvm2ice_tests/nop-insertion.ll
@@ -18,7 +18,7 @@
entry:
%res = mul <4 x i32> %a, %b
ret <4 x i32> %res
-; PROB50-LABEL: mul_v4i32:
+; PROB50-LABEL: mul_v4i32
; PROB50: nop # variant = 3
; PROB50: subl $60, %esp
; PROB50: nop # variant = 4
@@ -41,7 +41,7 @@
; PROB50: nop # variant = 0
; PROB50: ret
-; PROB90-LABEL: mul_v4i32:
+; PROB90-LABEL: mul_v4i32
; PROB90: nop # variant = 3
; PROB90: subl $60, %esp
; PROB90: nop # variant = 4
@@ -71,7 +71,7 @@
; PROB90: nop # variant = 3
; PROB90: ret
-; MAXNOPS2-LABEL: mul_v4i32:
+; MAXNOPS2-LABEL: mul_v4i32
; MAXNOPS2: subl $60, %esp
; MAXNOPS2: nop # variant = 4
; MAXNOPS2: movups %xmm0, 32(%esp)
diff --git a/tests_lit/llvm2ice_tests/phi.ll b/tests_lit/llvm2ice_tests/phi.ll
index 83fdee5..133ba0f 100644
--- a/tests_lit/llvm2ice_tests/phi.ll
+++ b/tests_lit/llvm2ice_tests/phi.ll
@@ -2,9 +2,9 @@
; it tests that it does the right thing when it tries to enable
; compare/branch fusing.
-; RUN: %p2i -i %s --args -O2 --verbose none --phi-edge-split=0 \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d -symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
+; RUN: --phi-edge-split=0 \
+; RUN: | FileCheck %s
define internal i32 @testPhi1(i32 %arg) {
entry:
@@ -20,15 +20,15 @@
; Test that compare/branch fusing does not happen, and Phi lowering is
; put in the right place.
; CHECK-LABEL: testPhi1
-; CHECK: cmp {{.*}}, 0
-; CHECK: mov {{.*}}, 1
+; CHECK: cmp {{.*}},0x0
+; CHECK: mov {{.*}},0x1
; CHECK: jg
-; CHECK: mov {{.*}}, 0
+; CHECK: mov {{.*}},0x0
; CHECK: mov [[PHI:.*]],
-; CHECK: cmp {{.*}}, 0
+; CHECK: cmp {{.*}},0x0
; CHECK: je
-; CHECK: mov [[PHI]], 0
-; CHECK: movzx {{.*}}, [[PHI]]
+; CHECK: mov [[PHI]],0x0
+; CHECK: movzx {{.*}},[[PHI]]
define internal i32 @testPhi2(i32 %arg) {
entry:
@@ -42,11 +42,11 @@
}
; Test that compare/branch fusing and Phi lowering happens as expected.
; CHECK-LABEL: testPhi2
-; CHECK: mov {{.*}}, 12345
-; CHECK: cmp {{.*}}, 0
+; CHECK: mov {{.*}},0x3039
+; CHECK: cmp {{.*}},0x0
; CHECK-NEXT: jle
-; CHECK: mov [[PHI:.*]], 54321
-; CHECK: mov {{.*}}, [[PHI]]
+; CHECK: mov [[PHI:.*]],0xd431
+; CHECK: mov {{.*}},[[PHI]]
; Test that address mode inference doesn't extend past
; multi-definition, non-SSA Phi temporaries.
@@ -77,14 +77,14 @@
;
; testPhi3:
; .LtestPhi3$entry:
-; mov eax, dword ptr [esp+4]
+; mov eax, DWORD PTR [esp+4]
; mov ecx, eax
; .LtestPhi3$body:
-; mov ecx, dword ptr [ecx+1000]
+; mov ecx, DWORD PTR [ecx+1000]
; cmp ecx, 0
; jne .LtestPhi3$body
; .LtestPhi3$exit:
-; mov dword ptr [ecx+1000], eax
+; mov DWORD PTR [ecx+1000], eax
; ret
;
; This is bad because the final store address is supposed to be the
@@ -93,10 +93,10 @@
; CHECK-LABEL: testPhi3
; CHECK: push [[EBX:.*]]
-; CHECK: mov {{.*}}, dword ptr [esp
+; CHECK: mov {{.*}},DWORD PTR [esp
; CHECK: mov
-; CHECK: mov {{.*}}, dword ptr [[ADDR:.*1000]]
-; CHECK: cmp {{.*}}, 0
+; CHECK: mov {{.*}},DWORD PTR [[ADDR:.*0x3e8]]
+; CHECK: cmp {{.*}},0x0
; CHECK: jne
-; CHECK: mov dword ptr [[ADDR]]
+; CHECK: mov DWORD PTR [[ADDR]]
; CHECK: pop [[EBX]]
diff --git a/tests_lit/llvm2ice_tests/randomize-regalloc.ll b/tests_lit/llvm2ice_tests/randomize-regalloc.ll
index 1834c16..b40734d 100644
--- a/tests_lit/llvm2ice_tests/randomize-regalloc.ll
+++ b/tests_lit/llvm2ice_tests/randomize-regalloc.ll
@@ -2,81 +2,77 @@
; of this test will change with changes to the random number generator
; implementation.
-; RUN: %p2i -i %s --args -O2 -sz-seed=1 -randomize-regalloc \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 -sz-seed=1 \
+; RUN: -randomize-regalloc \
; RUN: | FileCheck %s --check-prefix=CHECK_1
-; RUN: %p2i -i %s --args -Om1 -sz-seed=1 -randomize-regalloc \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i -i %s --assemble --disassemble --args -Om1 -sz-seed=1 \
+; RUN: -randomize-regalloc \
; RUN: | FileCheck %s --check-prefix=OPTM1_1
; Same tests but with a different seed, just to verify randomness.
-; RUN: %p2i -i %s --args -O2 -sz-seed=123 -randomize-regalloc \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 -sz-seed=123 \
+; RUN: -randomize-regalloc \
; RUN: | FileCheck %s --check-prefix=CHECK_123
-; RUN: %p2i -i %s --args -Om1 -sz-seed=123 -randomize-regalloc \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i -i %s --assemble --disassemble --args -Om1 -sz-seed=123 \
+; RUN: -randomize-regalloc \
; RUN: | FileCheck %s --check-prefix=OPTM1_123
define <4 x i32> @mul_v4i32(<4 x i32> %a, <4 x i32> %b) {
entry:
%res = mul <4 x i32> %a, %b
ret <4 x i32> %res
-; OPTM1_1-LABEL: mul_v4i32:
-; OPTM1_1: sub esp, 60
-; OPTM1_1-NEXT: movups xmmword ptr [esp + 32], xmm0
-; OPTM1_1-NEXT: movups xmmword ptr [esp + 16], xmm1
-; OPTM1_1-NEXT: movups xmm0, xmmword ptr [esp + 32]
-; OPTM1_1-NEXT: pshufd xmm7, xmmword ptr [esp + 32], 49
-; OPTM1_1-NEXT: pshufd xmm4, xmmword ptr [esp + 16], 49
-; OPTM1_1-NEXT: pmuludq xmm0, xmmword ptr [esp + 16]
-; OPTM1_1-NEXT: pmuludq xmm7, xmm4
-; OPTM1_1-NEXT: shufps xmm0, xmm7, -120
-; OPTM1_1-NEXT: pshufd xmm0, xmm0, -40
-; OPTM1_1-NEXT: movups xmmword ptr [esp], xmm0
-; OPTM1_1-NEXT: movups xmm0, xmmword ptr [esp]
-; OPTM1_1-NEXT: add esp, 60
+; OPTM1_1-LABEL: mul_v4i32
+; OPTM1_1: sub esp,0x3c
+; OPTM1_1-NEXT: movups XMMWORD PTR [esp+0x20],xmm0
+; OPTM1_1-NEXT: movups XMMWORD PTR [esp+0x10],xmm1
+; OPTM1_1-NEXT: movups xmm0,XMMWORD PTR [esp+0x20]
+; OPTM1_1-NEXT: pshufd xmm7,XMMWORD PTR [esp+0x20],0x31
+; OPTM1_1-NEXT: pshufd xmm4,XMMWORD PTR [esp+0x10],0x31
+; OPTM1_1-NEXT: pmuludq xmm0,XMMWORD PTR [esp+0x10]
+; OPTM1_1-NEXT: pmuludq xmm7,xmm4
+; OPTM1_1-NEXT: shufps xmm0,xmm7,0x88
+; OPTM1_1-NEXT: pshufd xmm0,xmm0,0xd8
+; OPTM1_1-NEXT: movups XMMWORD PTR [esp],xmm0
+; OPTM1_1-NEXT: movups xmm0,XMMWORD PTR [esp]
+; OPTM1_1-NEXT: add esp,0x3c
; OPTM1_1-NEXT: ret
-; CHECK_1-LABEL: mul_v4i32:
-; CHECK_1: movups xmm6, xmm0
-; CHECK_1-NEXT: pshufd xmm0, xmm0, 49
-; CHECK_1-NEXT: pshufd xmm5, xmm1, 49
-; CHECK_1-NEXT: pmuludq xmm6, xmm1
-; CHECK_1-NEXT: pmuludq xmm0, xmm5
-; CHECK_1-NEXT: shufps xmm6, xmm0, -120
-; CHECK_1-NEXT: pshufd xmm6, xmm6, -40
-; CHECK_1-NEXT: movups xmm0, xmm6
+; CHECK_1-LABEL: mul_v4i32
+; CHECK_1: movups xmm6,xmm0
+; CHECK_1-NEXT: pshufd xmm0,xmm0,0x31
+; CHECK_1-NEXT: pshufd xmm5,xmm1,0x31
+; CHECK_1-NEXT: pmuludq xmm6,xmm1
+; CHECK_1-NEXT: pmuludq xmm0,xmm5
+; CHECK_1-NEXT: shufps xmm6,xmm0,0x88
+; CHECK_1-NEXT: pshufd xmm6,xmm6,0xd8
+; CHECK_1-NEXT: movups xmm0,xmm6
; CHECK_1-NEXT: ret
-; OPTM1_123-LABEL: mul_v4i32:
-; OPTM1_123: sub esp, 60
-; OPTM1_123-NEXT: movups xmmword ptr [esp + 32], xmm0
-; OPTM1_123-NEXT: movups xmmword ptr [esp + 16], xmm1
-; OPTM1_123-NEXT: movups xmm0, xmmword ptr [esp + 32]
-; OPTM1_123-NEXT: pshufd xmm2, xmmword ptr [esp + 32], 49
-; OPTM1_123-NEXT: pshufd xmm6, xmmword ptr [esp + 16], 49
-; OPTM1_123-NEXT: pmuludq xmm0, xmmword ptr [esp + 16]
-; OPTM1_123-NEXT: pmuludq xmm2, xmm6
-; OPTM1_123-NEXT: shufps xmm0, xmm2, -120
-; OPTM1_123-NEXT: pshufd xmm0, xmm0, -40
-; OPTM1_123-NEXT: movups xmmword ptr [esp], xmm0
-; OPTM1_123-NEXT: movups xmm0, xmmword ptr [esp]
-; OPTM1_123-NEXT: add esp, 60
+; OPTM1_123-LABEL: mul_v4i32
+; OPTM1_123: sub esp,0x3c
+; OPTM1_123-NEXT: movups XMMWORD PTR [esp+0x20],xmm0
+; OPTM1_123-NEXT: movups XMMWORD PTR [esp+0x10],xmm1
+; OPTM1_123-NEXT: movups xmm0,XMMWORD PTR [esp+0x20]
+; OPTM1_123-NEXT: pshufd xmm2,XMMWORD PTR [esp+0x20],0x31
+; OPTM1_123-NEXT: pshufd xmm6,XMMWORD PTR [esp+0x10],0x31
+; OPTM1_123-NEXT: pmuludq xmm0,XMMWORD PTR [esp+0x10]
+; OPTM1_123-NEXT: pmuludq xmm2,xmm6
+; OPTM1_123-NEXT: shufps xmm0,xmm2,0x88
+; OPTM1_123-NEXT: pshufd xmm0,xmm0,0xd8
+; OPTM1_123-NEXT: movups XMMWORD PTR [esp],xmm0
+; OPTM1_123-NEXT: movups xmm0,XMMWORD PTR [esp]
+; OPTM1_123-NEXT: add esp,0x3c
; OPTM1_123-NEXT: ret
-; CHECK_123-LABEL: mul_v4i32:
-; CHECK_123: movups xmm3, xmm0
-; CHECK_123-NEXT: pshufd xmm0, xmm0, 49
-; CHECK_123-NEXT: pshufd xmm7, xmm1, 49
-; CHECK_123-NEXT: pmuludq xmm3, xmm1
-; CHECK_123-NEXT: pmuludq xmm0, xmm7
-; CHECK_123-NEXT: shufps xmm3, xmm0, -120
-; CHECK_123-NEXT: pshufd xmm3, xmm3, -40
-; CHECK_123-NEXT: movups xmm0, xmm3
+; CHECK_123-LABEL: mul_v4i32
+; CHECK_123: movups xmm3,xmm0
+; CHECK_123-NEXT: pshufd xmm0,xmm0,0x31
+; CHECK_123-NEXT: pshufd xmm7,xmm1,0x31
+; CHECK_123-NEXT: pmuludq xmm3,xmm1
+; CHECK_123-NEXT: pmuludq xmm0,xmm7
+; CHECK_123-NEXT: shufps xmm3,xmm0,0x88
+; CHECK_123-NEXT: pshufd xmm3,xmm3,0xd8
+; CHECK_123-NEXT: movups xmm0,xmm3
; CHECK_123-NEXT: ret
}
diff --git a/tests_lit/llvm2ice_tests/returns_twice_no_coalesce.ll b/tests_lit/llvm2ice_tests/returns_twice_no_coalesce.ll
index b6540fc..8ffdbfa 100644
--- a/tests_lit/llvm2ice_tests/returns_twice_no_coalesce.ll
+++ b/tests_lit/llvm2ice_tests/returns_twice_no_coalesce.ll
@@ -1,9 +1,8 @@
; This file checks that SimpleCoalescing of local stack slots is not done
; when calling a function with the "returns twice" attribute.
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
+; RUN: | FileCheck %s
; Setjmp is a function with the "returns twice" attribute.
declare i32 @llvm.nacl.setjmp(i8*)
@@ -28,11 +27,11 @@
}
; CHECK-LABEL: call_returns_twice
-; CHECK: add [[REG1:.*]], 12345
-; CHECK: mov dword ptr [esp + [[OFF:.*]]], [[REG1]]
-; CHECK: add [[REG2:.*]], 54321
+; CHECK: add [[REG1:.*]],0x3039
+; CHECK: mov DWORD PTR [esp+[[OFF:.*]]],[[REG1]]
+; CHECK: add [[REG2:.*]],0xd431
; There should not be sharing of the stack slot.
-; CHECK-NOT: mov dword ptr [esp + [[OFF]]], [[REG2]]
+; CHECK-NOT: mov DWORD PTR [esp + [[OFF]]], [[REG2]]
define i32 @no_call_returns_twice(i32 %iptr_jmpbuf, i32 %x) {
entry:
@@ -50,11 +49,11 @@
}
; CHECK-LABEL: no_call_returns_twice
-; CHECK: add [[REG1:.*]], 12345
-; CHECK: mov dword ptr [esp + [[OFF:.*]]], [[REG1]]
-; CHECK: add [[REG2:.*]], 54321
+; CHECK: add [[REG1:.*]],0x3039
+; CHECK: mov DWORD PTR [esp+[[OFF:.*]]],[[REG1]]
+; CHECK: add [[REG2:.*]],0xd431
; Now there should be sharing of the stack slot (OFF is the same).
; Commenting out after disabling simple coalescing for -Om1.
; TODO(stichnot): Add it back if/when we add a flag to enable simple
; coalescing.
-; xCHECK: mov dword ptr [esp + [[OFF]]], [[REG2]]
+; xCHECK: mov DWORD PTR [esp + [[OFF]]], [[REG2]]
diff --git a/tests_lit/llvm2ice_tests/sdiv.ll b/tests_lit/llvm2ice_tests/sdiv.ll
index 4429f77..91d9008 100644
--- a/tests_lit/llvm2ice_tests/sdiv.ll
+++ b/tests_lit/llvm2ice_tests/sdiv.ll
@@ -1,12 +1,10 @@
; This checks the correctness of the lowering code for the small
; integer variants of sdiv and srem.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
+; RUN: | FileCheck %s
define i32 @sdiv_i8(i32 %a.i32, i32 %b.i32) {
entry:
@@ -15,7 +13,7 @@
%res = sdiv i8 %a, %b
%res.i32 = zext i8 %res to i32
ret i32 %res.i32
-; CHECK-LABEL: sdiv_i8:
+; CHECK-LABEL: sdiv_i8
; CHECK: cbw
; CHECK: idiv
}
@@ -27,7 +25,7 @@
%res = sdiv i16 %a, %b
%res.i32 = zext i16 %res to i32
ret i32 %res.i32
-; CHECK-LABEL: sdiv_i16:
+; CHECK-LABEL: sdiv_i16
; CHECK: cwd
; CHECK: idiv
}
@@ -36,7 +34,7 @@
entry:
%res = sdiv i32 %a, %b
ret i32 %res
-; CHECK-LABEL: sdiv_i32:
+; CHECK-LABEL: sdiv_i32
; CHECK: cdq
; CHECK: idiv
}
@@ -48,7 +46,7 @@
%res = srem i8 %a, %b
%res.i32 = zext i8 %res to i32
ret i32 %res.i32
-; CHECK-LABEL: srem_i8:
+; CHECK-LABEL: srem_i8
; CHECK: cbw
; CHECK: idiv
}
@@ -60,7 +58,7 @@
%res = srem i16 %a, %b
%res.i32 = zext i16 %res to i32
ret i32 %res.i32
-; CHECK-LABEL: srem_i16:
+; CHECK-LABEL: srem_i16
; CHECK: cwd
; CHECK: idiv
}
@@ -69,7 +67,7 @@
entry:
%res = srem i32 %a, %b
ret i32 %res
-; CHECK-LABEL: srem_i32:
+; CHECK-LABEL: srem_i32
; CHECK: cdq
; CHECK: idiv
}
diff --git a/tests_lit/llvm2ice_tests/select-opt.ll b/tests_lit/llvm2ice_tests/select-opt.ll
index 511078e..d784379 100644
--- a/tests_lit/llvm2ice_tests/select-opt.ll
+++ b/tests_lit/llvm2ice_tests/select-opt.ll
@@ -3,12 +3,10 @@
; regardless of the optimization level, so there are no special OPTM1
; match lines.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
+; RUN: | FileCheck %s
define void @testSelect(i32 %a, i32 %b) {
entry:
@@ -21,21 +19,15 @@
ret void
}
-define void @useInt(i32 %x) {
-entry:
- call void @useIntHelper(i32 %x)
- ret void
-}
-
-declare void @useIntHelper(i32)
+declare void @useInt(i32 %x)
; CHECK-LABEL: testSelect
; CHECK: cmp
; CHECK: cmp
-; CHECK: call useInt
+; CHECK: call {{.*}} R_{{.*}} useInt
; CHECK: cmp
; CHECK: cmp
-; CHECK: call useInt
+; CHECK: call {{.*}} R_{{.*}} useInt
; CHECK: ret
; Check for valid addressing mode in the cmp instruction when the
@@ -46,7 +38,7 @@
ret i32 %cond
}
; CHECK-LABEL: testSelectImm32
-; CHECK-NOT: cmp {{[0-9]+}},
+; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
; Check for valid addressing mode in the cmp instruction when the
; operand is an immediate. There is a different x86-32 lowering
@@ -57,4 +49,4 @@
ret i64 %cond
}
; CHECK-LABEL: testSelectImm64
-; CHECK-NOT: cmp {{[0-9]+}},
+; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
diff --git a/tests_lit/llvm2ice_tests/shift.ll b/tests_lit/llvm2ice_tests/shift.ll
index faa3971..9169b5f 100644
--- a/tests_lit/llvm2ice_tests/shift.ll
+++ b/tests_lit/llvm2ice_tests/shift.ll
@@ -1,12 +1,10 @@
; This is a test of C-level conversion operations that clang lowers
; into pairs of shifts.
-; RUN: %p2i -i %s --no-local-syms --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --no-local-syms --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --no-local-syms --args -O2 \
+; RUN: --verbose none | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --no-local-syms --args -Om1 \
+; RUN: --verbose none | FileCheck %s
@i1 = internal global [4 x i8] zeroinitializer, align 4
@i2 = internal global [4 x i8] zeroinitializer, align 4
@@ -23,8 +21,8 @@
ret void
}
; CHECK-LABEL: conv1
-; CHECK: shl {{.*}}, 24
-; CHECK: sar {{.*}}, 24
+; CHECK: shl {{.*}},0x18
+; CHECK: sar {{.*}},0x18
define void @conv2() {
entry:
@@ -37,5 +35,5 @@
ret void
}
; CHECK-LABEL: conv2
-; CHECK: shl {{.*}}, 16
-; CHECK: sar {{.*}}, 16
+; CHECK: shl {{.*}},0x10
+; CHECK: sar {{.*}},0x10
diff --git a/tests_lit/llvm2ice_tests/simple-loop.ll b/tests_lit/llvm2ice_tests/simple-loop.ll
index ded4a28..f6be7a8 100644
--- a/tests_lit/llvm2ice_tests/simple-loop.ll
+++ b/tests_lit/llvm2ice_tests/simple-loop.ll
@@ -1,12 +1,9 @@
; This tests a simple loop that sums the elements of an input array.
; The O2 check patterns represent the best code currently achieved.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d -symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d -symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
; RUN: | FileCheck --check-prefix=OPTM1 %s
define i32 @simple_loop(i32 %a, i32 %n) {
@@ -32,22 +29,22 @@
}
; CHECK-LABEL: simple_loop
-; CHECK: mov ecx, dword ptr [esp{{.*}}+{{.*}}{{[0-9]+}}]
-; CHECK: cmp ecx, 0
+; CHECK: mov ecx,DWORD PTR [esp{{.*}}+0x{{[0-9a-f]+}}]
+; CHECK: cmp ecx,0x0
; CHECK-NEXT: j{{le|g}} {{[0-9]}}
; Check for the combination of address mode inference, register
; allocation, and load/arithmetic fusing.
-; CHECK: add e{{..}}, dword ptr [e{{..}} + 4*[[IREG:e..]]]
+; CHECK: [[L:[0-9a-f]+]]{{.*}} add e{{..}},DWORD PTR [e{{..}}+[[IREG:e..]]*4]
; Check for incrementing of the register-allocated induction variable.
-; CHECK-NEXT: add [[IREG]], 1
+; CHECK-NEXT: add [[IREG]],0x1
; Check for comparing the induction variable against the loop size.
; CHECK-NEXT: cmp [[IREG]],
-; CHECK-NEXT: jl -{{[0-9]}}
+; CHECK-NEXT: jl [[L]]
;
; There's nothing remarkable under Om1 to test for, since Om1 generates
; such atrocious code (by design).
; OPTM1-LABEL: simple_loop
-; OPTM1: cmp {{.*}}, 0
+; OPTM1: cmp {{.*}},0x0
; OPTM1: jg
; OPTM1: ret
diff --git a/tests_lit/llvm2ice_tests/switch-opt.ll b/tests_lit/llvm2ice_tests/switch-opt.ll
index 5125411..05d3ecb 100644
--- a/tests_lit/llvm2ice_tests/switch-opt.ll
+++ b/tests_lit/llvm2ice_tests/switch-opt.ll
@@ -2,9 +2,8 @@
; same label which also results in phi instructions with multiple
; entries for the same incoming edge.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
+; RUN: | FileCheck %s
define i32 @testSwitch(i32 %a) {
entry:
@@ -49,7 +48,7 @@
ret i32 20
}
; CHECK-LABEL: testSwitchImm
-; CHECK-NOT: cmp {{[0-9]*}},
+; CHECK-NOT: cmp 0x{{[0-9a-f]*}},
; Test for correct 64-bit lowering.
define internal i32 @testSwitch64(i64 %a) {
@@ -78,21 +77,21 @@
ret i32 %retval.0
}
; CHECK-LABEL: testSwitch64
-; CHECK: cmp {{.*}}, 123
+; CHECK: cmp {{.*}},0x7b
; CHECK-NEXT: jne
-; CHECK-NEXT: cmp {{.*}}, 0
+; CHECK-NEXT: cmp {{.*}},0x0
; CHECK-NEXT: je
-; CHECK: cmp {{.*}}, 234
+; CHECK: cmp {{.*}},0xea
; CHECK-NEXT: jne
-; CHECK-NEXT: cmp {{.*}}, 0
+; CHECK-NEXT: cmp {{.*}},0x0
; CHECK-NEXT: je
-; CHECK: cmp {{.*}}, 345
+; CHECK: cmp {{.*}},0x159
; CHECK-NEXT: jne
-; CHECK-NEXT: cmp {{.*}}, 0
+; CHECK-NEXT: cmp {{.*}},0x0
; CHECK-NEXT: je
-; CHECK: cmp {{.*}}, 878082192
+; CHECK: cmp {{.*}},0x34567890
; CHECK-NEXT: jne
-; CHECK-NEXT: cmp {{.*}}, 18
+; CHECK-NEXT: cmp {{.*}},0x12
; CHECK-NEXT: je
; Similar to testSwitchImm, make sure proper addressing modes are
@@ -108,7 +107,7 @@
ret i32 20
}
; CHECK-LABEL: testSwitchImm64
-; CHECK: cmp {{.*}}, 1
+; CHECK: cmp {{.*}},0x1
; CHECK-NEXT: jne
-; CHECK-NEXT: cmp {{.*}}, 0
+; CHECK-NEXT: cmp {{.*}},0x0
; CHECK-NEXT: je
diff --git a/tests_lit/llvm2ice_tests/test_i1.ll b/tests_lit/llvm2ice_tests/test_i1.ll
index dd1d9c2..d3934cc 100644
--- a/tests_lit/llvm2ice_tests/test_i1.ll
+++ b/tests_lit/llvm2ice_tests/test_i1.ll
@@ -1,11 +1,9 @@
; Tests various aspects of i1 related lowering.
-; RUN: %p2i -i %s -a -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s -a -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble -a -O2 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble -a -Om1 --verbose none \
+; RUN: | FileCheck %s
; Test that and with true uses immediate 1, not -1.
define internal i32 @testAndTrue(i32 %arg) {
@@ -16,7 +14,7 @@
ret i32 %result
}
; CHECK-LABEL: testAndTrue
-; CHECK: and {{.*}}, 1
+; CHECK: and {{.*}},0x1
; Test that or with true uses immediate 1, not -1.
define internal i32 @testOrTrue(i32 %arg) {
@@ -27,7 +25,7 @@
ret i32 %result
}
; CHECK-LABEL: testOrTrue
-; CHECK: or {{.*}}, 1
+; CHECK: or {{.*}},0x1
; Test that xor with true uses immediate 1, not -1.
define internal i32 @testXorTrue(i32 %arg) {
@@ -38,7 +36,7 @@
ret i32 %result
}
; CHECK-LABEL: testXorTrue
-; CHECK: xor {{.*}}, 1
+; CHECK: xor {{.*}},0x1
; Test that trunc to i1 masks correctly.
define internal i32 @testTrunc(i32 %arg) {
@@ -48,7 +46,7 @@
ret i32 %result
}
; CHECK-LABEL: testTrunc
-; CHECK: and {{.*}}, 1
+; CHECK: and {{.*}},0x1
; Test zext to i8.
define internal i32 @testZextI8(i32 %arg) {
@@ -60,9 +58,9 @@
}
; CHECK-LABEL: testZextI8
; match the trunc instruction
-; CHECK: and {{.*}}, 1
+; CHECK: and {{.*}},0x1
; match the zext i1 instruction (NOTE: no mov need between i1 and i8).
-; CHECK: and {{.*}}, 1
+; CHECK: and {{.*}},0x1
; Test zext to i16.
define internal i32 @testZextI16(i32 %arg) {
@@ -74,10 +72,10 @@
}
; CHECK-LABEL: testZextI16
; match the trunc instruction
-; CHECK: and {{.*}}, 1
+; CHECK: and {{.*}},0x1
; match the zext i1 instruction (note 32-bit reg is used because it's shorter).
-; CHECK: movzx [[REG:e.*]], {{[a-d]l|byte ptr}}
-; CHECK: and [[REG]], 1
+; CHECK: movzx [[REG:e.*]],{{[a-d]l|BYTE PTR}}
+; CHECK: and [[REG]],0x1
; Test zext to i32.
define internal i32 @testZextI32(i32 %arg) {
@@ -88,10 +86,10 @@
}
; CHECK-LABEL: testZextI32
; match the trunc instruction
-; CHECK: and {{.*}}, 1
+; CHECK: and {{.*}},0x1
; match the zext i1 instruction
; CHECK: movzx
-; CHECK: and {{.*}}, 1
+; CHECK: and {{.*}},0x1
; Test zext to i64.
define internal i64 @testZextI64(i32 %arg) {
@@ -102,11 +100,11 @@
}
; CHECK-LABEL: testZextI64
; match the trunc instruction
-; CHECK: and {{.*}}, 1
+; CHECK: and {{.*}},0x1
; match the zext i1 instruction
; CHECK: movzx
-; CHECK: and {{.*}}, 1
-; CHECK: mov {{.*}}, 0
+; CHECK: and {{.*}},0x1
+; CHECK: mov {{.*}},0x0
; Test sext to i8.
define internal i32 @testSextI8(i32 %arg) {
@@ -118,10 +116,10 @@
}
; CHECK-LABEL: testSextI8
; match the trunc instruction
-; CHECK: and {{.*}}, 1
+; CHECK: and {{.*}},0x1
; match the sext i1 instruction
-; CHECK: shl [[REG:.*]], 7
-; CHECK-NEXT: sar [[REG]], 7
+; CHECK: shl [[REG:.*]],0x7
+; CHECK-NEXT: sar [[REG]],0x7
; Test sext to i16.
define internal i32 @testSextI16(i32 %arg) {
@@ -133,11 +131,11 @@
}
; CHECK-LABEL: testSextI16
; match the trunc instruction
-; CHECK: and {{.*}}, 1
+; CHECK: and {{.*}},0x1
; match the sext i1 instruction
-; CHECK: movzx e[[REG:.*]], {{[a-d]l|byte ptr}}
-; CHECK-NEXT: shl [[REG]], 15
-; CHECK-NEXT: sar [[REG]], 15
+; CHECK: movzx e[[REG:.*]],{{[a-d]l|BYTE PTR}}
+; CHECK-NEXT: shl [[REG]],0xf
+; CHECK-NEXT: sar [[REG]],0xf
; Test sext to i32.
define internal i32 @testSextI32(i32 %arg) {
@@ -148,11 +146,11 @@
}
; CHECK-LABEL: testSextI32
; match the trunc instruction
-; CHECK: and {{.*}}, 1
+; CHECK: and {{.*}},0x1
; match the sext i1 instruction
; CHECK: movzx [[REG:.*]],
-; CHECK-NEXT: shl [[REG]], 31
-; CHECK-NEXT: sar [[REG]], 31
+; CHECK-NEXT: shl [[REG]],0x1f
+; CHECK-NEXT: sar [[REG]],0x1f
; Test sext to i64.
define internal i64 @testSextI64(i32 %arg) {
@@ -163,11 +161,11 @@
}
; CHECK-LABEL: testSextI64
; match the trunc instruction
-; CHECK: and {{.*}}, 1
+; CHECK: and {{.*}},0x1
; match the sext i1 instruction
; CHECK: movzx [[REG:.*]],
-; CHECK-NEXT: shl [[REG]], 31
-; CHECK-NEXT: sar [[REG]], 31
+; CHECK-NEXT: shl [[REG]],0x1f
+; CHECK-NEXT: sar [[REG]],0x1f
; Test fptosi float to i1.
define internal i32 @testFptosiFloat(float %arg) {
@@ -178,10 +176,10 @@
}
; CHECK-LABEL: testFptosiFloat
; CHECK: cvttss2si
-; CHECK: and {{.*}}, 1
+; CHECK: and {{.*}},0x1
; CHECK: movzx [[REG:.*]],
-; CHECK-NEXT: shl [[REG]], 31
-; CHECK-NEXT: sar [[REG]], 31
+; CHECK-NEXT: shl [[REG]],0x1f
+; CHECK-NEXT: sar [[REG]],0x1f
; Test fptosi double to i1.
define internal i32 @testFptosiDouble(double %arg) {
@@ -192,7 +190,7 @@
}
; CHECK-LABEL: testFptosiDouble
; CHECK: cvttsd2si
-; CHECK: and {{.*}}, 1
+; CHECK: and {{.*}},0x1
; CHECK: movzx [[REG:.*]],
-; CHECK-NEXT: shl [[REG]], 31
-; CHECK-NEXT: sar [[REG]], 31
+; CHECK-NEXT: shl [[REG]],0x1f
+; CHECK-NEXT: sar [[REG]],0x1f
diff --git a/tests_lit/llvm2ice_tests/undef.ll b/tests_lit/llvm2ice_tests/undef.ll
index 12d134a..b033ce1 100644
--- a/tests_lit/llvm2ice_tests/undef.ll
+++ b/tests_lit/llvm2ice_tests/undef.ll
@@ -1,31 +1,27 @@
; This test checks that undef values are represented as zero.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -O2 -mattr=sse4.1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 -mattr=sse4.1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 -mattr=sse4.1 \
+; RUN: --verbose none | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -Om1 -mattr=sse4.1 \
+; RUN: --verbose none | FileCheck %s
define i32 @undef_i32() {
entry:
ret i32 undef
; CHECK-LABEL: undef_i32
-; CHECK: mov eax, 0
+; CHECK: mov eax,0x0
}
define i64 @undef_i64() {
entry:
ret i64 undef
; CHECK-LABEL: undef_i64
-; CHECK-DAG: mov eax, 0
-; CHECK-DAG: mov edx, 0
+; CHECK-DAG: mov eax,0x0
+; CHECK-DAG: mov edx,0x0
; CHECK: ret
}
@@ -33,7 +29,7 @@
entry:
ret float undef
; CHECK-LABEL: undef_float
-; CHECK: fld dword ptr [.L$float$0]
+; CHECK: fld DWORD PTR {{.*}} .L$float$0
}
define <4 x i1> @undef_v4i1() {
@@ -186,7 +182,7 @@
%val = insertelement <4 x float> %arg, float undef, i32 0
ret <4 x float> %val
; CHECK-LABEL: vector_insertelement_arg2
-; CHECK: movss {{.*}}, dword ptr [.L$float$0]
+; CHECK: movss {{.*}},DWORD PTR {{.*}} .L$float$0
}
define float @vector_extractelement_v4f32_index_0() {
diff --git a/tests_lit/llvm2ice_tests/unreachable.ll b/tests_lit/llvm2ice_tests/unreachable.ll
index 7938e17..fc6620f 100644
--- a/tests_lit/llvm2ice_tests/unreachable.ll
+++ b/tests_lit/llvm2ice_tests/unreachable.ll
@@ -1,11 +1,9 @@
; This tests the basic structure of the Unreachable instruction.
-; RUN: %p2i -i %s -a -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s -a -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble -a -O2 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble -a -Om1 --verbose none \
+; RUN: | FileCheck %s
define internal i32 @divide(i32 %num, i32 %den) {
entry:
@@ -22,7 +20,7 @@
; CHECK-LABEL: divide
; CHECK: cmp
-; CHECK: call ice_unreachable
+; CHECK: call {{.*}} R_{{.*}} ice_unreachable
; CHECK: cdq
; CHECK: idiv
; CHECK: ret
diff --git a/tests_lit/llvm2ice_tests/vector-arg.ll b/tests_lit/llvm2ice_tests/vector-arg.ll
index 4621821..2c6c2fc 100644
--- a/tests_lit/llvm2ice_tests/vector-arg.ll
+++ b/tests_lit/llvm2ice_tests/vector-arg.ll
@@ -1,12 +1,9 @@
; This file checks that Subzero generates code in accordance with the
; calling convention for vectors.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
; RUN: | FileCheck --check-prefix=OPTM1 %s
; The first five functions test that vectors are moved from their
@@ -15,64 +12,64 @@
define <4 x float> @test_returning_arg0(<4 x float> %arg0, <4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3, <4 x float> %arg4, <4 x float> %arg5) {
entry:
ret <4 x float> %arg0
-; CHECK-LABEL: test_returning_arg0:
+; CHECK-LABEL: test_returning_arg0
; CHECK-NOT: mov
; CHECK: ret
-; OPTM1-LABEL: test_returning_arg0:
-; OPTM1: movups xmmword ptr [[LOC:.*]], xmm0
-; OPTM1: movups xmm0, xmmword ptr [[LOC]]
+; OPTM1-LABEL: test_returning_arg0
+; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm0
+; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
; OPTM1: ret
}
define <4 x float> @test_returning_arg1(<4 x float> %arg0, <4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3, <4 x float> %arg4, <4 x float> %arg5) {
entry:
ret <4 x float> %arg1
-; CHECK-LABEL: test_returning_arg1:
-; CHECK: movups xmm0, xmm1
+; CHECK-LABEL: test_returning_arg1
+; CHECK: movups xmm0,xmm1
; CHECK: ret
-; OPTM1-LABEL: test_returning_arg1:
-; OPTM1: movups xmmword ptr [[LOC:.*]], xmm1
-; OPTM1: movups xmm0, xmmword ptr [[LOC]]
+; OPTM1-LABEL: test_returning_arg1
+; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm1
+; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
; OPTM1: ret
}
define <4 x float> @test_returning_arg2(<4 x float> %arg0, <4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3, <4 x float> %arg4, <4 x float> %arg5) {
entry:
ret <4 x float> %arg2
-; CHECK-LABEL: test_returning_arg2:
-; CHECK: movups xmm0, xmm2
+; CHECK-LABEL: test_returning_arg2
+; CHECK: movups xmm0,xmm2
; CHECK: ret
-; OPTM1-LABEL: test_returning_arg2:
-; OPTM1: movups xmmword ptr [[LOC:.*]], xmm2
-; OPTM1: movups xmm0, xmmword ptr [[LOC]]
+; OPTM1-LABEL: test_returning_arg2
+; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm2
+; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
; OPTM1: ret
}
define <4 x float> @test_returning_arg3(<4 x float> %arg0, <4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3, <4 x float> %arg4, <4 x float> %arg5) {
entry:
ret <4 x float> %arg3
-; CHECK-LABEL: test_returning_arg3:
-; CHECK: movups xmm0, xmm3
+; CHECK-LABEL: test_returning_arg3
+; CHECK: movups xmm0,xmm3
; CHECK: ret
-; OPTM1-LABEL: test_returning_arg3:
-; OPTM1: movups xmmword ptr [[LOC:.*]], xmm3
-; OPTM1: movups xmm0, xmmword ptr [[LOC]]
+; OPTM1-LABEL: test_returning_arg3
+; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm3
+; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
; OPTM1: ret
}
define <4 x float> @test_returning_arg4(<4 x float> %arg0, <4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3, <4 x float> %arg4, <4 x float> %arg5) {
entry:
ret <4 x float> %arg4
-; CHECK-LABEL: test_returning_arg4:
-; CHECK: movups xmm0, xmmword ptr [esp + 4]
+; CHECK-LABEL: test_returning_arg4
+; CHECK: movups xmm0,XMMWORD PTR [esp+0x4]
; CHECK: ret
-; OPTM1-LABEL: test_returning_arg4:
-; OPTM1: movups xmm0, xmmword ptr {{.*}}
+; OPTM1-LABEL: test_returning_arg4
+; OPTM1: movups xmm0,XMMWORD PTR {{.*}}
; OPTM1: ret
}
@@ -83,64 +80,64 @@
define <4 x float> @test_returning_interspersed_arg0(i32 %i32arg0, double %doublearg0, <4 x float> %arg0, <4 x float> %arg1, i32 %i32arg1, <4 x float> %arg2, double %doublearg1, <4 x float> %arg3, i32 %i32arg2, double %doublearg2, float %floatarg0, <4 x float> %arg4, <4 x float> %arg5, float %floatarg1) {
entry:
ret <4 x float> %arg0
-; CHECK-LABEL: test_returning_interspersed_arg0:
+; CHECK-LABEL: test_returning_interspersed_arg0
; CHECK-NOT: mov
; CHECK: ret
-; OPTM1-LABEL: test_returning_interspersed_arg0:
-; OPTM1: movups xmmword ptr [[LOC:.*]], xmm0
-; OPTM1: movups xmm0, xmmword ptr [[LOC]]
+; OPTM1-LABEL: test_returning_interspersed_arg0
+; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm0
+; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
; OPTM1: ret
}
define <4 x float> @test_returning_interspersed_arg1(i32 %i32arg0, double %doublearg0, <4 x float> %arg0, <4 x float> %arg1, i32 %i32arg1, <4 x float> %arg2, double %doublearg1, <4 x float> %arg3, i32 %i32arg2, double %doublearg2, float %floatarg0, <4 x float> %arg4, <4 x float> %arg5, float %floatarg1) {
entry:
ret <4 x float> %arg1
-; CHECK-LABEL: test_returning_interspersed_arg1:
-; CHECK: movups xmm0, xmm1
+; CHECK-LABEL: test_returning_interspersed_arg1
+; CHECK: movups xmm0,xmm1
; CHECK: ret
-; OPTM1-LABEL: test_returning_interspersed_arg1:
-; OPTM1: movups xmmword ptr [[LOC:.*]], xmm1
-; OPTM1: movups xmm0, xmmword ptr [[LOC]]
+; OPTM1-LABEL: test_returning_interspersed_arg1
+; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm1
+; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
; OPTM1: ret
}
define <4 x float> @test_returning_interspersed_arg2(i32 %i32arg0, double %doublearg0, <4 x float> %arg0, <4 x float> %arg1, i32 %i32arg1, <4 x float> %arg2, double %doublearg1, <4 x float> %arg3, i32 %i32arg2, double %doublearg2, float %floatarg0, <4 x float> %arg4, <4 x float> %arg5, float %floatarg1) {
entry:
ret <4 x float> %arg2
-; CHECK-LABEL: test_returning_interspersed_arg2:
-; CHECK: movups xmm0, xmm2
+; CHECK-LABEL: test_returning_interspersed_arg2
+; CHECK: movups xmm0,xmm2
; CHECK: ret
-; OPTM1-LABEL: test_returning_interspersed_arg2:
-; OPTM1: movups xmmword ptr [[LOC:.*]], xmm2
-; OPTM1: movups xmm0, xmmword ptr [[LOC]]
+; OPTM1-LABEL: test_returning_interspersed_arg2
+; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm2
+; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
; OPTM1: ret
}
define <4 x float> @test_returning_interspersed_arg3(i32 %i32arg0, double %doublearg0, <4 x float> %arg0, <4 x float> %arg1, i32 %i32arg1, <4 x float> %arg2, double %doublearg1, <4 x float> %arg3, i32 %i32arg2, double %doublearg2, float %floatarg0, <4 x float> %arg4, <4 x float> %arg5, float %floatarg1) {
entry:
ret <4 x float> %arg3
-; CHECK-LABEL: test_returning_interspersed_arg3:
-; CHECK: movups xmm0, xmm3
+; CHECK-LABEL: test_returning_interspersed_arg3
+; CHECK: movups xmm0,xmm3
; CHECK: ret
-; OPTM1-LABEL: test_returning_interspersed_arg3:
-; OPTM1: movups xmmword ptr [[LOC:.*]], xmm3
-; OPTM1: movups xmm0, xmmword ptr [[LOC]]
+; OPTM1-LABEL: test_returning_interspersed_arg3
+; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm3
+; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
; OPTM1: ret
}
define <4 x float> @test_returning_interspersed_arg4(i32 %i32arg0, double %doublearg0, <4 x float> %arg0, <4 x float> %arg1, i32 %i32arg1, <4 x float> %arg2, double %doublearg1, <4 x float> %arg3, i32 %i32arg2, double %doublearg2, float %floatarg0, <4 x float> %arg4, <4 x float> %arg5, float %floatarg1) {
entry:
ret <4 x float> %arg4
-; CHECK-LABEL: test_returning_interspersed_arg4:
-; CHECK: movups xmm0, xmmword ptr [esp + 52]
+; CHECK-LABEL: test_returning_interspersed_arg4
+; CHECK: movups xmm0,XMMWORD PTR [esp+0x34]
; CHECK: ret
-; OPTM1-LABEL: test_returning_interspersed_arg4:
-; OPTM1: movups xmm0, xmmword ptr {{.*}}
+; OPTM1-LABEL: test_returning_interspersed_arg4
+; OPTM1: movups xmm0,XMMWORD PTR {{.*}}
; OPTM1: ret
}
@@ -157,31 +154,31 @@
call void @killXmmRegisters()
call void @VectorArgs(<4 x float> %arg9, <4 x float> %arg8, <4 x float> %arg7, <4 x float> %arg6, <4 x float> %arg5, <4 x float> %arg4)
ret void
-; CHECK-LABEL: test_passing_vectors:
-; CHECK: sub esp, 32
-; CHECK: movups [[ARG5:.*]], xmmword ptr [esp + 64]
-; CHECK: movups xmmword ptr [esp], [[ARG5]]
-; CHECK: movups [[ARG6:.*]], xmmword ptr [esp + 48]
-; CHECK: movups xmmword ptr [esp + 16], [[ARG6]]
-; CHECK: movups xmm0, xmmword ptr [esp + 128]
-; CHECK: movups xmm1, xmmword ptr [esp + 112]
-; CHECK: movups xmm2, xmmword ptr [esp + 96]
-; CHECK: movups xmm3, xmmword ptr [esp + 80]
-; CHECK: call VectorArgs
-; CHECK-NEXT: add esp, 32
+; CHECK-LABEL: test_passing_vectors
+; CHECK: sub esp,0x20
+; CHECK: movups [[ARG5:.*]],XMMWORD PTR [esp+0x40]
+; CHECK: movups XMMWORD PTR [esp],[[ARG5]]
+; CHECK: movups [[ARG6:.*]],XMMWORD PTR [esp+0x30]
+; CHECK: movups XMMWORD PTR [esp+0x10],[[ARG6]]
+; CHECK: movups xmm0,XMMWORD PTR [esp+0x80]
+; CHECK: movups xmm1,XMMWORD PTR [esp+0x70]
+; CHECK: movups xmm2,XMMWORD PTR [esp+0x60]
+; CHECK: movups xmm3,XMMWORD PTR [esp+0x50]
+; CHECK: call {{.*}} R_{{.*}} VectorArgs
+; CHECK-NEXT: add esp,0x20
-; OPTM1-LABEL: test_passing_vectors:
-; OPTM1: sub esp, 32
-; OPTM1: movups [[ARG5:.*]], xmmword ptr {{.*}}
-; OPTM1: movups xmmword ptr [esp], [[ARG5]]
-; OPTM1: movups [[ARG6:.*]], xmmword ptr {{.*}}
-; OPTM1: movups xmmword ptr [esp + 16], [[ARG6]]
-; OPTM1: movups xmm0, xmmword ptr {{.*}}
-; OPTM1: movups xmm1, xmmword ptr {{.*}}
-; OPTM1: movups xmm2, xmmword ptr {{.*}}
-; OPTM1: movups xmm3, xmmword ptr {{.*}}
-; OPTM1: call VectorArgs
-; OPTM1-NEXT: add esp, 32
+; OPTM1-LABEL: test_passing_vectors
+; OPTM1: sub esp,0x20
+; OPTM1: movups [[ARG5:.*]],XMMWORD PTR {{.*}}
+; OPTM1: movups XMMWORD PTR [esp],[[ARG5]]
+; OPTM1: movups [[ARG6:.*]],XMMWORD PTR {{.*}}
+; OPTM1: movups XMMWORD PTR [esp+0x10],[[ARG6]]
+; OPTM1: movups xmm0,XMMWORD PTR {{.*}}
+; OPTM1: movups xmm1,XMMWORD PTR {{.*}}
+; OPTM1: movups xmm2,XMMWORD PTR {{.*}}
+; OPTM1: movups xmm3,XMMWORD PTR {{.*}}
+; OPTM1: call {{.*}} R_{{.*}} VectorArgs
+; OPTM1-NEXT: add esp,0x20
}
declare void @InterspersedVectorArgs(<4 x float>, i64, <4 x float>, i64, <4 x float>, float, <4 x float>, double, <4 x float>, i32, <4 x float>)
@@ -193,32 +190,32 @@
call void @killXmmRegisters()
call void @InterspersedVectorArgs(<4 x float> %arg9, i64 0, <4 x float> %arg8, i64 1, <4 x float> %arg7, float 2.000000e+00, <4 x float> %arg6, double 3.000000e+00, <4 x float> %arg5, i32 4, <4 x float> %arg4)
ret void
-; CHECK-LABEL: test_passing_vectors_interspersed:
-; CHECK: sub esp, 80
-; CHECK: movups [[ARG9:.*]], xmmword ptr [esp + 112]
-; CHECK: movups xmmword ptr [esp + 32], [[ARG9]]
-; CHECK: movups [[ARG11:.*]], xmmword ptr [esp + 96]
-; CHECK: movups xmmword ptr [esp + 64], [[ARG11]]
-; CHECK: movups xmm0, xmmword ptr [esp + 176]
-; CHECK: movups xmm1, xmmword ptr [esp + 160]
-; CHECK: movups xmm2, xmmword ptr [esp + 144]
-; CHECK: movups xmm3, xmmword ptr [esp + 128]
-; CHECK: call InterspersedVectorArgs
-; CHECK-NEXT: add esp, 80
+; CHECK-LABEL: test_passing_vectors_interspersed
+; CHECK: sub esp,0x50
+; CHECK: movups [[ARG9:.*]],XMMWORD PTR [esp+0x70]
+; CHECK: movups XMMWORD PTR [esp+0x20],[[ARG9]]
+; CHECK: movups [[ARG11:.*]],XMMWORD PTR [esp+0x60]
+; CHECK: movups XMMWORD PTR [esp+0x40],[[ARG11]]
+; CHECK: movups xmm0,XMMWORD PTR [esp+0xb0]
+; CHECK: movups xmm1,XMMWORD PTR [esp+0xa0]
+; CHECK: movups xmm2,XMMWORD PTR [esp+0x90]
+; CHECK: movups xmm3,XMMWORD PTR [esp+0x80]
+; CHECK: call {{.*}} R_{{.*}} InterspersedVectorArgs
+; CHECK-NEXT: add esp,0x50
; CHECK: ret
-; OPTM1-LABEL: test_passing_vectors_interspersed:
-; OPTM1: sub esp, 80
-; OPTM1: movups [[ARG9:.*]], xmmword ptr {{.*}}
-; OPTM1: movups xmmword ptr [esp + 32], [[ARG9]]
-; OPTM1: movups [[ARG11:.*]], xmmword ptr {{.*}}
-; OPTM1: movups xmmword ptr [esp + 64], [[ARG11]]
-; OPTM1: movups xmm0, xmmword ptr {{.*}}
-; OPTM1: movups xmm1, xmmword ptr {{.*}}
-; OPTM1: movups xmm2, xmmword ptr {{.*}}
-; OPTM1: movups xmm3, xmmword ptr {{.*}}
-; OPTM1: call InterspersedVectorArgs
-; OPTM1-NEXT: add esp, 80
+; OPTM1-LABEL: test_passing_vectors_interspersed
+; OPTM1: sub esp,0x50
+; OPTM1: movups [[ARG9:.*]],XMMWORD PTR {{.*}}
+; OPTM1: movups XMMWORD PTR [esp+0x20],[[ARG9]]
+; OPTM1: movups [[ARG11:.*]],XMMWORD PTR {{.*}}
+; OPTM1: movups XMMWORD PTR [esp+0x40],[[ARG11]]
+; OPTM1: movups xmm0,XMMWORD PTR {{.*}}
+; OPTM1: movups xmm1,XMMWORD PTR {{.*}}
+; OPTM1: movups xmm2,XMMWORD PTR {{.*}}
+; OPTM1: movups xmm3,XMMWORD PTR {{.*}}
+; OPTM1: call {{.*}} R_{{.*}} InterspersedVectorArgs
+; OPTM1-NEXT: add esp,0x50
; OPTM1: ret
}
@@ -232,16 +229,16 @@
%result = call <4 x float> @VectorReturn(<4 x float> %arg0)
%result2 = call <4 x float> @VectorReturn(<4 x float> %result)
ret void
-; CHECK-LABEL: test_receiving_vectors:
-; CHECK: call VectorReturn
+; CHECK-LABEL: test_receiving_vectors
+; CHECK: call {{.*}} R_{{.*}} VectorReturn
; CHECK-NOT: movups xmm0
-; CHECK: call VectorReturn
+; CHECK: call {{.*}} R_{{.*}} VectorReturn
; CHECK: ret
-; OPTM1-LABEL: test_receiving_vectors:
-; OPTM1: call VectorReturn
-; OPTM1: movups {{.*}}, xmm0
-; OPTM1: movups xmm0, {{.*}}
-; OPTM1: call VectorReturn
+; OPTM1-LABEL: test_receiving_vectors
+; OPTM1: call {{.*}} R_{{.*}} VectorReturn
+; OPTM1: movups {{.*}},xmm0
+; OPTM1: movups xmm0,{{.*}}
+; OPTM1: call {{.*}} R_{{.*}} VectorReturn
; OPTM1: ret
}
diff --git a/tests_lit/llvm2ice_tests/vector-arith.ll b/tests_lit/llvm2ice_tests/vector-arith.ll
index c7ef44f..86e338d 100644
--- a/tests_lit/llvm2ice_tests/vector-arith.ll
+++ b/tests_lit/llvm2ice_tests/vector-arith.ll
@@ -1,25 +1,19 @@
; This test checks support for vector arithmetic.
-; RUN: %p2i -i %s -a -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s -a -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s -a -O2 -mattr=sse4.1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i -i %s --assemble --disassemble -a -O2 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble -a -Om1 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble -a -O2 -mattr=sse4.1 --verbose none \
; RUN: | FileCheck --check-prefix=SSE41 %s
-; RUN: %p2i -i %s -a -Om1 -mattr=sse4.1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
-; RUN: | FileCheck --check-prefix=SSE41 %s
+; RUN: %p2i -i %s --assemble --disassemble -a -Om1 -mattr=sse4.1 \
+; RUN: --verbose none | FileCheck --check-prefix=SSE41 %s
define <4 x float> @test_fadd(<4 x float> %arg0, <4 x float> %arg1) {
entry:
%res = fadd <4 x float> %arg0, %arg1
ret <4 x float> %res
-; CHECK-LABEL: test_fadd:
+; CHECK-LABEL: test_fadd
; CHECK: addps
}
@@ -27,7 +21,7 @@
entry:
%res = fsub <4 x float> %arg0, %arg1
ret <4 x float> %res
-; CHECK-LABEL: test_fsub:
+; CHECK-LABEL: test_fsub
; CHECK: subps
}
@@ -35,7 +29,7 @@
entry:
%res = fmul <4 x float> %arg0, %arg1
ret <4 x float> %res
-; CHECK-LABEL: test_fmul:
+; CHECK-LABEL: test_fmul
; CHECK: mulps
}
@@ -43,7 +37,7 @@
entry:
%res = fdiv <4 x float> %arg0, %arg1
ret <4 x float> %res
-; CHECK-LABEL: test_fdiv:
+; CHECK-LABEL: test_fdiv
; CHECK: divps
}
@@ -51,7 +45,7 @@
entry:
%res = frem <4 x float> %arg0, %arg1
ret <4 x float> %res
-; CHECK-LABEL: test_frem:
+; CHECK-LABEL: test_frem
; CHECK: fmodf
; CHECK: fmodf
; CHECK: fmodf
@@ -62,7 +56,7 @@
entry:
%res = add <16 x i8> %arg0, %arg1
ret <16 x i8> %res
-; CHECK-LABEL: test_add_v16i8:
+; CHECK-LABEL: test_add_v16i8
; CHECK: paddb
}
@@ -70,7 +64,7 @@
entry:
%res = and <16 x i8> %arg0, %arg1
ret <16 x i8> %res
-; CHECK-LABEL: test_and_v16i8:
+; CHECK-LABEL: test_and_v16i8
; CHECK: pand
}
@@ -78,7 +72,7 @@
entry:
%res = or <16 x i8> %arg0, %arg1
ret <16 x i8> %res
-; CHECK-LABEL: test_or_v16i8:
+; CHECK-LABEL: test_or_v16i8
; CHECK: por
}
@@ -86,7 +80,7 @@
entry:
%res = xor <16 x i8> %arg0, %arg1
ret <16 x i8> %res
-; CHECK-LABEL: test_xor_v16i8:
+; CHECK-LABEL: test_xor_v16i8
; CHECK: pxor
}
@@ -94,7 +88,7 @@
entry:
%res = sub <16 x i8> %arg0, %arg1
ret <16 x i8> %res
-; CHECK-LABEL: test_sub_v16i8:
+; CHECK-LABEL: test_sub_v16i8
; CHECK: psubb
}
@@ -102,7 +96,7 @@
entry:
%res = mul <16 x i8> %arg0, %arg1
ret <16 x i8> %res
-; CHECK-LABEL: test_mul_v16i8:
+; CHECK-LABEL: test_mul_v16i8
; CHECK: imul
; CHECK: imul
; CHECK: imul
@@ -125,7 +119,7 @@
entry:
%res = shl <16 x i8> %arg0, %arg1
ret <16 x i8> %res
-; CHECK-LABEL: test_shl_v16i8:
+; CHECK-LABEL: test_shl_v16i8
; CHECK: shl
; CHECK: shl
; CHECK: shl
@@ -148,7 +142,7 @@
entry:
%res = lshr <16 x i8> %arg0, %arg1
ret <16 x i8> %res
-; CHECK-LABEL: test_lshr_v16i8:
+; CHECK-LABEL: test_lshr_v16i8
; CHECK: shr
; CHECK: shr
; CHECK: shr
@@ -171,7 +165,7 @@
entry:
%res = ashr <16 x i8> %arg0, %arg1
ret <16 x i8> %res
-; CHECK-LABEL: test_ashr_v16i8:
+; CHECK-LABEL: test_ashr_v16i8
; CHECK: sar
; CHECK: sar
; CHECK: sar
@@ -194,7 +188,7 @@
entry:
%res = udiv <16 x i8> %arg0, %arg1
ret <16 x i8> %res
-; CHECK-LABEL: test_udiv_v16i8:
+; CHECK-LABEL: test_udiv_v16i8
; CHECK: div
; CHECK: div
; CHECK: div
@@ -217,7 +211,7 @@
entry:
%res = sdiv <16 x i8> %arg0, %arg1
ret <16 x i8> %res
-; CHECK-LABEL: test_sdiv_v16i8:
+; CHECK-LABEL: test_sdiv_v16i8
; CHECK: idiv
; CHECK: idiv
; CHECK: idiv
@@ -240,7 +234,7 @@
entry:
%res = urem <16 x i8> %arg0, %arg1
ret <16 x i8> %res
-; CHECK-LABEL: test_urem_v16i8:
+; CHECK-LABEL: test_urem_v16i8
; CHECK: div
; CHECK: div
; CHECK: div
@@ -263,7 +257,7 @@
entry:
%res = srem <16 x i8> %arg0, %arg1
ret <16 x i8> %res
-; CHECK-LABEL: test_srem_v16i8:
+; CHECK-LABEL: test_srem_v16i8
; CHECK: idiv
; CHECK: idiv
; CHECK: idiv
@@ -286,7 +280,7 @@
entry:
%res = add <8 x i16> %arg0, %arg1
ret <8 x i16> %res
-; CHECK-LABEL: test_add_v8i16:
+; CHECK-LABEL: test_add_v8i16
; CHECK: paddw
}
@@ -294,7 +288,7 @@
entry:
%res = and <8 x i16> %arg0, %arg1
ret <8 x i16> %res
-; CHECK-LABEL: test_and_v8i16:
+; CHECK-LABEL: test_and_v8i16
; CHECK: pand
}
@@ -302,7 +296,7 @@
entry:
%res = or <8 x i16> %arg0, %arg1
ret <8 x i16> %res
-; CHECK-LABEL: test_or_v8i16:
+; CHECK-LABEL: test_or_v8i16
; CHECK: por
}
@@ -310,7 +304,7 @@
entry:
%res = xor <8 x i16> %arg0, %arg1
ret <8 x i16> %res
-; CHECK-LABEL: test_xor_v8i16:
+; CHECK-LABEL: test_xor_v8i16
; CHECK: pxor
}
@@ -318,7 +312,7 @@
entry:
%res = sub <8 x i16> %arg0, %arg1
ret <8 x i16> %res
-; CHECK-LABEL: test_sub_v8i16:
+; CHECK-LABEL: test_sub_v8i16
; CHECK: psubw
}
@@ -326,7 +320,7 @@
entry:
%res = mul <8 x i16> %arg0, %arg1
ret <8 x i16> %res
-; CHECK-LABEL: test_mul_v8i16:
+; CHECK-LABEL: test_mul_v8i16
; CHECK: pmullw
}
@@ -334,7 +328,7 @@
entry:
%res = shl <8 x i16> %arg0, %arg1
ret <8 x i16> %res
-; CHECK-LABEL: test_shl_v8i16:
+; CHECK-LABEL: test_shl_v8i16
; CHECK: shl
; CHECK: shl
; CHECK: shl
@@ -349,7 +343,7 @@
entry:
%res = lshr <8 x i16> %arg0, %arg1
ret <8 x i16> %res
-; CHECK-LABEL: test_lshr_v8i16:
+; CHECK-LABEL: test_lshr_v8i16
; CHECK: shr
; CHECK: shr
; CHECK: shr
@@ -364,7 +358,7 @@
entry:
%res = ashr <8 x i16> %arg0, %arg1
ret <8 x i16> %res
-; CHECK-LABEL: test_ashr_v8i16:
+; CHECK-LABEL: test_ashr_v8i16
; CHECK: sar
; CHECK: sar
; CHECK: sar
@@ -379,7 +373,7 @@
entry:
%res = udiv <8 x i16> %arg0, %arg1
ret <8 x i16> %res
-; CHECK-LABEL: test_udiv_v8i16:
+; CHECK-LABEL: test_udiv_v8i16
; CHECK: div
; CHECK: div
; CHECK: div
@@ -394,7 +388,7 @@
entry:
%res = sdiv <8 x i16> %arg0, %arg1
ret <8 x i16> %res
-; CHECK-LABEL: test_sdiv_v8i16:
+; CHECK-LABEL: test_sdiv_v8i16
; CHECK: idiv
; CHECK: idiv
; CHECK: idiv
@@ -409,7 +403,7 @@
entry:
%res = urem <8 x i16> %arg0, %arg1
ret <8 x i16> %res
-; CHECK-LABEL: test_urem_v8i16:
+; CHECK-LABEL: test_urem_v8i16
; CHECK: div
; CHECK: div
; CHECK: div
@@ -424,7 +418,7 @@
entry:
%res = srem <8 x i16> %arg0, %arg1
ret <8 x i16> %res
-; CHECK-LABEL: test_srem_v8i16:
+; CHECK-LABEL: test_srem_v8i16
; CHECK: idiv
; CHECK: idiv
; CHECK: idiv
@@ -439,7 +433,7 @@
entry:
%res = add <4 x i32> %arg0, %arg1
ret <4 x i32> %res
-; CHECK-LABEL: test_add_v4i32:
+; CHECK-LABEL: test_add_v4i32
; CHECK: paddd
}
@@ -447,7 +441,7 @@
entry:
%res = and <4 x i32> %arg0, %arg1
ret <4 x i32> %res
-; CHECK-LABEL: test_and_v4i32:
+; CHECK-LABEL: test_and_v4i32
; CHECK: pand
}
@@ -455,7 +449,7 @@
entry:
%res = or <4 x i32> %arg0, %arg1
ret <4 x i32> %res
-; CHECK-LABEL: test_or_v4i32:
+; CHECK-LABEL: test_or_v4i32
; CHECK: por
}
@@ -463,7 +457,7 @@
entry:
%res = xor <4 x i32> %arg0, %arg1
ret <4 x i32> %res
-; CHECK-LABEL: test_xor_v4i32:
+; CHECK-LABEL: test_xor_v4i32
; CHECK: pxor
}
@@ -471,7 +465,7 @@
entry:
%res = sub <4 x i32> %arg0, %arg1
ret <4 x i32> %res
-; CHECK-LABEL: test_sub_v4i32:
+; CHECK-LABEL: test_sub_v4i32
; CHECK: psubd
}
@@ -479,11 +473,11 @@
entry:
%res = mul <4 x i32> %arg0, %arg1
ret <4 x i32> %res
-; CHECK-LABEL: test_mul_v4i32:
+; CHECK-LABEL: test_mul_v4i32
; CHECK: pmuludq
; CHECK: pmuludq
;
-; SSE41-LABEL: test_mul_v4i32:
+; SSE41-LABEL: test_mul_v4i32
; SSE41: pmulld
}
@@ -491,21 +485,21 @@
entry:
%res = shl <4 x i32> %arg0, %arg1
ret <4 x i32> %res
-; CHECK-LABEL: test_shl_v4i32:
+; CHECK-LABEL: test_shl_v4i32
; CHECK: shl
; CHECK: shl
; CHECK: shl
; CHECK: shl
; This line is to ensure that pmulld is generated in test_mul_v4i32 above.
-; SSE41-LABEL: test_shl_v4i32:
+; SSE41-LABEL: test_shl_v4i32
}
define <4 x i32> @test_lshr_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
entry:
%res = lshr <4 x i32> %arg0, %arg1
ret <4 x i32> %res
-; CHECK-LABEL: test_lshr_v4i32:
+; CHECK-LABEL: test_lshr_v4i32
; CHECK: shr
; CHECK: shr
; CHECK: shr
@@ -516,7 +510,7 @@
entry:
%res = ashr <4 x i32> %arg0, %arg1
ret <4 x i32> %res
-; CHECK-LABEL: test_ashr_v4i32:
+; CHECK-LABEL: test_ashr_v4i32
; CHECK: sar
; CHECK: sar
; CHECK: sar
@@ -527,7 +521,7 @@
entry:
%res = udiv <4 x i32> %arg0, %arg1
ret <4 x i32> %res
-; CHECK-LABEL: test_udiv_v4i32:
+; CHECK-LABEL: test_udiv_v4i32
; CHECK: div
; CHECK: div
; CHECK: div
@@ -538,7 +532,7 @@
entry:
%res = sdiv <4 x i32> %arg0, %arg1
ret <4 x i32> %res
-; CHECK-LABEL: test_sdiv_v4i32:
+; CHECK-LABEL: test_sdiv_v4i32
; CHECK: idiv
; CHECK: idiv
; CHECK: idiv
@@ -549,7 +543,7 @@
entry:
%res = urem <4 x i32> %arg0, %arg1
ret <4 x i32> %res
-; CHECK-LABEL: test_urem_v4i32:
+; CHECK-LABEL: test_urem_v4i32
; CHECK: div
; CHECK: div
; CHECK: div
@@ -560,7 +554,7 @@
entry:
%res = srem <4 x i32> %arg0, %arg1
ret <4 x i32> %res
-; CHECK-LABEL: test_srem_v4i32:
+; CHECK-LABEL: test_srem_v4i32
; CHECK: idiv
; CHECK: idiv
; CHECK: idiv
diff --git a/tests_lit/llvm2ice_tests/vector-bitcast.ll b/tests_lit/llvm2ice_tests/vector-bitcast.ll
index a91b107..ac9f49e 100644
--- a/tests_lit/llvm2ice_tests/vector-bitcast.ll
+++ b/tests_lit/llvm2ice_tests/vector-bitcast.ll
@@ -1,12 +1,9 @@
; This file tests bitcasts of vector type. For most operations, these
; should be lowered to a no-op on -O2.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d -symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d -symbolize -x86-asm-syntax=intel - \
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
; RUN: | FileCheck --check-prefix=OPTM1 %s
define <16 x i8> @test_bitcast_v16i8_to_v16i8(<16 x i8> %arg) {
@@ -32,7 +29,7 @@
%res = bitcast <16 x i8> %arg to <4 x i32>
ret <4 x i32> %res
-; CHECK-LABEL: test_bitcast_v16i8_to_v4i32:
+; CHECK-LABEL: test_bitcast_v16i8_to_v4i32
; CHECK-NEXT: ret
}
@@ -41,7 +38,7 @@
%res = bitcast <16 x i8> %arg to <4 x float>
ret <4 x float> %res
-; CHECK-LABEL: test_bitcast_v16i8_to_v4f32:
+; CHECK-LABEL: test_bitcast_v16i8_to_v4f32
; CHECK-NEXT: ret
}
@@ -50,7 +47,7 @@
%res = bitcast <8 x i16> %arg to <16 x i8>
ret <16 x i8> %res
-; CHECK-LABEL: test_bitcast_v8i16_to_v16i8:
+; CHECK-LABEL: test_bitcast_v8i16_to_v16i8
; CHECK-NEXT: ret
}
@@ -59,7 +56,7 @@
%res = bitcast <8 x i16> %arg to <8 x i16>
ret <8 x i16> %res
-; CHECK-LABEL: test_bitcast_v8i16_to_v8i16:
+; CHECK-LABEL: test_bitcast_v8i16_to_v8i16
; CHECK-NEXT: ret
}
@@ -68,7 +65,7 @@
%res = bitcast <8 x i16> %arg to <4 x i32>
ret <4 x i32> %res
-; CHECK-LABEL: test_bitcast_v8i16_to_v4i32:
+; CHECK-LABEL: test_bitcast_v8i16_to_v4i32
; CHECK-NEXT: ret
}
@@ -77,7 +74,7 @@
%res = bitcast <8 x i16> %arg to <4 x float>
ret <4 x float> %res
-; CHECK-LABEL: test_bitcast_v8i16_to_v4f32:
+; CHECK-LABEL: test_bitcast_v8i16_to_v4f32
; CHECK-NEXT: ret
}
@@ -86,7 +83,7 @@
%res = bitcast <4 x i32> %arg to <16 x i8>
ret <16 x i8> %res
-; CHECK-LABEL: test_bitcast_v4i32_to_v16i8:
+; CHECK-LABEL: test_bitcast_v4i32_to_v16i8
; CHECK-NEXT: ret
}
@@ -95,7 +92,7 @@
%res = bitcast <4 x i32> %arg to <8 x i16>
ret <8 x i16> %res
-; CHECK-LABEL: test_bitcast_v4i32_to_v8i16:
+; CHECK-LABEL: test_bitcast_v4i32_to_v8i16
; CHECK-NEXT: ret
}
@@ -104,7 +101,7 @@
%res = bitcast <4 x i32> %arg to <4 x i32>
ret <4 x i32> %res
-; CHECK-LABEL: test_bitcast_v4i32_to_v4i32:
+; CHECK-LABEL: test_bitcast_v4i32_to_v4i32
; CHECK-NEXT: ret
}
@@ -113,7 +110,7 @@
%res = bitcast <4 x i32> %arg to <4 x float>
ret <4 x float> %res
-; CHECK-LABEL: test_bitcast_v4i32_to_v4f32:
+; CHECK-LABEL: test_bitcast_v4i32_to_v4f32
; CHECK-NEXT: ret
}
@@ -122,7 +119,7 @@
%res = bitcast <4 x float> %arg to <16 x i8>
ret <16 x i8> %res
-; CHECK-LABEL: test_bitcast_v4f32_to_v16i8:
+; CHECK-LABEL: test_bitcast_v4f32_to_v16i8
; CHECK-NEXT: ret
}
@@ -131,7 +128,7 @@
%res = bitcast <4 x float> %arg to <8 x i16>
ret <8 x i16> %res
-; CHECK-LABEL: test_bitcast_v4f32_to_v8i16:
+; CHECK-LABEL: test_bitcast_v4f32_to_v8i16
; CHECK-NEXT: ret
}
@@ -140,7 +137,7 @@
%res = bitcast <4 x float> %arg to <4 x i32>
ret <4 x i32> %res
-; CHECK-LABEL: test_bitcast_v4f32_to_v4i32:
+; CHECK-LABEL: test_bitcast_v4f32_to_v4i32
; CHECK-NEXT: ret
}
@@ -149,7 +146,7 @@
%res = bitcast <4 x float> %arg to <4 x float>
ret <4 x float> %res
-; CHECK-LABEL: test_bitcast_v4f32_to_v4f32:
+; CHECK-LABEL: test_bitcast_v4f32_to_v4f32
; CHECK-NEXT: ret
}
@@ -158,10 +155,10 @@
%res = bitcast <8 x i1> %arg to i8
ret i8 %res
-; CHECK-LABEL: test_bitcast_v8i1_to_i8:
-; CHECK: call Sz_bitcast_v8i1_to_i8
+; CHECK-LABEL: test_bitcast_v8i1_to_i8
+; CHECK: call {{.*}} R_{{.*}} Sz_bitcast_v8i1_to_i8
-; OPTM1-LABEL: test_bitcast_v8i1_to_i8:
+; OPTM1-LABEL: test_bitcast_v8i1_to_i8
; OPMT1: call -4
}
@@ -170,10 +167,10 @@
%res = bitcast <16 x i1> %arg to i16
ret i16 %res
-; CHECK-LABEL: test_bitcast_v16i1_to_i16:
-; CHECK: call Sz_bitcast_v16i1_to_i16
+; CHECK-LABEL: test_bitcast_v16i1_to_i16
+; CHECK: call {{.*}} R_{{.*}} Sz_bitcast_v16i1_to_i16
-; OPTM1-LABEL: test_bitcast_v16i1_to_i16:
+; OPTM1-LABEL: test_bitcast_v16i1_to_i16
; OPMT1: call -4
}
@@ -183,11 +180,11 @@
%res = bitcast i8 %arg.trunc to <8 x i1>
ret <8 x i1> %res
-; CHECK-LABEL: test_bitcast_i8_to_v8i1:
-; CHECK: call Sz_bitcast_i8_to_v8i1
+; CHECK-LABEL: test_bitcast_i8_to_v8i1
+; CHECK: call {{.*}} R_{{.*}} Sz_bitcast_i8_to_v8i1
-; OPTM1-LABEL: test_bitcast_i8_to_v8i1:
-; OPTM1: call Sz_bitcast_i8_to_v8i1
+; OPTM1-LABEL: test_bitcast_i8_to_v8i1
+; OPTM1: call {{.*}} R_{{.*}} Sz_bitcast_i8_to_v8i1
}
define <16 x i1> @test_bitcast_i16_to_v16i1(i32 %arg) {
@@ -196,9 +193,9 @@
%res = bitcast i16 %arg.trunc to <16 x i1>
ret <16 x i1> %res
-; CHECK-LABEL: test_bitcast_i16_to_v16i1:
-; CHECK: call Sz_bitcast_i16_to_v16i1
+; CHECK-LABEL: test_bitcast_i16_to_v16i1
+; CHECK: call {{.*}} R_{{.*}} Sz_bitcast_i16_to_v16i1
-; OPTM1-LABEL: test_bitcast_i16_to_v16i1:
-; OPTM1: call Sz_bitcast_i16_to_v16i1
+; OPTM1-LABEL: test_bitcast_i16_to_v16i1
+; OPTM1: call {{.*}} R_{{.*}} Sz_bitcast_i16_to_v16i1
}
diff --git a/tests_lit/llvm2ice_tests/vector-cast.ll b/tests_lit/llvm2ice_tests/vector-cast.ll
index 30d3578..d46e5b8 100644
--- a/tests_lit/llvm2ice_tests/vector-cast.ll
+++ b/tests_lit/llvm2ice_tests/vector-cast.ll
@@ -1,12 +1,10 @@
; This file tests casting / conversion operations that apply to vector types.
; bitcast operations are in vector-bitcast.ll.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
+; RUN: | FileCheck %s
; sext operations
@@ -15,7 +13,7 @@
%res = sext <16 x i1> %arg to <16 x i8>
ret <16 x i8> %res
-; CHECK-LABEL: test_sext_v16i1_to_v16i8:
+; CHECK-LABEL: test_sext_v16i1_to_v16i8
; CHECK: pxor
; CHECK: pcmpeqb
; CHECK: psubb
@@ -29,9 +27,9 @@
%res = sext <8 x i1> %arg to <8 x i16>
ret <8 x i16> %res
-; CHECK-LABEL: test_sext_v8i1_to_v8i16:
-; CHECK: psllw {{.*}}, 15
-; CHECK: psraw {{.*}}, 15
+; CHECK-LABEL: test_sext_v8i1_to_v8i16
+; CHECK: psllw {{.*}},0xf
+; CHECK: psraw {{.*}},0xf
}
define <4 x i32> @test_sext_v4i1_to_v4i32(<4 x i1> %arg) {
@@ -39,9 +37,9 @@
%res = sext <4 x i1> %arg to <4 x i32>
ret <4 x i32> %res
-; CHECK-LABEL: test_sext_v4i1_to_v4i32:
-; CHECK: pslld {{.*}}, 31
-; CHECK: psrad {{.*}}, 31
+; CHECK-LABEL: test_sext_v4i1_to_v4i32
+; CHECK: pslld {{.*}},0x1f
+; CHECK: psrad {{.*}},0x1f
}
; zext operations
@@ -51,7 +49,7 @@
%res = zext <16 x i1> %arg to <16 x i8>
ret <16 x i8> %res
-; CHECK-LABEL: test_zext_v16i1_to_v16i8:
+; CHECK-LABEL: test_zext_v16i1_to_v16i8
; CHECK: pxor
; CHECK: pcmpeqb
; CHECK: psubb
@@ -63,7 +61,7 @@
%res = zext <8 x i1> %arg to <8 x i16>
ret <8 x i16> %res
-; CHECK-LABEL: test_zext_v8i1_to_v8i16:
+; CHECK-LABEL: test_zext_v8i1_to_v8i16
; CHECK: pxor
; CHECK: pcmpeqw
; CHECK: psubw
@@ -75,7 +73,7 @@
%res = zext <4 x i1> %arg to <4 x i32>
ret <4 x i32> %res
-; CHECK-LABEL: test_zext_v4i1_to_v4i32:
+; CHECK-LABEL: test_zext_v4i1_to_v4i32
; CHECK: pxor
; CHECK: pcmpeqd
; CHECK: psubd
@@ -89,7 +87,7 @@
%res = trunc <16 x i8> %arg to <16 x i1>
ret <16 x i1> %res
-; CHECK-LABEL: test_trunc_v16i8_to_v16i1:
+; CHECK-LABEL: test_trunc_v16i8_to_v16i1
; CHECK: pxor
; CHECK: pcmpeqb
; CHECK: psubb
@@ -101,7 +99,7 @@
%res = trunc <8 x i16> %arg to <8 x i1>
ret <8 x i1> %res
-; CHECK-LABEL: test_trunc_v8i16_to_v8i1:
+; CHECK-LABEL: test_trunc_v8i16_to_v8i1
; CHECK: pxor
; CHECK: pcmpeqw
; CHECK: psubw
@@ -113,7 +111,7 @@
%res = trunc <4 x i32> %arg to <4 x i1>
ret <4 x i1> %res
-; CHECK-LABEL: test_trunc_v4i32_to_v4i1:
+; CHECK-LABEL: test_trunc_v4i32_to_v4i1
; CHECK: pxor
; CHECK: pcmpeqd
; CHECK: psubd
@@ -127,7 +125,7 @@
%res = fptosi <4 x float> %arg to <4 x i32>
ret <4 x i32> %res
-; CHECK-LABEL: test_fptosi_v4f32_to_v4i32:
+; CHECK-LABEL: test_fptosi_v4f32_to_v4i32
; CHECK: cvttps2dq
}
@@ -136,8 +134,8 @@
%res = fptoui <4 x float> %arg to <4 x i32>
ret <4 x i32> %res
-; CHECK-LABEL: test_fptoui_v4f32_to_v4i32:
-; CHECK: call Sz_fptoui_v4f32
+; CHECK-LABEL: test_fptoui_v4f32_to_v4i32
+; CHECK: call {{.*}} R_{{.*}} Sz_fptoui_v4f32
}
; [su]itofp operations
@@ -147,7 +145,7 @@
%res = sitofp <4 x i32> %arg to <4 x float>
ret <4 x float> %res
-; CHECK-LABEL: test_sitofp_v4i32_to_v4f32:
+; CHECK-LABEL: test_sitofp_v4i32_to_v4f32
; CHECK: cvtdq2ps
}
@@ -156,6 +154,6 @@
%res = uitofp <4 x i32> %arg to <4 x float>
ret <4 x float> %res
-; CHECK-LABEL: test_uitofp_v4i32_to_v4f32:
-; CHECK: call Sz_uitofp_v4i32
+; CHECK-LABEL: test_uitofp_v4i32_to_v4f32
+; CHECK: call {{.*}} R_{{.*}} Sz_uitofp_v4i32
}
diff --git a/tests_lit/llvm2ice_tests/vector-fcmp.ll b/tests_lit/llvm2ice_tests/vector-fcmp.ll
index 247337f..a84ef7b 100644
--- a/tests_lit/llvm2ice_tests/vector-fcmp.ll
+++ b/tests_lit/llvm2ice_tests/vector-fcmp.ll
@@ -1,12 +1,10 @@
; This file checks support for comparing vector values with the fcmp
; instruction.
-; RUN: %p2i -i %s -a -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s -a -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble -a -O2 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble -a -Om1 --verbose none \
+; RUN: | FileCheck %s
; Check that sext elimination occurs when the result of the comparison
; instruction is alrady sign extended. Sign extension to 4 x i32 uses
@@ -16,7 +14,7 @@
%res.trunc = fcmp oeq <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
-; CHECK-LABEL: sextElimination:
+; CHECK-LABEL: sextElimination
; CHECK: cmpeqps
; CHECK-NOT: pslld
}
@@ -26,7 +24,7 @@
%res.trunc = fcmp false <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
-; CHECK-LABEL: fcmpFalseVector:
+; CHECK-LABEL: fcmpFalseVector
; CHECK: pxor
}
@@ -35,7 +33,7 @@
%res.trunc = fcmp oeq <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
-; CHECK-LABEL: fcmpOeqVector:
+; CHECK-LABEL: fcmpOeqVector
; CHECK: cmpeqps
}
@@ -44,7 +42,7 @@
%res.trunc = fcmp oge <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
-; CHECK-LABEL: fcmpOgeVector:
+; CHECK-LABEL: fcmpOgeVector
; CHECK: cmpleps
}
@@ -53,7 +51,7 @@
%res.trunc = fcmp ogt <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
-; CHECK-LABEL: fcmpOgtVector:
+; CHECK-LABEL: fcmpOgtVector
; CHECK: cmpltps
}
@@ -62,7 +60,7 @@
%res.trunc = fcmp ole <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
-; CHECK-LABEL: fcmpOleVector:
+; CHECK-LABEL: fcmpOleVector
; CHECK: cmpleps
}
@@ -71,7 +69,7 @@
%res.trunc = fcmp olt <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
-; CHECK-LABEL: fcmpOltVector:
+; CHECK-LABEL: fcmpOltVector
; CHECK: cmpltps
}
@@ -80,7 +78,7 @@
%res.trunc = fcmp one <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
-; CHECK-LABEL: fcmpOneVector:
+; CHECK-LABEL: fcmpOneVector
; CHECK: cmpneqps
; CHECK: cmpordps
; CHECK: pand
@@ -91,7 +89,7 @@
%res.trunc = fcmp ord <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
-; CHECK-LABEL: fcmpOrdVector:
+; CHECK-LABEL: fcmpOrdVector
; CHECK: cmpordps
}
@@ -100,7 +98,7 @@
%res.trunc = fcmp true <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
-; CHECK-LABEL: fcmpTrueVector:
+; CHECK-LABEL: fcmpTrueVector
; CHECK: pcmpeqd
}
@@ -109,7 +107,7 @@
%res.trunc = fcmp ueq <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
-; CHECK-LABEL: fcmpUeqVector:
+; CHECK-LABEL: fcmpUeqVector
; CHECK: cmpeqps
; CHECK: cmpunordps
; CHECK: por
@@ -120,7 +118,7 @@
%res.trunc = fcmp uge <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
-; CHECK-LABEL: fcmpUgeVector:
+; CHECK-LABEL: fcmpUgeVector
; CHECK: cmpnltps
}
@@ -129,7 +127,7 @@
%res.trunc = fcmp ugt <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
-; CHECK-LABEL: fcmpUgtVector:
+; CHECK-LABEL: fcmpUgtVector
; CHECK: cmpnleps
}
@@ -138,7 +136,7 @@
%res.trunc = fcmp ule <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
-; CHECK-LABEL: fcmpUleVector:
+; CHECK-LABEL: fcmpUleVector
; CHECK: cmpnltps
}
@@ -147,7 +145,7 @@
%res.trunc = fcmp ult <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
-; CHECK-LABEL: fcmpUltVector:
+; CHECK-LABEL: fcmpUltVector
; CHECK: cmpnleps
}
@@ -156,7 +154,7 @@
%res.trunc = fcmp une <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
-; CHECK-LABEL: fcmpUneVector:
+; CHECK-LABEL: fcmpUneVector
; CHECK: cmpneqps
}
@@ -165,6 +163,6 @@
%res.trunc = fcmp uno <4 x float> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
-; CHECK-LABEL: fcmpUnoVector:
+; CHECK-LABEL: fcmpUnoVector
; CHECK: cmpunordps
}
diff --git a/tests_lit/llvm2ice_tests/vector-icmp.ll b/tests_lit/llvm2ice_tests/vector-icmp.ll
index 2be3ffa..e474976 100644
--- a/tests_lit/llvm2ice_tests/vector-icmp.ll
+++ b/tests_lit/llvm2ice_tests/vector-icmp.ll
@@ -1,12 +1,10 @@
; This file checks support for comparing vector values with the icmp
; instruction.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
+; RUN: | FileCheck %s
; Check that sext elimination occurs when the result of the comparison
; instruction is alrady sign extended. Sign extension to 4 x i32 uses
@@ -16,7 +14,7 @@
%res.trunc = icmp eq <4 x i32> %a, %b
%res = sext <4 x i1> %res.trunc to <4 x i32>
ret <4 x i32> %res
-; CHECK-LABEL: test_sext_elimination:
+; CHECK-LABEL: test_sext_elimination
; CHECK: pcmpeqd
; CHECK-NOT: pslld
}
@@ -25,7 +23,7 @@
entry:
%res = icmp eq <4 x i32> %a, %b
ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i32_eq:
+; CHECK-LABEL: test_icmp_v4i32_eq
; CHECK: pcmpeqd
}
@@ -33,7 +31,7 @@
entry:
%res = icmp ne <4 x i32> %a, %b
ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i32_ne:
+; CHECK-LABEL: test_icmp_v4i32_ne
; CHECK: pcmpeqd
; CHECK: pxor
}
@@ -49,7 +47,7 @@
entry:
%res = icmp sle <4 x i32> %a, %b
ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i32_sle:
+; CHECK-LABEL: test_icmp_v4i32_sle
; CHECK: pcmpgtd
; CHECK: pxor
}
@@ -58,7 +56,7 @@
entry:
%res = icmp slt <4 x i32> %a, %b
ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i32_slt:
+; CHECK-LABEL: test_icmp_v4i32_slt
; CHECK: pcmpgtd
}
@@ -66,7 +64,7 @@
entry:
%res = icmp uge <4 x i32> %a, %b
ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i32_uge:
+; CHECK-LABEL: test_icmp_v4i32_uge
; CHECK: pxor
; CHECK: pcmpgtd
; CHECK: pxor
@@ -76,7 +74,7 @@
entry:
%res = icmp ugt <4 x i32> %a, %b
ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i32_ugt:
+; CHECK-LABEL: test_icmp_v4i32_ugt
; CHECK: pxor
; CHECK: pcmpgtd
}
@@ -85,7 +83,7 @@
entry:
%res = icmp ule <4 x i32> %a, %b
ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i32_ule:
+; CHECK-LABEL: test_icmp_v4i32_ule
; CHECK: pxor
; CHECK: pcmpgtd
; CHECK: pxor
@@ -95,7 +93,7 @@
entry:
%res = icmp ult <4 x i32> %a, %b
ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i32_ult:
+; CHECK-LABEL: test_icmp_v4i32_ult
; CHECK: pxor
; CHECK: pcmpgtd
}
@@ -104,7 +102,7 @@
entry:
%res = icmp eq <4 x i1> %a, %b
ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i1_eq:
+; CHECK-LABEL: test_icmp_v4i1_eq
; CHECK: pcmpeqd
}
@@ -112,7 +110,7 @@
entry:
%res = icmp ne <4 x i1> %a, %b
ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i1_ne:
+; CHECK-LABEL: test_icmp_v4i1_ne
; CHECK: pcmpeqd
; CHECK: pxor
}
@@ -121,7 +119,7 @@
entry:
%res = icmp sgt <4 x i1> %a, %b
ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i1_sgt:
+; CHECK-LABEL: test_icmp_v4i1_sgt
; CHECK: pcmpgtd
}
@@ -129,7 +127,7 @@
entry:
%res = icmp sle <4 x i1> %a, %b
ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i1_sle:
+; CHECK-LABEL: test_icmp_v4i1_sle
; CHECK: pcmpgtd
; CHECK: pxor
}
@@ -138,7 +136,7 @@
entry:
%res = icmp slt <4 x i1> %a, %b
ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i1_slt:
+; CHECK-LABEL: test_icmp_v4i1_slt
; CHECK: pcmpgtd
}
@@ -146,7 +144,7 @@
entry:
%res = icmp uge <4 x i1> %a, %b
ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i1_uge:
+; CHECK-LABEL: test_icmp_v4i1_uge
; CHECK: pxor
; CHECK: pcmpgtd
; CHECK: pxor
@@ -156,7 +154,7 @@
entry:
%res = icmp ugt <4 x i1> %a, %b
ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i1_ugt:
+; CHECK-LABEL: test_icmp_v4i1_ugt
; CHECK: pxor
; CHECK: pcmpgtd
}
@@ -165,7 +163,7 @@
entry:
%res = icmp ule <4 x i1> %a, %b
ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i1_ule:
+; CHECK-LABEL: test_icmp_v4i1_ule
; CHECK: pxor
; CHECK: pcmpgtd
; CHECK: pxor
@@ -175,7 +173,7 @@
entry:
%res = icmp ult <4 x i1> %a, %b
ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i1_ult:
+; CHECK-LABEL: test_icmp_v4i1_ult
; CHECK: pxor
; CHECK: pcmpgtd
}
@@ -184,7 +182,7 @@
entry:
%res = icmp eq <8 x i16> %a, %b
ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i16_eq:
+; CHECK-LABEL: test_icmp_v8i16_eq
; CHECK: pcmpeqw
}
@@ -192,7 +190,7 @@
entry:
%res = icmp ne <8 x i16> %a, %b
ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i16_ne:
+; CHECK-LABEL: test_icmp_v8i16_ne
; CHECK: pcmpeqw
; CHECK: pxor
}
@@ -201,7 +199,7 @@
entry:
%res = icmp sgt <8 x i16> %a, %b
ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i16_sgt:
+; CHECK-LABEL: test_icmp_v8i16_sgt
; CHECK: pcmpgtw
}
@@ -209,7 +207,7 @@
entry:
%res = icmp sle <8 x i16> %a, %b
ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i16_sle:
+; CHECK-LABEL: test_icmp_v8i16_sle
; CHECK: pcmpgtw
; CHECK: pxor
}
@@ -218,7 +216,7 @@
entry:
%res = icmp slt <8 x i16> %a, %b
ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i16_slt:
+; CHECK-LABEL: test_icmp_v8i16_slt
; CHECK: pcmpgtw
}
@@ -226,7 +224,7 @@
entry:
%res = icmp uge <8 x i16> %a, %b
ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i16_uge:
+; CHECK-LABEL: test_icmp_v8i16_uge
; CHECK: pxor
; CHECK: pcmpgtw
; CHECK: pxor
@@ -236,7 +234,7 @@
entry:
%res = icmp ugt <8 x i16> %a, %b
ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i16_ugt:
+; CHECK-LABEL: test_icmp_v8i16_ugt
; CHECK: pxor
; CHECK: pcmpgtw
}
@@ -245,7 +243,7 @@
entry:
%res = icmp ule <8 x i16> %a, %b
ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i16_ule:
+; CHECK-LABEL: test_icmp_v8i16_ule
; CHECK: pxor
; CHECK: pcmpgtw
; CHECK: pxor
@@ -255,7 +253,7 @@
entry:
%res = icmp ult <8 x i16> %a, %b
ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i16_ult:
+; CHECK-LABEL: test_icmp_v8i16_ult
; CHECK: pxor
; CHECK: pcmpgtw
}
@@ -264,7 +262,7 @@
entry:
%res = icmp eq <8 x i1> %a, %b
ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i1_eq:
+; CHECK-LABEL: test_icmp_v8i1_eq
; CHECK: pcmpeqw
}
@@ -272,7 +270,7 @@
entry:
%res = icmp ne <8 x i1> %a, %b
ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i1_ne:
+; CHECK-LABEL: test_icmp_v8i1_ne
; CHECK: pcmpeqw
; CHECK: pxor
}
@@ -281,7 +279,7 @@
entry:
%res = icmp sgt <8 x i1> %a, %b
ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i1_sgt:
+; CHECK-LABEL: test_icmp_v8i1_sgt
; CHECK: pcmpgtw
}
@@ -289,7 +287,7 @@
entry:
%res = icmp sle <8 x i1> %a, %b
ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i1_sle:
+; CHECK-LABEL: test_icmp_v8i1_sle
; CHECK: pcmpgtw
; CHECK: pxor
}
@@ -298,7 +296,7 @@
entry:
%res = icmp slt <8 x i1> %a, %b
ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i1_slt:
+; CHECK-LABEL: test_icmp_v8i1_slt
; CHECK: pcmpgtw
}
@@ -306,7 +304,7 @@
entry:
%res = icmp uge <8 x i1> %a, %b
ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i1_uge:
+; CHECK-LABEL: test_icmp_v8i1_uge
; CHECK: pxor
; CHECK: pcmpgtw
; CHECK: pxor
@@ -316,7 +314,7 @@
entry:
%res = icmp ugt <8 x i1> %a, %b
ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i1_ugt:
+; CHECK-LABEL: test_icmp_v8i1_ugt
; CHECK: pxor
; CHECK: pcmpgtw
}
@@ -325,7 +323,7 @@
entry:
%res = icmp ule <8 x i1> %a, %b
ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i1_ule:
+; CHECK-LABEL: test_icmp_v8i1_ule
; CHECK: pxor
; CHECK: pcmpgtw
; CHECK: pxor
@@ -335,7 +333,7 @@
entry:
%res = icmp ult <8 x i1> %a, %b
ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i1_ult:
+; CHECK-LABEL: test_icmp_v8i1_ult
; CHECK: pxor
; CHECK: pcmpgtw
}
@@ -344,7 +342,7 @@
entry:
%res = icmp eq <16 x i8> %a, %b
ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i8_eq:
+; CHECK-LABEL: test_icmp_v16i8_eq
; CHECK: pcmpeqb
}
@@ -352,7 +350,7 @@
entry:
%res = icmp ne <16 x i8> %a, %b
ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i8_ne:
+; CHECK-LABEL: test_icmp_v16i8_ne
; CHECK: pcmpeqb
; CHECK: pxor
}
@@ -361,7 +359,7 @@
entry:
%res = icmp sgt <16 x i8> %a, %b
ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i8_sgt:
+; CHECK-LABEL: test_icmp_v16i8_sgt
; CHECK: pcmpgtb
}
@@ -369,7 +367,7 @@
entry:
%res = icmp sle <16 x i8> %a, %b
ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i8_sle:
+; CHECK-LABEL: test_icmp_v16i8_sle
; CHECK: pcmpgtb
; CHECK: pxor
}
@@ -378,7 +376,7 @@
entry:
%res = icmp slt <16 x i8> %a, %b
ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i8_slt:
+; CHECK-LABEL: test_icmp_v16i8_slt
; CHECK: pcmpgtb
}
@@ -386,7 +384,7 @@
entry:
%res = icmp uge <16 x i8> %a, %b
ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i8_uge:
+; CHECK-LABEL: test_icmp_v16i8_uge
; CHECK: pxor
; CHECK: pcmpgtb
; CHECK: pxor
@@ -396,7 +394,7 @@
entry:
%res = icmp ugt <16 x i8> %a, %b
ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i8_ugt:
+; CHECK-LABEL: test_icmp_v16i8_ugt
; CHECK: pxor
; CHECK: pcmpgtb
}
@@ -405,7 +403,7 @@
entry:
%res = icmp ule <16 x i8> %a, %b
ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i8_ule:
+; CHECK-LABEL: test_icmp_v16i8_ule
; CHECK: pxor
; CHECK: pcmpgtb
; CHECK: pxor
@@ -415,7 +413,7 @@
entry:
%res = icmp ult <16 x i8> %a, %b
ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i8_ult:
+; CHECK-LABEL: test_icmp_v16i8_ult
; CHECK: pxor
; CHECK: pcmpgtb
}
@@ -424,7 +422,7 @@
entry:
%res = icmp eq <16 x i1> %a, %b
ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i1_eq:
+; CHECK-LABEL: test_icmp_v16i1_eq
; CHECK: pcmpeqb
}
@@ -432,7 +430,7 @@
entry:
%res = icmp ne <16 x i1> %a, %b
ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i1_ne:
+; CHECK-LABEL: test_icmp_v16i1_ne
; CHECK: pcmpeqb
; CHECK: pxor
}
@@ -441,7 +439,7 @@
entry:
%res = icmp sgt <16 x i1> %a, %b
ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i1_sgt:
+; CHECK-LABEL: test_icmp_v16i1_sgt
; CHECK: pcmpgtb
}
@@ -449,7 +447,7 @@
entry:
%res = icmp sle <16 x i1> %a, %b
ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i1_sle:
+; CHECK-LABEL: test_icmp_v16i1_sle
; CHECK: pcmpgtb
; CHECK: pxor
}
@@ -458,7 +456,7 @@
entry:
%res = icmp slt <16 x i1> %a, %b
ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i1_slt:
+; CHECK-LABEL: test_icmp_v16i1_slt
; CHECK: pcmpgtb
}
@@ -466,7 +464,7 @@
entry:
%res = icmp uge <16 x i1> %a, %b
ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i1_uge:
+; CHECK-LABEL: test_icmp_v16i1_uge
; CHECK: pxor
; CHECK: pcmpgtb
; CHECK: pxor
@@ -476,7 +474,7 @@
entry:
%res = icmp ugt <16 x i1> %a, %b
ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i1_ugt:
+; CHECK-LABEL: test_icmp_v16i1_ugt
; CHECK: pxor
; CHECK: pcmpgtb
}
@@ -485,7 +483,7 @@
entry:
%res = icmp ule <16 x i1> %a, %b
ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i1_ule:
+; CHECK-LABEL: test_icmp_v16i1_ule
; CHECK: pxor
; CHECK: pcmpgtb
; CHECK: pxor
@@ -495,7 +493,7 @@
entry:
%res = icmp ult <16 x i1> %a, %b
ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i1_ult:
+; CHECK-LABEL: test_icmp_v16i1_ult
; CHECK: pxor
; CHECK: pcmpgtb
}
diff --git a/tests_lit/llvm2ice_tests/vector-ops.ll b/tests_lit/llvm2ice_tests/vector-ops.ll
index 0e093e9..ccffd39 100644
--- a/tests_lit/llvm2ice_tests/vector-ops.ll
+++ b/tests_lit/llvm2ice_tests/vector-ops.ll
@@ -1,19 +1,13 @@
; This checks support for insertelement and extractelement.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -O2 -mattr=sse4.1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
-; RUN: | FileCheck --check-prefix=SSE41 %s
-; RUN: %p2i -i %s --args -Om1 -mattr=sse4.1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
-; RUN: | FileCheck --check-prefix=SSE41 %s
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 -mattr=sse4.1 \
+; RUN: --verbose none | FileCheck --check-prefix=SSE41 %s
+; RUN: %p2i -i %s --assemble --disassemble --args -Om1 -mattr=sse4.1 \
+; RUN: --verbose none | FileCheck --check-prefix=SSE41 %s
; insertelement operations
@@ -21,23 +15,23 @@
entry:
%res = insertelement <4 x float> %vec, float %elt, i32 0
ret <4 x float> %res
-; CHECK-LABEL: insertelement_v4f32_0:
+; CHECK-LABEL: insertelement_v4f32_0
; CHECK: movss
-; SSE41-LABEL: insertelement_v4f32_0:
-; SSE41: insertps {{.*}}, {{.*}}, 0
+; SSE41-LABEL: insertelement_v4f32_0
+; SSE41: insertps {{.*}},{{.*}},0x0
}
define <4 x i32> @insertelement_v4i32_0(<4 x i32> %vec, i32 %elt) {
entry:
%res = insertelement <4 x i32> %vec, i32 %elt, i32 0
ret <4 x i32> %res
-; CHECK-LABEL: insertelement_v4i32_0:
+; CHECK-LABEL: insertelement_v4i32_0
; CHECK: movd xmm{{.*}},
; CHECK: movss
-; SSE41-LABEL: insertelement_v4i32_0:
-; SSE41: pinsrd {{.*}}, {{.*}}, 0
+; SSE41-LABEL: insertelement_v4i32_0
+; SSE41: pinsrd {{.*}},{{.*}},0x0
}
@@ -45,24 +39,24 @@
entry:
%res = insertelement <4 x float> %vec, float %elt, i32 1
ret <4 x float> %res
-; CHECK-LABEL: insertelement_v4f32_1:
+; CHECK-LABEL: insertelement_v4f32_1
; CHECK: shufps
; CHECK: shufps
-; SSE41-LABEL: insertelement_v4f32_1:
-; SSE41: insertps {{.*}}, {{.*}}, 16
+; SSE41-LABEL: insertelement_v4f32_1
+; SSE41: insertps {{.*}},{{.*}},0x10
}
define <4 x i32> @insertelement_v4i32_1(<4 x i32> %vec, i32 %elt) {
entry:
%res = insertelement <4 x i32> %vec, i32 %elt, i32 1
ret <4 x i32> %res
-; CHECK-LABEL: insertelement_v4i32_1:
+; CHECK-LABEL: insertelement_v4i32_1
; CHECK: shufps
; CHECK: shufps
-; SSE41-LABEL: insertelement_v4i32_1:
-; SSE41: pinsrd {{.*}}, {{.*}}, 1
+; SSE41-LABEL: insertelement_v4i32_1
+; SSE41: pinsrd {{.*}},{{.*}},0x1
}
define <8 x i16> @insertelement_v8i16(<8 x i16> %vec, i32 %elt.arg) {
@@ -70,10 +64,10 @@
%elt = trunc i32 %elt.arg to i16
%res = insertelement <8 x i16> %vec, i16 %elt, i32 1
ret <8 x i16> %res
-; CHECK-LABEL: insertelement_v8i16:
+; CHECK-LABEL: insertelement_v8i16
; CHECK: pinsrw
-; SSE41-LABEL: insertelement_v8i16:
+; SSE41-LABEL: insertelement_v8i16
; SSE41: pinsrw
}
@@ -82,12 +76,12 @@
%elt = trunc i32 %elt.arg to i8
%res = insertelement <16 x i8> %vec, i8 %elt, i32 1
ret <16 x i8> %res
-; CHECK-LABEL: insertelement_v16i8:
+; CHECK-LABEL: insertelement_v16i8
; CHECK: movups
; CHECK: lea
; CHECK: mov
-; SSE41-LABEL: insertelement_v16i8:
+; SSE41-LABEL: insertelement_v16i8
; SSE41: pinsrb
}
@@ -96,11 +90,11 @@
%elt = trunc i32 %elt.arg to i1
%res = insertelement <4 x i1> %vec, i1 %elt, i32 0
ret <4 x i1> %res
-; CHECK-LABEL: insertelement_v4i1_0:
+; CHECK-LABEL: insertelement_v4i1_0
; CHECK: movss
-; SSE41-LABEL: insertelement_v4i1_0:
-; SSE41: pinsrd {{.*}}, {{.*}}, 0
+; SSE41-LABEL: insertelement_v4i1_0
+; SSE41: pinsrd {{.*}},{{.*}},0x0
}
define <4 x i1> @insertelement_v4i1_1(<4 x i1> %vec, i32 %elt.arg) {
@@ -108,12 +102,12 @@
%elt = trunc i32 %elt.arg to i1
%res = insertelement <4 x i1> %vec, i1 %elt, i32 1
ret <4 x i1> %res
-; CHECK-LABEL: insertelement_v4i1_1:
+; CHECK-LABEL: insertelement_v4i1_1
; CHECK: shufps
; CHECK: shufps
-; SSE41-LABEL: insertelement_v4i1_1:
-; SSE41: pinsrd {{.*}}, {{.*}}, 1
+; SSE41-LABEL: insertelement_v4i1_1
+; SSE41: pinsrd {{.*}},{{.*}},0x1
}
define <8 x i1> @insertelement_v8i1(<8 x i1> %vec, i32 %elt.arg) {
@@ -121,10 +115,10 @@
%elt = trunc i32 %elt.arg to i1
%res = insertelement <8 x i1> %vec, i1 %elt, i32 1
ret <8 x i1> %res
-; CHECK-LABEL: insertelement_v8i1:
+; CHECK-LABEL: insertelement_v8i1
; CHECK: pinsrw
-; SSE41-LABEL: insertelement_v8i1:
+; SSE41-LABEL: insertelement_v8i1
; SSE41: pinsrw
}
@@ -133,12 +127,12 @@
%elt = trunc i32 %elt.arg to i1
%res = insertelement <16 x i1> %vec, i1 %elt, i32 1
ret <16 x i1> %res
-; CHECK-LABEL: insertelement_v16i1:
+; CHECK-LABEL: insertelement_v16i1
; CHECK: movups
; CHECK: lea
; CHECK: mov
-; SSE41-LABEL: insertelement_v16i1:
+; SSE41-LABEL: insertelement_v16i1
; SSE41: pinsrb
}
@@ -148,10 +142,10 @@
entry:
%res = extractelement <4 x float> %vec, i32 1
ret float %res
-; CHECK-LABEL: extractelement_v4f32:
+; CHECK-LABEL: extractelement_v4f32
; CHECK: pshufd
-; SSE41-LABEL: extractelement_v4f32:
+; SSE41-LABEL: extractelement_v4f32
; SSE41: pshufd
}
@@ -159,11 +153,11 @@
entry:
%res = extractelement <4 x i32> %vec, i32 1
ret i32 %res
-; CHECK-LABEL: extractelement_v4i32:
+; CHECK-LABEL: extractelement_v4i32
; CHECK: pshufd
-; CHECK: movd {{.*}}, xmm
+; CHECK: movd {{.*}},xmm
-; SSE41-LABEL: extractelement_v4i32:
+; SSE41-LABEL: extractelement_v4i32
; SSE41: pextrd
}
@@ -172,10 +166,10 @@
%res = extractelement <8 x i16> %vec, i32 1
%res.ext = zext i16 %res to i32
ret i32 %res.ext
-; CHECK-LABEL: extractelement_v8i16:
+; CHECK-LABEL: extractelement_v8i16
; CHECK: pextrw
-; SSE41-LABEL: extractelement_v8i16:
+; SSE41-LABEL: extractelement_v8i16
; SSE41: pextrw
}
@@ -184,12 +178,12 @@
%res = extractelement <16 x i8> %vec, i32 1
%res.ext = zext i8 %res to i32
ret i32 %res.ext
-; CHECK-LABEL: extractelement_v16i8:
+; CHECK-LABEL: extractelement_v16i8
; CHECK: movups
; CHECK: lea
; CHECK: mov
-; SSE41-LABEL: extractelement_v16i8:
+; SSE41-LABEL: extractelement_v16i8
; SSE41: pextrb
}
@@ -198,10 +192,10 @@
%res = extractelement <4 x i1> %vec, i32 1
%res.ext = zext i1 %res to i32
ret i32 %res.ext
-; CHECK-LABEL: extractelement_v4i1:
+; CHECK-LABEL: extractelement_v4i1
; CHECK: pshufd
-; SSE41-LABEL: extractelement_v4i1:
+; SSE41-LABEL: extractelement_v4i1
; SSE41: pextrd
}
@@ -210,10 +204,10 @@
%res = extractelement <8 x i1> %vec, i32 1
%res.ext = zext i1 %res to i32
ret i32 %res.ext
-; CHECK-LABEL: extractelement_v8i1:
+; CHECK-LABEL: extractelement_v8i1
; CHECK: pextrw
-; SSE41-LABEL: extractelement_v8i1:
+; SSE41-LABEL: extractelement_v8i1
; SSE41: pextrw
}
@@ -222,11 +216,11 @@
%res = extractelement <16 x i1> %vec, i32 1
%res.ext = zext i1 %res to i32
ret i32 %res.ext
-; CHECK-LABEL: extractelement_v16i1:
+; CHECK-LABEL: extractelement_v16i1
; CHECK: movups
; CHECK: lea
; CHECK: mov
-; SSE41-LABEL: extractelement_v16i1:
+; SSE41-LABEL: extractelement_v16i1
; SSE41: pextrb
}
diff --git a/tests_lit/llvm2ice_tests/vector-select.ll b/tests_lit/llvm2ice_tests/vector-select.ll
index 7596c2a..e3beef3 100644
--- a/tests_lit/llvm2ice_tests/vector-select.ll
+++ b/tests_lit/llvm2ice_tests/vector-select.ll
@@ -1,110 +1,104 @@
; This file tests support for the select instruction with vector valued inputs.
-; RUN: %p2i -i %s --args -O2 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
-; RUN: %p2i -i %s --args -O2 -mattr=sse4.1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
-; RUN: | FileCheck --check-prefix=SSE41 %s
-; RUN: %p2i -i %s --args -Om1 -mattr=sse4.1 --verbose none \
-; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
-; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - \
-; RUN: | FileCheck --check-prefix=SSE41 %s
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -Om1 --verbose none \
+; RUN: | FileCheck %s
+; RUN: %p2i -i %s --assemble --disassemble --args -O2 -mattr=sse4.1 \
+; RUN: --verbose none | FileCheck --check-prefix=SSE41 %s
+; RUN: %p2i -i %s --assemble --disassemble --args -Om1 -mattr=sse4.1 \
+; RUN: --verbose none | FileCheck --check-prefix=SSE41 %s
define <16 x i8> @test_select_v16i8(<16 x i1> %cond, <16 x i8> %arg1, <16 x i8> %arg2) {
entry:
%res = select <16 x i1> %cond, <16 x i8> %arg1, <16 x i8> %arg2
ret <16 x i8> %res
-; CHECK-LABEL: test_select_v16i8:
+; CHECK-LABEL: test_select_v16i8
; CHECK: pand
; CHECK: pandn
; CHECK: por
-; SSE41-LABEL: test_select_v16i8:
-; SSE41: pblendvb xmm{{[0-7]}}, {{xmm[0-7]|xmmword}}
+; SSE41-LABEL: test_select_v16i8
+; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
}
define <16 x i1> @test_select_v16i1(<16 x i1> %cond, <16 x i1> %arg1, <16 x i1> %arg2) {
entry:
%res = select <16 x i1> %cond, <16 x i1> %arg1, <16 x i1> %arg2
ret <16 x i1> %res
-; CHECK-LABEL: test_select_v16i1:
+; CHECK-LABEL: test_select_v16i1
; CHECK: pand
; CHECK: pandn
; CHECK: por
-; SSE41-LABEL: test_select_v16i1:
-; SSE41: pblendvb xmm{{[0-7]}}, {{xmm[0-7]|xmmword}}
+; SSE41-LABEL: test_select_v16i1
+; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
}
define <8 x i16> @test_select_v8i16(<8 x i1> %cond, <8 x i16> %arg1, <8 x i16> %arg2) {
entry:
%res = select <8 x i1> %cond, <8 x i16> %arg1, <8 x i16> %arg2
ret <8 x i16> %res
-; CHECK-LABEL: test_select_v8i16:
+; CHECK-LABEL: test_select_v8i16
; CHECK: pand
; CHECK: pandn
; CHECK: por
-; SSE41-LABEL: test_select_v8i16:
-; SSE41: pblendvb xmm{{[0-7]}}, {{xmm[0-7]|xmmword}}
+; SSE41-LABEL: test_select_v8i16
+; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
}
define <8 x i1> @test_select_v8i1(<8 x i1> %cond, <8 x i1> %arg1, <8 x i1> %arg2) {
entry:
%res = select <8 x i1> %cond, <8 x i1> %arg1, <8 x i1> %arg2
ret <8 x i1> %res
-; CHECK-LABEL: test_select_v8i1:
+; CHECK-LABEL: test_select_v8i1
; CHECK: pand
; CHECK: pandn
; CHECK: por
-; SSE41-LABEL: test_select_v8i1:
-; SSE41: pblendvb xmm{{[0-7]}}, {{xmm[0-7]|xmmword}}
+; SSE41-LABEL: test_select_v8i1
+; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
}
define <4 x i32> @test_select_v4i32(<4 x i1> %cond, <4 x i32> %arg1, <4 x i32> %arg2) {
entry:
%res = select <4 x i1> %cond, <4 x i32> %arg1, <4 x i32> %arg2
ret <4 x i32> %res
-; CHECK-LABEL: test_select_v4i32:
+; CHECK-LABEL: test_select_v4i32
; CHECK: pand
; CHECK: pandn
; CHECK: por
-; SSE41-LABEL: test_select_v4i32:
-; SSE41: pslld xmm0, 31
-; SSE41: blendvps xmm{{[0-7]}}, {{xmm[0-7]|xmmword}}
+; SSE41-LABEL: test_select_v4i32
+; SSE41: pslld xmm0,0x1f
+; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
}
define <4 x float> @test_select_v4f32(<4 x i1> %cond, <4 x float> %arg1, <4 x float> %arg2) {
entry:
%res = select <4 x i1> %cond, <4 x float> %arg1, <4 x float> %arg2
ret <4 x float> %res
-; CHECK-LABEL: test_select_v4f32:
+; CHECK-LABEL: test_select_v4f32
; CHECK: pand
; CHECK: pandn
; CHECK: por
-; SSE41-LABEL: test_select_v4f32:
-; SSE41: pslld xmm0, 31
-; SSE41: blendvps xmm{{[0-7]}}, {{xmm[0-7]|xmmword}}
+; SSE41-LABEL: test_select_v4f32
+; SSE41: pslld xmm0,0x1f
+; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
}
define <4 x i1> @test_select_v4i1(<4 x i1> %cond, <4 x i1> %arg1, <4 x i1> %arg2) {
entry:
%res = select <4 x i1> %cond, <4 x i1> %arg1, <4 x i1> %arg2
ret <4 x i1> %res
-; CHECK-LABEL: test_select_v4i1:
+; CHECK-LABEL: test_select_v4i1
; CHECK: pand
; CHECK: pandn
; CHECK: por
-; SSE41-LABEL: test_select_v4i1:
-; SSE41: pslld xmm0, 31
-; SSE41: blendvps xmm{{[0-7]}}, {{xmm[0-7]|xmmword}}
+; SSE41-LABEL: test_select_v4i1
+; SSE41: pslld xmm0,0x1f
+; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
}
