commit 90d251aa4175651ed33dc086434f7dbd43fbe1a5
author Ben Clayton <bclayton@google.com> Thu May 09 14:06:27 2019 +0100
committer Ben Clayton <bclayton@google.com> Thu May 09 13:57:49 2019 +0000
tree 01a44a1c8a5e2367d94983cded3872abad46835f
parent 6ef1936102e441dc3cb9aa328473e0fab7dc7634

OpenGL/compiler: Error if parameters spill max temp registers

Bug: chromium:950230
Bug: chromium:958072
Change-Id: Iaf806df9b35606c9f18d78c3a98f8d3a0d6b3a93
Reviewed-on: https://swiftshader-review.googlesource.com/c/SwiftShader/+/31008
Tested-by: Ben Clayton <bclayton@google.com>
Reviewed-by: Nicolas Capens <nicolascapens@google.com>
Kokoro-Presubmit: kokoro <noreply+kokoro@google.com>

src/OpenGL/compiler/OutputASM.cpp

diff --git a/src/OpenGL/compiler/OutputASM.cpp b/src/OpenGL/compiler/OutputASM.cpp
index 7ca0353..75f7167 100644
--- a/src/OpenGL/compiler/OutputASM.cpp
+++ b/src/OpenGL/compiler/OutputASM.cpp
@@ -2479,6 +2479,13 @@
 					int stride = (argumentInfo.typedMemberInfo.matrixStride > 0) ? argumentInfo.typedMemberInfo.matrixStride : argumentInfo.typedMemberInfo.arrayStride;
 					parameter.index = argumentInfo.typedMemberInfo.offset + argumentInfo.clampedIndex * stride;
 				}
+
+				if(parameter.index >= sw::NUM_TEMPORARY_REGISTERS)
+				{
+					mContext.error(arg->getLine(),
+						"Too many temporary registers required to compile shader",
+						pixelShader ? "pixel shader" : "vertex shader");
+				}
 			}
 
 			if(!IsSampler(arg->getBasicType()))
@@ -2493,6 +2500,14 @@
 		parameter.type = registerType(arg);
 		parameter.index = registerIndex(arg) + index;
 		parameter.mask = writeMask(arg, index);
+
+		if(parameter.index >= sw::NUM_TEMPORARY_REGISTERS)
+		{
+			mContext.error(arg->getLine(),
+				"Too many temporary registers required to compile shader",
+				pixelShader ? "pixel shader" : "vertex shader");
+		}
+
 	}
 
 	void OutputASM::copy(TIntermTyped *dst, TIntermNode *src, int offset)

src/Shader/ShaderCore.hpp

diff --git a/src/Shader/ShaderCore.hpp b/src/Shader/ShaderCore.hpp
index 6b54428..27f6efd 100644
--- a/src/Shader/ShaderCore.hpp
+++ b/src/Shader/ShaderCore.hpp
@@ -190,6 +190,7 @@
 
 		Register operator[](int i)
 		{
+			ASSERT(i < size);
 			if(indirectAddressable)
 			{
 				return Register(x[0][i], y[0][i], z[0][i], w[0][i]);