Subzero: Add Non-SFI support for x86-32.
The basic model is that each translated function begins with a special "GotVar = getIP" instruction, and each ConstantRelocatable reference is changed to GotVar+ConstantRelocatable@GOTOFF (assuming GotVar is legalized into a physical register). The getIP instruction is late-lowered into:
call __Sz_getIP_<reg>
add <reg>, $_GLOBAL_OFFSET_TABLE_
mov GotVar, <reg>
Note that _GLOBAL_OFFSET_TABLE_ gets a special relocation type.
The register allocator takes GotVar uses into account, giving appropriate weight toward register allocation.
If there are no uses of GotVar, the getIP instruction gets naturally dead-code eliminated. Special treatment is needed to prevent this elimination when the only GotVar uses are for (floating point) constant pool values from Phi instructions, since the Phi lowering with its GotVar legalization happens after the main round of register allocation.
The x86 mem operand now has a IsPIC field to indicate whether it has been PIC-legalized. Mem operands are sometimes legalized more than once, and this IsPIC field keeps GotVar from being added more than once.
We have to limit the aggressiveness of address mode inference, to make sure a register slot is left for the GotVar.
The Subzero runtime has new asm files to implement all possible __Sz_getIP_<reg> helpers.
The szbuild.py script and the spec2k version support Non-SFI builds. Running spec2k depends on a pending change to the spec2k run_all.sh script.
Read-only data sections need to be named .data.rel.ro instead of .rodata because of PIC rules.
Most cross tests are working, but there is some problem with vector types that seems to be not Subzero related, so most vector tests are disabled for now.
Still to do:
* Fix "--nonsfi --filetype=iasm". The llvm-mc assembler doesn't properly apply the _GLOBAL_OFFSET_TABLE_ relocation in iasm mode. Maybe I can find a different syntactic trick that works, or use hybrid iasm for this limited case.
BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4327
R=jpp@chromium.org
Review URL: https://codereview.chromium.org/1506653002 .
diff --git a/src/IceTargetLoweringARM32.cpp b/src/IceTargetLoweringARM32.cpp
index 551fed3..878f95e 100644
--- a/src/IceTargetLoweringARM32.cpp
+++ b/src/IceTargetLoweringARM32.cpp
@@ -50,7 +50,9 @@
return ::Ice::ARM32::TargetHeaderARM32::create(Ctx);
}
-void staticInit() { ::Ice::ARM32::TargetARM32::staticInit(); }
+void staticInit(const ::Ice::ClFlags &Flags) {
+ ::Ice::ARM32::TargetARM32::staticInit(Flags);
+}
} // end of namespace ARM32
namespace Ice {
@@ -233,7 +235,8 @@
: TargetLowering(Func), NeedSandboxing(Ctx->getFlags().getUseSandboxing()),
CPUFeatures(Func->getContext()->getFlags()) {}
-void TargetARM32::staticInit() {
+void TargetARM32::staticInit(const ClFlags &Flags) {
+ (void)Flags;
// Limit this size (or do all bitsets need to be the same width)???
llvm::SmallBitVector IntegerRegisters(RegARM32::Reg_NUM);
llvm::SmallBitVector I64PairRegisters(RegARM32::Reg_NUM);
@@ -897,7 +900,7 @@
const Type VarTy = Var->getType();
Str << "[" << getRegName(BaseRegNum, VarTy);
if (Offset != 0) {
- Str << ", " << getConstantPrefix() << Offset;
+ Str << ", #" << Offset;
}
Str << "]";
}
@@ -5706,7 +5709,7 @@
if (!BuildDefs::dump())
return;
Ostream &Str = Ctx->getStrEmit();
- Str << getConstantPrefix() << C->getValue();
+ Str << "#" << C->getValue();
}
void TargetARM32::emit(const ConstantInteger64 *) const {
@@ -5727,6 +5730,14 @@
llvm::report_fatal_error("undef value encountered by emitter.");
}
+void TargetARM32::emit(const ConstantRelocatable *C) const {
+ if (!BuildDefs::dump())
+ return;
+ Ostream &Str = Ctx->getStrEmit();
+ Str << "#";
+ emitWithoutPrefix(C);
+}
+
void TargetARM32::lowerInt1ForSelect(Variable *Dest, Operand *Boolean,
Operand *TrueValue, Operand *FalseValue) {
Operand *_1 = legalize(Ctx->getConstantInt1(1), Legal_Reg | Legal_Flex);
@@ -6251,10 +6262,12 @@
void TargetDataARM32::lowerGlobals(const VariableDeclarationList &Vars,
const IceString &SectionSuffix) {
+ const bool IsPIC = Ctx->getFlags().getUseNonsfi();
switch (Ctx->getFlags().getOutFileType()) {
case FT_Elf: {
ELFObjectWriter *Writer = Ctx->getObjectWriter();
- Writer->writeDataSection(Vars, llvm::ELF::R_ARM_ABS32, SectionSuffix);
+ Writer->writeDataSection(Vars, llvm::ELF::R_ARM_ABS32, SectionSuffix,
+ IsPIC);
} break;
case FT_Asm:
case FT_Iasm: {
