Handle GPR and vector shift ops. Handle pmull also.
For the integer shift ops, since the Src1 operand is forced
to be an immediate or register (cl), it should be legal to
have Dest+Src0 be either register or memory. However, we
are currently only using the register form. It might be the
case that shift w/ Dest+Src0 as mem are less optimized
on some micro-architectures though, since it has to load,
shift, and store all in one operation, but I'm not sure.
BUG=none
R=stichnot@chromium.org
Review URL: https://codereview.chromium.org/622113002
10 files changed
