Handle MOV (immediate) and MOVT to load ARM global addresses.
Adds a new type of fixup to handle the relocatable fixups needed
for movw and movt on a global addresses. Also adds movw and movt
methods to the ARM assembler.
Also makes ARM register names visible (without a target lowering
object), so that the ARM integrated assembler can generate the appropriate assembly.
Note that the integrated assembler needs to generate the
corresponding movw/movt, and follows the instruction with the bytes
that appear in the corresponding assembler buffer. This allows the
ability to test if we have generated the correct values, and will be
set up properly for ELF emission.
BUG= https://code.google.com/p/nativeclient/issues/detail?id=4334
R=stichnot@chromium.org
Review URL: https://codereview.chromium.org/1424863005 .
diff --git a/src/IceTargetLoweringARM32.cpp b/src/IceTargetLoweringARM32.cpp
index a15b4f6..9caa2ff 100644
--- a/src/IceTargetLoweringARM32.cpp
+++ b/src/IceTargetLoweringARM32.cpp
@@ -386,18 +386,18 @@
return false;
}
-IceString TargetARM32::getRegName(SizeT RegNum, Type Ty) const {
- assert(RegNum < RegARM32::Reg_NUM);
- (void)Ty;
- static const char *RegNames[] = {
+const char *RegARM32::RegNames[] = {
#define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
isI64Pair, isFP32, isFP64, isVec128, alias_init) \
name,
- REGARM32_TABLE
+ REGARM32_TABLE
#undef X
- };
+};
- return RegNames[RegNum];
+IceString TargetARM32::getRegName(SizeT RegNum, Type Ty) const {
+ assert(RegNum < RegARM32::Reg_NUM);
+ (void)Ty;
+ return RegARM32::RegNames[RegNum];
}
Variable *TargetARM32::getPhysicalRegister(SizeT RegNum, Type Ty) {
