)]}'
{
  "commit": "7cb12682204f56e0c49f695599c434f77ed6cf29",
  "tree": "bec3a4827fc2a67895427a901d5d62a74938997c",
  "parents": [
    "16991847500a48932426d979c4f2d4adffaf3649"
  ],
  "author": {
    "name": "John Porto",
    "email": "jpp@chromium.org",
    "time": "Thu Oct 01 15:13:24 2015 -0700"
  },
  "committer": {
    "name": "John Porto",
    "email": "jpp@chromium.org",
    "time": "Thu Oct 01 15:13:24 2015 -0700"
  },
  "message": "Subzero. Fixes a bug in the register allocator.\n\nThis bug was uncovered While implementing the llvm.nacl.atomic.cmpxchg\nlowering for i64 for ARM32. For reference, the lowering is\n\nretry:\n    ldrexd     tmp_i, tmp_i+1 [addr]\n    cmp        tmp_i+1, expected_i+1\n    cmpeq      tmp_i, expected_i\n    strexdeq   success, new_i, new_i+1, [addr]\n    movne      expected_i+1, tmp_i+1\n    movne      expected_i, tmp_i\n    cmpeq      success, #0\n    bne        retry\n    mov        dest_i+1, tmp_i+1\n    mov        dest_i, tmp_i\n\nThe register allocator would allocate r4 to both success and new_i,\nwhich is clearly wrong (expected_i is alive thought the cmpxchg loop.)\nAdding a fake-use(new_i) after the loop caused the register allocator\nto fail due to the impossibility to allocate a register for an infinite\nweight register. The problem was being caused for not evicting live\nranges that were assigned registers that alias the selected register.\n\nBUG\u003d\nR\u003dkschimpf@google.com, stichnot@chromium.org\n\nReview URL: https://codereview.chromium.org/1373823006 .\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "50e014aa5f2018f522a910f519c16d20b46f1294",
      "old_mode": 33188,
      "old_path": "src/IceRegAlloc.cpp",
      "new_id": "480b9077c6956209817c11f578431f090b71fa05",
      "new_mode": 33188,
      "new_path": "src/IceRegAlloc.cpp"
    }
  ]
}