This patch enables running a couple more of lit tests for MIPS32
R=stichnot@chromium.org
Review URL: https://codereview.chromium.org/2448193008 .
Patch from Stefan Maksimovic <makdstefan@gmail.com>.
diff --git a/tests_lit/llvm2ice_tests/64bit.pnacl.ll b/tests_lit/llvm2ice_tests/64bit.pnacl.ll
index f195b1e..55f6832 100644
--- a/tests_lit/llvm2ice_tests/64bit.pnacl.ll
+++ b/tests_lit/llvm2ice_tests/64bit.pnacl.ll
@@ -120,6 +120,27 @@
; ARM32: bl {{.*}} ignore64BitArgNoInline
; MIPS32-LABEL: pass64BitArg
+; MIPS32-O2: sw a3,{{.*}}(sp)
+; MIPS32-O2: sw a2,{{.*}}(sp)
+; MIPS32-O2: li a2,123
+; MIPS32-O2: jal {{.*}} ignore64BitArgNoInline
+; MIPS32-O2: nop
+; MIPS32-O2: move s0,v0
+; MIPS32-O2: sw s3,{{.*}}(sp)
+; MIPS32-O2: sw s2,{{.*}}(sp)
+; MIPS32-O2: lw a0,{{.*}}(sp)
+; MIPS32-O2: move a1,s1
+; MIPS32-O2: li a2,123
+; MIPS32-O2: jal {{.*}} ignore64BitArgNoInline
+; MIPS32-O2: nop
+; MIPS32-O2: move s1,v0
+; MIPS32-O2: sw s7,{{.*}}(sp)
+; MIPS32-O2: sw s6,{{.*}}(sp)
+; MIPS32-O2: move a0,s4
+; MIPS32-O2: move a1,s5
+; MIPS32-O2: li a2,123
+; MIPS32-O2: jal {{.*}} ignore64BitArgNoInline
+; MIPS32-O2: nop
declare i32 @ignore64BitArgNoInline(i64, i32, i64)
@@ -164,6 +185,18 @@
; ARM32: mov r2, #123
; ARM32: bl {{.*}} ignore64BitArgNoInline
+; MIPS32-LABEL: pass64BitConstArg
+; MIPS32-O2: lui [[REG:.*]],0xdead
+; MIPS32-O2: ori [[REG1:.*]],[[REG]],0xbeef
+; MIPS32-O2: lui [[REG:.*]],0x1234
+; MIPS32-O2: ori [[REG2:.*]],[[REG]],0x5678
+; MIPS32-O2: sw [[REG1]],{{.*}}(sp)
+; MIPS32-O2: sw [[REG2]],{{.*}}(sp)
+; MIPS32-O2: move a0,a2
+; MIPS32-O2: move a1,a3
+; MIPS32-O2: li a2,123
+; MIPS32-O2: jal {{.*}} ignore64BitArgNoInline
+
define internal i32 @pass64BitUndefArg() {
entry:
%call = call i32 @ignore64BitArgNoInline(i64 0, i32 123, i64 undef)
@@ -566,6 +599,11 @@
; ARM32-LABEL: shl64BitSignedTrunc
; ARM32: lsl r
+; MIPS32-LABEL: shl64BitSignedTrunc
+; MIPS32-O2: sllv
+; MIPS32-O2: andi {{.*}},0x20
+; MIPS32-O2: movn
+
define internal i64 @shl64BitUnsigned(i64 %a, i64 %b) {
entry:
%shl = shl i64 %a, %b
@@ -675,6 +713,16 @@
; ARM32: cmp
; ARM32: asrge
+; MIPS32-LABEL: shr64BitSignedTrunc
+; MIPS32-O2: srlv
+; MIPS32-O2: nor
+; MIPS32-O2: sll
+; MIPS32-O2: sllv
+; MIPS32-O2: or
+; MIPS32-O2: srav
+; MIPS32-O2: andi {{.*}},0x20
+; MIPS32-O2: movn
+
define internal i64 @shr64BitUnsigned(i64 %a, i64 %b) {
entry:
%shr = lshr i64 %a, %b
@@ -739,6 +787,16 @@
; ARM32: cmp
; ARM32: lsrge
+; MIPS32-LABEL: shr64BitUnsignedTrunc
+; MIPS32-O2: srlv
+; MIPS32-O2: nor
+; MIPS32-O2: sll
+; MIPS32-O2: sllv
+; MIPS32-O2: or
+; MIPS32-O2: srlv
+; MIPS32-O2: andi
+; MIPS32-O2: movn
+
define internal i64 @and64BitSigned(i64 %a, i64 %b) {
entry:
%and = and i64 %b, %a
@@ -2173,6 +2231,10 @@
; ARM32: ldr r{{.*}}, [r[[REG:.*]]]
; ARM32: ldr r{{.*}}, [r[[REG]], #4]
+; MIPS32-LABEL: load64
+; MIPS32-O2: lw {{.*}},0([[REG:.*]])
+; MIPS32-O2: lw [[REG]],4([[REG]])
+
define internal void @store64(i32 %a, i64 %value) {
entry:
%__2 = inttoptr i32 %a to i64*
@@ -2192,6 +2254,10 @@
; ARM32: str r{{.*}}, [r[[REG:.*]], #4]
; ARM32: str r{{.*}}, [r[[REG]]]
+; MIPS32-LABEL: store64
+; MIPS32-O2: sw {{.*}},4([[REG:.*]])
+; MIPS32-O2: sw {{.*}},0([[REG]])
+
define internal void @store64Const(i32 %a) {
entry:
%__1 = inttoptr i32 %a to i64*
@@ -2215,6 +2281,14 @@
; ARM32: str [[REG1]], [r[[REG:.*]], #4]
; ARM32: str [[REG2]], [r[[REG]]]
+; MIPS32-LABEL: store64Const
+; MIPS32-O2: lui [[REG1:.*]],0xdead
+; MIPS32-O2: ori [[REG1:.*]],[[REG1]],0xbeef
+; MIPS32-O2: lui [[REG2:.*]],0x1234
+; MIPS32-O2: ori [[REG2:.*]],[[REG2]],0x5678
+; MIPS32-O2: sw [[REG1]],4([[REG:.*]])
+; MIPS32-O2: sw [[REG2]],0([[REG]])
+
define internal i64 @select64VarVar(i64 %a, i64 %b) {
entry:
%cmp = icmp ult i64 %a, %b
diff --git a/tests_lit/llvm2ice_tests/8bit.pnacl.ll b/tests_lit/llvm2ice_tests/8bit.pnacl.ll
index d11c857..d73dc40 100644
--- a/tests_lit/llvm2ice_tests/8bit.pnacl.ll
+++ b/tests_lit/llvm2ice_tests/8bit.pnacl.ll
@@ -14,6 +14,12 @@
; RUN: -reg-exclude=al,bl,cl,dl -reg-reserve \
; RUN: -allow-externally-defined-symbols | FileCheck %s --check-prefix=REM
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
+; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
+; RUN: | %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command FileCheck --check-prefix MIPS32 %s
+
declare void @useInt(i32 %x)
define internal i32 @add8Bit(i32 %a, i32 %b) {
@@ -26,6 +32,12 @@
}
; CHECK-LABEL: add8Bit
; CHECK: add {{[abcd]l}}
+; MIPS32-LABEL: add8Bit
+; MIPS32: addu
+; MIPS32: andi {{.*}},0xff
+; MIPS32: move
+; MIPS32: jr
+; MIPS32: nop
define internal i32 @add8BitConst(i32 %a) {
entry:
@@ -36,6 +48,13 @@
}
; CHECK-LABEL: add8BitConst
; CHECK: add {{[abcd]l}}
+; MIPS32-LABEL: add8BitConst
+; MIPS32: li
+; MIPS32: addu
+; MIPS32: andi {{.*}},0xff
+; MIPS32: move
+; MIPS32: jr
+; MIPS32: nop
define internal i32 @sub8Bit(i32 %a, i32 %b) {
entry:
@@ -47,6 +66,12 @@
}
; CHECK-LABEL: sub8Bit
; CHECK: sub {{[abcd]l}}
+; MIPS32-LABEL: sub8Bit
+; MIPS32: subu
+; MIPS32: andi {{.*}},0xff
+; MIPS32: move
+; MIPS32: jr
+; MIPS32: nop
define internal i32 @sub8BitConst(i32 %a) {
entry:
@@ -57,6 +82,13 @@
}
; CHECK-LABEL: sub8BitConst
; CHECK: sub {{[abcd]l}}
+; MIPS32-LABEL: sub8BitConst
+; MIPS32: li
+; MIPS32: subu
+; MIPS32: andi {{.*}},0xff
+; MIPS32: move
+; MIPS32: jr
+; MIPS32: nop
define internal i32 @mul8Bit(i32 %a, i32 %b) {
entry:
@@ -68,6 +100,12 @@
}
; CHECK-LABEL: mul8Bit
; CHECK: mul {{[abcd]l|BYTE PTR}}
+; MIPS32-LABEL: mul8Bit
+; MIPS32: mul
+; MIPS32: andi {{.*}},0xff
+; MIPS32: move
+; MIPS32: jr
+; MIPS32: nop
define internal i32 @mul8BitConst(i32 %a) {
entry:
@@ -80,6 +118,13 @@
; 8-bit imul only accepts r/m, not imm
; CHECK: mov {{.*}},0x38
; CHECK: mul {{[abcd]l|BYTE PTR}}
+; MIPS32-LABEL: mul8BitConst
+; MIPS32: li
+; MIPS32: mul
+; MIPS32: andi {{.*}},0xff
+; MIPS32: move
+; MIPS32: jr
+; MIPS32: nop
define internal i32 @udiv8Bit(i32 %a, i32 %b) {
entry:
@@ -91,6 +136,13 @@
}
; CHECK-LABEL: udiv8Bit
; CHECK: div {{[abcd]l|BYTE PTR}}
+; MIPS32-LABEL: udiv8Bit
+; MIPS32: divu
+; MIPS32: teq
+; MIPS32: mflo
+; MIPS32: andi {{.*}},0xff
+; MIPS32: jr
+; MIPS32: nop
define internal i32 @udiv8BitConst(i32 %a) {
entry:
@@ -101,6 +153,14 @@
}
; CHECK-LABEL: udiv8BitConst
; CHECK: div {{[abcd]l|BYTE PTR}}
+; MIPS32-LABEL: udiv8BitConst
+; MIPS32: li
+; MIPS32: divu
+; MIPS32: teq
+; MIPS32: mflo
+; MIPS32: andi {{.*}},0xff
+; MIPS32: jr
+; MIPS32: nop
define internal i32 @urem8Bit(i32 %a, i32 %b) {
entry:
@@ -115,6 +175,13 @@
; REM-LABEL: urem8Bit
; REM: div
; REM-NEXT: mov {{[abcd]}}l,ah
+; MIPS32-LABEL: urem8Bit
+; MIPS32: divu
+; MIPS32: teq
+; MIPS32: mfhi
+; MIPS32: andi {{.*}},0xff
+; MIPS32: jr
+; MIPS32: nop
define internal i32 @urem8BitConst(i32 %a) {
entry:
@@ -126,6 +193,14 @@
; CHECK-LABEL: urem8BitConst
; CHECK: div {{[abcd]l|BYTE PTR}}
; REM-LABEL: urem8BitConst
+; MIPS32-LABEL: urem8BitConst
+; MIPS32: li
+; MIPS32: divu
+; MIPS32: teq
+; MIPS32: mfhi
+; MIPS32: andi {{.*}},0xff
+; MIPS32: jr
+; MIPS32: nop
define internal i32 @sdiv8Bit(i32 %a, i32 %b) {
@@ -138,6 +213,13 @@
}
; CHECK-LABEL: sdiv8Bit
; CHECK: idiv {{[abcd]l|BYTE PTR}}
+; MIPS32-LABEL: sdiv8Bit
+; MIPS32: div
+; MIPS32: teq
+; MIPS32: mflo
+; MIPS32: andi {{.*}},0xff
+; MIPS32: jr
+; MIPS32: nop
define internal i32 @sdiv8BitConst(i32 %a) {
entry:
@@ -148,6 +230,14 @@
}
; CHECK-LABEL: sdiv8BitConst
; CHECK: idiv {{[abcd]l|BYTE PTR}}
+; MIPS32-LABEL: sdiv8BitConst
+; MIPS32: li
+; MIPS32: div
+; MIPS32: teq
+; MIPS32: mflo
+; MIPS32: andi {{.*}},0xff
+; MIPS32: jr
+; MIPS32: nop
define internal i32 @srem8Bit(i32 %a, i32 %b) {
entry:
@@ -162,6 +252,13 @@
; REM-LABEL: srem8Bit
; REM: idiv
; REM-NEXT: mov {{[abcd]}}l,ah
+; MIPS32-LABEL: srem8Bit
+; MIPS32: div
+; MIPS32: teq
+; MIPS32: mfhi
+; MIPS32: andi {{.*}},0xff
+; MIPS32: jr
+; MIPS32: nop
define internal i32 @srem8BitConst(i32 %a) {
entry:
@@ -173,6 +270,14 @@
; CHECK-LABEL: srem8BitConst
; CHECK: idiv {{[abcd]l|BYTE PTR}}
; REM-LABEL: srem8BitConst
+; MIPS32-LABEL: srem8BitConst
+; MIPS32: li
+; MIPS32: div
+; MIPS32: teq
+; MIPS32: mfhi
+; MIPS32: andi {{.*}},0xff
+; MIPS32: jr
+; MIPS32: nop
define internal i32 @shl8Bit(i32 %a, i32 %b) {
entry:
@@ -184,6 +289,12 @@
}
; CHECK-LABEL: shl8Bit
; CHECK: shl {{[abd]l|BYTE PTR}},cl
+; MIPS32-LABEL: shl8Bit
+; MIPS32: sllv
+; MIPS32: andi {{.*}},0xff
+; MIPS32: move
+; MIPS32: jr
+; MIPS32: nop
define internal i32 @shl8BitConst(i32 %a, i32 %b) {
entry:
@@ -194,6 +305,13 @@
}
; CHECK-LABEL: shl8BitConst
; CHECK: shl {{[abcd]l|BYTE PTR}},0x6
+; MIPS32-LABEL: shl8BitConst
+; MIPS32: li
+; MIPS32: sllv
+; MIPS32: andi {{.*}},0xff
+; MIPS32: move
+; MIPS32: jr
+; MIPS32: nop
define internal i32 @lshr8Bit(i32 %a, i32 %b) {
entry:
@@ -205,6 +323,12 @@
}
; CHECK-LABEL: lshr8Bit
; CHECK: shr {{[abd]l|BYTE PTR}},cl
+; MIPS32-LABEL: lshr8Bit
+; MIPS32: srlv
+; MIPS32: andi {{.*}},0xff
+; MIPS32: move
+; MIPS32: jr
+; MIPS32: nop
define internal i32 @lshr8BitConst(i32 %a, i32 %b) {
entry:
@@ -215,6 +339,13 @@
}
; CHECK-LABEL: lshr8BitConst
; CHECK: shr {{[abcd]l|BYTE PTR}},0x6
+; MIPS32-LABEL: lshr8BitConst
+; MIPS32: li
+; MIPS32: srlv
+; MIPS32: andi {{.*}},0xff
+; MIPS32: move
+; MIPS32: jr
+; MIPS32: nop
define internal i32 @ashr8Bit(i32 %a, i32 %b) {
entry:
@@ -226,6 +357,12 @@
}
; CHECK-LABEL: ashr8Bit
; CHECK: sar {{[abd]l|BYTE PTR}},cl
+; MIPS32-LABEL: ashr8Bit
+; MIPS32: sra
+; MIPS32: andi {{.*}},0xff
+; MIPS32: move
+; MIPS32: jr
+; MIPS32: nop
define internal i32 @ashr8BitConst(i32 %a, i32 %b) {
entry:
@@ -236,6 +373,13 @@
}
; CHECK-LABEL: ashr8BitConst
; CHECK: sar {{[abcd]l|BYTE PTR}},0x6
+; MIPS32-LABEL: ashr8BitConst
+; MIPS32: li
+; MIPS32: srav
+; MIPS32: andi {{.*}},0xff
+; MIPS32: move
+; MIPS32: jr
+; MIPS32: nop
define internal i32 @icmp8Bit(i32 %a, i32 %b) {
entry:
@@ -247,6 +391,15 @@
}
; CHECK-LABEL: icmp8Bit
; CHECK: cmp {{[abcd]l|BYTE PTR}}
+; MIPS32-LABEL: icmp8Bit
+; MIPS32: sll {{.*}},0x18
+; MIPS32: sll {{.*}},0x18
+; MIPS32: xor
+; MIPS32: sltu
+; MIPS32: andi {{.*}},0x1
+; MIPS32: move
+; MIPS32: jr
+; MIPS32: nop
define internal i32 @icmp8BitConst(i32 %a) {
entry:
@@ -257,6 +410,16 @@
}
; CHECK-LABEL: icmp8BitConst
; CHECK: cmp {{[abcd]l|BYTE PTR}}
+; MIPS32-LABEL: icmp8BitConst
+; MIPS32: li
+; MIPS32: sll {{.*}},0x18
+; MIPS32: sll {{.*}},0x18
+; MIPS32: xor
+; MIPS32: sltu
+; MIPS32: andi {{.*}},0x1
+; MIPS32: move
+; MIPS32: jr
+; MIPS32: nop
define internal i32 @icmp8BitConstSwapped(i32 %a) {
entry:
@@ -267,6 +430,15 @@
}
; CHECK-LABEL: icmp8BitConstSwapped
; CHECK: cmp {{[abcd]l|BYTE PTR}}
+; MIPS32-LABEL: icmp8BitConstSwapped
+; MIPS32: li
+; MIPS32: sll {{.*}},0x18
+; MIPS32: sll {{.*}},0x18
+; MIPS32: xor v0,v0,a0
+; MIPS32: sltu
+; MIPS32: andi {{.*}},0x1
+; MIPS32: jr
+; MIPS32: nop
define internal i32 @icmp8BitMem(i32 %a, i32 %b_iptr) {
entry:
@@ -279,6 +451,16 @@
}
; CHECK-LABEL: icmp8BitMem
; CHECK: cmp {{[abcd]l|BYTE PTR}}
+; MIPS32-LABEL: icmp8BitMem
+; MIPS32: lb
+; MIPS32: sll {{.*}},0x18
+; MIPS32: sll {{.*}},0x18
+; MIPS32: xor
+; MIPS32: sltu
+; MIPS32: andi {{.*}},0x1
+; MIPS32: move
+; MIPS32: jr
+; MIPS32: nop
define internal i32 @icmp8BitMemSwapped(i32 %a, i32 %b_iptr) {
entry:
@@ -291,6 +473,16 @@
}
; CHECK-LABEL: icmp8BitMemSwapped
; CHECK: cmp {{[abcd]l|BYTE PTR}}
+; MIPS32-LABEL: icmp8BitMemSwapped
+; MIPS32: lb
+; MIPS32: sll {{.*}},0x18
+; MIPS32: sll {{.*}},0x18
+; MIPS32: xor
+; MIPS32: sltu
+; MIPS32: andi {{.*}},0x1
+; MIPS32: move
+; MIPS32: jr
+; MIPS32: nop
define internal i32 @selectI8Var(i32 %a, i32 %b) {
entry:
@@ -308,6 +500,29 @@
; CHECK: cmp
; CHECK: setl
; CHECK: mov {{[a-d]l}}
+; MIPS32-LABEL: selectI8Var
+; MIPS32: addiu
+; MIPS32: sw
+; MIPS32: sw
+; MIPS32: move
+; MIPS32: move
+; MIPS32: sll {{.*}},0x18
+; MIPS32: sll {{.*}},0x18
+; MIPS32: slt
+; MIPS32: move
+; MIPS32: movn
+; MIPS32: andi {{.*}},0xff
+; MIPS32: move
+; MIPS32: andi {{.*}},0x1
+; MIPS32: move
+; MIPS32: jal
+; MIPS32: nop
+; MIPS32: move
+; MIPS32: lw
+; MIPS32: lw
+; MIPS32: addiu
+; MIPS32: jr
+; MIPS32: nop
define internal i32 @testPhi8(i32 %arg, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) {
entry:
@@ -360,6 +575,14 @@
}
; CHECK-LABEL: load_i8
; CHECK: mov {{[a-d]l}},BYTE PTR
+; MIPS32-LABEL: load_i8
+; MIPS32: lb
+; MIPS32: li
+; MIPS32: subu
+; MIPS32: andi {{.*}},0xff
+; MIPS32: move
+; MIPS32: jr
+; MIPS32: nop
define i32 @load_i8_global(i32 %addr_arg) {
entry:
@@ -371,6 +594,15 @@
}
; CHECK-LABEL: load_i8_global
; CHECK: mov {{[a-d]l}},{{(BYTE PTR)?}}
+; MIPS32-LABEL: load_i8_global
+; MIPS32: lui
+; MIPS32: addiu
+; MIPS32: lb
+; MIPS32: li
+; MIPS32: subu
+; MIPS32: andi {{.*}},0xff
+; MIPS32: jr
+; MIPS32: nop
define void @store_i8(i32 %addr_arg, i32 %val) {
entry:
@@ -381,6 +613,10 @@
}
; CHECK-LABEL: store_i8
; CHECK: mov BYTE PTR {{.*}},{{[a-d]l}}
+; MIPS32-LABEL: store_i8
+; MIPS32: sb
+; MIPS32: jr
+; MIPS32: nop
define void @store_i8_const(i32 %addr_arg) {
entry:
@@ -390,3 +626,8 @@
}
; CHECK-LABEL: store_i8_const
; CHECK: mov BYTE PTR {{.*}},0x7b
+; MIPS32-LABEL: store_i8_const
+; MIPS32: li
+; MIPS32: sb
+; MIPS32: jr
+; MIPS32: nop
diff --git a/tests_lit/llvm2ice_tests/adv-switch-opt.ll b/tests_lit/llvm2ice_tests/adv-switch-opt.ll
index 1942ae9..506da41 100644
--- a/tests_lit/llvm2ice_tests/adv-switch-opt.ll
+++ b/tests_lit/llvm2ice_tests/adv-switch-opt.ll
@@ -6,6 +6,12 @@
; RUN: %p2i -i %s --target=x8664 --filetype=obj --disassemble --args -O2 \
; RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=X8664
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
+; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
+; RUN: | %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command FileCheck --check-prefix MIPS32 %s
+
; Dense but non-continuous ranges should be converted into a jump table.
define internal i32 @testJumpTable(i32 %a) {
entry:
@@ -43,6 +49,32 @@
; "mov eax, [...]; jmp rax", so we assume the all characters except the first
; one in the register name will match.
+; MIPS32-LABEL: testJumpTable
+; MIPS32: move [[REG1:.*]],{{.*}}
+; MIPS32: li [[REG2:.*]],91
+; MIPS32: beq [[REG1]],[[REG2]],6c <.LtestJumpTable$sw.default>
+; MIPS32: nop
+; MIPS32: li [[REG2:.*]],92
+; MIPS32: beq [[REG1]],[[REG2]],7c <.LtestJumpTable$sw.bb1>
+; MIPS32: nop
+; MIPS32: li [[REG2:.*]],93
+; MIPS32: beq [[REG1]],[[REG2]],6c <.LtestJumpTable$sw.default>
+; MIPS32: nop
+; MIPS32: li [[REG2:.*]],99
+; MIPS32: beq [[REG1]],[[REG2]],7c <.LtestJumpTable$sw.bb1>
+; MIPS32: nop
+; MIPS32: li [[REG2:.*]],98
+; MIPS32: beq [[REG1]],[[REG2]],6c <.LtestJumpTable$sw.default>
+; MIPS32: nop
+; MIPS32: li [[REG2:.*]],96
+; MIPS32: beq [[REG1]],[[REG2]],7c <.LtestJumpTable$sw.bb1>
+; MIPS32: nop
+; MIPS32: li [[REG2:.*]],97
+; MIPS32: beq [[REG1]],[[REG2]],60 <.LtestJumpTable$split_entry_sw.epilog_0>
+; MIPS32: nop
+; MIPS32: b 6c <.LtestJumpTable$sw.default>
+; MIPS32: nop
+
; Continuous ranges which map to the same target should be grouped and
; efficiently tested.
define internal i32 @testRangeTest() {
@@ -76,6 +108,35 @@
; CHECK-NEXT: jbe
; CHECK-NEXT: jmp
+; MIPS32-LABEL: testRangeTest
+; MIPS32: li [[REG1:.*]],10
+; MIPS32: li [[REG2:.*]],0
+; MIPS32: beq [[REG1]],[[REG2]],114 <.LtestRangeTest$split_entry_sw.epilog_0>
+; MIPS32: nop
+; MIPS32: li [[REG2:.*]],1
+; MIPS32: beq [[REG1]],[[REG2]],114 <.LtestRangeTest$split_entry_sw.epilog_0>
+; MIPS32: nop
+; MIPS32: li [[REG2:.*]],2
+; MIPS32: beq [[REG1]],[[REG2]],114 <.LtestRangeTest$split_entry_sw.epilog_0>
+; MIPS32: nop
+; MIPS32: li [[REG2:.*]],3
+; MIPS32: beq [[REG1]],[[REG2]],114 <.LtestRangeTest$split_entry_sw.epilog_0>
+; MIPS32: nop
+; MIPS32: li [[REG2:.*]],10
+; MIPS32: beq [[REG1]],[[REG2]],fc <.LtestRangeTest$split_sw.bb1_sw.epilog_2>
+; MIPS32: nop
+; MIPS32: li [[REG2:.*]],11
+; MIPS32: beq [[REG1]],[[REG2]],fc <.LtestRangeTest$split_sw.bb1_sw.epilog_2>
+; MIPS32: nop
+; MIPS32: li [[REG2:.*]],12
+; MIPS32: beq [[REG1]],[[REG2]],fc <.LtestRangeTest$split_sw.bb1_sw.epilog_2>
+; MIPS32: nop
+; MIPS32: li [[REG2:.*]],13
+; MIPS32: beq [[REG1]],[[REG2]],fc <.LtestRangeTest$split_sw.bb1_sw.epilog_2>
+; MIPS32: nop
+; MIPS32: b 108 <.LtestRangeTest$split_sw.default_sw.epilog_1>
+; MIPS32: nop
+
; Sparse cases should be searched with a binary search.
define internal i32 @testBinarySearch() {
entry:
@@ -109,6 +170,23 @@
; CHECK-NEXT: je
; CHECK-NEXT: jmp
+; MIPS32-LABEL: testBinarySearch
+; MIPS32: li [[REG1:.*]],10
+; MIPS32: li [[REG2:.*]],0
+; MIPS32: beq [[REG1]],[[REG2]],174 <.LtestBinarySearch$split_entry_sw.epilog_0>
+; MIPS32: nop
+; MIPS32: li [[REG2:.*]],10
+; MIPS32: beq [[REG1]],[[REG2]],174 <.LtestBinarySearch$split_entry_sw.epilog_0>
+; MIPS32: nop
+; MIPS32: li [[REG2:.*]],20
+; MIPS32: beq [[REG1]],[[REG2]],15c <.LtestBinarySearch$split_sw.bb1_sw.epilog_2>
+; MIPS32: nop
+; MIPS32: li [[REG2:.*]],30
+; MIPS32: beq [[REG1]],[[REG2]],15c <.LtestBinarySearch$split_sw.bb1_sw.epilog_2>
+; MIPS32: nop
+; MIPS32: b 168 <.LtestBinarySearch$split_sw.default_sw.epilog_1>
+; MIPS32: nop
+
; 64-bit switches where the cases are all 32-bit values should be reduced to a
; 32-bit switch after checking the top byte is 0.
define internal i32 @testSwitchSmall64(i64 %a) {
@@ -150,6 +228,14 @@
; X8632-NEXT: cmp {{.*}},0xea
; X8632-NEXT: je
+; MIPS32-LABEL: testSwitchSmall64
+; MIPS32: li [[REG:.*]],0
+; MIPS32: bne {{.*}},[[REG]],198 <.LtestSwitchSmall64$local$__0>
+; MIPS32: nop
+; MIPS32: li [[REG:.*]],123
+; MIPS32: beq {{.*}},[[REG]],210 <.LtestSwitchSmall64$split_entry_return_0>
+; MIPS32: nop
+
; Test for correct 64-bit lowering.
; TODO(ascull): this should generate better code like the 32-bit version
define internal i32 @testSwitch64(i64 %a) {
@@ -195,6 +281,14 @@
; X8632-NEXT: cmp {{.*}},0x12
; X8632-NEXT: je
+; MIPS32-LABEL: testSwitch64
+; MIPS32: li [[REG:.*]],0
+; MIPS32: bne {{.*}},[[REG]],238 <.LtestSwitch64$local$__0>
+; MIPS32: nop
+; MIPS32: li [[REG:.*]],123
+; MIPS32: beq {{.*}},[[REG]],2b4 <.LtestSwitch64$split_entry_return_0>
+; MIPS32: nop
+
; Test for correct 64-bit jump table with UINT64_MAX as one of the values.
define internal i32 @testJumpTable64(i64 %a) {
entry:
diff --git a/tests_lit/llvm2ice_tests/callindirect.pnacl.ll b/tests_lit/llvm2ice_tests/callindirect.pnacl.ll
index 2329b87..fded7f4 100644
--- a/tests_lit/llvm2ice_tests/callindirect.pnacl.ll
+++ b/tests_lit/llvm2ice_tests/callindirect.pnacl.ll
@@ -35,6 +35,12 @@
; RUN: | %if --need=target_ARM32_dump \
; RUN: --command FileCheck --check-prefix ARM32 %s
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
+; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
+; RUN: | %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command FileCheck --check-prefix MIPS32 %s
+
@__init_array_start = internal constant [0 x i8] zeroinitializer, align 4
@__fini_array_start = internal constant [0 x i8] zeroinitializer, align 4
@__tls_template_start = internal constant [0 x i8] zeroinitializer, align 8
@@ -98,6 +104,11 @@
; ARM32: blx [[REGISTER]]
; ARM32: blx [[REGISTER]]
+; MIPS32-LABEL: CallIndirect
+; MIPS32: jalr [[REGISTER:.*]]
+; MIPS32: jalr [[REGISTER]]
+; MIPS32: jalr [[REGISTER]]
+; MIPS32: jalr [[REGISTER]]
@fp_v = internal global [4 x i8] zeroinitializer, align 4
@@ -150,6 +161,12 @@
; ARM32: blx [[REGISTER]]
; ARM32: blx [[REGISTER]]
+; MIPS32-LABEL: CallIndirectGlobal
+; MIPS32: jalr [[REGISTER:.*]]
+; MIPS32: jalr [[REGISTER]]
+; MIPS32: jalr [[REGISTER]]
+; MIPS32: jalr [[REGISTER]]
+
; Calling an absolute address is used for non-IRT PNaCl pexes to directly
; access syscall trampolines. This is not really an indirect call, but
; there is a cast from int to pointer first.
diff --git a/tests_lit/llvm2ice_tests/commutativity.ll b/tests_lit/llvm2ice_tests/commutativity.ll
index a8ceccc..ca5f6c7 100644
--- a/tests_lit/llvm2ice_tests/commutativity.ll
+++ b/tests_lit/llvm2ice_tests/commutativity.ll
@@ -6,6 +6,12 @@
; RUN: --target x8632 -i %s --args -O2 \
; RUN: | %if --need=target_X8632 --command FileCheck %s
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
+; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
+; RUN: | %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command FileCheck --check-prefix MIPS32 %s
+
define internal i32 @integerAddLeft(i32 %a, i32 %b) {
entry:
%tmp = add i32 %a, %b
@@ -17,6 +23,10 @@
; CHECK-NEXT: mov {{e..}},DWORD PTR
; CHECK-NEXT: add {{e..}},{{e..}}
; CHECK-NEXT: add {{e..}},{{e..}}
+; MIPS32-LABEL: integerAddLeft
+; MIPS32: move v0,a0
+; MIPS32: addu v0,v0,a1
+; MIPS32: addu a0,a0,v0
define internal i32 @integerAddRight(i32 %a, i32 %b) {
entry:
@@ -29,6 +39,10 @@
; CHECK-NEXT: mov {{e..}},DWORD PTR
; CHECK-NEXT: add {{e..}},{{e..}}
; CHECK-NEXT: add {{e..}},{{e..}}
+; MIPS32-LABEL: integerAddRight
+; MIPS32: move v0,a1
+; MIPS32: addu a0,a0,v0
+; MIPS32: addu a1,a1,a0
define internal i32 @integerMultiplyLeft(i32 %a, i32 %b) {
entry:
@@ -41,6 +55,10 @@
; CHECK-NEXT: mov {{e..}},DWORD PTR
; CHECK-NEXT: imul {{e..}},{{e..}}
; CHECK-NEXT: imul {{e..}},{{e..}}
+; MIPS32-LABEL: integerMultiplyLeft
+; MIPS32: move v0,a0
+; MIPS32: mul v0,v0,a1
+; MIPS32: mul a0,a0,v0
define internal i32 @integerMultiplyRight(i32 %a, i32 %b) {
entry:
@@ -53,6 +71,10 @@
; CHECK-NEXT: mov {{e..}},DWORD PTR
; CHECK-NEXT: imul {{e..}},{{e..}}
; CHECK-NEXT: imul {{e..}},{{e..}}
+; MIPS32-LABEL: integerMultiplyRight
+; MIPS32: move v0,a1
+; MIPS32: mul a0,a0,v0
+; MIPS32: mul a1,a1,a0
define internal float @floatAddLeft(float %a, float %b) {
entry:
@@ -66,6 +88,10 @@
; CHECK-NEXT: movss xmm1,DWORD PTR
; CHECK-NEXT: addss xmm1,xmm0
; CHECK-NEXT: addss xmm0,xmm1
+; MIPS32-LABEL: floatAddLeft
+; MIPS32: mov.s $f0,$f12
+; MIPS32: add.s $f0,$f0,$f14
+; MIPS32: add.s $f12,$f12,$f0
define internal float @floatAddRight(float %a, float %b) {
entry:
@@ -79,6 +105,10 @@
; CHECK-NEXT: movss xmm1,DWORD PTR
; CHECK-NEXT: addss xmm0,xmm1
; CHECK-NEXT: addss xmm1,xmm0
+; MIPS32-LABEL: floatAddRight
+; MIPS32: mov.s $f0,$f14
+; MIPS32: add.s $f12,$f12,$f0
+; MIPS32: add.s $f14,$f14,$f12
define internal float @floatMultiplyLeft(float %a, float %b) {
entry:
@@ -92,6 +122,10 @@
; CHECK-NEXT: movss xmm1,DWORD PTR
; CHECK-NEXT: mulss xmm1,xmm0
; CHECK-NEXT: mulss xmm0,xmm1
+; MIPS32-LABEL: floatMultiplyLeft
+; MIPS32: mov.s $f0,$f12
+; MIPS32: mul.s $f0,$f0,$f14
+; MIPS32: mul.s $f12,$f12,$f0
define internal float @floatMultiplyRight(float %a, float %b) {
entry:
@@ -105,3 +139,7 @@
; CHECK-NEXT: movss xmm1,DWORD PTR
; CHECK-NEXT: mulss xmm0,xmm1
; CHECK-NEXT: mulss xmm1,xmm0
+; MIPS32-LABEL: floatMultiplyRight
+; MIPS32: mov.s $f0,$f14
+; MIPS32: mul.s $f12,$f12,$f0
+; MIPS32: mul.s $f14,$f14,$f12
diff --git a/tests_lit/llvm2ice_tests/convert.ll b/tests_lit/llvm2ice_tests/convert.ll
index 52c55ef..743cdad 100644
--- a/tests_lit/llvm2ice_tests/convert.ll
+++ b/tests_lit/llvm2ice_tests/convert.ll
@@ -20,6 +20,12 @@
; RUN: | %if --need=target_ARM32 \
; RUN: --command FileCheck --check-prefix ARM32 %s
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
+; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
+; RUN: | %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command FileCheck --check-prefix MIPS32 %s
+
@i8v = internal global [1 x i8] zeroinitializer, align 1
@i16v = internal global [2 x i8] zeroinitializer, align 2
@i32v = internal global [4 x i8] zeroinitializer, align 4
@@ -70,6 +76,28 @@
; ARM32-DAG: str r{{.*}}, [r{{[0-9]+}}]
; ARM32-DAG: str r{{.*}}, [{{.*}}, #4]
+; MIPS32-LABEL: from_int8
+; MIPS32: lui {{.*}} i8v
+; MIPS32: addiu {{.*}} i8v
+; MIPS32: lb
+; MIPS32: move
+; MIPS32: sll {{.*}},0x18
+; MIPS32: sra {{.*}},0x18
+; MIPS32: lui {{.*}} i16v
+; MIPS32: addiu {{.*}} i16v
+; MIPS32: sh
+; MIPS32: move
+; MIPS32: sll {{.*}},0x18
+; MIPS32: sra {{.*}},0x18
+; MIPS32: lui {{.*}} i32v
+; MIPS32: addiu {{.*}} i32v
+; MIPS32: sw
+; MIPS32: sll {{.*}},0x18
+; MIPS32: sra {{.*}},0x18
+; MIPS32: sra {{.*}},0x1f
+; MIPS32: lui {{.*}} i64v
+; MIPS32: addiu {{.*}} i64v
+
define internal void @from_int16() {
entry:
%__0 = bitcast [2 x i8]* @i16v to i16*
@@ -107,6 +135,26 @@
; ARM32: movw {{.*}}i64v
; ARM32: str r
+; MIPS32-LABEL: from_int16
+; MIPS32: lui {{.*}} i16v
+; MIPS32: addiu {{.*}} i16v
+; MIPS32: lh
+; MIPS32: move
+; MIPS32: lui {{.*}} i8v
+; MIPS32: addiu {{.*}} i8v
+; MIPS32: sb
+; MIPS32: move
+; MIPS32: sll {{.*}},0x10
+; MIPS32: sra {{.*}},0x10
+; MIPS32: lui {{.*}} i32v
+; MIPS32: addiu {{.*}} i32v
+; MIPS32: sw
+; MIPS32: sll {{.*}},0x10
+; MIPS32: sra {{.*}},0x10
+; MIPS32: sra {{.*}},0x1f
+; MIPS32: lui {{.*}} i64v
+; MIPS32: addiu {{.*}} i64v
+
define internal void @from_int32() {
entry:
%__0 = bitcast [4 x i8]* @i32v to i32*
@@ -140,6 +188,22 @@
; ARM32: movw {{.*}}i64v
; ARM32: str r
+; MIPS32-LABEL: from_int32
+; MIPS32: lui {{.*}} i32v
+; MIPS32: addiu {{.*}} i32v
+; MIPS32: lw
+; MIPS32: move
+; MIPS32: lui {{.*}} i8v
+; MIPS32: addiu {{.*}} i8v
+; MIPS32: sb
+; MIPS32: move
+; MIPS32: lui {{.*}} i16v
+; MIPS32: addiu {{.*}} i16v
+; MIPS32: sh
+; MIPS32: sra {{.*}},0x1f
+; MIPS32: lui {{.*}} i64v
+; MIPS32: addiu {{.*}} i64v
+
define internal void @from_int64() {
entry:
%__0 = bitcast [8 x i8]* @i64v to i64*
@@ -171,6 +235,21 @@
; ARM32: movw {{.*}}i32v
; ARM32: str r
+; MIPS32-LABEL: from_int64
+; MIPS32: lui {{.*}} i64v
+; MIPS32: addiu {{.*}} i64v
+; MIPS32: lw
+; MIPS32: move
+; MIPS32: lui {{.*}} i8v
+; MIPS32: addiu {{.*}} i8v
+; MIPS32: sb
+; MIPS32: move
+; MIPS32: lui {{.*}} i16v
+; MIPS32: addiu {{.*}} i16v
+; MIPS32: sh
+; MIPS32: lui {{.*}} i32v
+; MIPS32: addiu {{.*}} i32v
+
define internal void @from_uint8() {
entry:
%__0 = bitcast [1 x i8]* @u8v to i8*
@@ -210,6 +289,25 @@
; ARM32: movw {{.*}}i64v
; ARM32: str r
+; MIPS32-LABEL: from_uint8
+; MIPS32: lui {{.*}} u8v
+; MIPS32: addiu {{.*}} u8v
+; MIPS32: lb
+; MIPS32: move
+; MIPS32: andi {{.*}},0xff
+; MIPS32: lui {{.*}} i16v
+; MIPS32: addiu {{.*}} i16v
+; MIPS32: sh
+; MIPS32: move
+; MIPS32: andi {{.*}},0xff
+; MIPS32: lui {{.*}} i32v
+; MIPS32: addiu {{.*}} i32v
+; MIPS32: sw
+; MIPS32: andi {{.*}},0xff
+; MIPS32: li {{.*}},0
+; MIPS32: lui {{.*}} i64v
+; MIPS32: addiu {{.*}} i64v
+
define internal void @from_uint16() {
entry:
%__0 = bitcast [2 x i8]* @u16v to i16*
@@ -247,6 +345,24 @@
; ARM32: movw {{.*}}i64v
; ARM32: str r
+; MIPS32-LABEL: from_uint16
+; MIPS32: lui {{.*}} u16v
+; MIPS32: addiu {{.*}} u16v
+; MIPS32: lh
+; MIPS32: move
+; MIPS32: lui {{.*}} i8v
+; MIPS32: addiu {{.*}} i8v
+; MIPS32: sb
+; MIPS32: move
+; MIPS32: andi {{.*}},0xffff
+; MIPS32: lui {{.*}} i32v
+; MIPS32: addiu {{.*}} i32v
+; MIPS32: sw
+; MIPS32: andi {{.*}},0xffff
+; MIPS32: li {{.*}},0
+; MIPS32: lui {{.*}} i64v
+; MIPS32: addiu {{.*}} i64v
+
define internal void @from_uint32() {
entry:
%__0 = bitcast [4 x i8]* @u32v to i32*
@@ -280,6 +396,22 @@
; ARM32: movw {{.*}}i64v
; ARM32: str r
+; MIPS32-LABEL: from_uint32
+; MIPS32: lui {{.*}} u32v
+; MIPS32: addiu {{.*}} u32v
+; MIPS32: lw
+; MIPS32: move
+; MIPS32: lui {{.*}} i8v
+; MIPS32: addiu {{.*}} i8v
+; MIPS32: sb
+; MIPS32: move
+; MIPS32: lui {{.*}} i16v
+; MIPS32: addiu {{.*}} i16v
+; MIPS32: sh
+; MIPS32: li {{.*}},0
+; MIPS32: lui {{.*}} i64v
+; MIPS32: addiu {{.*}} i64v
+
define internal void @from_uint64() {
entry:
%__0 = bitcast [8 x i8]* @u64v to i64*
@@ -310,3 +442,18 @@
; ARM32: strh
; ARM32: movw {{.*}}i32v
; ARM32: str r
+
+; MIPS32-LABEL: from_uint64
+; MIPS32: lui {{.*}} u64v
+; MIPS32: addiu {{.*}} u64v
+; MIPS32: lw
+; MIPS32: move
+; MIPS32: lui {{.*}} i8v
+; MIPS32: addiu {{.*}} i8v
+; MIPS32: sb
+; MIPS32: move
+; MIPS32: lui {{.*}} i16v
+; MIPS32: addiu {{.*}} i16v
+; MIPS32: sh
+; MIPS32: lui {{.*}} i32v
+; MIPS32: addiu {{.*}} i32v
diff --git a/tests_lit/llvm2ice_tests/fp.call_ret.ll b/tests_lit/llvm2ice_tests/fp.call_ret.ll
index b305ae9..833b9a6 100644
--- a/tests_lit/llvm2ice_tests/fp.call_ret.ll
+++ b/tests_lit/llvm2ice_tests/fp.call_ret.ll
@@ -10,6 +10,12 @@
; RUN: --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
; RUN: | %if --need=target_X8632 --command FileCheck %s
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
+; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
+; RUN: | %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command FileCheck --check-prefix MIPS32 %s
+
; Can't test on ARM yet. Need to use several vpush {contiguous FP regs},
; instead of push {any GPR list}.
@@ -21,6 +27,9 @@
; CHECK: mov eax,DWORD PTR [esp+0xc]
; CHECK-NEXT: ret
; ARM32-LABEL: doubleArgs
+; MIPS32-LABEL: doubleArgs
+; MIPS32: move v0,a2
+; MIPS32: jr ra
define internal i32 @floatArgs(float %a, i32 %b, float %c) {
entry:
@@ -29,6 +38,9 @@
; CHECK-LABEL: floatArgs
; CHECK: mov eax,DWORD PTR [esp+0x8]
; CHECK-NEXT: ret
+; MIPS32-LABEL: floatArgs
+; MIPS32: move v0,a1
+; MIPS32: jr ra
define internal i32 @passFpArgs(float %a, double %b, float %c, double %d, float %e, double %f) {
entry:
@@ -46,6 +58,19 @@
; CHECK: call {{.*}} R_{{.*}} ignoreFpArgsNoInline
; CHECK: mov DWORD PTR [esp+0x4],0x7b
; CHECK: call {{.*}} R_{{.*}} ignoreFpArgsNoInline
+; MIPS32-LABEL: passFpArgs
+; MIPS32: mfc1 a2,$f15
+; MIPS32: mfc1 a3,$f14
+; MIPS32: li a1,123
+; MIPS32: jal {{.*}} ignoreFpArgsNoInline
+; MIPS32: mfc1 a2,$f23
+; MIPS32: mfc1 a3,$f22
+; MIPS32: li a1,123
+; MIPS32: jal {{.*}} ignoreFpArgsNoInline
+; MIPS32: mfc1 a2,$f25
+; MIPS32: mfc1 a3,$f24
+; MIPS32: li a1,123
+; MIPS32: jal {{.*}} ignoreFpArgsNoInline
declare i32 @ignoreFpArgsNoInline(float %x, i32 %y, double %z)
@@ -57,6 +82,11 @@
; CHECK-LABEL: passFpConstArg
; CHECK: mov DWORD PTR [esp+0x4],0x7b
; CHECK: call {{.*}} R_{{.*}} ignoreFpArgsNoInline
+; MIPS32-LABEL: passFpConstArg
+; MIPS32: mfc1 a2,$f1
+; MIPS32: mfc1 a3,$f0
+; MIPS32: li a1,123
+; MIPS32: jal {{.*}} ignoreFpArgsNoInline
define internal i32 @passFp32ConstArg(float %a) {
entry:
@@ -67,6 +97,10 @@
; CHECK: mov DWORD PTR [esp+0x4],0x7b
; CHECK: movss DWORD PTR [esp+0x8]
; CHECK: call {{.*}} R_{{.*}} ignoreFp32ArgsNoInline
+; MIPS32-LABEL: passFp32ConstArg
+; MIPS32: mfc1 a2,$f0
+; MIPS32: li a1,123
+; MIPS32: jal {{.*}} ignoreFp32ArgsNoInline
declare i32 @ignoreFp32ArgsNoInline(float %x, i32 %y, float %z)
@@ -76,6 +110,9 @@
}
; CHECK-LABEL: returnFloatArg
; CHECK: fld DWORD PTR [esp
+; MIPS32-LABEL: returnFloatArg
+; MIPS32: mov.s $f0,$f12
+; MIPS32: jr ra
define internal double @returnDoubleArg(double %a) {
entry:
@@ -83,6 +120,9 @@
}
; CHECK-LABEL: returnDoubleArg
; CHECK: fld QWORD PTR [esp
+; MIPS32-LABEL: returnDoubleArg
+; MIPS32: mov.d $f0,$f12
+; MIPS32: jr ra
define internal float @returnFloatConst() {
entry:
@@ -90,6 +130,10 @@
}
; CHECK-LABEL: returnFloatConst
; CHECK: fld
+; MIPS32-LABEL: returnFloatConst
+; MIPS32: lui v0,0x0 160: R_MIPS_HI16 .L$float$3f9d70a4
+; MIPS32: lwc1 $f0,0(v0) 164: R_MIPS_LO16 .L$float$3f9d70a4
+; MIPS32: jr ra
define internal double @returnDoubleConst() {
entry:
@@ -97,3 +141,7 @@
}
; CHECK-LABEL: returnDoubleConst
; CHECK: fld
+; MIPS32-LABEL: returnDoubleConst
+; MIPS32: lui v0,0x0 170: R_MIPS_HI16 .L$double$3ff3ae147ae147ae
+; MIPS32: ldc1 $f0,0(v0) 174: R_MIPS_LO16 .L$double$3ff3ae147ae147ae
+; MIPS32: jr ra
diff --git a/tests_lit/llvm2ice_tests/fused-alloca-arg.ll b/tests_lit/llvm2ice_tests/fused-alloca-arg.ll
index 1b009ba..7affa5d 100644
--- a/tests_lit/llvm2ice_tests/fused-alloca-arg.ll
+++ b/tests_lit/llvm2ice_tests/fused-alloca-arg.ll
@@ -4,6 +4,12 @@
; RUN: --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
; RUN: | %if --need=target_X8632 --command FileCheck %s
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
+; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
+; RUN: | %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command FileCheck --check-prefix MIPS32 %s
+
declare void @copy(i32 %arg1, i8* %arr1, i8* %arr2, i8* %arr3, i8* %arr4);
; Test that alloca base addresses get passed correctly to functions.
@@ -32,6 +38,21 @@
; CHECK-NEXT: call
; CHECK-NEXT: add esp,0x4c
; CHECK-NEXT: ret
+; MIPS32-LABEL: caller1
+; MIPS32: addiu sp,sp,{{.*}}
+; MIPS32: sw ra,{{.*}}(sp)
+; MIPS32: move v0,a0
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: addiu v0,sp,16
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: addiu a1,sp,16
+; MIPS32: addiu a2,sp,16
+; MIPS32: addiu a3,sp,16
+; MIPS32: jal
+; MIPS32: nop
+; MIPS32: lw ra,{{.*}}(sp)
+; MIPS32: addiu sp,sp,{{.*}}
+; MIPS32: jr ra
; Test that alloca base addresses get passed correctly to functions.
define internal void @caller2(i32 %arg) {
@@ -63,3 +84,20 @@
; CHECK-NEXT: call
; CHECK-NEXT: add esp,0x6c
; CHECK-NEXT: ret
+; MIPS32-LABEL: caller2
+; MIPS32: addiu sp,sp,{{.*}}
+; MIPS32: sw ra,{{.*}}(sp)
+; MIPS32: move v0,a0
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: move v0,a0
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: addiu v0,sp,48
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: addiu a1,sp,16
+; MIPS32: addiu a2,sp,48
+; MIPS32: addiu a3,sp,16
+; MIPS32: jal
+; MIPS32: nop
+; MIPS32: lw ra,{{.*}}(sp)
+; MIPS32: addiu sp,sp,{{.*}}
+; MIPS32: jr ra
diff --git a/tests_lit/llvm2ice_tests/fused-alloca.ll b/tests_lit/llvm2ice_tests/fused-alloca.ll
index 1b46305..6cc64fe 100644
--- a/tests_lit/llvm2ice_tests/fused-alloca.ll
+++ b/tests_lit/llvm2ice_tests/fused-alloca.ll
@@ -4,6 +4,12 @@
; RUN: --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
; RUN: | %if --need=target_X8632 --command FileCheck %s
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
+; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
+; RUN: | %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command FileCheck --check-prefix MIPS32 %s
+
; Test that a sequence of allocas with less than stack alignment get fused.
define internal void @fused_small_align(i32 %arg) {
entry:
@@ -25,6 +31,14 @@
; CHECK-NEXT: mov DWORD PTR [esp+0x18],eax
; CHECK-NEXT: mov DWORD PTR [esp],eax
; CHECK-NEXT: add esp,0x30
+; MIPS32-LABEL: fused_small_align
+; MIPS32: addiu sp,sp,{{.*}}
+; MIPS32: move v0,a0
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: move v0,a0
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: sw a0,{{.*}}(sp)
+; MIPS32: addiu sp,sp,{{.*}}
; Test that a sequence of allocas with greater than stack alignment get fused.
define internal void @fused_large_align(i32 %arg) {
@@ -51,6 +65,18 @@
; CHECK-NEXT: mov DWORD PTR [esp+0x60],eax
; CHECK-NEXT: mov esp,ebp
; CHECK-NEXT: pop ebp
+; MIPS32-LABEL: fused_large_align
+; MIPS32: addiu sp,sp,{{.*}}
+; MIPS32: sw s8,{{.*}}(sp)
+; MIPS32: move s8,sp
+; MIPS32: move v0,a0
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: move v0,a0
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: sw a0,{{.*}}(sp)
+; MIPS32: move sp,s8
+; MIPS32: lw s8,{{.*}}(sp)
+; MIPS32: addiu sp,sp,{{.*}}
; Test that an interior pointer into a rematerializable variable is also
; rematerializable, and test that it is detected even when the use appears
@@ -84,6 +110,14 @@
; CHECK-NEXT: lea eax,[esp+0x81]
; CHECK-NEXT: add esp,0x180
; CHECK-NEXT: ret
+; MIPS32-LABEL: fused_derived
+; MIPS32: addiu sp,sp,{{.*}}
+; MIPS32: b
+; MIPS32: move v0,a0
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: sw a0,{{.*}}(sp)
+; MIPS32: addiu v0,sp,129
+; MIPS32: addiu sp,sp,{{.*}}
; Test that a fixed alloca gets referenced by the frame pointer.
define internal void @fused_small_align_with_dynamic(i32 %arg) {
@@ -115,6 +149,20 @@
; CHECK-NEXT: mov DWORD PTR [edx],eax
; CHECK-NEXT: mov esp,ebp
; CHECK-NEXT: pop ebp
+; MIPS32-LABEL: fused_small_align_with_dynamic
+; MIPS32: addiu sp,sp,{{.*}}
+; MIPS32: sw s8,{{.*}}(sp)
+; MIPS32: move s8,sp
+; MIPS32: addiu v0,sp,0
+; MIPS32: addiu v1,sp,16
+; MIPS32: move a1,a0
+; MIPS32: sw a1,16(s8)
+; MIPS32: move a1,a0
+; MIPS32: sw a1,0(v0)
+; MIPS32: sw a0,0(v1)
+; MIPS32: move sp,s8
+; MIPS32: lw s8,{{.*}}(sp)
+; MIPS32: addiu sp,sp,{{.*}}
; Test that a sequence with greater than stack alignment and dynamic size
; get folded and referenced correctly;
@@ -161,3 +209,22 @@
; CHECK-NEXT: mov DWORD PTR [ebx],eax
; CHECK-NEXT: mov esp,ebp
; CHECK-NEXT: pop ebp
+; MIPS32-LABEL: fused_large_align_with_dynamic
+; MIPS32: addiu sp,sp,{{.*}}
+; MIPS32: sw s8,{{.*}}(sp)
+; MIPS32: move s8,sp
+; MIPS32: addiu v0,sp,0
+; MIPS32: addiu v1,sp,64
+; MIPS32: move a1,v0
+; MIPS32: move a2,a0
+; MIPS32: sw a2,0(a1)
+; MIPS32: move a1,a0
+; MIPS32: sw a1,32(v0)
+; MIPS32: move v0,a0
+; MIPS32: sw v0,64(s8)
+; MIPS32: move v0,a0
+; MIPS32: sw v0,48(s8)
+; MIPS32: sw a0,0(v1)
+; MIPS32: move sp,s8
+; MIPS32: lw s8,{{.*}}(sp)
+; MIPS32: addiu sp,sp,{{.*}}
diff --git a/tests_lit/llvm2ice_tests/globalinit.pnacl.ll b/tests_lit/llvm2ice_tests/globalinit.pnacl.ll
index b7ac1f6..4495eaa 100644
--- a/tests_lit/llvm2ice_tests/globalinit.pnacl.ll
+++ b/tests_lit/llvm2ice_tests/globalinit.pnacl.ll
@@ -44,6 +44,19 @@
; RUN: -allow-externally-defined-symbols \
; RUN: | %if --need=target_ARM32 --command FileCheck --check-prefix=SYMTAB %s
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
+; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
+; RUN: | %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command FileCheck --check-prefix=IASMIPS32 %s
+
+; RUN: %if --need=target_MIPS32 --need=allow_dump --command %p2i \
+; RUN: --filetype=asm --assemble --disassemble --dis-flags=-t \
+; RUN: --target mips32 -i %s --args --verbose none \
+; RUN: -allow-externally-defined-symbols \
+; RUN: | %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command FileCheck --check-prefix=SYMTAB %s
+
define internal i32 @main(i32 %argc, i32 %argv) {
entry:
%expanded1 = ptrtoint [4 x i8]* @PrimitiveInit to i32
@@ -84,6 +97,9 @@
; IASARM32: movw {{.*}} PrimitiveInit
; IASARM32: movt {{.*}} PrimitiveInit
; IASARM32: bl
+; IASMIPS32: lui {{.*}} PrimitiveInit
+; IASMIPS32: addiu {{.*}} PrimitiveInit
+; IASMIPS32: jal
; SYMTAB-DAG: 00000000 {{.*}} .rodata {{.*}} PrimitiveInitConst
; IAS: mov {{.*}},0x0 {{.*}} .rodata
@@ -91,6 +107,9 @@
; IASARM32: movw {{.*}} PrimitiveInitConst
; IASARM32: movt {{.*}} PrimitiveInitConst
; IASARM32: bl
+; IASMIPS32: lui {{.*}} PrimitiveInitConst
+; IASMIPS32: addiu {{.*}} PrimitiveInitConst
+; IASMIPS32: jal
; SYMTAB-DAG: 00000000 {{.*}} .bss {{.*}} PrimitiveInitStatic
; IAS: mov {{.*}},0x0 {{.*}} .bss
@@ -98,6 +117,9 @@
; IASARM32: movw {{.*}} PrimitiveInitStatic
; IASARM32: movt {{.*}} PrimitiveInitStatic
; IASARM32: bl
+; IASMIPS32: lui {{.*}} PrimitiveInitStatic
+; IASMIPS32: addiu {{.*}} PrimitiveInitStatic
+; IASMIPS32: jal
; SYMTAB-DAG: 00000004 {{.*}} .bss {{.*}} PrimitiveUninit
; IAS: mov {{.*}},0x4 {{.*}} .bss
@@ -105,6 +127,9 @@
; IASARM32: movw {{.*}} PrimitiveUninit
; IASARM32: movt {{.*}} PrimitiveUninit
; IASARM32: bl
+; IASMIPS32: lui {{.*}} PrimitiveUninit
+; IASMIPS32: addiu {{.*}} PrimitiveUninit
+; IASMIPS32: jal
; SYMTAB-DAG: 00000004{{.*}}.data{{.*}}ArrayInit
; IAS: mov {{.*}},0x4 {{.*}} .data
@@ -112,6 +137,9 @@
; IASARM32: movw {{.*}} ArrayInit
; IASARM32: movt {{.*}} ArrayInit
; IASARM32: bl
+; IASMIPS32: lui {{.*}} ArrayInit
+; IASMIPS32: addiu {{.*}} ArrayInit
+; IASMIPS32: jal
; SYMTAB-DAG: 00000018 {{.*}} .data {{.*}} ArrayInitPartial
; IAS: mov {{.*}},0x18 {{.*}} .data
@@ -119,6 +147,9 @@
; IASARM32: movw {{.*}} ArrayInitPartial
; IASARM32: movt {{.*}} ArrayInitPartial
; IASARM32: bl
+; IASMIPS32: lui {{.*}} ArrayInitPartial
+; IASMIPS32: addiu {{.*}} ArrayInitPartial
+; IASMIPS32: jal
; SYMTAB-DAG: 00000008 {{.*}} .bss {{.*}} ArrayUninit
; IAS: mov {{.*}},0x8 {{.*}} .bss
@@ -126,6 +157,9 @@
; IASARM32: movw {{.*}} ArrayUninit
; IASARM32: movt {{.*}} ArrayUninit
; IASARM32: bl
+; IASMIPS32: lui {{.*}} ArrayUninit
+; IASMIPS32: addiu {{.*}} ArrayUninit
+; IASMIPS32: jal
declare void @use(i32)
diff --git a/tests_lit/llvm2ice_tests/reorder-global-variables.ll b/tests_lit/llvm2ice_tests/reorder-global-variables.ll
index 64dbe7e..a1239b6 100644
--- a/tests_lit/llvm2ice_tests/reorder-global-variables.ll
+++ b/tests_lit/llvm2ice_tests/reorder-global-variables.ll
@@ -34,6 +34,11 @@
; RUN: -Om1 \
; RUN: | %if --need=target_ARM32 --command FileCheck %s
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
+; RUN: mips32 -i %s --dis-flags=-rD --args -O2 -sz-seed=1 \
+; RUN: -reorder-global-variables \
+; RUN: | %if --need=target_MIPS32 --need=allow_dump --command FileCheck %s
@PrimitiveInit = internal global [4 x i8] c"\1B\00\00\00", align 4
diff --git a/tests_lit/llvm2ice_tests/sdiv.ll b/tests_lit/llvm2ice_tests/sdiv.ll
index cac138e..4097a55 100644
--- a/tests_lit/llvm2ice_tests/sdiv.ll
+++ b/tests_lit/llvm2ice_tests/sdiv.ll
@@ -4,6 +4,12 @@
; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 | FileCheck %s
; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 | FileCheck %s
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
+; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
+; RUN: | %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command FileCheck --check-prefix MIPS32 %s
+
define internal i32 @sdiv_i8(i32 %a.i32, i32 %b.i32) {
entry:
%a = trunc i32 %a.i32 to i8
@@ -14,6 +20,11 @@
; CHECK-LABEL: sdiv_i8
; CHECK: cbw
; CHECK: idiv
+; MIPS32-LABEL: sdiv_i8
+; MIPS32: div
+; MIPS32: teq
+; MIPS32: mflo
+; MIPS32: andi {{.*}},0xff
}
define internal i32 @sdiv_i16(i32 %a.i32, i32 %b.i32) {
@@ -26,6 +37,11 @@
; CHECK-LABEL: sdiv_i16
; CHECK: cwd
; CHECK: idiv
+; MIPS32-LABEL: sdiv_i16
+; MIPS32: div
+; MIPS32: teq
+; MIPS32: mflo
+; MIPS32: andi {{.*}},0xffff
}
define internal i32 @sdiv_i32(i32 %a, i32 %b) {
@@ -35,6 +51,10 @@
; CHECK-LABEL: sdiv_i32
; CHECK: cdq
; CHECK: idiv
+; MIPS32-LABEL: sdiv_i32
+; MIPS32: div
+; MIPS32: teq
+; MIPS32: mflo
}
define internal i32 @srem_i8(i32 %a.i32, i32 %b.i32) {
@@ -47,6 +67,11 @@
; CHECK-LABEL: srem_i8
; CHECK: cbw
; CHECK: idiv
+; MIPS32-LABEL: srem_i8
+; MIPS32: div
+; MIPS32: teq
+; MIPS32: mfhi
+; MIPS32: andi {{.*}},0xff
}
define internal i32 @srem_i16(i32 %a.i32, i32 %b.i32) {
@@ -59,6 +84,11 @@
; CHECK-LABEL: srem_i16
; CHECK: cwd
; CHECK: idiv
+; MIPS32-LABEL: srem_i16
+; MIPS32: div
+; MIPS32: teq
+; MIPS32: mfhi
+; MIPS32: andi {{.*}},0xffff
}
define internal i32 @srem_i32(i32 %a, i32 %b) {
@@ -68,4 +98,8 @@
; CHECK-LABEL: srem_i32
; CHECK: cdq
; CHECK: idiv
+; MIPS32-LABEL: srem_i32
+; MIPS32: div
+; MIPS32: teq
+; MIPS32: mfhi
}
diff --git a/tests_lit/llvm2ice_tests/square.ll b/tests_lit/llvm2ice_tests/square.ll
index 137310a..08e7d67 100644
--- a/tests_lit/llvm2ice_tests/square.ll
+++ b/tests_lit/llvm2ice_tests/square.ll
@@ -9,6 +9,12 @@
; RUN: --target x8632 -i %s --args -Om1 -mattr=sse4.1 \
; RUN: | %if --need=target_X8632 --command FileCheck %s
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
+; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
+; RUN: | %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command FileCheck --check-prefix MIPS32 %s
+
define internal float @Square_float(float %a) {
entry:
%result = fmul float %a, %a
@@ -16,6 +22,9 @@
}
; CHECK-LABEL: Square_float
; CHECK: mulss [[REG:xmm.]],[[REG]]
+; MIPS32-LABEL: Square_float
+; MIPS32: mov.s
+; MIPS32: mul.s
define internal double @Square_double(double %a) {
entry:
@@ -24,6 +33,9 @@
}
; CHECK-LABEL: Square_double
; CHECK: mulsd [[REG:xmm.]],[[REG]]
+; MIPS32-LABEL: Square_double
+; MIPS32: mov.d
+; MIPS32: mul.d
define internal i32 @Square_i32(i32 %a) {
entry:
@@ -32,6 +44,9 @@
}
; CHECK-LABEL: Square_i32
; CHECK: imul [[REG:e..]],[[REG]]
+; MIPS32-LABEL: Square_i32
+; MIPS32: move
+; MIPS32: mul
define internal i32 @Square_i16(i32 %a) {
entry:
@@ -42,6 +57,11 @@
}
; CHECK-LABEL: Square_i16
; CHECK: imul [[REG:..]],[[REG]]
+; MIPS32-LABEL: Square_i16
+; MIPS32: move
+; MIPS32: mul
+; MIPS32: sll
+; MIPS32: sra
define internal i32 @Square_i8(i32 %a) {
entry:
@@ -52,6 +72,11 @@
}
; CHECK-LABEL: Square_i8
; CHECK: imul al
+; MIPS32-LABEL: Square_i8
+; MIPS32: move
+; MIPS32: mul
+; MIPS32: sll
+; MIPS32: sra
define internal <4 x float> @Square_v4f32(<4 x float> %a) {
entry:
diff --git a/tests_lit/llvm2ice_tests/test_i1.ll b/tests_lit/llvm2ice_tests/test_i1.ll
index 514d1ed..70558c5 100644
--- a/tests_lit/llvm2ice_tests/test_i1.ll
+++ b/tests_lit/llvm2ice_tests/test_i1.ll
@@ -15,6 +15,12 @@
; RUN: | %if --need=target_ARM32 --need=allow_dump \
; RUN: --command FileCheck --check-prefix ARM32 %s
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
+; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
+; RUN: | %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command FileCheck --check-prefix MIPS32 %s
+
; Test that and with true uses immediate 1, not -1.
define internal i32 @testAndTrue(i32 %arg) {
entry:
@@ -27,6 +33,9 @@
; CHECK: and {{.*}},0x1
; ARM32-LABEL: testAndTrue
; ARM32: and {{.*}}, #1
+; MIPS32-LABEL: testAndTrue
+; MIPS32: li [[REG:.*]],1
+; MIPS32: and {{.*}},[[REG]]
; Test that or with true uses immediate 1, not -1.
define internal i32 @testOrTrue(i32 %arg) {
@@ -40,6 +49,9 @@
; CHECK: or {{.*}},0x1
; ARM32-LABEL: testOrTrue
; ARM32: orr {{.*}}, #1
+; MIPS32-LABEL: testOrTrue
+; MIPS32: li [[REG:.*]],1
+; MIPS32: or {{.*}},[[REG]]
; Test that xor with true uses immediate 1, not -1.
define internal i32 @testXorTrue(i32 %arg) {
@@ -53,6 +65,9 @@
; CHECK: xor {{.*}},0x1
; ARM32-LABEL: testXorTrue
; ARM32: eor {{.*}}, #1
+; MIPS32-LABEL: testXorTrue
+; MIPS32: li [[REG:.*]],1
+; MIPS32: xor {{.*}},[[REG]]
; Test that trunc to i1 masks correctly.
define internal i32 @testTrunc(i32 %arg) {
@@ -65,6 +80,8 @@
; CHECK: and {{.*}},0x1
; ARM32-LABEL: testTrunc
; ARM32: and {{.*}}, #1
+; MIPS32-LABEL: testTrunc
+; MIPS32: andi {{.*}},0x1
; Test zext to i8.
define internal i32 @testZextI8(i32 %arg) {
@@ -82,6 +99,9 @@
; ARM32-LABEL: testZextI8
; ARM32: {{.*}}, #1
; ARM32: uxtb
+; MIPS32-LABEL: testZextI8
+; MIPS32: andi {{.*}},0x1
+; MIPS32: andi {{.*}},0xff
; Test zext to i16.
define internal i32 @testZextI16(i32 %arg) {
@@ -102,6 +122,10 @@
; ARM32: and {{.*}}, #1
; ARM32: uxth
+; MIPS32-LABEL: testZextI16
+; MIPS32: andi {{.*}},0x1
+; MIPS32: andi {{.*}},0xffff
+
; Test zext to i32.
define internal i32 @testZextI32(i32 %arg) {
entry:
@@ -117,6 +141,8 @@
; CHECK-NOT: and {{.*}},0x1
; ARM32-LABEL: testZextI32
; ARM32: and {{.*}}, #1
+; MIPS32-LABEL: testZextI32
+; MIPS32: andi {{.*}},0x1
; Test zext to i64.
define internal i64 @testZextI64(i32 %arg) {
@@ -134,6 +160,11 @@
; ARM32-LABEL: testZextI64
; ARM32: and {{.*}}, #1
; ARM32: mov {{.*}}, #0
+; MIPS32-LABEL: testZextI64
+; MIPS32: andi {{.*}},0x1
+; MIPS32: li {{.*}},0
+; MIPS32: move
+; MIPS32: move
; Test sext to i8.
define internal i32 @testSextI8(i32 %arg) {
@@ -156,6 +187,12 @@
; ARM32: mvn {{.*}}, #0
; ARM32: movne
; ARM32: sxtb
+;
+; MIPS32-LABEL: testSextI8
+; MIPS32: sll {{.*}},0x1f
+; MIPS32: sra {{.*}},0x1f
+; MIPS32: sll {{.*}},0x18
+; MIPS32: sra {{.*}},0x18
; Test sext to i16.
define internal i32 @testSextI16(i32 %arg) {
@@ -180,6 +217,12 @@
; ARM32: movne
; ARM32: sxth
+; MIPS32-LABEL: testSextI16
+; MIPS32: sll {{.*}},0x1f
+; MIPS32: sra {{.*}},0x1f
+; MIPS32: sll {{.*}},0x10
+; MIPS32: sra {{.*}},0x10
+
; Test sext to i32.
define internal i32 @testSextI32(i32 %arg) {
entry:
@@ -201,6 +244,10 @@
; ARM32: mvn {{.*}}, #0
; ARM32: movne
+; MIPS32-LABEL: testSextI32
+; MIPS32: sll {{.*}},0x1f
+; MIPS32: sra {{.*}},0x1f
+
; Test sext to i64.
define internal i64 @testSextI64(i32 %arg) {
entry:
@@ -223,6 +270,12 @@
; ARM32: movne [[REG:r[0-9]+]]
; ARM32: mov {{.*}}, [[REG]]
+; MIPS32-LABEL: testSextI64
+; MIPS32: sll {{.*}},0x1f
+; MIPS32: sra {{.*}},0x1f
+; MIPS32: move
+; MIPS32: move
+
; Kind of like sext i1 to i32, but with an immediate source. On ARM,
; sxtb cannot take an immediate operand, so make sure it's using a reg.
; If we had optimized constants, this could just be mov dst, 0xffffffff
@@ -240,6 +293,10 @@
; ARM32: tst {{.*}}, #1
; ARM32: mvn {{.*}}, #0
; ARM32: movne
+; MIPS32-LABEL: testSextTrue
+; MIPS32: li {{.*}},1
+; MIPS32: sll {{.*}},0x1f
+; MIPS32: sra {{.*}},0x1f
define internal i32 @testZextTrue() {
%result = zext i1 true to i32
@@ -251,6 +308,9 @@
; ARM32-LABEL: testZextTrue
; ARM32: mov{{.*}}, #1
; ARM32: and {{.*}}, #1
+; MIPS32-LABEL: testZextTrue
+; MIPS32: li {{.*}},1
+; MIPS32: andi {{.*}},0x1
; Test fptosi float to i1.
define internal i32 @testFptosiFloat(float %arg) {
@@ -265,6 +325,11 @@
; CHECK: movzx [[REG:.*]],
; CHECK-NEXT: shl [[REG]],0x1f
; CHECK-NEXT: sar [[REG]],0x1f
+; MIPS32-LABEL: testFptosiFloat
+; MIPS32: trunc.w.s
+; MIPS32: mfc1
+; MIPS32: sll {{.*}},0x1f
+; MIPS32: sra {{.*}},0x1f
; Test fptosi double to i1.
define internal i32 @testFptosiDouble(double %arg) {
@@ -279,3 +344,8 @@
; CHECK: movzx [[REG:.*]],
; CHECK-NEXT: shl [[REG]],0x1f
; CHECK-NEXT: sar [[REG]],0x1f
+; MIPS32-LABEL: testFptosiDouble
+; MIPS32: trunc.w.d
+; MIPS32: mfc1
+; MIPS32: sll {{.*}},0x1f
+; MIPS32: sra {{.*}},0x1f
diff --git a/tests_lit/llvm2ice_tests/vector-arg.ll b/tests_lit/llvm2ice_tests/vector-arg.ll
index 71224fd..64698d6 100644
--- a/tests_lit/llvm2ice_tests/vector-arg.ll
+++ b/tests_lit/llvm2ice_tests/vector-arg.ll
@@ -6,6 +6,12 @@
; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
; RUN: -allow-externally-defined-symbols | FileCheck --check-prefix=OPTM1 %s
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
+; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
+; RUN: | %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command FileCheck --check-prefix MIPS32 %s
+
; The first five functions test that vectors are moved from their
; correct argument location to xmm0.
@@ -22,6 +28,15 @@
; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm0
; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
; OPTM1: ret
+; MIPS32-LABEL: test_returning_arg0
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: lw v1,{{.*}}(sp)
+; MIPS32: move a1,a0
+; MIPS32: sw a2,0(a1)
+; MIPS32: sw a3,4(a1)
+; MIPS32: sw v0,8(a1)
+; MIPS32: sw v1,12(a1)
+; MIPS32: move v0,a0
}
define internal <4 x float> @test_returning_arg1(
@@ -37,6 +52,17 @@
; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm1
; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
; OPTM1: ret
+; MIPS32-LABEL: test_returning_arg1
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: lw v1,{{.*}}(sp)
+; MIPS32: lw a1,{{.*}}(sp)
+; MIPS32: lw a2,{{.*}}(sp)
+; MIPS32: move a3,a0
+; MIPS32: sw v0,0(a3)
+; MIPS32: sw v1,4(a3)
+; MIPS32: sw a1,8(a3)
+; MIPS32: sw a2,12(a3)
+; MIPS32: move v0,a0
}
define internal <4 x float> @test_returning_arg2(
@@ -52,6 +78,17 @@
; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm2
; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
; OPTM1: ret
+; MIPS32-LABEL: test_returning_arg2
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: lw v1,{{.*}}(sp)
+; MIPS32: lw a1,{{.*}}(sp)
+; MIPS32: lw a2,{{.*}}(sp)
+; MIPS32: move a3,a0
+; MIPS32: sw v0,0(a3)
+; MIPS32: sw v1,4(a3)
+; MIPS32: sw a1,8(a3)
+; MIPS32: sw a2,12(a3)
+; MIPS32: move v0,a0
}
define internal <4 x float> @test_returning_arg3(
@@ -67,6 +104,17 @@
; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm3
; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
; OPTM1: ret
+; MIPS32-LABEL: test_returning_arg3
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: lw v1,{{.*}}(sp)
+; MIPS32: lw a1,{{.*}}(sp)
+; MIPS32: lw a2,{{.*}}(sp)
+; MIPS32: move a3,a0
+; MIPS32: sw v0,0(a3)
+; MIPS32: sw v1,4(a3)
+; MIPS32: sw a1,8(a3)
+; MIPS32: sw a2,12(a3)
+; MIPS32: move v0,a0
}
define internal <4 x float> @test_returning_arg4(
@@ -81,6 +129,17 @@
; OPTM1-LABEL: test_returning_arg4
; OPTM1: movups xmm0,XMMWORD PTR {{.*}}
; OPTM1: ret
+; MIPS32-LABEL: test_returning_arg4
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: lw v1,{{.*}}(sp)
+; MIPS32: lw a1,{{.*}}(sp)
+; MIPS32: lw a2,{{.*}}(sp)
+; MIPS32: move a3,a0
+; MIPS32: sw v0,0(a3)
+; MIPS32: sw v1,4(a3)
+; MIPS32: sw a1,8(a3)
+; MIPS32: sw a2,12(a3)
+; MIPS32: move v0,a0
}
; The next five functions check that xmm arguments are handled
@@ -102,6 +161,17 @@
; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm0
; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
; OPTM1: ret
+; MIPS32-LABEL: test_returning_interspersed_arg0
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: lw v1,{{.*}}(sp)
+; MIPS32: lw a1,{{.*}}(sp)
+; MIPS32: lw a2,{{.*}}(sp)
+; MIPS32: move a3,a0
+; MIPS32: sw v0,0(a3)
+; MIPS32: sw v1,4(a3)
+; MIPS32: sw a1,8(a3)
+; MIPS32: sw a2,12(a3)
+; MIPS32: move v0,a0
}
define internal <4 x float> @test_returning_interspersed_arg1(
@@ -119,6 +189,17 @@
; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm1
; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
; OPTM1: ret
+; MIPS32-LABEL: test_returning_interspersed_arg1
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: lw v1,{{.*}}(sp)
+; MIPS32: lw a1,{{.*}}(sp)
+; MIPS32: lw a2,{{.*}}(sp)
+; MIPS32: move a3,a0
+; MIPS32: sw v0,0(a3)
+; MIPS32: sw v1,4(a3)
+; MIPS32: sw a1,8(a3)
+; MIPS32: sw a2,12(a3)
+; MIPS32: move v0,a0
}
define internal <4 x float> @test_returning_interspersed_arg2(
@@ -136,6 +217,17 @@
; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm2
; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
; OPTM1: ret
+; MIPS32-LABEL: test_returning_interspersed_arg2
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: lw v1,{{.*}}(sp)
+; MIPS32: lw a1,{{.*}}(sp)
+; MIPS32: lw a2,{{.*}}(sp)
+; MIPS32: move a3,a0
+; MIPS32: sw v0,0(a3)
+; MIPS32: sw v1,4(a3)
+; MIPS32: sw a1,8(a3)
+; MIPS32: sw a2,12(a3)
+; MIPS32: move v0,a0
}
define internal <4 x float> @test_returning_interspersed_arg3(
@@ -153,6 +245,18 @@
; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm3
; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
; OPTM1: ret
+; MIPS32-LABEL: test_returning_interspersed_arg3
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: lw v1,{{.*}}(sp)
+; MIPS32: lw a1,{{.*}}(sp)
+; MIPS32: lw a2,{{.*}}(sp)
+; MIPS32: move a3,a0
+; MIPS32: sw v0,0(a3)
+; MIPS32: sw v1,4(a3)
+; MIPS32: sw a1,8(a3)
+; MIPS32: sw a2,12(a3)
+; MIPS32: move v0,a0
+
}
define internal <4 x float> @test_returning_interspersed_arg4(
@@ -169,6 +273,17 @@
; OPTM1-LABEL: test_returning_interspersed_arg4
; OPTM1: movups xmm0,XMMWORD PTR {{.*}}
; OPTM1: ret
+; MIPS32-LABEL: test_returning_interspersed_arg4
+; MIPS32: lw v0,1{{.*}}(sp)
+; MIPS32: lw v1,1{{.*}}(sp)
+; MIPS32: lw a1,1{{.*}}(sp)
+; MIPS32: lw a2,1{{.*}}(sp)
+; MIPS32: move a3,a0
+; MIPS32: sw v0,0(a3)
+; MIPS32: sw v1,4(a3)
+; MIPS32: sw a1,8(a3)
+; MIPS32: sw a2,12(a3)
+; MIPS32: move v0,a0
}
; Test that vectors are passed correctly as arguments to a function.
@@ -214,6 +329,73 @@
; OPTM1: movups xmm3,XMMWORD PTR {{.*}}
; OPTM1: call {{.*}} R_{{.*}} VectorArgs
; OPTM1-NEXT: add esp,0x6c
+; MIPS32-LABEL: test_passing_vectors
+; MIPS32: sw s7,{{.*}}(sp)
+; MIPS32: sw s6,{{.*}}(sp)
+; MIPS32: sw s5,{{.*}}(sp)
+; MIPS32: sw s4,{{.*}}(sp)
+; MIPS32: sw s3,{{.*}}(sp)
+; MIPS32: sw s2,{{.*}}(sp)
+; MIPS32: sw s1,{{.*}}(sp)
+; MIPS32: sw s0,{{.*}}(sp)
+; MIPS32: lw s0,{{.*}}(sp)
+; MIPS32: lw s1,{{.*}}(sp)
+; MIPS32: lw s2,{{.*}}(sp)
+; MIPS32: lw s3,{{.*}}(sp)
+; MIPS32: lw s4,{{.*}}(sp)
+; MIPS32: lw s5,{{.*}}(sp)
+; MIPS32: lw s6,{{.*}}(sp)
+; MIPS32: lw s7,{{.*}}(sp)
+; MIPS32: jal 0 <test_returning_arg0> 228: R_MIPS_26 killXmmRegisters
+; MIPS32: nop
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: sw s4,{{.*}}(sp)
+; MIPS32: sw s5,{{.*}}(sp)
+; MIPS32: sw s6,{{.*}}(sp)
+; MIPS32: sw s7,{{.*}}(sp)
+; MIPS32: sw s0,{{.*}}(sp)
+; MIPS32: sw s1,{{.*}}(sp)
+; MIPS32: sw s2,{{.*}}(sp)
+; MIPS32: sw s3,{{.*}}(sp)
+; MIPS32: lw a0,{{.*}}(sp)
+; MIPS32: lw a1,{{.*}}(sp)
+; MIPS32: lw a2,{{.*}}(sp)
+; MIPS32: lw a3,{{.*}}(sp)
+; MIPS32: jal 0 <test_returning_arg0> 2c0: R_MIPS_26 VectorArgs
+; MIPS32: nop
+; MIPS32: lw s0,{{.*}}(sp)
+; MIPS32: lw s1,{{.*}}(sp)
+; MIPS32: lw s2,{{.*}}(sp)
+; MIPS32: lw s3,{{.*}}(sp)
+; MIPS32: lw s4,{{.*}}(sp)
+; MIPS32: lw s5,{{.*}}(sp)
+; MIPS32: lw s6,{{.*}}(sp)
+; MIPS32: lw s7,{{.*}}(sp)
+; MIPS32: lw ra,{{.*}}(sp)
+
}
declare void @InterspersedVectorArgs(
@@ -260,6 +442,88 @@
; OPTM1: call {{.*}} R_{{.*}} InterspersedVectorArgs
; OPTM1-NEXT: add esp,0x9c
; OPTM1: ret
+; MIPS32-LABEL: test_passing_vectors_interspersed
+; MIPS32: sw s7,{{.*}}(sp)
+; MIPS32: sw s6,{{.*}}(sp)
+; MIPS32: sw s5,{{.*}}(sp)
+; MIPS32: sw s4,{{.*}}(sp)
+; MIPS32: sw s3,{{.*}}(sp)
+; MIPS32: sw s2,{{.*}}(sp)
+; MIPS32: sw s1,{{.*}}(sp)
+; MIPS32: sw s0,{{.*}}(sp)
+; MIPS32: lw s0,{{.*}}(sp)
+; MIPS32: lw s1,{{.*}}(sp)
+; MIPS32: lw s2,{{.*}}(sp)
+; MIPS32: lw s3,{{.*}}(sp)
+; MIPS32: lw s4,{{.*}}(sp)
+; MIPS32: lw s5,{{.*}}(sp)
+; MIPS32: lw s6,{{.*}}(sp)
+; MIPS32: lw s7,{{.*}}(sp)
+; MIPS32: jal 0 <test_returning_arg0> 348: R_MIPS_26 killXmmRegisters
+; MIPS32: nop
+; MIPS32: li v0,0
+; MIPS32: li v1,0
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: sw v1,{{.*}}(sp)
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: li v0,0
+; MIPS32: li v1,1
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: sw v1,{{.*}}(sp)
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: lui v0,0x0 3b0: R_MIPS_HI16 .L$float$40000000
+; MIPS32: lwc1 $f0,0(v0) 3b4: R_MIPS_LO16 .L$float$40000000
+; MIPS32: swc1 $f0,{{.*}}(sp)
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: lw v0,{{.*}}(sp)
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: lui v0,0x0 3dc: R_MIPS_HI16 .L$double$4008000000000000
+; MIPS32: ldc1 $f0,0(v0) 3e0: R_MIPS_LO16 .L$double$4008000000000000
+; MIPS32: sdc1 $f0,{{.*}}(sp)
+; MIPS32: sw s4,{{.*}}(sp)
+; MIPS32: sw s5,{{.*}}(sp)
+; MIPS32: sw s6,{{.*}}(sp)
+; MIPS32: sw s7,{{.*}}(sp)
+; MIPS32: li v0,4
+; MIPS32: sw v0,{{.*}}(sp)
+; MIPS32: sw s0,{{.*}}(sp)
+; MIPS32: sw s1,{{.*}}(sp)
+; MIPS32: sw s2,{{.*}}(sp)
+; MIPS32: sw s3,{{.*}}(sp)
+; MIPS32: lw a0,{{.*}}(sp)
+; MIPS32: lw a1,{{.*}}(sp)
+; MIPS32: lw a2,{{.*}}(sp)
+; MIPS32: lw a3,{{.*}}(sp)
+; MIPS32: jal 0 <test_returning_arg0> 420: R_MIPS_26 InterspersedVectorArgs
+; MIPS32: nop
+; MIPS32: lw s0,{{.*}}(sp)
+; MIPS32: lw s1,{{.*}}(sp)
+; MIPS32: lw s2,{{.*}}(sp)
+; MIPS32: lw s3,{{.*}}(sp)
+; MIPS32: lw s4,{{.*}}(sp)
+; MIPS32: lw s5,{{.*}}(sp)
+; MIPS32: lw s6,{{.*}}(sp)
+; MIPS32: lw s7,{{.*}}(sp)
+; MIPS32: lw ra,{{.*}}(sp)
}
; Test that a vector returned from a function is recognized to be in
@@ -284,4 +548,33 @@
; OPTM1: movups xmm0,{{.*}}
; OPTM1: call {{.*}} R_{{.*}} VectorReturn
; OPTM1: ret
+; MIPS32-LABEL: test_receiving_vectors
+; MIPS32: sw s8,{{.*}}(sp)
+; MIPS32: sw s0,{{.*}}(sp)
+; MIPS32: move s8,sp
+; MIPS32: move v0,a0
+; MIPS32: addiu v1,sp,16
+; MIPS32: move s0,v1
+; MIPS32: move a0,s0
+; MIPS32: sw a2,{{.*}}(sp)
+; MIPS32: sw a3,{{.*}}(sp)
+; MIPS32: move a2,v0
+; MIPS32: move a3,a1
+; MIPS32: jal 0 <test_returning_arg0> 494: R_MIPS_26 VectorReturn
+; MIPS32: nop
+; MIPS32: lw v0,0(s0)
+; MIPS32: lw v1,4(s0)
+; MIPS32: lw a1,8(s0)
+; MIPS32: lw s0,12(s0)
+; MIPS32: addiu a0,sp,32
+; MIPS32: sw a1,{{.*}}(sp)
+; MIPS32: sw s0,{{.*}}(sp)
+; MIPS32: move a2,v0
+; MIPS32: move a3,v1
+; MIPS32: jal 0 <test_returning_arg0> 4c0: R_MIPS_26 VectorReturn
+; MIPS32: nop
+; MIPS32: move sp,s8
+; MIPS32: lw s0,{{.*}}(sp)
+; MIPS32: lw s8,{{.*}}(sp)
+; MIPS32: lw ra,{{.*}}(sp)
}
diff --git a/tests_lit/llvm2ice_tests/vector-arith.ll b/tests_lit/llvm2ice_tests/vector-arith.ll
index abf09e2..a1b3126 100644
--- a/tests_lit/llvm2ice_tests/vector-arith.ll
+++ b/tests_lit/llvm2ice_tests/vector-arith.ll
@@ -9,12 +9,23 @@
; RUN: %p2i -i %s --filetype=obj --disassemble -a -Om1 -mattr=sse4.1 \
; RUN: | FileCheck --check-prefix=SSE41 %s
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
+; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
+; RUN: | %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command FileCheck --check-prefix MIPS32 %s
+
define internal <4 x float> @test_fadd(<4 x float> %arg0, <4 x float> %arg1) {
entry:
%res = fadd <4 x float> %arg0, %arg1
ret <4 x float> %res
; CHECK-LABEL: test_fadd
; CHECK: addps
+; MIPS32-LABEL: test_fadd
+; MIPS32: add.s
+; MIPS32: add.s
+; MIPS32: add.s
+; MIPS32: add.s
}
define internal <4 x float> @test_fsub(<4 x float> %arg0, <4 x float> %arg1) {
@@ -23,6 +34,11 @@
ret <4 x float> %res
; CHECK-LABEL: test_fsub
; CHECK: subps
+; MIPS32-LABEL: test_fsub
+; MIPS32: sub.s
+; MIPS32: sub.s
+; MIPS32: sub.s
+; MIPS32: sub.s
}
define internal <4 x float> @test_fmul(<4 x float> %arg0, <4 x float> %arg1) {
@@ -31,6 +47,11 @@
ret <4 x float> %res
; CHECK-LABEL: test_fmul
; CHECK: mulps
+; MIPS32-LABEL: test_fmul
+; MIPS32: mul.s
+; MIPS32: mul.s
+; MIPS32: mul.s
+; MIPS32: mul.s
}
define internal <4 x float> @test_fdiv(<4 x float> %arg0, <4 x float> %arg1) {
@@ -39,6 +60,11 @@
ret <4 x float> %res
; CHECK-LABEL: test_fdiv
; CHECK: divps
+; MIPS32-LABEL: test_fdiv
+; MIPS32: div.s
+; MIPS32: div.s
+; MIPS32: div.s
+; MIPS32: div.s
}
define internal <4 x float> @test_frem(<4 x float> %arg0, <4 x float> %arg1) {
@@ -58,6 +84,23 @@
ret <16 x i8> %res
; CHECK-LABEL: test_add_v16i8
; CHECK: paddb
+; MIPS32-LABEL: test_add_v16i8
+; MIPS32: addu
+; MIPS32: addu
+; MIPS32: addu
+; MIPS32: addu
+; MIPS32: addu
+; MIPS32: addu
+; MIPS32: addu
+; MIPS32: addu
+; MIPS32: addu
+; MIPS32: addu
+; MIPS32: addu
+; MIPS32: addu
+; MIPS32: addu
+; MIPS32: addu
+; MIPS32: addu
+; MIPS32: addu
}
define internal <16 x i8> @test_and_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
@@ -66,6 +109,23 @@
ret <16 x i8> %res
; CHECK-LABEL: test_and_v16i8
; CHECK: pand
+; MIPS32-LABEL: test_and_v16i8
+; MIPS32: and
+; MIPS32: and
+; MIPS32: and
+; MIPS32: and
+; MIPS32: and
+; MIPS32: and
+; MIPS32: and
+; MIPS32: and
+; MIPS32: and
+; MIPS32: and
+; MIPS32: and
+; MIPS32: and
+; MIPS32: and
+; MIPS32: and
+; MIPS32: and
+; MIPS32: and
}
define internal <16 x i8> @test_or_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
@@ -74,6 +134,23 @@
ret <16 x i8> %res
; CHECK-LABEL: test_or_v16i8
; CHECK: por
+; MIPS32-LABEL: test_or_v16i8
+; MIPS32: or
+; MIPS32: or
+; MIPS32: or
+; MIPS32: or
+; MIPS32: or
+; MIPS32: or
+; MIPS32: or
+; MIPS32: or
+; MIPS32: or
+; MIPS32: or
+; MIPS32: or
+; MIPS32: or
+; MIPS32: or
+; MIPS32: or
+; MIPS32: or
+; MIPS32: or
}
define internal <16 x i8> @test_xor_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
@@ -82,6 +159,23 @@
ret <16 x i8> %res
; CHECK-LABEL: test_xor_v16i8
; CHECK: pxor
+; MIPS32-LABEL: test_xor_v16i8
+; MIPS32: xor
+; MIPS32: xor
+; MIPS32: xor
+; MIPS32: xor
+; MIPS32: xor
+; MIPS32: xor
+; MIPS32: xor
+; MIPS32: xor
+; MIPS32: xor
+; MIPS32: xor
+; MIPS32: xor
+; MIPS32: xor
+; MIPS32: xor
+; MIPS32: xor
+; MIPS32: xor
+; MIPS32: xor
}
define internal <16 x i8> @test_sub_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
@@ -90,6 +184,23 @@
ret <16 x i8> %res
; CHECK-LABEL: test_sub_v16i8
; CHECK: psubb
+; MIPS32-LABEL: test_sub_v16i8
+; MIPS32: subu
+; MIPS32: subu
+; MIPS32: subu
+; MIPS32: subu
+; MIPS32: subu
+; MIPS32: subu
+; MIPS32: subu
+; MIPS32: subu
+; MIPS32: subu
+; MIPS32: subu
+; MIPS32: subu
+; MIPS32: subu
+; MIPS32: subu
+; MIPS32: subu
+; MIPS32: subu
+; MIPS32: subu
}
define internal <16 x i8> @test_mul_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
@@ -113,6 +224,23 @@
; CHECK: imul
; CHECK: imul
; CHECK: imul
+; MIPS32-LABEL: test_mul_v16i8
+; MIPS32: mul
+; MIPS32: mul
+; MIPS32: mul
+; MIPS32: mul
+; MIPS32: mul
+; MIPS32: mul
+; MIPS32: mul
+; MIPS32: mul
+; MIPS32: mul
+; MIPS32: mul
+; MIPS32: mul
+; MIPS32: mul
+; MIPS32: mul
+; MIPS32: mul
+; MIPS32: mul
+; MIPS32: mul
}
define internal <16 x i8> @test_shl_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
@@ -136,6 +264,23 @@
; CHECK: shl
; CHECK: shl
; CHECK: shl
+; MIPS32-LABEL: test_shl_v16i8
+; MIPS32: sllv
+; MIPS32: sllv
+; MIPS32: sllv
+; MIPS32: sllv
+; MIPS32: sllv
+; MIPS32: sllv
+; MIPS32: sllv
+; MIPS32: sllv
+; MIPS32: sllv
+; MIPS32: sllv
+; MIPS32: sllv
+; MIPS32: sllv
+; MIPS32: sllv
+; MIPS32: sllv
+; MIPS32: sllv
+; MIPS32: sllv
}
define internal <16 x i8> @test_lshr_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
@@ -159,6 +304,23 @@
; CHECK: shr
; CHECK: shr
; CHECK: shr
+; MIPS32-LABEL: test_lshr_v16i8
+; MIPS32: srlv
+; MIPS32: srlv
+; MIPS32: srlv
+; MIPS32: srlv
+; MIPS32: srlv
+; MIPS32: srlv
+; MIPS32: srlv
+; MIPS32: srlv
+; MIPS32: srlv
+; MIPS32: srlv
+; MIPS32: srlv
+; MIPS32: srlv
+; MIPS32: srlv
+; MIPS32: srlv
+; MIPS32: srlv
+; MIPS32: srlv
}
define internal <16 x i8> @test_ashr_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
@@ -182,6 +344,23 @@
; CHECK: sar
; CHECK: sar
; CHECK: sar
+; MIPS32-LABEL: test_ashr_v16i8
+; MIPS32: srav
+; MIPS32: srav
+; MIPS32: srav
+; MIPS32: srav
+; MIPS32: srav
+; MIPS32: srav
+; MIPS32: srav
+; MIPS32: srav
+; MIPS32: srav
+; MIPS32: srav
+; MIPS32: srav
+; MIPS32: srav
+; MIPS32: srav
+; MIPS32: srav
+; MIPS32: srav
+; MIPS32: srav
}
define internal <16 x i8> @test_udiv_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
@@ -205,6 +384,23 @@
; CHECK: div
; CHECK: div
; CHECK: div
+; MIPS32-LABEL: test_udiv_v16i8
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
}
define internal <16 x i8> @test_sdiv_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
@@ -228,6 +424,23 @@
; CHECK: idiv
; CHECK: idiv
; CHECK: idiv
+; MIPS32-LABEL: test_sdiv_v16i8
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
}
define internal <16 x i8> @test_urem_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
@@ -251,6 +464,23 @@
; CHECK: div
; CHECK: div
; CHECK: div
+; MIPS32-LABEL: test_urem_v16i8
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
}
define internal <16 x i8> @test_srem_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
@@ -274,6 +504,23 @@
; CHECK: idiv
; CHECK: idiv
; CHECK: idiv
+; MIPS32-LABEL: test_srem_v16i8
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
}
define internal <8 x i16> @test_add_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
@@ -282,6 +529,15 @@
ret <8 x i16> %res
; CHECK-LABEL: test_add_v8i16
; CHECK: paddw
+; MIPS32-LABEL: test_add_v8i16
+; MIPS32: addu
+; MIPS32: addu
+; MIPS32: addu
+; MIPS32: addu
+; MIPS32: addu
+; MIPS32: addu
+; MIPS32: addu
+; MIPS32: addu
}
define internal <8 x i16> @test_and_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
@@ -290,6 +546,15 @@
ret <8 x i16> %res
; CHECK-LABEL: test_and_v8i16
; CHECK: pand
+; MIPS32-LABEL: test_and_v8i16
+; MIPS32: andi
+; MIPS32: andi
+; MIPS32: andi
+; MIPS32: andi
+; MIPS32: andi
+; MIPS32: andi
+; MIPS32: andi
+; MIPS32: andi
}
define internal <8 x i16> @test_or_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
@@ -298,6 +563,15 @@
ret <8 x i16> %res
; CHECK-LABEL: test_or_v8i16
; CHECK: por
+; MIPS32-LABEL: test_or_v8i16
+; MIPS32: or
+; MIPS32: or
+; MIPS32: or
+; MIPS32: or
+; MIPS32: or
+; MIPS32: or
+; MIPS32: or
+; MIPS32: or
}
define internal <8 x i16> @test_xor_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
@@ -306,6 +580,15 @@
ret <8 x i16> %res
; CHECK-LABEL: test_xor_v8i16
; CHECK: pxor
+; MIPS32-LABEL: test_xor_v8i16
+; MIPS32: xor
+; MIPS32: xor
+; MIPS32: xor
+; MIPS32: xor
+; MIPS32: xor
+; MIPS32: xor
+; MIPS32: xor
+; MIPS32: xor
}
define internal <8 x i16> @test_sub_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
@@ -314,6 +597,15 @@
ret <8 x i16> %res
; CHECK-LABEL: test_sub_v8i16
; CHECK: psubw
+; MIPS32-LABEL: test_sub_v8i16
+; MIPS32: subu
+; MIPS32: subu
+; MIPS32: subu
+; MIPS32: subu
+; MIPS32: subu
+; MIPS32: subu
+; MIPS32: subu
+; MIPS32: subu
}
define internal <8 x i16> @test_mul_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
@@ -322,6 +614,15 @@
ret <8 x i16> %res
; CHECK-LABEL: test_mul_v8i16
; CHECK: pmullw
+; MIPS32-LABEL: test_mul_v8i16
+; MIPS32: mul
+; MIPS32: mul
+; MIPS32: mul
+; MIPS32: mul
+; MIPS32: mul
+; MIPS32: mul
+; MIPS32: mul
+; MIPS32: mul
}
define internal <8 x i16> @test_shl_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
@@ -337,6 +638,15 @@
; CHECK: shl
; CHECK: shl
; CHECK: shl
+; MIPS32-LABEL: test_shl_v8i16
+; MIPS32: sllv
+; MIPS32: sllv
+; MIPS32: sllv
+; MIPS32: sllv
+; MIPS32: sllv
+; MIPS32: sllv
+; MIPS32: sllv
+; MIPS32: sllv
}
define internal <8 x i16> @test_lshr_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
@@ -352,6 +662,15 @@
; CHECK: shr
; CHECK: shr
; CHECK: shr
+; MIPS32-LABEL: test_lshr_v8i16
+; MIPS32: srlv
+; MIPS32: srlv
+; MIPS32: srlv
+; MIPS32: srlv
+; MIPS32: srlv
+; MIPS32: srlv
+; MIPS32: srlv
+; MIPS32: srlv
}
define internal <8 x i16> @test_ashr_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
@@ -367,6 +686,15 @@
; CHECK: sar
; CHECK: sar
; CHECK: sar
+; MIPS32-LABEL: test_ashr_v8i16
+; MIPS32: srav
+; MIPS32: srav
+; MIPS32: srav
+; MIPS32: srav
+; MIPS32: srav
+; MIPS32: srav
+; MIPS32: srav
+; MIPS32: srav
}
define internal <8 x i16> @test_udiv_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
@@ -382,6 +710,15 @@
; CHECK: div
; CHECK: div
; CHECK: div
+; MIPS32-LABEL: test_udiv_v8i16
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
}
define internal <8 x i16> @test_sdiv_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
@@ -397,6 +734,15 @@
; CHECK: idiv
; CHECK: idiv
; CHECK: idiv
+; MIPS32-LABEL: test_sdiv_v8i16
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
}
define internal <8 x i16> @test_urem_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
@@ -412,6 +758,15 @@
; CHECK: div
; CHECK: div
; CHECK: div
+; MIPS32-LABEL: test_urem_v8i16
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
}
define internal <8 x i16> @test_srem_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
@@ -427,6 +782,15 @@
; CHECK: idiv
; CHECK: idiv
; CHECK: idiv
+; MIPS32-LABEL: test_srem_v8i16
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
}
define internal <4 x i32> @test_add_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
@@ -435,6 +799,11 @@
ret <4 x i32> %res
; CHECK-LABEL: test_add_v4i32
; CHECK: paddd
+; MIPS32-LABEL: test_add_v4i32
+; MIPS32: addu
+; MIPS32: addu
+; MIPS32: addu
+; MIPS32: addu
}
define internal <4 x i32> @test_and_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
@@ -443,6 +812,11 @@
ret <4 x i32> %res
; CHECK-LABEL: test_and_v4i32
; CHECK: pand
+; MIPS32-LABEL: test_and_v4i32
+; MIPS32: and
+; MIPS32: and
+; MIPS32: and
+; MIPS32: and
}
define internal <4 x i32> @test_or_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
@@ -451,6 +825,11 @@
ret <4 x i32> %res
; CHECK-LABEL: test_or_v4i32
; CHECK: por
+; MIPS32-LABEL: test_or_v4i32
+; MIPS32: or
+; MIPS32: or
+; MIPS32: or
+; MIPS32: or
}
define internal <4 x i32> @test_xor_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
@@ -459,6 +838,11 @@
ret <4 x i32> %res
; CHECK-LABEL: test_xor_v4i32
; CHECK: pxor
+; MIPS32-LABEL: test_xor_v4i32
+; MIPS32: xor
+; MIPS32: xor
+; MIPS32: xor
+; MIPS32: xor
}
define internal <4 x i32> @test_sub_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
@@ -467,6 +851,11 @@
ret <4 x i32> %res
; CHECK-LABEL: test_sub_v4i32
; CHECK: psubd
+; MIPS32-LABEL: test_sub_v4i32
+; MIPS32: subu
+; MIPS32: subu
+; MIPS32: subu
+; MIPS32: subu
}
define internal <4 x i32> @test_mul_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
@@ -479,6 +868,11 @@
;
; SSE41-LABEL: test_mul_v4i32
; SSE41: pmulld
+; MIPS32-LABEL: test_mul_v4i32
+; MIPS32: mul
+; MIPS32: mul
+; MIPS32: mul
+; MIPS32: mul
}
define internal <4 x i32> @test_shl_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
@@ -493,6 +887,11 @@
; This line is to ensure that pmulld is generated in test_mul_v4i32 above.
; SSE41-LABEL: test_shl_v4i32
+; MIPS32-LABEL: test_shl_v4i32
+; MIPS32: sllv
+; MIPS32: sllv
+; MIPS32: sllv
+; MIPS32: sllv
}
define internal <4 x i32> @test_lshr_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
@@ -504,6 +903,11 @@
; CHECK: shr
; CHECK: shr
; CHECK: shr
+; MIPS32-LABEL: test_lshr_v4i32
+; MIPS32: srlv
+; MIPS32: srlv
+; MIPS32: srlv
+; MIPS32: srlv
}
define internal <4 x i32> @test_ashr_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
@@ -515,6 +919,11 @@
; CHECK: sar
; CHECK: sar
; CHECK: sar
+; MIPS32-LABEL: test_ashr_v4i32
+; MIPS32: srav
+; MIPS32: srav
+; MIPS32: srav
+; MIPS32: srav
}
define internal <4 x i32> @test_udiv_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
@@ -526,6 +935,11 @@
; CHECK: div
; CHECK: div
; CHECK: div
+; MIPS32-LABEL: test_udiv_v4i32
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
}
define internal <4 x i32> @test_sdiv_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
@@ -537,6 +951,11 @@
; CHECK: idiv
; CHECK: idiv
; CHECK: idiv
+; MIPS32-LABEL: test_sdiv_v4i32
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
}
define internal <4 x i32> @test_urem_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
@@ -548,6 +967,11 @@
; CHECK: div
; CHECK: div
; CHECK: div
+; MIPS32-LABEL: test_urem_v4i32
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
+; MIPS32: divu
}
define internal <4 x i32> @test_srem_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
@@ -559,4 +983,9 @@
; CHECK: idiv
; CHECK: idiv
; CHECK: idiv
+; MIPS32-LABEL: test_srem_v4i32
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
+; MIPS32: div
}
diff --git a/tests_lit/llvm2ice_tests/vector-cast.ll b/tests_lit/llvm2ice_tests/vector-cast.ll
index 30d6674..a987d8c 100644
--- a/tests_lit/llvm2ice_tests/vector-cast.ll
+++ b/tests_lit/llvm2ice_tests/vector-cast.ll
@@ -11,6 +11,12 @@
; RUN: %p2i -i %s --target=arm32 --filetype=obj --disassemble --args -Om1 \
; RUN: | FileCheck %s --check-prefix=ARM32 --check-prefix=CHECK
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
+; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
+; RUN: | %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command FileCheck --check-prefix MIPS32 %s
+
; sext operations
define internal <16 x i8> @test_sext_v16i1_to_v16i8(<16 x i1> %arg) {
@@ -27,6 +33,158 @@
; X8632: pcmpgtb
; ARM32: vshl.s8
; ARM32-NEXT: vshr.s8
+; MIPS32: andi t2,a0,0xff
+; MIPS32: andi t2,t2,0x1
+; MIPS32: sll t2,t2,0x1f
+; MIPS32: sra t2,t2,0x1f
+; MIPS32: andi t2,t2,0xff
+; MIPS32: srl v0,v0,0x8
+; MIPS32: sll v0,v0,0x8
+; MIPS32: or t2,t2,v0
+; MIPS32: srl v0,a0,0x8
+; MIPS32: andi v0,v0,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: sll v0,v0,0x1f
+; MIPS32: sra v0,v0,0x1f
+; MIPS32: andi v0,v0,0xff
+; MIPS32: sll v0,v0,0x8
+; MIPS32: lui t3,0xffff
+; MIPS32: ori t3,t3,0xff
+; MIPS32: and t2,t2,t3
+; MIPS32: or v0,v0,t2
+; MIPS32: srl t2,a0,0x10
+; MIPS32: andi t2,t2,0xff
+; MIPS32: andi t2,t2,0x1
+; MIPS32: sll t2,t2,0x1f
+; MIPS32: sra t2,t2,0x1f
+; MIPS32: andi t2,t2,0xff
+; MIPS32: sll t2,t2,0x10
+; MIPS32: lui t3,0xff00
+; MIPS32: ori t3,t3,0xffff
+; MIPS32: and v0,v0,t3
+; MIPS32: or t2,t2,v0
+; MIPS32: srl a0,a0,0x18
+; MIPS32: andi a0,a0,0x1
+; MIPS32: sll a0,a0,0x1f
+; MIPS32: sra a0,a0,0x1f
+; MIPS32: srl a0,a0,0x18
+; MIPS32: sll t2,t2,0x8
+; MIPS32: srl t2,t2,0x8
+; MIPS32: or a0,a0,t2
+; MIPS32: andi v0,a1,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: sll v0,v0,0x1f
+; MIPS32: sra v0,v0,0x1f
+; MIPS32: andi v0,v0,0xff
+; MIPS32: srl v1,v1,0x8
+; MIPS32: sll v1,v1,0x8
+; MIPS32: or v0,v0,v1
+; MIPS32: srl v1,a1,0x8
+; MIPS32: andi v1,v1,0xff
+; MIPS32: andi v1,v1,0x1
+; MIPS32: sll v1,v1,0x1f
+; MIPS32: sra v1,v1,0x1f
+; MIPS32: andi v1,v1,0xff
+; MIPS32: sll v1,v1,0x8
+; MIPS32: lui t2,0xffff
+; MIPS32: ori t2,t2,0xff
+; MIPS32: and v0,v0,t2
+; MIPS32: or v1,v1,v0
+; MIPS32: srl v0,a1,0x10
+; MIPS32: andi v0,v0,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: sll v0,v0,0x1f
+; MIPS32: sra v0,v0,0x1f
+; MIPS32: andi v0,v0,0xff
+; MIPS32: sll v0,v0,0x10
+; MIPS32: lui t2,0xff00
+; MIPS32: ori t2,t2,0xffff
+; MIPS32: and v1,v1,t2
+; MIPS32: or v0,v0,v1
+; MIPS32: srl a1,a1,0x18
+; MIPS32: andi a1,a1,0x1
+; MIPS32: sll a1,a1,0x1f
+; MIPS32: sra a1,a1,0x1f
+; MIPS32: srl a1,a1,0x18
+; MIPS32: sll v0,v0,0x8
+; MIPS32: srl v0,v0,0x8
+; MIPS32: or a1,a1,v0
+; MIPS32: andi v0,a2,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: sll v0,v0,0x1f
+; MIPS32: sra v0,v0,0x1f
+; MIPS32: andi v0,v0,0xff
+; MIPS32: srl t0,t0,0x8
+; MIPS32: sll t0,t0,0x8
+; MIPS32: or v0,v0,t0
+; MIPS32: srl v1,a2,0x8
+; MIPS32: andi v1,v1,0xff
+; MIPS32: andi v1,v1,0x1
+; MIPS32: sll v1,v1,0x1f
+; MIPS32: sra v1,v1,0x1f
+; MIPS32: andi v1,v1,0xff
+; MIPS32: sll v1,v1,0x8
+; MIPS32: lui t0,0xffff
+; MIPS32: ori t0,t0,0xff
+; MIPS32: and v0,v0,t0
+; MIPS32: or v1,v1,v0
+; MIPS32: srl v0,a2,0x10
+; MIPS32: andi v0,v0,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: sll v0,v0,0x1f
+; MIPS32: sra v0,v0,0x1f
+; MIPS32: andi v0,v0,0xff
+; MIPS32: sll v0,v0,0x10
+; MIPS32: lui t0,0xff00
+; MIPS32: ori t0,t0,0xffff
+; MIPS32: and v1,v1,t0
+; MIPS32: or v0,v0,v1
+; MIPS32: srl a2,a2,0x18
+; MIPS32: andi a2,a2,0x1
+; MIPS32: sll a2,a2,0x1f
+; MIPS32: sra a2,a2,0x1f
+; MIPS32: srl a2,a2,0x18
+; MIPS32: sll v0,v0,0x8
+; MIPS32: srl v0,v0,0x8
+; MIPS32: or a2,a2,v0
+; MIPS32: andi v0,a3,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: sll v0,v0,0x1f
+; MIPS32: sra v0,v0,0x1f
+; MIPS32: andi v0,v0,0xff
+; MIPS32: srl t1,t1,0x8
+; MIPS32: sll t1,t1,0x8
+; MIPS32: or v0,v0,t1
+; MIPS32: srl v1,a3,0x8
+; MIPS32: andi v1,v1,0xff
+; MIPS32: andi v1,v1,0x1
+; MIPS32: sll v1,v1,0x1f
+; MIPS32: sra v1,v1,0x1f
+; MIPS32: andi v1,v1,0xff
+; MIPS32: sll v1,v1,0x8
+; MIPS32: lui t0,0xffff
+; MIPS32: ori t0,t0,0xff
+; MIPS32: and v0,v0,t0
+; MIPS32: or v1,v1,v0
+; MIPS32: srl v0,a3,0x10
+; MIPS32: andi v0,v0,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: sll v0,v0,0x1f
+; MIPS32: sra v0,v0,0x1f
+; MIPS32: andi v0,v0,0xff
+; MIPS32: sll v0,v0,0x10
+; MIPS32: lui t0,0xff00
+; MIPS32: ori t0,t0,0xffff
+; MIPS32: and v1,v1,t0
+; MIPS32: or v0,v0,v1
+; MIPS32: srl a3,a3,0x18
+; MIPS32: andi a3,a3,0x1
+; MIPS32: sll a3,a3,0x1f
+; MIPS32: sra a3,a3,0x1f
+; MIPS32: srl a3,a3,0x18
+; MIPS32: sll v0,v0,0x8
+; MIPS32: srl v0,v0,0x8
+; MIPS32: or a3,a3,v0
}
define internal <8 x i16> @test_sext_v8i1_to_v8i16(<8 x i1> %arg) {
@@ -39,6 +197,74 @@
; X8632: psraw {{.*}},0xf
; ARM32: vshl.s16
; ARM32-NEXT: vshr.s16
+; MIPS32: move v0,zero
+; MIPS32: move v1,zero
+; MIPS32: move t0,zero
+; MIPS32: move t1,zero
+; MIPS32: andi t2,a0,0xffff
+; MIPS32: andi t2,t2,0x1
+; MIPS32: sll t2,t2,0x1f
+; MIPS32: sra t2,t2,0x1f
+; MIPS32: andi t2,t2,0xffff
+; MIPS32: srl v0,v0,0x10
+; MIPS32: sll v0,v0,0x10
+; MIPS32: or t2,t2,v0
+; MIPS32: srl a0,a0,0x10
+; MIPS32: andi a0,a0,0x1
+; MIPS32: sll a0,a0,0x1f
+; MIPS32: sra a0,a0,0x1f
+; MIPS32: sll a0,a0,0x10
+; MIPS32: sll t2,t2,0x10
+; MIPS32: srl t2,t2,0x10
+; MIPS32: or a0,a0,t2
+; MIPS32: andi v0,a1,0xffff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: sll v0,v0,0x1f
+; MIPS32: sra v0,v0,0x1f
+; MIPS32: andi v0,v0,0xffff
+; MIPS32: srl v1,v1,0x10
+; MIPS32: sll v1,v1,0x10
+; MIPS32: or v0,v0,v1
+; MIPS32: srl a1,a1,0x10
+; MIPS32: andi a1,a1,0x1
+; MIPS32: sll a1,a1,0x1f
+; MIPS32: sra a1,a1,0x1f
+; MIPS32: sll a1,a1,0x10
+; MIPS32: sll v0,v0,0x10
+; MIPS32: srl v0,v0,0x10
+; MIPS32: or a1,a1,v0
+; MIPS32: andi v0,a2,0xffff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: sll v0,v0,0x1f
+; MIPS32: sra v0,v0,0x1f
+; MIPS32: andi v0,v0,0xffff
+; MIPS32: srl t0,t0,0x10
+; MIPS32: sll t0,t0,0x10
+; MIPS32: or v0,v0,t0
+; MIPS32: srl a2,a2,0x10
+; MIPS32: andi a2,a2,0x1
+; MIPS32: sll a2,a2,0x1f
+; MIPS32: sra a2,a2,0x1f
+; MIPS32: sll a2,a2,0x10
+; MIPS32: sll v0,v0,0x10
+; MIPS32: srl v0,v0,0x10
+; MIPS32: or a2,a2,v0
+; MIPS32: andi v0,a3,0xffff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: sll v0,v0,0x1f
+; MIPS32: sra v0,v0,0x1f
+; MIPS32: andi v0,v0,0xffff
+; MIPS32: srl t1,t1,0x10
+; MIPS32: sll t1,t1,0x10
+; MIPS32: or v0,v0,t1
+; MIPS32: srl a3,a3,0x10
+; MIPS32: andi a3,a3,0x1
+; MIPS32: sll a3,a3,0x1f
+; MIPS32: sra a3,a3,0x1f
+; MIPS32: sll a3,a3,0x10
+; MIPS32: sll v0,v0,0x10
+; MIPS32: srl v0,v0,0x10
+; MIPS32: or a3,a3,v0
}
define internal <4 x i32> @test_sext_v4i1_to_v4i32(<4 x i1> %arg) {
@@ -51,6 +277,18 @@
; X8632: psrad {{.*}},0x1f
; ARM32: vshl.s32
; ARM32-NEXT: vshr.s32
+; MIPS32: andi a0,a0,0x1
+; MIPS32: sll a0,a0,0x1f
+; MIPS32: sra a0,a0,0x1f
+; MIPS32: andi a1,a1,0x1
+; MIPS32: sll a1,a1,0x1f
+; MIPS32: sra a1,a1,0x1f
+; MIPS32: andi a2,a2,0x1
+; MIPS32: sll a2,a2,0x1f
+; MIPS32: sra a2,a2,0x1f
+; MIPS32: andi a3,a3,0x1
+; MIPS32: sll a3,a3,0x1f
+; MIPS32: sra a3,a3,0x1f
}
; zext operations
@@ -67,6 +305,142 @@
; X8632: pand
; ARM32: vmov.i8 [[S:.*]], #1
; ARM32-NEXT: vand {{.*}}, [[S]]
+; MIPS32: andi t2,a0,0xff
+; MIPS32: andi t2,t2,0x1
+; MIPS32: andi t2,t2,0x1
+; MIPS32: andi t2,t2,0xff
+; MIPS32: srl v0,v0,0x8
+; MIPS32: sll v0,v0,0x8
+; MIPS32: or t2,t2,v0
+; MIPS32: srl v0,a0,0x8
+; MIPS32: andi v0,v0,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0xff
+; MIPS32: sll v0,v0,0x8
+; MIPS32: lui t3,0xffff
+; MIPS32: ori t3,t3,0xff
+; MIPS32: and t2,t2,t3
+; MIPS32: or v0,v0,t2
+; MIPS32: srl t2,a0,0x10
+; MIPS32: andi t2,t2,0xff
+; MIPS32: andi t2,t2,0x1
+; MIPS32: andi t2,t2,0x1
+; MIPS32: andi t2,t2,0xff
+; MIPS32: sll t2,t2,0x10
+; MIPS32: lui t3,0xff00
+; MIPS32: ori t3,t3,0xffff
+; MIPS32: and v0,v0,t3
+; MIPS32: or t2,t2,v0
+; MIPS32: srl a0,a0,0x18
+; MIPS32: andi a0,a0,0x1
+; MIPS32: andi a0,a0,0x1
+; MIPS32: srl a0,a0,0x18
+; MIPS32: sll t2,t2,0x8
+; MIPS32: srl t2,t2,0x8
+; MIPS32: or a0,a0,t2
+; MIPS32: andi v0,a1,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0xff
+; MIPS32: srl v1,v1,0x8
+; MIPS32: sll v1,v1,0x8
+; MIPS32: or v0,v0,v1
+; MIPS32: srl v1,a1,0x8
+; MIPS32: andi v1,v1,0xff
+; MIPS32: andi v1,v1,0x1
+; MIPS32: andi v1,v1,0x1
+; MIPS32: andi v1,v1,0xff
+; MIPS32: sll v1,v1,0x8
+; MIPS32: lui t2,0xffff
+; MIPS32: ori t2,t2,0xff
+; MIPS32: and v0,v0,t2
+; MIPS32: or v1,v1,v0
+; MIPS32: srl v0,a1,0x10
+; MIPS32: andi v0,v0,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0xff
+; MIPS32: sll v0,v0,0x10
+; MIPS32: lui t2,0xff00
+; MIPS32: ori t2,t2,0xffff
+; MIPS32: and v1,v1,t2
+; MIPS32: or v0,v0,v1
+; MIPS32: srl a1,a1,0x18
+; MIPS32: andi a1,a1,0x1
+; MIPS32: andi a1,a1,0x1
+; MIPS32: srl a1,a1,0x18
+; MIPS32: sll v0,v0,0x8
+; MIPS32: srl v0,v0,0x8
+; MIPS32: or a1,a1,v0
+; MIPS32: andi v0,a2,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0xff
+; MIPS32: srl t0,t0,0x8
+; MIPS32: sll t0,t0,0x8
+; MIPS32: or v0,v0,t0
+; MIPS32: srl v1,a2,0x8
+; MIPS32: andi v1,v1,0xff
+; MIPS32: andi v1,v1,0x1
+; MIPS32: andi v1,v1,0x1
+; MIPS32: andi v1,v1,0xff
+; MIPS32: sll v1,v1,0x8
+; MIPS32: lui t0,0xffff
+; MIPS32: ori t0,t0,0xff
+; MIPS32: and v0,v0,t0
+; MIPS32: or v1,v1,v0
+; MIPS32: srl v0,a2,0x10
+; MIPS32: andi v0,v0,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0xff
+; MIPS32: sll v0,v0,0x10
+; MIPS32: lui t0,0xff00
+; MIPS32: ori t0,t0,0xffff
+; MIPS32: and v1,v1,t0
+; MIPS32: or v0,v0,v1
+; MIPS32: srl a2,a2,0x18
+; MIPS32: andi a2,a2,0x1
+; MIPS32: andi a2,a2,0x1
+; MIPS32: srl a2,a2,0x18
+; MIPS32: sll v0,v0,0x8
+; MIPS32: srl v0,v0,0x8
+; MIPS32: or a2,a2,v0
+; MIPS32: andi v0,a3,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0xff
+; MIPS32: srl t1,t1,0x8
+; MIPS32: sll t1,t1,0x8
+; MIPS32: or v0,v0,t1
+; MIPS32: srl v1,a3,0x8
+; MIPS32: andi v1,v1,0xff
+; MIPS32: andi v1,v1,0x1
+; MIPS32: andi v1,v1,0x1
+; MIPS32: andi v1,v1,0xff
+; MIPS32: sll v1,v1,0x8
+; MIPS32: lui t0,0xffff
+; MIPS32: ori t0,t0,0xff
+; MIPS32: and v0,v0,t0
+; MIPS32: or v1,v1,v0
+; MIPS32: srl v0,a3,0x10
+; MIPS32: andi v0,v0,0xff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0xff
+; MIPS32: sll v0,v0,0x10
+; MIPS32: lui t0,0xff00
+; MIPS32: ori t0,t0,0xffff
+; MIPS32: and v1,v1,t0
+; MIPS32: or v0,v0,v1
+; MIPS32: srl a3,a3,0x18
+; MIPS32: andi a3,a3,0x1
+; MIPS32: andi a3,a3,0x1
+; MIPS32: srl a3,a3,0x18
+; MIPS32: sll v0,v0,0x8
+; MIPS32: srl v0,v0,0x8
+; MIPS32: or a3,a3,v0
}
define internal <8 x i16> @test_zext_v8i1_to_v8i16(<8 x i1> %arg) {
@@ -81,6 +455,62 @@
; X8632: pand
; ARM32: vmov.i16 [[S:.*]], #1
; ARM32-NEXT: vand {{.*}}, [[S]]
+; MIPS32: andi t2,a0,0xffff
+; MIPS32: andi t2,t2,0x1
+; MIPS32: andi t2,t2,0x1
+; MIPS32: andi t2,t2,0xffff
+; MIPS32: srl v0,v0,0x10
+; MIPS32: sll v0,v0,0x10
+; MIPS32: or t2,t2,v0
+; MIPS32: srl a0,a0,0x10
+; MIPS32: andi a0,a0,0x1
+; MIPS32: andi a0,a0,0x1
+; MIPS32: sll a0,a0,0x10
+; MIPS32: sll t2,t2,0x10
+; MIPS32: srl t2,t2,0x10
+; MIPS32: or a0,a0,t2
+; MIPS32: andi v0,a1,0xffff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0xffff
+; MIPS32: srl v1,v1,0x10
+; MIPS32: sll v1,v1,0x10
+; MIPS32: or v0,v0,v1
+; MIPS32: srl a1,a1,0x10
+; MIPS32: andi a1,a1,0x1
+; MIPS32: andi a1,a1,0x1
+; MIPS32: sll a1,a1,0x10
+; MIPS32: sll v0,v0,0x10
+; MIPS32: srl v0,v0,0x10
+; MIPS32: or a1,a1,v0
+; MIPS32: andi v0,a2,0xffff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0xffff
+; MIPS32: srl t0,t0,0x10
+; MIPS32: sll t0,t0,0x10
+; MIPS32: or v0,v0,t0
+; MIPS32: srl a2,a2,0x10
+; MIPS32: andi a2,a2,0x1
+; MIPS32: andi a2,a2,0x1
+; MIPS32: sll a2,a2,0x10
+; MIPS32: sll v0,v0,0x10
+; MIPS32: srl v0,v0,0x10
+; MIPS32: or a2,a2,v0
+; MIPS32: andi v0,a3,0xffff
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0x1
+; MIPS32: andi v0,v0,0xffff
+; MIPS32: srl t1,t1,0x10
+; MIPS32: sll t1,t1,0x10
+; MIPS32: or v0,v0,t1
+; MIPS32: srl a3,a3,0x10
+; MIPS32: andi a3,a3,0x1
+; MIPS32: andi a3,a3,0x1
+; MIPS32: sll a3,a3,0x10
+; MIPS32: sll v0,v0,0x10
+; MIPS32: srl v0,v0,0x10
+; MIPS32: or a3,a3,v0
}
define internal <4 x i32> @test_zext_v4i1_to_v4i32(<4 x i1> %arg) {
@@ -95,6 +525,14 @@
; X8632: pand
; ARM32: vmov.i32 [[S:.*]], #1
; ARM32-NEXT: vand {{.*}}, [[S]]
+; MIPS32: andi a0,a0,0x1
+; MIPS32: andi a0,a0,0x1
+; MIPS32: andi a1,a1,0x1
+; MIPS32: andi a1,a1,0x1
+; MIPS32: andi a2,a2,0x1
+; MIPS32: andi a2,a2,0x1
+; MIPS32: andi a3,a3,0x1
+; MIPS32: andi a3,a3,0x1
}
; trunc operations
@@ -109,6 +547,110 @@
; X8632: pcmpeqb
; X8632: psubb
; X8632: pand
+; MIPS32: andi t2,a0,0xff
+; MIPS32: andi t2,t2,0xff
+; MIPS32: srl v0,v0,0x8
+; MIPS32: sll v0,v0,0x8
+; MIPS32: or t2,t2,v0
+; MIPS32: srl v0,a0,0x8
+; MIPS32: andi v0,v0,0xff
+; MIPS32: andi v0,v0,0xff
+; MIPS32: sll v0,v0,0x8
+; MIPS32: lui t3,0xffff
+; MIPS32: ori t3,t3,0xff
+; MIPS32: and t2,t2,t3
+; MIPS32: or v0,v0,t2
+; MIPS32: srl t2,a0,0x10
+; MIPS32: andi t2,t2,0xff
+; MIPS32: andi t2,t2,0xff
+; MIPS32: sll t2,t2,0x10
+; MIPS32: lui t3,0xff00
+; MIPS32: ori t3,t3,0xffff
+; MIPS32: and v0,v0,t3
+; MIPS32: or t2,t2,v0
+; MIPS32: srl a0,a0,0x18
+; MIPS32: srl a0,a0,0x18
+; MIPS32: sll t2,t2,0x8
+; MIPS32: srl t2,t2,0x8
+; MIPS32: or a0,a0,t2
+; MIPS32: andi v0,a1,0xff
+; MIPS32: andi v0,v0,0xff
+; MIPS32: srl v1,v1,0x8
+; MIPS32: sll v1,v1,0x8
+; MIPS32: or v0,v0,v1
+; MIPS32: srl v1,a1,0x8
+; MIPS32: andi v1,v1,0xff
+; MIPS32: andi v1,v1,0xff
+; MIPS32: sll v1,v1,0x8
+; MIPS32: lui t2,0xffff
+; MIPS32: ori t2,t2,0xff
+; MIPS32: and v0,v0,t2
+; MIPS32: or v1,v1,v0
+; MIPS32: srl v0,a1,0x10
+; MIPS32: andi v0,v0,0xff
+; MIPS32: andi v0,v0,0xff
+; MIPS32: sll v0,v0,0x10
+; MIPS32: lui t2,0xff00
+; MIPS32: ori t2,t2,0xffff
+; MIPS32: and v1,v1,t2
+; MIPS32: or v0,v0,v1
+; MIPS32: srl a1,a1,0x18
+; MIPS32: srl a1,a1,0x18
+; MIPS32: sll v0,v0,0x8
+; MIPS32: srl v0,v0,0x8
+; MIPS32: or a1,a1,v0
+; MIPS32: andi v0,a2,0xff
+; MIPS32: andi v0,v0,0xff
+; MIPS32: srl t0,t0,0x8
+; MIPS32: sll t0,t0,0x8
+; MIPS32: or v0,v0,t0
+; MIPS32: srl v1,a2,0x8
+; MIPS32: andi v1,v1,0xff
+; MIPS32: andi v1,v1,0xff
+; MIPS32: sll v1,v1,0x8
+; MIPS32: lui t0,0xffff
+; MIPS32: ori t0,t0,0xff
+; MIPS32: and v0,v0,t0
+; MIPS32: or v1,v1,v0
+; MIPS32: srl v0,a2,0x10
+; MIPS32: andi v0,v0,0xff
+; MIPS32: andi v0,v0,0xff
+; MIPS32: sll v0,v0,0x10
+; MIPS32: lui t0,0xff00
+; MIPS32: ori t0,t0,0xffff
+; MIPS32: and v1,v1,t0
+; MIPS32: or v0,v0,v1
+; MIPS32: srl a2,a2,0x18
+; MIPS32: srl a2,a2,0x18
+; MIPS32: sll v0,v0,0x8
+; MIPS32: srl v0,v0,0x8
+; MIPS32: or a2,a2,v0
+; MIPS32: andi v0,a3,0xff
+; MIPS32: andi v0,v0,0xff
+; MIPS32: srl t1,t1,0x8
+; MIPS32: sll t1,t1,0x8
+; MIPS32: or v0,v0,t1
+; MIPS32: srl v1,a3,0x8
+; MIPS32: andi v1,v1,0xff
+; MIPS32: andi v1,v1,0xff
+; MIPS32: sll v1,v1,0x8
+; MIPS32: lui t0,0xffff
+; MIPS32: ori t0,t0,0xff
+; MIPS32: and v0,v0,t0
+; MIPS32: or v1,v1,v0
+; MIPS32: srl v0,a3,0x10
+; MIPS32: andi v0,v0,0xff
+; MIPS32: andi v0,v0,0xff
+; MIPS32: sll v0,v0,0x10
+; MIPS32: lui t0,0xff00
+; MIPS32: ori t0,t0,0xffff
+; MIPS32: and v1,v1,t0
+; MIPS32: or v0,v0,v1
+; MIPS32: srl a3,a3,0x18
+; MIPS32: srl a3,a3,0x18
+; MIPS32: sll v0,v0,0x8
+; MIPS32: srl v0,v0,0x8
+; MIPS32: or a3,a3,v0
}
define internal <8 x i1> @test_trunc_v8i16_to_v8i1(<8 x i16> %arg) {
@@ -121,6 +663,46 @@
; X8632: pcmpeqw
; X8632: psubw
; X8632: pand
+; MIPS32: andi t2,a0,0xffff
+; MIPS32: andi t2,t2,0xffff
+; MIPS32: srl v0,v0,0x10
+; MIPS32: sll v0,v0,0x10
+; MIPS32: or t2,t2,v0
+; MIPS32: srl a0,a0,0x10
+; MIPS32: sll a0,a0,0x10
+; MIPS32: sll t2,t2,0x10
+; MIPS32: srl t2,t2,0x10
+; MIPS32: or a0,a0,t2
+; MIPS32: andi v0,a1,0xffff
+; MIPS32: andi v0,v0,0xffff
+; MIPS32: srl v1,v1,0x10
+; MIPS32: sll v1,v1,0x10
+; MIPS32: or v0,v0,v1
+; MIPS32: srl a1,a1,0x10
+; MIPS32: sll a1,a1,0x10
+; MIPS32: sll v0,v0,0x10
+; MIPS32: srl v0,v0,0x10
+; MIPS32: or a1,a1,v0
+; MIPS32: andi v0,a2,0xffff
+; MIPS32: andi v0,v0,0xffff
+; MIPS32: srl t0,t0,0x10
+; MIPS32: sll t0,t0,0x10
+; MIPS32: or v0,v0,t0
+; MIPS32: srl a2,a2,0x10
+; MIPS32: sll a2,a2,0x10
+; MIPS32: sll v0,v0,0x10
+; MIPS32: srl v0,v0,0x10
+; MIPS32: or a2,a2,v0
+; MIPS32: andi v0,a3,0xffff
+; MIPS32: andi v0,v0,0xffff
+; MIPS32: srl t1,t1,0x10
+; MIPS32: sll t1,t1,0x10
+; MIPS32: or v0,v0,t1
+; MIPS32: srl a3,a3,0x10
+; MIPS32: sll a3,a3,0x10
+; MIPS32: sll v0,v0,0x10
+; MIPS32: srl v0,v0,0x10
+; MIPS32: or a3,a3,v0
}
define internal <4 x i1> @test_trunc_v4i32_to_v4i1(<4 x i32> %arg) {
@@ -133,6 +715,10 @@
; X8632: pcmpeqd
; X8632: psubd
; X8632: pand
+; MIPS32: move v0,a0
+; MIPS32: move v1,a1
+; MIPS32: move a0,a2
+; MIPS32: move a1,a3
}
; fpto[us]i operations
@@ -145,6 +731,10 @@
; CHECK-LABEL: test_fptosi_v4f32_to_v4i32
; X8632: cvttps2dq
; ARM32: vcvt.s32.f32
+; MIPS32: trunc.w.s $f0,$f0
+; MIPS32: trunc.w.s $f0,$f0
+; MIPS32: trunc.w.s $f0,$f0
+; MIPS32: trunc.w.s $f0,$f0
}
define internal <4 x i32> @test_fptoui_v4f32_to_v4i32(<4 x float> %arg) {
@@ -155,6 +745,10 @@
; CHECK-LABEL: test_fptoui_v4f32_to_v4i32
; X8632: call {{.*}} R_{{.*}} __Sz_fptoui_4xi32_f32
; ARM32: vcvt.u32.f32
+; MIPS32: trunc.w.s $f0,$f0
+; MIPS32: trunc.w.s $f0,$f0
+; MIPS32: trunc.w.s $f0,$f0
+; MIPS32: trunc.w.s $f0,$f0
}
; [su]itofp operations
@@ -167,6 +761,11 @@
; CHECK-LABEL: test_sitofp_v4i32_to_v4f32
; X8632: cvtdq2ps
; ARM32: vcvt.f32.s32
+; MIPS32: cvt.s.w $f0,$f0
+; MIPS32: cvt.s.w $f0,$f0
+; MIPS32: cvt.s.w $f0,$f0
+; MIPS32: cvt.s.w $f0,$f0
+
}
define internal <4 x float> @test_uitofp_v4i32_to_v4f32(<4 x i32> %arg) {
@@ -177,4 +776,8 @@
; CHECK-LABEL: test_uitofp_v4i32_to_v4f32
; X8632: call {{.*}} R_{{.*}} __Sz_uitofp_4xi32_4xf32
; ARM32: vcvt.f32.u32
+; MIPS32: cvt.s.w $f0,$f0
+; MIPS32: cvt.s.w $f0,$f0
+; MIPS32: cvt.s.w $f0,$f0
+; MIPS32: cvt.s.w $f0,$f0
}
diff --git a/tests_lit/llvm2ice_tests/vector-shuffle.ll b/tests_lit/llvm2ice_tests/vector-shuffle.ll
index 62fbc9d..e0fa157 100644
--- a/tests_lit/llvm2ice_tests/vector-shuffle.ll
+++ b/tests_lit/llvm2ice_tests/vector-shuffle.ll
@@ -5,6 +5,12 @@
; RUN: %p2i -i %s --target=x8632 --filetype=obj --disassemble -a -O2 \
; RUN: --allow-externally-defined-symbols | FileCheck %s --check-prefix=X86
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
+; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
+; RUN: | %if --need=target_MIPS32 --need=allow_dump \
+; RUN: --command FileCheck --check-prefix MIPS32 %s
+
declare void @useV4I32(<4 x i32> %t);
define internal void @shuffleV4I32(<4 x i32> %a, <4 x i32> %b) {
@@ -51,3 +57,19 @@
ret void
}
+; MIPS32-LABEL: shuffleV4I32
+; MIPS32: move
+; MIPS32: move
+; MIPS32: move
+; MIPS32: move
+; MIPS32: jal
+; MIPS32: move
+; MIPS32: move
+; MIPS32: move
+; MIPS32: move
+; MIPS32: jal
+; MIPS32: move
+; MIPS32: move
+; MIPS32: move
+; MIPS32: move
+; MIPS32: jal
