ARM32 vector xor
BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4076
R=kschimpf@google.com
Review URL: https://codereview.chromium.org/1640933002 .
diff --git a/src/IceInstARM32.cpp b/src/IceInstARM32.cpp
index aa6f00f..8eca8cf 100644
--- a/src/IceInstARM32.cpp
+++ b/src/IceInstARM32.cpp
@@ -647,6 +647,11 @@
template <> void InstARM32Veor::emitIAS(const Cfg *Func) const {
auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
const Variable *Dest = getDest();
+ if (isVectorType(Dest->getType())) {
+ // TODO(kschimpf): Add support for this case
+ emitUsingTextFixup(Func);
+ return;
+ }
assert(Dest->getType() == IceType_f64);
Asm->veord(Dest, getSrc(0), getSrc(1));
assert(!Asm->needsTextFixup());
diff --git a/src/IceTargetLoweringARM32.cpp b/src/IceTargetLoweringARM32.cpp
index 4b2dc98..10e1dbe 100644
--- a/src/IceTargetLoweringARM32.cpp
+++ b/src/IceTargetLoweringARM32.cpp
@@ -2809,6 +2809,7 @@
case InstArithmetic::Sub:
case InstArithmetic::And:
case InstArithmetic::Or:
+ case InstArithmetic::Xor:
break;
}
}
@@ -2981,8 +2982,13 @@
}
case InstArithmetic::Xor: {
Variable *Src0R = Srcs.src0R(this);
- Operand *Src1RF = Srcs.src1RF(this);
- _eor(T, Src0R, Src1RF);
+ if (isVectorType(DestTy)) {
+ Variable *Src1R = legalizeToReg(Src1);
+ _veor(T, Src0R, Src1R);
+ } else {
+ Operand *Src1RF = Srcs.src1RF(this);
+ _eor(T, Src0R, Src1RF);
+ }
_mov(Dest, T);
return;
}
diff --git a/tests_lit/assembler/arm32/xor-vec.ll b/tests_lit/assembler/arm32/xor-vec.ll
new file mode 100644
index 0000000..668d5de
--- /dev/null
+++ b/tests_lit/assembler/arm32/xor-vec.ll
@@ -0,0 +1,115 @@
+; Show that we know how to translate veor vector instructions.
+
+; REQUIRES: allow_dump
+
+; Compile using standalone assembler.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
+; RUN: | FileCheck %s --check-prefix=ASM
+
+; Show bytes in assembled standalone code.
+; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
+; RUN: --args -O2 \
+; RUN: | FileCheck %s --check-prefix=DIS
+
+; Compile using integrated assembler.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
+; RUN: | FileCheck %s --check-prefix=IASM
+
+; Show bytes in assembled integrated code.
+; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
+; RUN: --args -O2 \
+; RUN: | FileCheck %s --check-prefix=DIS
+
+define internal <4 x i32> @testVxor4i32(<4 x i32> %v1, <4 x i32> %v2) {
+; ASM-LABEL: testVxor4i32:
+; DIS-LABEL: 00000000 <testVxor4i32>:
+; IASM-LABEL: testVxor4i32:
+
+entry:
+ %res = xor <4 x i32> %v1, %v2
+
+; ASM: veor.i32 q0, q0, q1
+; DIS: 0: f3000152
+; IASM: veor.i32
+
+ ret <4 x i32> %res
+}
+
+define internal <8 x i16> @testVxor8i16(<8 x i16> %v1, <8 x i16> %v2) {
+; ASM-LABEL: testVxor8i16:
+; DIS-LABEL: 00000010 <testVxor8i16>:
+; IASM-LABEL: testVxor8i16:
+
+entry:
+ %res = xor <8 x i16> %v1, %v2
+
+; ASM: veor.i16 q0, q0, q1
+; DIS: 10: f3000152
+; IASM: veor.i16
+
+ ret <8 x i16> %res
+}
+
+define internal <16 x i8> @testVxor16i8(<16 x i8> %v1, <16 x i8> %v2) {
+; ASM-LABEL: testVxor16i8:
+; DIS-LABEL: 00000020 <testVxor16i8>:
+; IASM-LABEL: testVxor16i8:
+
+entry:
+ %res = xor <16 x i8> %v1, %v2
+
+; ASM: veor.i8 q0, q0, q1
+; DIS: 20: f3000152
+; IASM: veor.i8
+
+ ret <16 x i8> %res
+}
+
+;;
+;; The following tests make sure logical xor works on predicate vectors.
+;;
+
+define internal <4 x i1> @testVxor4i1(<4 x i1> %v1, <4 x i1> %v2) {
+; ASM-LABEL: testVxor4i1:
+; DIS-LABEL: 00000030 <testVxor4i1>:
+; IASM-LABEL: testVxor4i1:
+
+entry:
+ %res = xor <4 x i1> %v1, %v2
+
+; ASM: veor.i32 q0, q0, q1
+; DIS: 30: f3000152
+; IASM: veor.i32
+
+ ret <4 x i1> %res
+}
+
+define internal <8 x i1> @testVxor8i1(<8 x i1> %v1, <8 x i1> %v2) {
+; ASM-LABEL: testVxor8i1:
+; DIS-LABEL: 00000040 <testVxor8i1>:
+; IASM-LABEL: testVxor8i1:
+
+entry:
+ %res = xor <8 x i1> %v1, %v2
+
+; ASM: veor.i16 q0, q0, q1
+; DIS: 40: f3000152
+; IASM: veor.i16
+
+ ret <8 x i1> %res
+}
+
+define internal <16 x i1> @testVxor16i1(<16 x i1> %v1, <16 x i1> %v2) {
+; ASM-LABEL: testVxor16i1:
+; DIS-LABEL: 00000050 <testVxor16i1>:
+; IASM-LABEL: testVxor16i1:
+
+entry:
+ %res = xor <16 x i1> %v1, %v2
+
+; ASM: veor.i8 q0, q0, q1
+; DIS: 50: f3000152
+; IASM: veor.i8
+
+ ret <16 x i1> %res
+}
