commit 71f6c8deb228ebf7fa586c6252d917b14bf54f98
author Jaydeep Patil <jaydeep.patil@imgtec.com> Fri Feb 10 06:45:40 2017 -0800
committer Jim Stichnoth <stichnot@chromium.org> Fri Feb 10 06:45:40 2017 -0800
tree cbc7a1972b919c021cc817bd3b395ba11615682b
parent c48bb8b02c98ae49438e43aa1143a958784822a5

[SubZero] Generate spin-lock for atomic load store

The patch generates LL-SC sequence for atomic load store operations.
64-bit atomic operations are lowered to __sync_*_8 functions.

R=stichnot@chromium.org

Patch from Jaydeep Patil <jaydeep.patil@imgtec.com>.

Review-Url: https://codereview.chromium.org/2682673002 .

src/IceTargetLoweringMIPS32.h

diff --git a/src/IceTargetLoweringMIPS32.h b/src/IceTargetLoweringMIPS32.h
index 1695f50..710e8e7 100644
--- a/src/IceTargetLoweringMIPS32.h
+++ b/src/IceTargetLoweringMIPS32.h
@@ -787,6 +787,7 @@
   void lowerStore(const InstStore *Instr) override;
   void lowerSwitch(const InstSwitch *Instr) override;
   void lowerUnreachable(const InstUnreachable *Instr) override;
+  void lowerOther(const Inst *Instr) override;
   void prelowerPhis() override;
   uint32_t getCallStackArgumentsSizeBytes(const InstCall *Instr) override;
   void genTargetHelperCallFor(Inst *Instr) override;