[SubZero] Generate spin-lock for atomic load store
The patch generates LL-SC sequence for atomic load store operations.
64-bit atomic operations are lowered to __sync_*_8 functions.
R=stichnot@chromium.org
Patch from Jaydeep Patil <jaydeep.patil@imgtec.com>.
Review-Url: https://codereview.chromium.org/2682673002 .
diff --git a/runtime/szrt.c b/runtime/szrt.c
index 7ac5030..ff0f9b0 100644
--- a/runtime/szrt.c
+++ b/runtime/szrt.c
@@ -64,3 +64,11 @@
// unsandboxed_irt:
// __nacl_read_tp
// __aeabi_read_tp [arm32 only]
+// MIPS runtime library:
+// __sync_fetch_and_add_8
+// __sync_fetch_and_and_8
+// __sync_fetch_and_or_8
+// __sync_fetch_and_sub_8
+// __sync_fetch_and_xor_8
+// __sync_lock_test_and_set_8
+// __sync_val_compare_and_swap_8
