commit 6e992147f2f4c99a8fd574e6a154b97e503e59e7
author Jim Stichnoth <stichnot@chromium.org> Wed Jul 30 14:45:20 2014 -0700
committer Jim Stichnoth <stichnot@chromium.org> Wed Jul 30 14:45:20 2014 -0700
tree e1714037ed496e6081f0c58cb1022918118ad374
parent 1e88958647219b7797d5c3b9fc02c24fe0156fc8

Subzero: Try to fix warnings and errors in the Windows build.

Quiet some unused-variable warnings when their only use is in an assert().

Forward-declare partial template specializations when the template method already has a default implementation, to avoid ODR violations and link errors.

BUG= https://codereview.chromium.org/296053008/
R=wala@chromium.org

Review URL: https://codereview.chromium.org/429993002

src/IceInstX8632.cpp

diff --git a/src/IceInstX8632.cpp b/src/IceInstX8632.cpp
index be84554..14e9503 100644
--- a/src/IceInstX8632.cpp
+++ b/src/IceInstX8632.cpp
@@ -640,6 +640,7 @@
   if (getDest()->getType() == IceType_i8) {
     // The 8-bit version of imul only allows the form "imul r/m8".
     Variable *Src0 = llvm::dyn_cast<Variable>(getSrc(0));
+    (void)Src0;
     assert(Src0 && Src0->getRegNum() == TargetX8632::Reg_eax);
     Str << "\timul\t";
     getSrc(1)->emit(Func);
@@ -686,6 +687,7 @@
   getSrc(1)->emit(Func);
   Str << ", ";
   if (Variable *ShiftReg = llvm::dyn_cast<Variable>(getSrc(2))) {
+    (void)ShiftReg;
     assert(ShiftReg->getRegNum() == TargetX8632::Reg_ecx);
     Str << "cl";
   } else {
@@ -711,6 +713,7 @@
   getSrc(1)->emit(Func);
   Str << ", ";
   if (Variable *ShiftReg = llvm::dyn_cast<Variable>(getSrc(2))) {
+    (void)ShiftReg;
     assert(ShiftReg->getRegNum() == TargetX8632::Reg_ecx);
     Str << "cl";
   } else {

src/IceInstX8632.h

diff --git a/src/IceInstX8632.h b/src/IceInstX8632.h
index fb57b75..18f0dde 100644
--- a/src/IceInstX8632.h
+++ b/src/IceInstX8632.h
@@ -1190,6 +1190,31 @@
   virtual ~InstX8632Xchg() {}
 };
 
+// Declare partial template specializations of emit() methods that
+// already have default implementations.  Without this, there is the
+// possibility of ODR violations and link errors.
+template <> void InstX8632Addss::emit(const Cfg *Func) const;
+template <> void InstX8632Blendvps::emit(const Cfg *Func) const;
+template <> void InstX8632Div::emit(const Cfg *Func) const;
+template <> void InstX8632Divss::emit(const Cfg *Func) const;
+template <> void InstX8632Idiv::emit(const Cfg *Func) const;
+template <> void InstX8632Imul::emit(const Cfg *Func) const;
+template <> void InstX8632Lea::emit(const Cfg *Func) const;
+template <> void InstX8632Mulss::emit(const Cfg *Func) const;
+template <> void InstX8632Padd::emit(const Cfg *Func) const;
+template <> void InstX8632Pblendvb::emit(const Cfg *Func) const;
+template <> void InstX8632Pcmpeq::emit(const Cfg *Func) const;
+template <> void InstX8632Pcmpgt::emit(const Cfg *Func) const;
+template <> void InstX8632Pextr::emit(const Cfg *Func) const;
+template <> void InstX8632Pinsr::emit(const Cfg *Func) const;
+template <> void InstX8632Pmull::emit(const Cfg *Func) const;
+template <> void InstX8632Pmuludq::emit(const Cfg *Func) const;
+template <> void InstX8632Psll::emit(const Cfg *Func) const;
+template <> void InstX8632Psra::emit(const Cfg *Func) const;
+template <> void InstX8632Psub::emit(const Cfg *Func) const;
+template <> void InstX8632Sqrtss::emit(const Cfg *Func) const;
+template <> void InstX8632Subss::emit(const Cfg *Func) const;
+
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTX8632_H

src/IceTargetLoweringX8632.cpp

diff --git a/src/IceTargetLoweringX8632.cpp b/src/IceTargetLoweringX8632.cpp
index cc6f222..72e9a05 100644
--- a/src/IceTargetLoweringX8632.cpp
+++ b/src/IceTargetLoweringX8632.cpp
@@ -115,6 +115,7 @@
 Type getInVectorElementType(Type Ty) {
   assert(isVectorType(Ty));
   size_t Index = static_cast<size_t>(Ty);
+  (void)Index;
   assert(Index < TableTypeX8632AttributesSize);
   return TableTypeX8632Attributes[Ty].InVectorElementType;
 }
@@ -2051,6 +2052,7 @@
       Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
       Type DestType = Dest->getType();
       Type SrcType = Src0RM->getType();
+      (void)DestType;
       assert((DestType == IceType_i32 && SrcType == IceType_f32) ||
              (DestType == IceType_f32 && SrcType == IceType_i32));
       // a.i32 = bitcast b.f32 ==>
@@ -2751,8 +2753,8 @@
     // Make sure the atomic load isn't elided when unused, by adding a FakeUse.
     // Since lowerLoad may fuse the load w/ an arithmetic instruction,
     // insert the FakeUse on the last-inserted instruction's dest.
-    Context.insert(InstFakeUse::create(Func,
-                                       Context.getLastInserted()->getDest()));
+    Context.insert(
+        InstFakeUse::create(Func, Context.getLastInserted()->getDest()));
     return;
   }
   case Intrinsics::AtomicRMW:
@@ -3144,6 +3146,7 @@
     return;
   }
   // Otherwise, we need a cmpxchg loop.
+  (void)NeedsCmpxchg;
   assert(NeedsCmpxchg);
   expandAtomicRMWAsCmpxchg(Op_Lo, Op_Hi, Dest, Ptr, Val);
 }