Add vector VEOR instruction to the integrated ARM assembler.
BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334
R=eholk@chromium.org, stichnot@chromium.org
Review URL: https://codereview.chromium.org/1655363002 .
diff --git a/src/DartARM32/assembler_arm.cc b/src/DartARM32/assembler_arm.cc
index fd01f2a..bc5c974 100644
--- a/src/DartARM32/assembler_arm.cc
+++ b/src/DartARM32/assembler_arm.cc
@@ -1301,12 +1301,12 @@
EmitSIMDqqq(B25 | B24 | B10, sz, qd, qn, qm);
}
-
+#if 0
+// Moved to ARM32::AssemblerARM32::veorq()
void Assembler::veorq(QRegister qd, QRegister qn, QRegister qm) {
EmitSIMDqqq(B24 | B8 | B4, kByte, qd, qn, qm);
}
-#if 0
// Moved to ARM32::AssemblerARM32::vorrq()
void Assembler::vorrq(QRegister qd, QRegister qn, QRegister qm) {
EmitSIMDqqq(B21 | B8 | B4, kByte, qd, qn, qm);
diff --git a/src/DartARM32/assembler_arm.h b/src/DartARM32/assembler_arm.h
index 2112209..ab536a4 100644
--- a/src/DartARM32/assembler_arm.h
+++ b/src/DartARM32/assembler_arm.h
@@ -716,9 +716,10 @@
void vrsqrteqs(QRegister qd, QRegister qm);
void vrsqrtsqs(QRegister qd, QRegister qn, QRegister qm);
- void veorq(QRegister qd, QRegister qn, QRegister qm);
#if 0
// Moved to ARM32::AssemblerARM32::vorrq()
+ void veorq(QRegister qd, QRegister qn, QRegister qm);
+ // Moved to ARM32::AssemblerARM32::vorrq()
void vorrq(QRegister qd, QRegister qn, QRegister qm);
#endif
void vornq(QRegister qd, QRegister qn, QRegister qm);
diff --git a/src/IceAssemblerARM32.cpp b/src/IceAssemblerARM32.cpp
index 2044050..1395b74 100644
--- a/src/IceAssemblerARM32.cpp
+++ b/src/IceAssemblerARM32.cpp
@@ -2471,6 +2471,13 @@
emitInst(Encoding);
}
+void AssemblerARM32::veorq(const Operand *OpQd, const Operand *OpQn,
+ const Operand *OpQm) {
+ constexpr const char *Veorq = "veorq";
+ constexpr IValueT VeorqOpcode = B24 | B8 | B4;
+ emitSIMDqqq(VeorqOpcode, IceType_i8, OpQd, OpQn, OpQm, Veorq);
+}
+
void AssemblerARM32::vldrd(const Operand *OpDd, const Operand *OpAddress,
CondARM32::Cond Cond, const TargetInfo &TInfo) {
// VLDR - ARM section A8.8.333, encoding A1.
diff --git a/src/IceAssemblerARM32.h b/src/IceAssemblerARM32.h
index 2e141c1..93d885b 100644
--- a/src/IceAssemblerARM32.h
+++ b/src/IceAssemblerARM32.h
@@ -377,6 +377,8 @@
void veord(const Operand *OpDd, const Operand *OpDn, const Operand *OpDm);
+ void veorq(const Operand *OpQd, const Operand *OpQn, const Operand *OpQm);
+
void vldrd(const Operand *OpDd, const Operand *OpAddress,
CondARM32::Cond Cond, const TargetInfo &TInfo);
diff --git a/src/IceInstARM32.cpp b/src/IceInstARM32.cpp
index 312a3d1..fbf9fac 100644
--- a/src/IceInstARM32.cpp
+++ b/src/IceInstARM32.cpp
@@ -680,8 +680,8 @@
auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
const Variable *Dest = getDest();
if (isVectorType(Dest->getType())) {
- // TODO(kschimpf): Add support for this case
- emitUsingTextFixup(Func);
+ Asm->veorq(Dest, getSrc(0), getSrc(1));
+ assert(!Asm->needsTextFixup());
return;
}
assert(Dest->getType() == IceType_f64);
diff --git a/src/IceTargetLoweringARM32.cpp b/src/IceTargetLoweringARM32.cpp
index 34069eb..815c41f 100644
--- a/src/IceTargetLoweringARM32.cpp
+++ b/src/IceTargetLoweringARM32.cpp
@@ -2989,6 +2989,7 @@
}
case InstArithmetic::Xor: {
Variable *Src0R = Srcs.src0R(this);
+ assert(isIntegerType(DestTy));
if (isVectorType(DestTy)) {
Variable *Src1R = legalizeToReg(Src1);
_veor(T, Src0R, Src1R);
diff --git a/tests_lit/assembler/arm32/xor-vec.ll b/tests_lit/assembler/arm32/xor-vec.ll
index 668d5de..eef201e 100644
--- a/tests_lit/assembler/arm32/xor-vec.ll
+++ b/tests_lit/assembler/arm32/xor-vec.ll
@@ -30,7 +30,7 @@
; ASM: veor.i32 q0, q0, q1
; DIS: 0: f3000152
-; IASM: veor.i32
+; IASM-NOT: veor.i32
ret <4 x i32> %res
}
@@ -45,7 +45,7 @@
; ASM: veor.i16 q0, q0, q1
; DIS: 10: f3000152
-; IASM: veor.i16
+; IASM-NOT: veor.i16
ret <8 x i16> %res
}
@@ -60,7 +60,7 @@
; ASM: veor.i8 q0, q0, q1
; DIS: 20: f3000152
-; IASM: veor.i8
+; IASM-NOT: veor.i8
ret <16 x i8> %res
}
@@ -79,7 +79,7 @@
; ASM: veor.i32 q0, q0, q1
; DIS: 30: f3000152
-; IASM: veor.i32
+; IASM-NOT: veor.i32
ret <4 x i1> %res
}
@@ -94,7 +94,7 @@
; ASM: veor.i16 q0, q0, q1
; DIS: 40: f3000152
-; IASM: veor.i16
+; IASM-NOT: veor.i16
ret <8 x i1> %res
}
@@ -109,7 +109,7 @@
; ASM: veor.i8 q0, q0, q1
; DIS: 50: f3000152
-; IASM: veor.i8
+; IASM-NOT: veor.i8
ret <16 x i1> %res
}
