Add Om1 lowering with no optimizations. This adds infrastructure for low-level x86-32 instructions, and the target lowering patterns. Practically no optimizations are performed. Optimizations to be introduced later include liveness analysis, dead-code elimination, global linear-scan register allocation, linear-scan based stack slot coalescing, and compare/branch fusing. One optimization that is present is simple coalescing of stack slots for variables that are only live within a single basic block. There are also some fairly comprehensive cross tests. This testing infrastructure translates bitcode using both Subzero and llc, and a testing harness calls both versions with a variety of "interesting" inputs and compares the results. Specifically, Arithmetic, Icmp, Fcmp, and Cast instructions are tested this way, across all PNaCl primitive types. BUG= R=jvoung@chromium.org Review URL: https://codereview.chromium.org/265703002
diff --git a/src/IceTargetLoweringX8632.def b/src/IceTargetLoweringX8632.def new file mode 100644 index 0000000..b88091a --- /dev/null +++ b/src/IceTargetLoweringX8632.def
@@ -0,0 +1,52 @@ +//===- subzero/src/IceTargetLoweringX8632.def - x86-32 X-macros -*- C++ -*-===// +// +// The Subzero Code Generator +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines certain patterns for lowering to x86-32 target +// instructions, in the form of x-macros. +// +//===----------------------------------------------------------------------===// + +#ifndef SUBZERO_SRC_ICETARGETLOWERINGX8632_DEF +#define SUBZERO_SRC_ICETARGETLOWERINGX8632_DEF + +#define FCMPX8632_TABLE \ + /* val, dflt, swap, C1, C2 */ \ + X(False, 0, 0, Br_None, Br_None) \ + X(Oeq, 0, 0, Br_ne, Br_p) \ + X(Ogt, 1, 0, Br_a, Br_None) \ + X(Oge, 1, 0, Br_ae, Br_None) \ + X(Olt, 1, 1, Br_a, Br_None) \ + X(Ole, 1, 1, Br_ae, Br_None) \ + X(One, 1, 0, Br_ne, Br_None) \ + X(Ord, 1, 0, Br_np, Br_None) \ + X(Ueq, 1, 0, Br_e, Br_None) \ + X(Ugt, 1, 1, Br_b, Br_None) \ + X(Uge, 1, 1, Br_be, Br_None) \ + X(Ult, 1, 0, Br_b, Br_None) \ + X(Ule, 1, 0, Br_be, Br_None) \ + X(Une, 1, 0, Br_ne, Br_p) \ + X(Uno, 1, 0, Br_p, Br_None) \ + X(True, 1, 0, Br_None, Br_None) \ +//#define X(val, dflt, swap, C1, C2) + +#define ICMPX8632_TABLE \ + /* val, C_32, C1_64, C2_64, C3_64 */ \ + X(Eq, Br_e, Br_None, Br_None, Br_None) \ + X(Ne, Br_ne, Br_None, Br_None, Br_None) \ + X(Ugt, Br_a, Br_a, Br_b, Br_a) \ + X(Uge, Br_ae, Br_a, Br_b, Br_ae) \ + X(Ult, Br_b, Br_b, Br_a, Br_b) \ + X(Ule, Br_be, Br_b, Br_a, Br_be) \ + X(Sgt, Br_g, Br_g, Br_l, Br_a) \ + X(Sge, Br_ge, Br_g, Br_l, Br_ae) \ + X(Slt, Br_l, Br_l, Br_g, Br_b) \ + X(Sle, Br_le, Br_l, Br_g, Br_be) \ +//#define X(val, C_32, C1_64, C2_64, C3_64) + +#endif // SUBZERO_SRC_ICETARGETLOWERINGX8632_DEF