| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* Assembly Writer Source Fragment *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| /// printInstruction - This method is automatically generated by tablegen |
| /// from the instruction set description. |
| void AArch64InstPrinter::printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O) { |
| static const char AsmStrs[] = { |
| /* 0 */ 's', 'h', 'a', '1', 's', 'u', '0', 9, 0, |
| /* 9 */ 's', 'h', 'a', '5', '1', '2', 's', 'u', '0', 9, 0, |
| /* 20 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '0', 9, 0, |
| /* 31 */ 'l', 'd', '1', 9, 0, |
| /* 36 */ 't', 'r', 'n', '1', 9, 0, |
| /* 42 */ 'z', 'i', 'p', '1', 9, 0, |
| /* 48 */ 'u', 'z', 'p', '1', 9, 0, |
| /* 54 */ 'd', 'c', 'p', 's', '1', 9, 0, |
| /* 61 */ 's', 'm', '3', 's', 's', '1', 9, 0, |
| /* 69 */ 's', 't', '1', 9, 0, |
| /* 74 */ 's', 'h', 'a', '1', 's', 'u', '1', 9, 0, |
| /* 83 */ 's', 'h', 'a', '5', '1', '2', 's', 'u', '1', 9, 0, |
| /* 94 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '1', 9, 0, |
| /* 105 */ 's', 'm', '3', 'p', 'a', 'r', 't', 'w', '1', 9, 0, |
| /* 116 */ 'r', 'a', 'x', '1', 9, 0, |
| /* 122 */ 'r', 'e', 'v', '3', '2', 9, 0, |
| /* 129 */ 'l', 'd', '2', 9, 0, |
| /* 134 */ 's', 'h', 'a', '5', '1', '2', 'h', '2', 9, 0, |
| /* 144 */ 's', 'h', 'a', '2', '5', '6', 'h', '2', 9, 0, |
| /* 154 */ 's', 'a', 'b', 'a', 'l', '2', 9, 0, |
| /* 162 */ 'u', 'a', 'b', 'a', 'l', '2', 9, 0, |
| /* 170 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', '2', 9, 0, |
| /* 180 */ 's', 'm', 'l', 'a', 'l', '2', 9, 0, |
| /* 188 */ 'u', 'm', 'l', 'a', 'l', '2', 9, 0, |
| /* 196 */ 's', 's', 'u', 'b', 'l', '2', 9, 0, |
| /* 204 */ 'u', 's', 'u', 'b', 'l', '2', 9, 0, |
| /* 212 */ 's', 'a', 'b', 'd', 'l', '2', 9, 0, |
| /* 220 */ 'u', 'a', 'b', 'd', 'l', '2', 9, 0, |
| /* 228 */ 's', 'a', 'd', 'd', 'l', '2', 9, 0, |
| /* 236 */ 'u', 'a', 'd', 'd', 'l', '2', 9, 0, |
| /* 244 */ 's', 's', 'h', 'l', 'l', '2', 9, 0, |
| /* 252 */ 'u', 's', 'h', 'l', 'l', '2', 9, 0, |
| /* 260 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', '2', 9, 0, |
| /* 270 */ 'p', 'm', 'u', 'l', 'l', '2', 9, 0, |
| /* 278 */ 's', 'm', 'u', 'l', 'l', '2', 9, 0, |
| /* 286 */ 'u', 'm', 'u', 'l', 'l', '2', 9, 0, |
| /* 294 */ 's', 'q', 'd', 'm', 'l', 's', 'l', '2', 9, 0, |
| /* 304 */ 's', 'm', 'l', 's', 'l', '2', 9, 0, |
| /* 312 */ 'u', 'm', 'l', 's', 'l', '2', 9, 0, |
| /* 320 */ 'f', 'c', 'v', 't', 'l', '2', 9, 0, |
| /* 328 */ 'r', 's', 'u', 'b', 'h', 'n', '2', 9, 0, |
| /* 337 */ 'r', 'a', 'd', 'd', 'h', 'n', '2', 9, 0, |
| /* 346 */ 's', 'q', 's', 'h', 'r', 'n', '2', 9, 0, |
| /* 355 */ 'u', 'q', 's', 'h', 'r', 'n', '2', 9, 0, |
| /* 364 */ 's', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0, |
| /* 374 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0, |
| /* 384 */ 't', 'r', 'n', '2', 9, 0, |
| /* 390 */ 'f', 'c', 'v', 't', 'n', '2', 9, 0, |
| /* 398 */ 's', 'q', 'x', 't', 'n', '2', 9, 0, |
| /* 406 */ 'u', 'q', 'x', 't', 'n', '2', 9, 0, |
| /* 414 */ 's', 'q', 's', 'h', 'r', 'u', 'n', '2', 9, 0, |
| /* 424 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', '2', 9, 0, |
| /* 435 */ 's', 'q', 'x', 't', 'u', 'n', '2', 9, 0, |
| /* 444 */ 'f', 'c', 'v', 't', 'x', 'n', '2', 9, 0, |
| /* 453 */ 'z', 'i', 'p', '2', 9, 0, |
| /* 459 */ 'u', 'z', 'p', '2', 9, 0, |
| /* 465 */ 'd', 'c', 'p', 's', '2', 9, 0, |
| /* 472 */ 's', 't', '2', 9, 0, |
| /* 477 */ 's', 's', 'u', 'b', 'w', '2', 9, 0, |
| /* 485 */ 'u', 's', 'u', 'b', 'w', '2', 9, 0, |
| /* 493 */ 's', 'a', 'd', 'd', 'w', '2', 9, 0, |
| /* 501 */ 'u', 'a', 'd', 'd', 'w', '2', 9, 0, |
| /* 509 */ 's', 'm', '3', 'p', 'a', 'r', 't', 'w', '2', 9, 0, |
| /* 520 */ 'l', 'd', '3', 9, 0, |
| /* 525 */ 'e', 'o', 'r', '3', 9, 0, |
| /* 531 */ 'd', 'c', 'p', 's', '3', 9, 0, |
| /* 538 */ 's', 't', '3', 9, 0, |
| /* 543 */ 'r', 'e', 'v', '6', '4', 9, 0, |
| /* 550 */ 'l', 'd', '4', 9, 0, |
| /* 555 */ 's', 't', '4', 9, 0, |
| /* 560 */ 's', 'e', 't', 'f', '1', '6', 9, 0, |
| /* 568 */ 'r', 'e', 'v', '1', '6', 9, 0, |
| /* 575 */ 's', 'e', 't', 'f', '8', 9, 0, |
| /* 582 */ 's', 'm', '3', 't', 't', '1', 'a', 9, 0, |
| /* 591 */ 's', 'm', '3', 't', 't', '2', 'a', 9, 0, |
| /* 600 */ 'b', 'r', 'a', 'a', 9, 0, |
| /* 606 */ 'l', 'd', 'r', 'a', 'a', 9, 0, |
| /* 613 */ 'b', 'l', 'r', 'a', 'a', 9, 0, |
| /* 620 */ 's', 'a', 'b', 'a', 9, 0, |
| /* 626 */ 'u', 'a', 'b', 'a', 9, 0, |
| /* 632 */ 'p', 'a', 'c', 'd', 'a', 9, 0, |
| /* 639 */ 'l', 'd', 'a', 'd', 'd', 'a', 9, 0, |
| /* 647 */ 'f', 'a', 'd', 'd', 'a', 9, 0, |
| /* 654 */ 'a', 'u', 't', 'd', 'a', 9, 0, |
| /* 661 */ 'p', 'a', 'c', 'g', 'a', 9, 0, |
| /* 668 */ 'p', 'a', 'c', 'i', 'a', 9, 0, |
| /* 675 */ 'a', 'u', 't', 'i', 'a', 9, 0, |
| /* 682 */ 'b', 'r', 'k', 'a', 9, 0, |
| /* 688 */ 'f', 'c', 'm', 'l', 'a', 9, 0, |
| /* 695 */ 'f', 'm', 'l', 'a', 9, 0, |
| /* 701 */ 'f', 'n', 'm', 'l', 'a', 9, 0, |
| /* 708 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 9, 0, |
| /* 717 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 9, 0, |
| /* 726 */ 'b', 'r', 'k', 'p', 'a', 9, 0, |
| /* 733 */ 'c', 'a', 's', 'p', 'a', 9, 0, |
| /* 740 */ 's', 'w', 'p', 'a', 9, 0, |
| /* 746 */ 'f', 'e', 'x', 'p', 'a', 9, 0, |
| /* 753 */ 'l', 'd', 'c', 'l', 'r', 'a', 9, 0, |
| /* 761 */ 'l', 'd', 'e', 'o', 'r', 'a', 9, 0, |
| /* 769 */ 's', 'r', 's', 'r', 'a', 9, 0, |
| /* 776 */ 'u', 'r', 's', 'r', 'a', 9, 0, |
| /* 783 */ 's', 's', 'r', 'a', 9, 0, |
| /* 789 */ 'u', 's', 'r', 'a', 9, 0, |
| /* 795 */ 'c', 'a', 's', 'a', 9, 0, |
| /* 801 */ 'l', 'd', 's', 'e', 't', 'a', 9, 0, |
| /* 809 */ 'f', 'r', 'i', 'n', 't', 'a', 9, 0, |
| /* 817 */ 'c', 'l', 'a', 's', 't', 'a', 9, 0, |
| /* 825 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 9, 0, |
| /* 834 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 9, 0, |
| /* 843 */ 'p', 'a', 'c', 'd', 'z', 'a', 9, 0, |
| /* 851 */ 'a', 'u', 't', 'd', 'z', 'a', 9, 0, |
| /* 859 */ 'p', 'a', 'c', 'i', 'z', 'a', 9, 0, |
| /* 867 */ 'a', 'u', 't', 'i', 'z', 'a', 9, 0, |
| /* 875 */ 'l', 'd', '1', 'b', 9, 0, |
| /* 881 */ 'l', 'd', 'f', 'f', '1', 'b', 9, 0, |
| /* 889 */ 'l', 'd', 'n', 'f', '1', 'b', 9, 0, |
| /* 897 */ 'l', 'd', 'n', 't', '1', 'b', 9, 0, |
| /* 905 */ 's', 't', 'n', 't', '1', 'b', 9, 0, |
| /* 913 */ 's', 't', '1', 'b', 9, 0, |
| /* 919 */ 's', 'm', '3', 't', 't', '1', 'b', 9, 0, |
| /* 928 */ 'c', 'r', 'c', '3', '2', 'b', 9, 0, |
| /* 936 */ 'l', 'd', '2', 'b', 9, 0, |
| /* 942 */ 's', 't', '2', 'b', 9, 0, |
| /* 948 */ 's', 'm', '3', 't', 't', '2', 'b', 9, 0, |
| /* 957 */ 'l', 'd', '3', 'b', 9, 0, |
| /* 963 */ 's', 't', '3', 'b', 9, 0, |
| /* 969 */ 'l', 'd', '4', 'b', 9, 0, |
| /* 975 */ 's', 't', '4', 'b', 9, 0, |
| /* 981 */ 'l', 'd', 'a', 'd', 'd', 'a', 'b', 9, 0, |
| /* 990 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'b', 9, 0, |
| /* 1000 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'b', 9, 0, |
| /* 1010 */ 's', 'w', 'p', 'a', 'b', 9, 0, |
| /* 1017 */ 'b', 'r', 'a', 'b', 9, 0, |
| /* 1023 */ 'l', 'd', 'r', 'a', 'b', 9, 0, |
| /* 1030 */ 'b', 'l', 'r', 'a', 'b', 9, 0, |
| /* 1037 */ 'l', 'd', 'c', 'l', 'r', 'a', 'b', 9, 0, |
| /* 1046 */ 'l', 'd', 'e', 'o', 'r', 'a', 'b', 9, 0, |
| /* 1055 */ 'c', 'a', 's', 'a', 'b', 9, 0, |
| /* 1062 */ 'l', 'd', 's', 'e', 't', 'a', 'b', 9, 0, |
| /* 1071 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'b', 9, 0, |
| /* 1081 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'b', 9, 0, |
| /* 1091 */ 'c', 'r', 'c', '3', '2', 'c', 'b', 9, 0, |
| /* 1100 */ 's', 'q', 'd', 'e', 'c', 'b', 9, 0, |
| /* 1108 */ 'u', 'q', 'd', 'e', 'c', 'b', 9, 0, |
| /* 1116 */ 's', 'q', 'i', 'n', 'c', 'b', 9, 0, |
| /* 1124 */ 'u', 'q', 'i', 'n', 'c', 'b', 9, 0, |
| /* 1132 */ 'p', 'a', 'c', 'd', 'b', 9, 0, |
| /* 1139 */ 'l', 'd', 'a', 'd', 'd', 'b', 9, 0, |
| /* 1147 */ 'a', 'u', 't', 'd', 'b', 9, 0, |
| /* 1154 */ 'p', 'r', 'f', 'b', 9, 0, |
| /* 1160 */ 'p', 'a', 'c', 'i', 'b', 9, 0, |
| /* 1167 */ 'a', 'u', 't', 'i', 'b', 9, 0, |
| /* 1174 */ 'b', 'r', 'k', 'b', 9, 0, |
| /* 1180 */ 'l', 'd', 'a', 'd', 'd', 'a', 'l', 'b', 9, 0, |
| /* 1190 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'l', 'b', 9, 0, |
| /* 1201 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'l', 'b', 9, 0, |
| /* 1212 */ 's', 'w', 'p', 'a', 'l', 'b', 9, 0, |
| /* 1220 */ 'l', 'd', 'c', 'l', 'r', 'a', 'l', 'b', 9, 0, |
| /* 1230 */ 'l', 'd', 'e', 'o', 'r', 'a', 'l', 'b', 9, 0, |
| /* 1240 */ 'c', 'a', 's', 'a', 'l', 'b', 9, 0, |
| /* 1248 */ 'l', 'd', 's', 'e', 't', 'a', 'l', 'b', 9, 0, |
| /* 1258 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'l', 'b', 9, 0, |
| /* 1269 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'l', 'b', 9, 0, |
| /* 1280 */ 'l', 'd', 'a', 'd', 'd', 'l', 'b', 9, 0, |
| /* 1289 */ 'l', 'd', 's', 'm', 'i', 'n', 'l', 'b', 9, 0, |
| /* 1299 */ 'l', 'd', 'u', 'm', 'i', 'n', 'l', 'b', 9, 0, |
| /* 1309 */ 's', 'w', 'p', 'l', 'b', 9, 0, |
| /* 1316 */ 'l', 'd', 'c', 'l', 'r', 'l', 'b', 9, 0, |
| /* 1325 */ 'l', 'd', 'e', 'o', 'r', 'l', 'b', 9, 0, |
| /* 1334 */ 'c', 'a', 's', 'l', 'b', 9, 0, |
| /* 1341 */ 'l', 'd', 's', 'e', 't', 'l', 'b', 9, 0, |
| /* 1350 */ 'l', 'd', 's', 'm', 'a', 'x', 'l', 'b', 9, 0, |
| /* 1360 */ 'l', 'd', 'u', 'm', 'a', 'x', 'l', 'b', 9, 0, |
| /* 1370 */ 'd', 'm', 'b', 9, 0, |
| /* 1375 */ 'l', 'd', 's', 'm', 'i', 'n', 'b', 9, 0, |
| /* 1384 */ 'l', 'd', 'u', 'm', 'i', 'n', 'b', 9, 0, |
| /* 1393 */ 'b', 'r', 'k', 'p', 'b', 9, 0, |
| /* 1400 */ 's', 'w', 'p', 'b', 9, 0, |
| /* 1406 */ 'l', 'd', '1', 'r', 'q', 'b', 9, 0, |
| /* 1414 */ 'l', 'd', '1', 'r', 'b', 9, 0, |
| /* 1421 */ 'l', 'd', 'a', 'r', 'b', 9, 0, |
| /* 1428 */ 'l', 'd', 'l', 'a', 'r', 'b', 9, 0, |
| /* 1436 */ 'l', 'd', 'r', 'b', 9, 0, |
| /* 1442 */ 'l', 'd', 'c', 'l', 'r', 'b', 9, 0, |
| /* 1450 */ 's', 't', 'l', 'l', 'r', 'b', 9, 0, |
| /* 1458 */ 's', 't', 'l', 'r', 'b', 9, 0, |
| /* 1465 */ 'l', 'd', 'e', 'o', 'r', 'b', 9, 0, |
| /* 1473 */ 'l', 'd', 'a', 'p', 'r', 'b', 9, 0, |
| /* 1481 */ 'l', 'd', 't', 'r', 'b', 9, 0, |
| /* 1488 */ 's', 't', 'r', 'b', 9, 0, |
| /* 1494 */ 's', 't', 't', 'r', 'b', 9, 0, |
| /* 1501 */ 'l', 'd', 'u', 'r', 'b', 9, 0, |
| /* 1508 */ 's', 't', 'l', 'u', 'r', 'b', 9, 0, |
| /* 1516 */ 'l', 'd', 'a', 'p', 'u', 'r', 'b', 9, 0, |
| /* 1525 */ 's', 't', 'u', 'r', 'b', 9, 0, |
| /* 1532 */ 'l', 'd', 'a', 'x', 'r', 'b', 9, 0, |
| /* 1540 */ 'l', 'd', 'x', 'r', 'b', 9, 0, |
| /* 1547 */ 's', 't', 'l', 'x', 'r', 'b', 9, 0, |
| /* 1555 */ 's', 't', 'x', 'r', 'b', 9, 0, |
| /* 1562 */ 'l', 'd', '1', 's', 'b', 9, 0, |
| /* 1569 */ 'l', 'd', 'f', 'f', '1', 's', 'b', 9, 0, |
| /* 1578 */ 'l', 'd', 'n', 'f', '1', 's', 'b', 9, 0, |
| /* 1587 */ 'c', 'a', 's', 'b', 9, 0, |
| /* 1593 */ 'd', 's', 'b', 9, 0, |
| /* 1598 */ 'i', 's', 'b', 9, 0, |
| /* 1603 */ 'f', 'm', 's', 'b', 9, 0, |
| /* 1609 */ 'f', 'n', 'm', 's', 'b', 9, 0, |
| /* 1616 */ 'l', 'd', '1', 'r', 's', 'b', 9, 0, |
| /* 1624 */ 'l', 'd', 'r', 's', 'b', 9, 0, |
| /* 1631 */ 'l', 'd', 't', 'r', 's', 'b', 9, 0, |
| /* 1639 */ 'l', 'd', 'u', 'r', 's', 'b', 9, 0, |
| /* 1647 */ 'l', 'd', 'a', 'p', 'u', 'r', 's', 'b', 9, 0, |
| /* 1657 */ 't', 's', 'b', 9, 0, |
| /* 1662 */ 'l', 'd', 's', 'e', 't', 'b', 9, 0, |
| /* 1670 */ 'c', 'n', 't', 'b', 9, 0, |
| /* 1676 */ 'c', 'l', 'a', 's', 't', 'b', 9, 0, |
| /* 1684 */ 's', 'x', 't', 'b', 9, 0, |
| /* 1690 */ 'u', 'x', 't', 'b', 9, 0, |
| /* 1696 */ 'f', 's', 'u', 'b', 9, 0, |
| /* 1702 */ 's', 'h', 's', 'u', 'b', 9, 0, |
| /* 1709 */ 'u', 'h', 's', 'u', 'b', 9, 0, |
| /* 1716 */ 'f', 'm', 's', 'u', 'b', 9, 0, |
| /* 1723 */ 'f', 'n', 'm', 's', 'u', 'b', 9, 0, |
| /* 1731 */ 's', 'q', 's', 'u', 'b', 9, 0, |
| /* 1738 */ 'u', 'q', 's', 'u', 'b', 9, 0, |
| /* 1745 */ 'r', 'e', 'v', 'b', 9, 0, |
| /* 1751 */ 'l', 'd', 's', 'm', 'a', 'x', 'b', 9, 0, |
| /* 1760 */ 'l', 'd', 'u', 'm', 'a', 'x', 'b', 9, 0, |
| /* 1769 */ 'p', 'a', 'c', 'd', 'z', 'b', 9, 0, |
| /* 1777 */ 'a', 'u', 't', 'd', 'z', 'b', 9, 0, |
| /* 1785 */ 'p', 'a', 'c', 'i', 'z', 'b', 9, 0, |
| /* 1793 */ 'a', 'u', 't', 'i', 'z', 'b', 9, 0, |
| /* 1801 */ 's', 'h', 'a', '1', 'c', 9, 0, |
| /* 1808 */ 's', 'b', 'c', 9, 0, |
| /* 1813 */ 'a', 'd', 'c', 9, 0, |
| /* 1818 */ 'b', 'i', 'c', 9, 0, |
| /* 1823 */ 'a', 'e', 's', 'i', 'm', 'c', 9, 0, |
| /* 1831 */ 'a', 'e', 's', 'm', 'c', 9, 0, |
| /* 1838 */ 'c', 's', 'i', 'n', 'c', 9, 0, |
| /* 1845 */ 'h', 'v', 'c', 9, 0, |
| /* 1850 */ 's', 'v', 'c', 9, 0, |
| /* 1855 */ 'l', 'd', '1', 'd', 9, 0, |
| /* 1861 */ 'l', 'd', 'f', 'f', '1', 'd', 9, 0, |
| /* 1869 */ 'l', 'd', 'n', 'f', '1', 'd', 9, 0, |
| /* 1877 */ 'l', 'd', 'n', 't', '1', 'd', 9, 0, |
| /* 1885 */ 's', 't', 'n', 't', '1', 'd', 9, 0, |
| /* 1893 */ 's', 't', '1', 'd', 9, 0, |
| /* 1899 */ 'l', 'd', '2', 'd', 9, 0, |
| /* 1905 */ 's', 't', '2', 'd', 9, 0, |
| /* 1911 */ 'l', 'd', '3', 'd', 9, 0, |
| /* 1917 */ 's', 't', '3', 'd', 9, 0, |
| /* 1923 */ 'l', 'd', '4', 'd', 9, 0, |
| /* 1929 */ 's', 't', '4', 'd', 9, 0, |
| /* 1935 */ 'f', 'm', 'a', 'd', 9, 0, |
| /* 1941 */ 'f', 'n', 'm', 'a', 'd', 9, 0, |
| /* 1948 */ 'f', 't', 'm', 'a', 'd', 9, 0, |
| /* 1955 */ 'f', 'a', 'b', 'd', 9, 0, |
| /* 1961 */ 's', 'a', 'b', 'd', 9, 0, |
| /* 1967 */ 'u', 'a', 'b', 'd', 9, 0, |
| /* 1973 */ 'x', 'p', 'a', 'c', 'd', 9, 0, |
| /* 1980 */ 's', 'q', 'd', 'e', 'c', 'd', 9, 0, |
| /* 1988 */ 'u', 'q', 'd', 'e', 'c', 'd', 9, 0, |
| /* 1996 */ 's', 'q', 'i', 'n', 'c', 'd', 9, 0, |
| /* 2004 */ 'u', 'q', 'i', 'n', 'c', 'd', 9, 0, |
| /* 2012 */ 'f', 'c', 'a', 'd', 'd', 9, 0, |
| /* 2019 */ 'l', 'd', 'a', 'd', 'd', 9, 0, |
| /* 2026 */ 'f', 'a', 'd', 'd', 9, 0, |
| /* 2032 */ 's', 'r', 'h', 'a', 'd', 'd', 9, 0, |
| /* 2040 */ 'u', 'r', 'h', 'a', 'd', 'd', 9, 0, |
| /* 2048 */ 's', 'h', 'a', 'd', 'd', 9, 0, |
| /* 2055 */ 'u', 'h', 'a', 'd', 'd', 9, 0, |
| /* 2062 */ 'f', 'm', 'a', 'd', 'd', 9, 0, |
| /* 2069 */ 'f', 'n', 'm', 'a', 'd', 'd', 9, 0, |
| /* 2077 */ 'u', 's', 'q', 'a', 'd', 'd', 9, 0, |
| /* 2085 */ 's', 'u', 'q', 'a', 'd', 'd', 9, 0, |
| /* 2093 */ 'p', 'r', 'f', 'd', 9, 0, |
| /* 2099 */ 'n', 'a', 'n', 'd', 9, 0, |
| /* 2105 */ 'l', 'd', '1', 'r', 'q', 'd', 9, 0, |
| /* 2113 */ 'l', 'd', '1', 'r', 'd', 9, 0, |
| /* 2120 */ 'a', 's', 'r', 'd', 9, 0, |
| /* 2126 */ 'a', 'e', 's', 'd', 9, 0, |
| /* 2132 */ 'c', 'n', 't', 'd', 9, 0, |
| /* 2138 */ 's', 'm', '4', 'e', 9, 0, |
| /* 2144 */ 's', 'p', 'l', 'i', 'c', 'e', 9, 0, |
| /* 2152 */ 'f', 'a', 'c', 'g', 'e', 9, 0, |
| /* 2159 */ 'f', 'c', 'm', 'g', 'e', 9, 0, |
| /* 2166 */ 'c', 'm', 'p', 'g', 'e', 9, 0, |
| /* 2173 */ 'f', 's', 'c', 'a', 'l', 'e', 9, 0, |
| /* 2181 */ 'w', 'h', 'i', 'l', 'e', 'l', 'e', 9, 0, |
| /* 2190 */ 'f', 'c', 'm', 'l', 'e', 9, 0, |
| /* 2197 */ 'c', 'm', 'p', 'l', 'e', 9, 0, |
| /* 2204 */ 'f', 'c', 'm', 'n', 'e', 9, 0, |
| /* 2211 */ 'c', 't', 'e', 'r', 'm', 'n', 'e', 9, 0, |
| /* 2220 */ 'c', 'm', 'p', 'n', 'e', 9, 0, |
| /* 2227 */ 'f', 'r', 'e', 'c', 'p', 'e', 9, 0, |
| /* 2235 */ 'u', 'r', 'e', 'c', 'p', 'e', 9, 0, |
| /* 2243 */ 'f', 'c', 'c', 'm', 'p', 'e', 9, 0, |
| /* 2251 */ 'f', 'c', 'm', 'p', 'e', 9, 0, |
| /* 2258 */ 'a', 'e', 's', 'e', 9, 0, |
| /* 2264 */ 'p', 'f', 'a', 'l', 's', 'e', 9, 0, |
| /* 2272 */ 'f', 'r', 's', 'q', 'r', 't', 'e', 9, 0, |
| /* 2281 */ 'u', 'r', 's', 'q', 'r', 't', 'e', 9, 0, |
| /* 2290 */ 'p', 't', 'r', 'u', 'e', 9, 0, |
| /* 2297 */ 'b', 'i', 'f', 9, 0, |
| /* 2302 */ 'r', 'm', 'i', 'f', 9, 0, |
| /* 2308 */ 's', 'c', 'v', 't', 'f', 9, 0, |
| /* 2315 */ 'u', 'c', 'v', 't', 'f', 9, 0, |
| /* 2322 */ 'f', 'n', 'e', 'g', 9, 0, |
| /* 2328 */ 's', 'q', 'n', 'e', 'g', 9, 0, |
| /* 2335 */ 'c', 's', 'n', 'e', 'g', 9, 0, |
| /* 2342 */ 's', 'h', 'a', '1', 'h', 9, 0, |
| /* 2349 */ 'l', 'd', '1', 'h', 9, 0, |
| /* 2355 */ 'l', 'd', 'f', 'f', '1', 'h', 9, 0, |
| /* 2363 */ 'l', 'd', 'n', 'f', '1', 'h', 9, 0, |
| /* 2371 */ 'l', 'd', 'n', 't', '1', 'h', 9, 0, |
| /* 2379 */ 's', 't', 'n', 't', '1', 'h', 9, 0, |
| /* 2387 */ 's', 't', '1', 'h', 9, 0, |
| /* 2393 */ 's', 'h', 'a', '5', '1', '2', 'h', 9, 0, |
| /* 2402 */ 'c', 'r', 'c', '3', '2', 'h', 9, 0, |
| /* 2410 */ 'l', 'd', '2', 'h', 9, 0, |
| /* 2416 */ 's', 't', '2', 'h', 9, 0, |
| /* 2422 */ 'l', 'd', '3', 'h', 9, 0, |
| /* 2428 */ 's', 't', '3', 'h', 9, 0, |
| /* 2434 */ 'l', 'd', '4', 'h', 9, 0, |
| /* 2440 */ 's', 't', '4', 'h', 9, 0, |
| /* 2446 */ 's', 'h', 'a', '2', '5', '6', 'h', 9, 0, |
| /* 2455 */ 'l', 'd', 'a', 'd', 'd', 'a', 'h', 9, 0, |
| /* 2464 */ 's', 'q', 'r', 'd', 'm', 'l', 'a', 'h', 9, 0, |
| /* 2474 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'h', 9, 0, |
| /* 2484 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'h', 9, 0, |
| /* 2494 */ 's', 'w', 'p', 'a', 'h', 9, 0, |
| /* 2501 */ 'l', 'd', 'c', 'l', 'r', 'a', 'h', 9, 0, |
| /* 2510 */ 'l', 'd', 'e', 'o', 'r', 'a', 'h', 9, 0, |
| /* 2519 */ 'c', 'a', 's', 'a', 'h', 9, 0, |
| /* 2526 */ 'l', 'd', 's', 'e', 't', 'a', 'h', 9, 0, |
| /* 2535 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'h', 9, 0, |
| /* 2545 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'h', 9, 0, |
| /* 2555 */ 'c', 'r', 'c', '3', '2', 'c', 'h', 9, 0, |
| /* 2564 */ 's', 'q', 'd', 'e', 'c', 'h', 9, 0, |
| /* 2572 */ 'u', 'q', 'd', 'e', 'c', 'h', 9, 0, |
| /* 2580 */ 's', 'q', 'i', 'n', 'c', 'h', 9, 0, |
| /* 2588 */ 'u', 'q', 'i', 'n', 'c', 'h', 9, 0, |
| /* 2596 */ 'l', 'd', 'a', 'd', 'd', 'h', 9, 0, |
| /* 2604 */ 'p', 'r', 'f', 'h', 9, 0, |
| /* 2610 */ 'l', 'd', 'a', 'd', 'd', 'a', 'l', 'h', 9, 0, |
| /* 2620 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'l', 'h', 9, 0, |
| /* 2631 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'l', 'h', 9, 0, |
| /* 2642 */ 's', 'w', 'p', 'a', 'l', 'h', 9, 0, |
| /* 2650 */ 'l', 'd', 'c', 'l', 'r', 'a', 'l', 'h', 9, 0, |
| /* 2660 */ 'l', 'd', 'e', 'o', 'r', 'a', 'l', 'h', 9, 0, |
| /* 2670 */ 'c', 'a', 's', 'a', 'l', 'h', 9, 0, |
| /* 2678 */ 'l', 'd', 's', 'e', 't', 'a', 'l', 'h', 9, 0, |
| /* 2688 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'l', 'h', 9, 0, |
| /* 2699 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'l', 'h', 9, 0, |
| /* 2710 */ 'l', 'd', 'a', 'd', 'd', 'l', 'h', 9, 0, |
| /* 2719 */ 'l', 'd', 's', 'm', 'i', 'n', 'l', 'h', 9, 0, |
| /* 2729 */ 'l', 'd', 'u', 'm', 'i', 'n', 'l', 'h', 9, 0, |
| /* 2739 */ 's', 'w', 'p', 'l', 'h', 9, 0, |
| /* 2746 */ 'l', 'd', 'c', 'l', 'r', 'l', 'h', 9, 0, |
| /* 2755 */ 'l', 'd', 'e', 'o', 'r', 'l', 'h', 9, 0, |
| /* 2764 */ 'c', 'a', 's', 'l', 'h', 9, 0, |
| /* 2771 */ 'l', 'd', 's', 'e', 't', 'l', 'h', 9, 0, |
| /* 2780 */ 's', 'q', 'd', 'm', 'u', 'l', 'h', 9, 0, |
| /* 2789 */ 's', 'q', 'r', 'd', 'm', 'u', 'l', 'h', 9, 0, |
| /* 2799 */ 's', 'm', 'u', 'l', 'h', 9, 0, |
| /* 2806 */ 'u', 'm', 'u', 'l', 'h', 9, 0, |
| /* 2813 */ 'l', 'd', 's', 'm', 'a', 'x', 'l', 'h', 9, 0, |
| /* 2823 */ 'l', 'd', 'u', 'm', 'a', 'x', 'l', 'h', 9, 0, |
| /* 2833 */ 'l', 'd', 's', 'm', 'i', 'n', 'h', 9, 0, |
| /* 2842 */ 'l', 'd', 'u', 'm', 'i', 'n', 'h', 9, 0, |
| /* 2851 */ 's', 'w', 'p', 'h', 9, 0, |
| /* 2857 */ 'l', 'd', '1', 'r', 'q', 'h', 9, 0, |
| /* 2865 */ 'l', 'd', '1', 'r', 'h', 9, 0, |
| /* 2872 */ 'l', 'd', 'a', 'r', 'h', 9, 0, |
| /* 2879 */ 'l', 'd', 'l', 'a', 'r', 'h', 9, 0, |
| /* 2887 */ 'l', 'd', 'r', 'h', 9, 0, |
| /* 2893 */ 'l', 'd', 'c', 'l', 'r', 'h', 9, 0, |
| /* 2901 */ 's', 't', 'l', 'l', 'r', 'h', 9, 0, |
| /* 2909 */ 's', 't', 'l', 'r', 'h', 9, 0, |
| /* 2916 */ 'l', 'd', 'e', 'o', 'r', 'h', 9, 0, |
| /* 2924 */ 'l', 'd', 'a', 'p', 'r', 'h', 9, 0, |
| /* 2932 */ 'l', 'd', 't', 'r', 'h', 9, 0, |
| /* 2939 */ 's', 't', 'r', 'h', 9, 0, |
| /* 2945 */ 's', 't', 't', 'r', 'h', 9, 0, |
| /* 2952 */ 'l', 'd', 'u', 'r', 'h', 9, 0, |
| /* 2959 */ 's', 't', 'l', 'u', 'r', 'h', 9, 0, |
| /* 2967 */ 'l', 'd', 'a', 'p', 'u', 'r', 'h', 9, 0, |
| /* 2976 */ 's', 't', 'u', 'r', 'h', 9, 0, |
| /* 2983 */ 'l', 'd', 'a', 'x', 'r', 'h', 9, 0, |
| /* 2991 */ 'l', 'd', 'x', 'r', 'h', 9, 0, |
| /* 2998 */ 's', 't', 'l', 'x', 'r', 'h', 9, 0, |
| /* 3006 */ 's', 't', 'x', 'r', 'h', 9, 0, |
| /* 3013 */ 'l', 'd', '1', 's', 'h', 9, 0, |
| /* 3020 */ 'l', 'd', 'f', 'f', '1', 's', 'h', 9, 0, |
| /* 3029 */ 'l', 'd', 'n', 'f', '1', 's', 'h', 9, 0, |
| /* 3038 */ 'c', 'a', 's', 'h', 9, 0, |
| /* 3044 */ 's', 'q', 'r', 'd', 'm', 'l', 's', 'h', 9, 0, |
| /* 3054 */ 'l', 'd', '1', 'r', 's', 'h', 9, 0, |
| /* 3062 */ 'l', 'd', 'r', 's', 'h', 9, 0, |
| /* 3069 */ 'l', 'd', 't', 'r', 's', 'h', 9, 0, |
| /* 3077 */ 'l', 'd', 'u', 'r', 's', 'h', 9, 0, |
| /* 3085 */ 'l', 'd', 'a', 'p', 'u', 'r', 's', 'h', 9, 0, |
| /* 3095 */ 'l', 'd', 's', 'e', 't', 'h', 9, 0, |
| /* 3103 */ 'c', 'n', 't', 'h', 9, 0, |
| /* 3109 */ 's', 'x', 't', 'h', 9, 0, |
| /* 3115 */ 'u', 'x', 't', 'h', 9, 0, |
| /* 3121 */ 'r', 'e', 'v', 'h', 9, 0, |
| /* 3127 */ 'l', 'd', 's', 'm', 'a', 'x', 'h', 9, 0, |
| /* 3136 */ 'l', 'd', 'u', 'm', 'a', 'x', 'h', 9, 0, |
| /* 3145 */ 'x', 'p', 'a', 'c', 'i', 9, 0, |
| /* 3152 */ 'p', 'u', 'n', 'p', 'k', 'h', 'i', 9, 0, |
| /* 3161 */ 's', 'u', 'n', 'p', 'k', 'h', 'i', 9, 0, |
| /* 3170 */ 'u', 'u', 'n', 'p', 'k', 'h', 'i', 9, 0, |
| /* 3179 */ 'c', 'm', 'h', 'i', 9, 0, |
| /* 3185 */ 'c', 'm', 'p', 'h', 'i', 9, 0, |
| /* 3192 */ 's', 'l', 'i', 9, 0, |
| /* 3197 */ 'm', 'v', 'n', 'i', 9, 0, |
| /* 3203 */ 's', 'r', 'i', 9, 0, |
| /* 3208 */ 'f', 'r', 'i', 'n', 't', 'i', 9, 0, |
| /* 3216 */ 'm', 'o', 'v', 'i', 9, 0, |
| /* 3222 */ 'b', 'r', 'k', 9, 0, |
| /* 3227 */ 'm', 'o', 'v', 'k', 9, 0, |
| /* 3233 */ 's', 'a', 'b', 'a', 'l', 9, 0, |
| /* 3240 */ 'u', 'a', 'b', 'a', 'l', 9, 0, |
| /* 3247 */ 'l', 'd', 'a', 'd', 'd', 'a', 'l', 9, 0, |
| /* 3256 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', 9, 0, |
| /* 3265 */ 's', 'm', 'l', 'a', 'l', 9, 0, |
| /* 3272 */ 'u', 'm', 'l', 'a', 'l', 9, 0, |
| /* 3279 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'l', 9, 0, |
| /* 3289 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'l', 9, 0, |
| /* 3299 */ 'c', 'a', 's', 'p', 'a', 'l', 9, 0, |
| /* 3307 */ 's', 'w', 'p', 'a', 'l', 9, 0, |
| /* 3314 */ 'l', 'd', 'c', 'l', 'r', 'a', 'l', 9, 0, |
| /* 3323 */ 'l', 'd', 'e', 'o', 'r', 'a', 'l', 9, 0, |
| /* 3332 */ 'c', 'a', 's', 'a', 'l', 9, 0, |
| /* 3339 */ 'l', 'd', 's', 'e', 't', 'a', 'l', 9, 0, |
| /* 3348 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'l', 9, 0, |
| /* 3358 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'l', 9, 0, |
| /* 3368 */ 't', 'b', 'l', 9, 0, |
| /* 3373 */ 's', 'm', 's', 'u', 'b', 'l', 9, 0, |
| /* 3381 */ 'u', 'm', 's', 'u', 'b', 'l', 9, 0, |
| /* 3389 */ 's', 's', 'u', 'b', 'l', 9, 0, |
| /* 3396 */ 'u', 's', 'u', 'b', 'l', 9, 0, |
| /* 3403 */ 's', 'a', 'b', 'd', 'l', 9, 0, |
| /* 3410 */ 'u', 'a', 'b', 'd', 'l', 9, 0, |
| /* 3417 */ 'l', 'd', 'a', 'd', 'd', 'l', 9, 0, |
| /* 3425 */ 's', 'm', 'a', 'd', 'd', 'l', 9, 0, |
| /* 3433 */ 'u', 'm', 'a', 'd', 'd', 'l', 9, 0, |
| /* 3441 */ 's', 'a', 'd', 'd', 'l', 9, 0, |
| /* 3448 */ 'u', 'a', 'd', 'd', 'l', 9, 0, |
| /* 3455 */ 'f', 'c', 's', 'e', 'l', 9, 0, |
| /* 3462 */ 'f', 't', 's', 's', 'e', 'l', 9, 0, |
| /* 3470 */ 's', 'q', 's', 'h', 'l', 9, 0, |
| /* 3477 */ 'u', 'q', 's', 'h', 'l', 9, 0, |
| /* 3484 */ 's', 'q', 'r', 's', 'h', 'l', 9, 0, |
| /* 3492 */ 'u', 'q', 'r', 's', 'h', 'l', 9, 0, |
| /* 3500 */ 's', 'r', 's', 'h', 'l', 9, 0, |
| /* 3507 */ 'u', 'r', 's', 'h', 'l', 9, 0, |
| /* 3514 */ 's', 's', 'h', 'l', 9, 0, |
| /* 3520 */ 'u', 's', 'h', 'l', 9, 0, |
| /* 3526 */ 's', 's', 'h', 'l', 'l', 9, 0, |
| /* 3533 */ 'u', 's', 'h', 'l', 'l', 9, 0, |
| /* 3540 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', 9, 0, |
| /* 3549 */ 'p', 'm', 'u', 'l', 'l', 9, 0, |
| /* 3556 */ 's', 'm', 'u', 'l', 'l', 9, 0, |
| /* 3563 */ 'u', 'm', 'u', 'l', 'l', 9, 0, |
| /* 3570 */ 'l', 'd', 's', 'm', 'i', 'n', 'l', 9, 0, |
| /* 3579 */ 'l', 'd', 'u', 'm', 'i', 'n', 'l', 9, 0, |
| /* 3588 */ 'a', 'd', 'd', 'p', 'l', 9, 0, |
| /* 3595 */ 'c', 'a', 's', 'p', 'l', 9, 0, |
| /* 3602 */ 's', 'w', 'p', 'l', 9, 0, |
| /* 3608 */ 'l', 'd', 'c', 'l', 'r', 'l', 9, 0, |
| /* 3616 */ 'l', 'd', 'e', 'o', 'r', 'l', 9, 0, |
| /* 3624 */ 'c', 'a', 's', 'l', 9, 0, |
| /* 3630 */ 'b', 's', 'l', 9, 0, |
| /* 3635 */ 's', 'q', 'd', 'm', 'l', 's', 'l', 9, 0, |
| /* 3644 */ 's', 'm', 'l', 's', 'l', 9, 0, |
| /* 3651 */ 'u', 'm', 'l', 's', 'l', 9, 0, |
| /* 3658 */ 's', 'y', 's', 'l', 9, 0, |
| /* 3664 */ 'l', 'd', 's', 'e', 't', 'l', 9, 0, |
| /* 3672 */ 'f', 'c', 'v', 't', 'l', 9, 0, |
| /* 3679 */ 'f', 'm', 'u', 'l', 9, 0, |
| /* 3685 */ 'f', 'n', 'm', 'u', 'l', 9, 0, |
| /* 3692 */ 'p', 'm', 'u', 'l', 9, 0, |
| /* 3698 */ 'f', 't', 's', 'm', 'u', 'l', 9, 0, |
| /* 3706 */ 'a', 'd', 'd', 'v', 'l', 9, 0, |
| /* 3713 */ 'r', 'd', 'v', 'l', 9, 0, |
| /* 3719 */ 'l', 'd', 's', 'm', 'a', 'x', 'l', 9, 0, |
| /* 3728 */ 'l', 'd', 'u', 'm', 'a', 'x', 'l', 9, 0, |
| /* 3737 */ 's', 'h', 'a', '1', 'm', 9, 0, |
| /* 3744 */ 's', 'b', 'f', 'm', 9, 0, |
| /* 3750 */ 'u', 'b', 'f', 'm', 9, 0, |
| /* 3756 */ 'p', 'r', 'f', 'm', 9, 0, |
| /* 3762 */ 'f', 'm', 'i', 'n', 'n', 'm', 9, 0, |
| /* 3770 */ 'f', 'm', 'a', 'x', 'n', 'm', 9, 0, |
| /* 3778 */ 'd', 'u', 'p', 'm', 9, 0, |
| /* 3784 */ 'f', 'r', 'i', 'n', 't', 'm', 9, 0, |
| /* 3792 */ 'p', 'r', 'f', 'u', 'm', 9, 0, |
| /* 3799 */ 'r', 's', 'u', 'b', 'h', 'n', 9, 0, |
| /* 3807 */ 'r', 'a', 'd', 'd', 'h', 'n', 9, 0, |
| /* 3815 */ 'f', 'm', 'i', 'n', 9, 0, |
| /* 3821 */ 'l', 'd', 's', 'm', 'i', 'n', 9, 0, |
| /* 3829 */ 'l', 'd', 'u', 'm', 'i', 'n', 9, 0, |
| /* 3837 */ 'b', 'r', 'k', 'n', 9, 0, |
| /* 3843 */ 'c', 'c', 'm', 'n', 9, 0, |
| /* 3849 */ 'e', 'o', 'n', 9, 0, |
| /* 3854 */ 's', 'q', 's', 'h', 'r', 'n', 9, 0, |
| /* 3862 */ 'u', 'q', 's', 'h', 'r', 'n', 9, 0, |
| /* 3870 */ 's', 'q', 'r', 's', 'h', 'r', 'n', 9, 0, |
| /* 3879 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', 9, 0, |
| /* 3888 */ 'o', 'r', 'n', 9, 0, |
| /* 3893 */ 'f', 'r', 'i', 'n', 't', 'n', 9, 0, |
| /* 3901 */ 'f', 'c', 'v', 't', 'n', 9, 0, |
| /* 3908 */ 's', 'q', 'x', 't', 'n', 9, 0, |
| /* 3915 */ 'u', 'q', 'x', 't', 'n', 9, 0, |
| /* 3922 */ 's', 'q', 's', 'h', 'r', 'u', 'n', 9, 0, |
| /* 3931 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', 9, 0, |
| /* 3941 */ 's', 'q', 'x', 't', 'u', 'n', 9, 0, |
| /* 3949 */ 'm', 'o', 'v', 'n', 9, 0, |
| /* 3955 */ 'f', 'c', 'v', 't', 'x', 'n', 9, 0, |
| /* 3963 */ 'w', 'h', 'i', 'l', 'e', 'l', 'o', 9, 0, |
| /* 3972 */ 'p', 'u', 'n', 'p', 'k', 'l', 'o', 9, 0, |
| /* 3981 */ 's', 'u', 'n', 'p', 'k', 'l', 'o', 9, 0, |
| /* 3990 */ 'u', 'u', 'n', 'p', 'k', 'l', 'o', 9, 0, |
| /* 3999 */ 'c', 'm', 'p', 'l', 'o', 9, 0, |
| /* 4006 */ 'f', 'c', 'm', 'u', 'o', 9, 0, |
| /* 4013 */ 's', 'h', 'a', '1', 'p', 9, 0, |
| /* 4020 */ 's', 'q', 'd', 'e', 'c', 'p', 9, 0, |
| /* 4028 */ 'u', 'q', 'd', 'e', 'c', 'p', 9, 0, |
| /* 4036 */ 's', 'q', 'i', 'n', 'c', 'p', 9, 0, |
| /* 4044 */ 'u', 'q', 'i', 'n', 'c', 'p', 9, 0, |
| /* 4052 */ 'f', 'a', 'd', 'd', 'p', 9, 0, |
| /* 4059 */ 'l', 'd', 'p', 9, 0, |
| /* 4064 */ 's', 'a', 'd', 'a', 'l', 'p', 9, 0, |
| /* 4072 */ 'u', 'a', 'd', 'a', 'l', 'p', 9, 0, |
| /* 4080 */ 's', 'a', 'd', 'd', 'l', 'p', 9, 0, |
| /* 4088 */ 'u', 'a', 'd', 'd', 'l', 'p', 9, 0, |
| /* 4096 */ 'f', 'c', 'c', 'm', 'p', 9, 0, |
| /* 4103 */ 'f', 'c', 'm', 'p', 9, 0, |
| /* 4109 */ 'f', 'm', 'i', 'n', 'n', 'm', 'p', 9, 0, |
| /* 4118 */ 'f', 'm', 'a', 'x', 'n', 'm', 'p', 9, 0, |
| /* 4127 */ 'l', 'd', 'n', 'p', 9, 0, |
| /* 4133 */ 'f', 'm', 'i', 'n', 'p', 9, 0, |
| /* 4140 */ 's', 'm', 'i', 'n', 'p', 9, 0, |
| /* 4147 */ 'u', 'm', 'i', 'n', 'p', 9, 0, |
| /* 4154 */ 's', 't', 'n', 'p', 9, 0, |
| /* 4160 */ 'a', 'd', 'r', 'p', 9, 0, |
| /* 4166 */ 'c', 'a', 's', 'p', 9, 0, |
| /* 4172 */ 'c', 'n', 't', 'p', 9, 0, |
| /* 4178 */ 'f', 'r', 'i', 'n', 't', 'p', 9, 0, |
| /* 4186 */ 's', 't', 'p', 9, 0, |
| /* 4191 */ 'f', 'd', 'u', 'p', 9, 0, |
| /* 4197 */ 's', 'w', 'p', 9, 0, |
| /* 4202 */ 'l', 'd', 'a', 'x', 'p', 9, 0, |
| /* 4209 */ 'f', 'm', 'a', 'x', 'p', 9, 0, |
| /* 4216 */ 's', 'm', 'a', 'x', 'p', 9, 0, |
| /* 4223 */ 'u', 'm', 'a', 'x', 'p', 9, 0, |
| /* 4230 */ 'l', 'd', 'x', 'p', 9, 0, |
| /* 4236 */ 's', 't', 'l', 'x', 'p', 9, 0, |
| /* 4243 */ 's', 't', 'x', 'p', 9, 0, |
| /* 4249 */ 'f', 'c', 'm', 'e', 'q', 9, 0, |
| /* 4256 */ 'c', 't', 'e', 'r', 'm', 'e', 'q', 9, 0, |
| /* 4265 */ 'c', 'm', 'p', 'e', 'q', 9, 0, |
| /* 4272 */ 'l', 'd', '1', 'r', 9, 0, |
| /* 4278 */ 'l', 'd', '2', 'r', 9, 0, |
| /* 4284 */ 'l', 'd', '3', 'r', 9, 0, |
| /* 4290 */ 'l', 'd', '4', 'r', 9, 0, |
| /* 4296 */ 'l', 'd', 'a', 'r', 9, 0, |
| /* 4302 */ 'l', 'd', 'l', 'a', 'r', 9, 0, |
| /* 4309 */ 'x', 'a', 'r', 9, 0, |
| /* 4314 */ 'f', 's', 'u', 'b', 'r', 9, 0, |
| /* 4321 */ 'a', 'd', 'r', 9, 0, |
| /* 4326 */ 'l', 'd', 'r', 9, 0, |
| /* 4331 */ 'r', 'd', 'f', 'f', 'r', 9, 0, |
| /* 4338 */ 'w', 'r', 'f', 'f', 'r', 9, 0, |
| /* 4345 */ 's', 'r', 's', 'h', 'r', 9, 0, |
| /* 4352 */ 'u', 'r', 's', 'h', 'r', 9, 0, |
| /* 4359 */ 's', 's', 'h', 'r', 9, 0, |
| /* 4365 */ 'u', 's', 'h', 'r', 9, 0, |
| /* 4371 */ 'b', 'l', 'r', 9, 0, |
| /* 4376 */ 'l', 'd', 'c', 'l', 'r', 9, 0, |
| /* 4383 */ 's', 't', 'l', 'l', 'r', 9, 0, |
| /* 4390 */ 'l', 's', 'l', 'r', 9, 0, |
| /* 4396 */ 's', 't', 'l', 'r', 9, 0, |
| /* 4402 */ 'l', 'd', 'e', 'o', 'r', 9, 0, |
| /* 4409 */ 'n', 'o', 'r', 9, 0, |
| /* 4414 */ 'r', 'o', 'r', 9, 0, |
| /* 4419 */ 'l', 'd', 'a', 'p', 'r', 9, 0, |
| /* 4426 */ 'o', 'r', 'r', 9, 0, |
| /* 4431 */ 'a', 's', 'r', 'r', 9, 0, |
| /* 4437 */ 'l', 's', 'r', 'r', 9, 0, |
| /* 4443 */ 'a', 's', 'r', 9, 0, |
| /* 4448 */ 'l', 's', 'r', 9, 0, |
| /* 4453 */ 'm', 's', 'r', 9, 0, |
| /* 4458 */ 'i', 'n', 's', 'r', 9, 0, |
| /* 4464 */ 'l', 'd', 't', 'r', 9, 0, |
| /* 4470 */ 's', 't', 'r', 9, 0, |
| /* 4475 */ 's', 't', 't', 'r', 9, 0, |
| /* 4481 */ 'e', 'x', 't', 'r', 9, 0, |
| /* 4487 */ 'l', 'd', 'u', 'r', 9, 0, |
| /* 4493 */ 's', 't', 'l', 'u', 'r', 9, 0, |
| /* 4500 */ 'l', 'd', 'a', 'p', 'u', 'r', 9, 0, |
| /* 4508 */ 's', 't', 'u', 'r', 9, 0, |
| /* 4514 */ 'f', 'd', 'i', 'v', 'r', 9, 0, |
| /* 4521 */ 's', 'd', 'i', 'v', 'r', 9, 0, |
| /* 4528 */ 'u', 'd', 'i', 'v', 'r', 9, 0, |
| /* 4535 */ 'l', 'd', 'a', 'x', 'r', 9, 0, |
| /* 4542 */ 'l', 'd', 'x', 'r', 9, 0, |
| /* 4548 */ 's', 't', 'l', 'x', 'r', 9, 0, |
| /* 4555 */ 's', 't', 'x', 'r', 9, 0, |
| /* 4561 */ 'c', 'a', 's', 9, 0, |
| /* 4566 */ 'b', 'r', 'k', 'a', 's', 9, 0, |
| /* 4573 */ 'b', 'r', 'k', 'p', 'a', 's', 9, 0, |
| /* 4581 */ 'f', 'c', 'v', 't', 'a', 's', 9, 0, |
| /* 4589 */ 'f', 'a', 'b', 's', 9, 0, |
| /* 4595 */ 's', 'q', 'a', 'b', 's', 9, 0, |
| /* 4602 */ 'b', 'r', 'k', 'b', 's', 9, 0, |
| /* 4609 */ 'b', 'r', 'k', 'p', 'b', 's', 9, 0, |
| /* 4617 */ 's', 'u', 'b', 's', 9, 0, |
| /* 4623 */ 's', 'b', 'c', 's', 9, 0, |
| /* 4629 */ 'a', 'd', 'c', 's', 9, 0, |
| /* 4635 */ 'b', 'i', 'c', 's', 9, 0, |
| /* 4641 */ 'a', 'd', 'd', 's', 9, 0, |
| /* 4647 */ 'n', 'a', 'n', 'd', 's', 9, 0, |
| /* 4654 */ 'p', 't', 'r', 'u', 'e', 's', 9, 0, |
| /* 4662 */ 'c', 'm', 'h', 's', 9, 0, |
| /* 4668 */ 'c', 'm', 'p', 'h', 's', 9, 0, |
| /* 4675 */ 'c', 'l', 's', 9, 0, |
| /* 4680 */ 'w', 'h', 'i', 'l', 'e', 'l', 's', 9, 0, |
| /* 4689 */ 'f', 'm', 'l', 's', 9, 0, |
| /* 4695 */ 'f', 'n', 'm', 'l', 's', 9, 0, |
| /* 4702 */ 'c', 'm', 'p', 'l', 's', 9, 0, |
| /* 4709 */ 'f', 'c', 'v', 't', 'm', 's', 9, 0, |
| /* 4717 */ 'i', 'n', 's', 9, 0, |
| /* 4722 */ 'b', 'r', 'k', 'n', 's', 9, 0, |
| /* 4729 */ 'o', 'r', 'n', 's', 9, 0, |
| /* 4735 */ 'f', 'c', 'v', 't', 'n', 's', 9, 0, |
| /* 4743 */ 'f', 'r', 'e', 'c', 'p', 's', 9, 0, |
| /* 4751 */ 'f', 'c', 'v', 't', 'p', 's', 9, 0, |
| /* 4759 */ 'r', 'd', 'f', 'f', 'r', 's', 9, 0, |
| /* 4767 */ 'm', 'r', 's', 9, 0, |
| /* 4772 */ 'e', 'o', 'r', 's', 9, 0, |
| /* 4778 */ 'n', 'o', 'r', 's', 9, 0, |
| /* 4784 */ 'o', 'r', 'r', 's', 9, 0, |
| /* 4790 */ 'f', 'r', 's', 'q', 'r', 't', 's', 9, 0, |
| /* 4799 */ 's', 'y', 's', 9, 0, |
| /* 4804 */ 'f', 'c', 'v', 't', 'z', 's', 9, 0, |
| /* 4812 */ 'f', 'j', 'c', 'v', 't', 'z', 's', 9, 0, |
| /* 4821 */ 'c', 'o', 'm', 'p', 'a', 'c', 't', 9, 0, |
| /* 4830 */ 'r', 'e', 't', 9, 0, |
| /* 4835 */ 'l', 'd', 's', 'e', 't', 9, 0, |
| /* 4842 */ 'f', 'a', 'c', 'g', 't', 9, 0, |
| /* 4849 */ 'f', 'c', 'm', 'g', 't', 9, 0, |
| /* 4856 */ 'c', 'm', 'p', 'g', 't', 9, 0, |
| /* 4863 */ 'r', 'b', 'i', 't', 9, 0, |
| /* 4869 */ 'w', 'h', 'i', 'l', 'e', 'l', 't', 9, 0, |
| /* 4878 */ 'h', 'l', 't', 9, 0, |
| /* 4883 */ 'f', 'c', 'm', 'l', 't', 9, 0, |
| /* 4890 */ 'c', 'm', 'p', 'l', 't', 9, 0, |
| /* 4897 */ 'c', 'n', 't', 9, 0, |
| /* 4902 */ 'h', 'i', 'n', 't', 9, 0, |
| /* 4908 */ 's', 'd', 'o', 't', 9, 0, |
| /* 4914 */ 'u', 'd', 'o', 't', 9, 0, |
| /* 4920 */ 'c', 'n', 'o', 't', 9, 0, |
| /* 4926 */ 'f', 's', 'q', 'r', 't', 9, 0, |
| /* 4933 */ 'p', 't', 'e', 's', 't', 9, 0, |
| /* 4940 */ 'p', 'f', 'i', 'r', 's', 't', 9, 0, |
| /* 4948 */ 'c', 'm', 't', 's', 't', 9, 0, |
| /* 4955 */ 'f', 'c', 'v', 't', 9, 0, |
| /* 4961 */ 'p', 'n', 'e', 'x', 't', 9, 0, |
| /* 4968 */ 'f', 'c', 'v', 't', 'a', 'u', 9, 0, |
| /* 4976 */ 's', 'q', 's', 'h', 'l', 'u', 9, 0, |
| /* 4984 */ 'f', 'c', 'v', 't', 'm', 'u', 9, 0, |
| /* 4992 */ 'f', 'c', 'v', 't', 'n', 'u', 9, 0, |
| /* 5000 */ 'f', 'c', 'v', 't', 'p', 'u', 9, 0, |
| /* 5008 */ 'f', 'c', 'v', 't', 'z', 'u', 9, 0, |
| /* 5016 */ 'f', 'a', 'd', 'd', 'v', 9, 0, |
| /* 5023 */ 's', 'a', 'd', 'd', 'v', 9, 0, |
| /* 5030 */ 'u', 'a', 'd', 'd', 'v', 9, 0, |
| /* 5037 */ 'a', 'n', 'd', 'v', 9, 0, |
| /* 5043 */ 'r', 'e', 'v', 9, 0, |
| /* 5048 */ 'f', 'd', 'i', 'v', 9, 0, |
| /* 5054 */ 's', 'd', 'i', 'v', 9, 0, |
| /* 5060 */ 'u', 'd', 'i', 'v', 9, 0, |
| /* 5066 */ 's', 'a', 'd', 'd', 'l', 'v', 9, 0, |
| /* 5074 */ 'u', 'a', 'd', 'd', 'l', 'v', 9, 0, |
| /* 5082 */ 'f', 'm', 'i', 'n', 'n', 'm', 'v', 9, 0, |
| /* 5091 */ 'f', 'm', 'a', 'x', 'n', 'm', 'v', 9, 0, |
| /* 5100 */ 'f', 'm', 'i', 'n', 'v', 9, 0, |
| /* 5107 */ 's', 'm', 'i', 'n', 'v', 9, 0, |
| /* 5114 */ 'u', 'm', 'i', 'n', 'v', 9, 0, |
| /* 5121 */ 'c', 's', 'i', 'n', 'v', 9, 0, |
| /* 5128 */ 'f', 'm', 'o', 'v', 9, 0, |
| /* 5134 */ 's', 'm', 'o', 'v', 9, 0, |
| /* 5140 */ 'u', 'm', 'o', 'v', 9, 0, |
| /* 5146 */ 'e', 'o', 'r', 'v', 9, 0, |
| /* 5152 */ 'f', 'm', 'a', 'x', 'v', 9, 0, |
| /* 5159 */ 's', 'm', 'a', 'x', 'v', 9, 0, |
| /* 5166 */ 'u', 'm', 'a', 'x', 'v', 9, 0, |
| /* 5173 */ 'l', 'd', '1', 'w', 9, 0, |
| /* 5179 */ 'l', 'd', 'f', 'f', '1', 'w', 9, 0, |
| /* 5187 */ 'l', 'd', 'n', 'f', '1', 'w', 9, 0, |
| /* 5195 */ 'l', 'd', 'n', 't', '1', 'w', 9, 0, |
| /* 5203 */ 's', 't', 'n', 't', '1', 'w', 9, 0, |
| /* 5211 */ 's', 't', '1', 'w', 9, 0, |
| /* 5217 */ 'c', 'r', 'c', '3', '2', 'w', 9, 0, |
| /* 5225 */ 'l', 'd', '2', 'w', 9, 0, |
| /* 5231 */ 's', 't', '2', 'w', 9, 0, |
| /* 5237 */ 'l', 'd', '3', 'w', 9, 0, |
| /* 5243 */ 's', 't', '3', 'w', 9, 0, |
| /* 5249 */ 'l', 'd', '4', 'w', 9, 0, |
| /* 5255 */ 's', 't', '4', 'w', 9, 0, |
| /* 5261 */ 's', 's', 'u', 'b', 'w', 9, 0, |
| /* 5268 */ 'u', 's', 'u', 'b', 'w', 9, 0, |
| /* 5275 */ 'c', 'r', 'c', '3', '2', 'c', 'w', 9, 0, |
| /* 5284 */ 's', 'q', 'd', 'e', 'c', 'w', 9, 0, |
| /* 5292 */ 'u', 'q', 'd', 'e', 'c', 'w', 9, 0, |
| /* 5300 */ 's', 'q', 'i', 'n', 'c', 'w', 9, 0, |
| /* 5308 */ 'u', 'q', 'i', 'n', 'c', 'w', 9, 0, |
| /* 5316 */ 's', 'a', 'd', 'd', 'w', 9, 0, |
| /* 5323 */ 'u', 'a', 'd', 'd', 'w', 9, 0, |
| /* 5330 */ 'p', 'r', 'f', 'w', 9, 0, |
| /* 5336 */ 'l', 'd', '1', 'r', 'q', 'w', 9, 0, |
| /* 5344 */ 'l', 'd', '1', 'r', 'w', 9, 0, |
| /* 5351 */ 'l', 'd', '1', 's', 'w', 9, 0, |
| /* 5358 */ 'l', 'd', 'f', 'f', '1', 's', 'w', 9, 0, |
| /* 5367 */ 'l', 'd', 'n', 'f', '1', 's', 'w', 9, 0, |
| /* 5376 */ 'l', 'd', 'p', 's', 'w', 9, 0, |
| /* 5383 */ 'l', 'd', '1', 'r', 's', 'w', 9, 0, |
| /* 5391 */ 'l', 'd', 'r', 's', 'w', 9, 0, |
| /* 5398 */ 'l', 'd', 't', 'r', 's', 'w', 9, 0, |
| /* 5406 */ 'l', 'd', 'u', 'r', 's', 'w', 9, 0, |
| /* 5414 */ 'l', 'd', 'a', 'p', 'u', 'r', 's', 'w', 9, 0, |
| /* 5424 */ 'c', 'n', 't', 'w', 9, 0, |
| /* 5430 */ 's', 'x', 't', 'w', 9, 0, |
| /* 5436 */ 'u', 'x', 't', 'w', 9, 0, |
| /* 5442 */ 'r', 'e', 'v', 'w', 9, 0, |
| /* 5448 */ 'c', 'r', 'c', '3', '2', 'x', 9, 0, |
| /* 5456 */ 'b', 'c', 'a', 'x', 9, 0, |
| /* 5462 */ 'f', 'm', 'a', 'x', 9, 0, |
| /* 5468 */ 'l', 'd', 's', 'm', 'a', 'x', 9, 0, |
| /* 5476 */ 'l', 'd', 'u', 'm', 'a', 'x', 9, 0, |
| /* 5484 */ 't', 'b', 'x', 9, 0, |
| /* 5489 */ 'c', 'r', 'c', '3', '2', 'c', 'x', 9, 0, |
| /* 5498 */ 'i', 'n', 'd', 'e', 'x', 9, 0, |
| /* 5505 */ 'c', 'l', 'r', 'e', 'x', 9, 0, |
| /* 5512 */ 'm', 'o', 'v', 'p', 'r', 'f', 'x', 9, 0, |
| /* 5521 */ 'f', 'm', 'u', 'l', 'x', 9, 0, |
| /* 5528 */ 'f', 'r', 'e', 'c', 'p', 'x', 9, 0, |
| /* 5536 */ 'f', 'r', 'i', 'n', 't', 'x', 9, 0, |
| /* 5544 */ 's', 'm', '4', 'e', 'k', 'e', 'y', 9, 0, |
| /* 5553 */ 'f', 'c', 'p', 'y', 9, 0, |
| /* 5559 */ 'b', 'r', 'a', 'a', 'z', 9, 0, |
| /* 5566 */ 'b', 'l', 'r', 'a', 'a', 'z', 9, 0, |
| /* 5574 */ 'b', 'r', 'a', 'b', 'z', 9, 0, |
| /* 5581 */ 'b', 'l', 'r', 'a', 'b', 'z', 9, 0, |
| /* 5589 */ 'c', 'b', 'z', 9, 0, |
| /* 5594 */ 't', 'b', 'z', 9, 0, |
| /* 5599 */ 'c', 'l', 'z', 9, 0, |
| /* 5604 */ 'c', 'b', 'n', 'z', 9, 0, |
| /* 5610 */ 't', 'b', 'n', 'z', 9, 0, |
| /* 5616 */ 'f', 'r', 'i', 'n', 't', 'z', 9, 0, |
| /* 5624 */ 'm', 'o', 'v', 'z', 9, 0, |
| /* 5630 */ '.', 't', 'l', 's', 'd', 'e', 's', 'c', 'c', 'a', 'l', 'l', 32, 0, |
| /* 5644 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0, |
| /* 5675 */ 'b', '.', 0, |
| /* 5678 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, |
| /* 5702 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, |
| /* 5727 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0, |
| /* 5750 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0, |
| /* 5773 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0, |
| /* 5795 */ 'p', 'a', 'c', 'i', 'a', '1', '7', '1', '6', 0, |
| /* 5805 */ 'a', 'u', 't', 'i', 'a', '1', '7', '1', '6', 0, |
| /* 5815 */ 'p', 'a', 'c', 'i', 'b', '1', '7', '1', '6', 0, |
| /* 5825 */ 'a', 'u', 't', 'i', 'b', '1', '7', '1', '6', 0, |
| /* 5835 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, |
| /* 5848 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, |
| /* 5855 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, |
| /* 5865 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, |
| /* 5875 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, |
| /* 5890 */ 'e', 'r', 'e', 't', 'a', 'a', 0, |
| /* 5897 */ 'e', 'r', 'e', 't', 'a', 'b', 0, |
| /* 5904 */ 'x', 'p', 'a', 'c', 'l', 'r', 'i', 0, |
| /* 5912 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, |
| /* 5926 */ 'p', 'a', 'c', 'i', 'a', 's', 'p', 0, |
| /* 5934 */ 'a', 'u', 't', 'i', 'a', 's', 'p', 0, |
| /* 5942 */ 'p', 'a', 'c', 'i', 'b', 's', 'p', 0, |
| /* 5950 */ 'a', 'u', 't', 'i', 'b', 's', 'p', 0, |
| /* 5958 */ 's', 'e', 't', 'f', 'f', 'r', 0, |
| /* 5965 */ 'd', 'r', 'p', 's', 0, |
| /* 5970 */ 'e', 'r', 'e', 't', 0, |
| /* 5975 */ 'c', 'f', 'i', 'n', 'v', 0, |
| /* 5981 */ 'p', 'a', 'c', 'i', 'a', 'z', 0, |
| /* 5988 */ 'a', 'u', 't', 'i', 'a', 'z', 0, |
| /* 5995 */ 'p', 'a', 'c', 'i', 'b', 'z', 0, |
| /* 6002 */ 'a', 'u', 't', 'i', 'b', 'z', 0, |
| }; |
| |
| static const uint32_t OpInfo0[] = { |
| 0U, // PHI |
| 0U, // INLINEASM |
| 0U, // CFI_INSTRUCTION |
| 0U, // EH_LABEL |
| 0U, // GC_LABEL |
| 0U, // ANNOTATION_LABEL |
| 0U, // KILL |
| 0U, // EXTRACT_SUBREG |
| 0U, // INSERT_SUBREG |
| 0U, // IMPLICIT_DEF |
| 0U, // SUBREG_TO_REG |
| 0U, // COPY_TO_REGCLASS |
| 5856U, // DBG_VALUE |
| 5866U, // DBG_LABEL |
| 0U, // REG_SEQUENCE |
| 0U, // COPY |
| 5849U, // BUNDLE |
| 5876U, // LIFETIME_START |
| 5836U, // LIFETIME_END |
| 0U, // STACKMAP |
| 5913U, // FENTRY_CALL |
| 0U, // PATCHPOINT |
| 0U, // LOAD_STACK_GUARD |
| 0U, // STATEPOINT |
| 0U, // LOCAL_ESCAPE |
| 0U, // FAULTING_OP |
| 0U, // PATCHABLE_OP |
| 5728U, // PATCHABLE_FUNCTION_ENTER |
| 5645U, // PATCHABLE_RET |
| 5774U, // PATCHABLE_FUNCTION_EXIT |
| 5751U, // PATCHABLE_TAIL_CALL |
| 5703U, // PATCHABLE_EVENT_CALL |
| 5679U, // PATCHABLE_TYPED_EVENT_CALL |
| 0U, // ICALL_BRANCH_FUNNEL |
| 0U, // G_ADD |
| 0U, // G_SUB |
| 0U, // G_MUL |
| 0U, // G_SDIV |
| 0U, // G_UDIV |
| 0U, // G_SREM |
| 0U, // G_UREM |
| 0U, // G_AND |
| 0U, // G_OR |
| 0U, // G_XOR |
| 0U, // G_IMPLICIT_DEF |
| 0U, // G_PHI |
| 0U, // G_FRAME_INDEX |
| 0U, // G_GLOBAL_VALUE |
| 0U, // G_EXTRACT |
| 0U, // G_UNMERGE_VALUES |
| 0U, // G_INSERT |
| 0U, // G_MERGE_VALUES |
| 0U, // G_PTRTOINT |
| 0U, // G_INTTOPTR |
| 0U, // G_BITCAST |
| 0U, // G_LOAD |
| 0U, // G_SEXTLOAD |
| 0U, // G_ZEXTLOAD |
| 0U, // G_STORE |
| 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 0U, // G_ATOMIC_CMPXCHG |
| 0U, // G_ATOMICRMW_XCHG |
| 0U, // G_ATOMICRMW_ADD |
| 0U, // G_ATOMICRMW_SUB |
| 0U, // G_ATOMICRMW_AND |
| 0U, // G_ATOMICRMW_NAND |
| 0U, // G_ATOMICRMW_OR |
| 0U, // G_ATOMICRMW_XOR |
| 0U, // G_ATOMICRMW_MAX |
| 0U, // G_ATOMICRMW_MIN |
| 0U, // G_ATOMICRMW_UMAX |
| 0U, // G_ATOMICRMW_UMIN |
| 0U, // G_BRCOND |
| 0U, // G_BRINDIRECT |
| 0U, // G_INTRINSIC |
| 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
| 0U, // G_ANYEXT |
| 0U, // G_TRUNC |
| 0U, // G_CONSTANT |
| 0U, // G_FCONSTANT |
| 0U, // G_VASTART |
| 0U, // G_VAARG |
| 0U, // G_SEXT |
| 0U, // G_ZEXT |
| 0U, // G_SHL |
| 0U, // G_LSHR |
| 0U, // G_ASHR |
| 0U, // G_ICMP |
| 0U, // G_FCMP |
| 0U, // G_SELECT |
| 0U, // G_UADDE |
| 0U, // G_USUBE |
| 0U, // G_SADDO |
| 0U, // G_SSUBO |
| 0U, // G_UMULO |
| 0U, // G_SMULO |
| 0U, // G_UMULH |
| 0U, // G_SMULH |
| 0U, // G_FADD |
| 0U, // G_FSUB |
| 0U, // G_FMUL |
| 0U, // G_FMA |
| 0U, // G_FDIV |
| 0U, // G_FREM |
| 0U, // G_FPOW |
| 0U, // G_FEXP |
| 0U, // G_FEXP2 |
| 0U, // G_FLOG |
| 0U, // G_FLOG2 |
| 0U, // G_FNEG |
| 0U, // G_FPEXT |
| 0U, // G_FPTRUNC |
| 0U, // G_FPTOSI |
| 0U, // G_FPTOUI |
| 0U, // G_SITOFP |
| 0U, // G_UITOFP |
| 0U, // G_FABS |
| 0U, // G_GEP |
| 0U, // G_PTR_MASK |
| 0U, // G_BR |
| 0U, // G_INSERT_VECTOR_ELT |
| 0U, // G_EXTRACT_VECTOR_ELT |
| 0U, // G_SHUFFLE_VECTOR |
| 0U, // G_BSWAP |
| 0U, // G_ADDRSPACE_CAST |
| 0U, // G_BLOCK_ADDR |
| 12783U, // ABS_ZPmZ_B |
| 20975U, // ABS_ZPmZ_D |
| 2181591535U, // ABS_ZPmZ_H |
| 37359U, // ABS_ZPmZ_S |
| 68202991U, // ABSv16i8 |
| 2248200687U, // ABSv1i64 |
| 68727279U, // ABSv2i32 |
| 2216735215U, // ABSv2i64 |
| 69775855U, // ABSv4i16 |
| 2217783791U, // ABSv4i32 |
| 70824431U, // ABSv8i16 |
| 2218832367U, // ABSv8i8 |
| 100717078U, // ADCSWr |
| 100717078U, // ADCSXr |
| 100714262U, // ADCWr |
| 100714262U, // ADCXr |
| 2216210145U, // ADDHNv2i64_v2i32 |
| 2284904787U, // ADDHNv2i64_v4i32 |
| 69775073U, // ADDHNv4i32_v4i16 |
| 137945427U, // ADDHNv4i32_v8i16 |
| 2282807635U, // ADDHNv8i16_v16i8 |
| 2218831585U, // ADDHNv8i16_v8i8 |
| 100716037U, // ADDPL_XXI |
| 68202454U, // ADDPv16i8 |
| 2216210390U, // ADDPv2i32 |
| 2216734678U, // ADDPv2i64 |
| 2214645718U, // ADDPv2i64p |
| 69775318U, // ADDPv4i16 |
| 70299606U, // ADDPv4i32 |
| 2218307542U, // ADDPv8i16 |
| 2218831830U, // ADDPv8i8 |
| 100717090U, // ADDSWri |
| 0U, // ADDSWrr |
| 100717090U, // ADDSWrs |
| 100717090U, // ADDSWrx |
| 100717090U, // ADDSXri |
| 0U, // ADDSXrr |
| 100717090U, // ADDSXrs |
| 100717090U, // ADDSXrx |
| 100717090U, // ADDSXrx64 |
| 100716155U, // ADDVL_XXI |
| 67163034U, // ADDVv16i8v |
| 67163034U, // ADDVv4i16v |
| 2214646682U, // ADDVv4i32v |
| 67163034U, // ADDVv8i16v |
| 2214646682U, // ADDVv8i8v |
| 100714463U, // ADDWri |
| 0U, // ADDWrr |
| 100714463U, // ADDWrs |
| 100714463U, // ADDWrx |
| 100714463U, // ADDXri |
| 0U, // ADDXrr |
| 100714463U, // ADDXrs |
| 100714463U, // ADDXrx |
| 100714463U, // ADDXrx64 |
| 167782367U, // ADD_ZI_B |
| 201344991U, // ADD_ZI_D |
| 239626207U, // ADD_ZI_H |
| 268470239U, // ADD_ZI_S |
| 302000095U, // ADD_ZPmZ_B |
| 302008287U, // ADD_ZPmZ_D |
| 2186307551U, // ADD_ZPmZ_H |
| 302024671U, // ADD_ZPmZ_S |
| 167782367U, // ADD_ZZZ_B |
| 201344991U, // ADD_ZZZ_D |
| 2387109855U, // ADD_ZZZ_H |
| 268470239U, // ADD_ZZZ_S |
| 0U, // ADDlowTLS |
| 68200415U, // ADDv16i8 |
| 100714463U, // ADDv1i64 |
| 2216208351U, // ADDv2i32 |
| 2216732639U, // ADDv2i64 |
| 69773279U, // ADDv4i16 |
| 70297567U, // ADDv4i32 |
| 2218305503U, // ADDv8i16 |
| 2218829791U, // ADDv8i8 |
| 0U, // ADJCALLSTACKDOWN |
| 0U, // ADJCALLSTACKUP |
| 2248200418U, // ADR |
| 335597633U, // ADRP |
| 207114466U, // ADR_LSL_ZZZ_D_0 |
| 207114466U, // ADR_LSL_ZZZ_D_1 |
| 207114466U, // ADR_LSL_ZZZ_D_2 |
| 207114466U, // ADR_LSL_ZZZ_D_3 |
| 274239714U, // ADR_LSL_ZZZ_S_0 |
| 274239714U, // ADR_LSL_ZZZ_S_1 |
| 274239714U, // ADR_LSL_ZZZ_S_2 |
| 274239714U, // ADR_LSL_ZZZ_S_3 |
| 207114466U, // ADR_SXTW_ZZZ_D_0 |
| 207114466U, // ADR_SXTW_ZZZ_D_1 |
| 207114466U, // ADR_SXTW_ZZZ_D_2 |
| 207114466U, // ADR_SXTW_ZZZ_D_3 |
| 207114466U, // ADR_UXTW_ZZZ_D_0 |
| 207114466U, // ADR_UXTW_ZZZ_D_1 |
| 207114466U, // ADR_UXTW_ZZZ_D_2 |
| 207114466U, // ADR_UXTW_ZZZ_D_3 |
| 135325775U, // AESDrr |
| 135325907U, // AESErr |
| 68200224U, // AESIMCrr |
| 0U, // AESIMCrrTied |
| 68200232U, // AESMCrr |
| 0U, // AESMCrrTied |
| 100717097U, // ANDSWri |
| 0U, // ANDSWrr |
| 100717097U, // ANDSWrs |
| 100717097U, // ANDSXri |
| 0U, // ANDSXrr |
| 100717097U, // ANDSXrs |
| 302002729U, // ANDS_PPzPP |
| 302044078U, // ANDV_VPZ_B |
| 302044078U, // ANDV_VPZ_D |
| 302044078U, // ANDV_VPZ_H |
| 302044078U, // ANDV_VPZ_S |
| 100714549U, // ANDWri |
| 0U, // ANDWrr |
| 100714549U, // ANDWrs |
| 100714549U, // ANDXri |
| 0U, // ANDXrr |
| 100714549U, // ANDXrs |
| 302000181U, // AND_PPzPP |
| 201345077U, // AND_ZI |
| 302000181U, // AND_ZPmZ_B |
| 302008373U, // AND_ZPmZ_D |
| 2186307637U, // AND_ZPmZ_H |
| 302024757U, // AND_ZPmZ_S |
| 201345077U, // AND_ZZZ |
| 68200501U, // ANDv16i8 |
| 2218829877U, // ANDv8i8 |
| 302000201U, // ASRD_ZPmI_B |
| 302008393U, // ASRD_ZPmI_D |
| 2186307657U, // ASRD_ZPmI_H |
| 302024777U, // ASRD_ZPmI_S |
| 302002512U, // ASRR_ZPmZ_B |
| 302010704U, // ASRR_ZPmZ_D |
| 2186309968U, // ASRR_ZPmZ_H |
| 302027088U, // ASRR_ZPmZ_S |
| 100716892U, // ASRVWr |
| 100716892U, // ASRVXr |
| 302002524U, // ASR_WIDE_ZPmZ_B |
| 2186309980U, // ASR_WIDE_ZPmZ_H |
| 302027100U, // ASR_WIDE_ZPmZ_S |
| 167784796U, // ASR_WIDE_ZZZ_B |
| 2387112284U, // ASR_WIDE_ZZZ_H |
| 268472668U, // ASR_WIDE_ZZZ_S |
| 302002524U, // ASR_ZPmI_B |
| 302010716U, // ASR_ZPmI_D |
| 2186309980U, // ASR_ZPmI_H |
| 302027100U, // ASR_ZPmI_S |
| 302002524U, // ASR_ZPmZ_B |
| 302010716U, // ASR_ZPmZ_D |
| 2186309980U, // ASR_ZPmZ_H |
| 302027100U, // ASR_ZPmZ_S |
| 167784796U, // ASR_ZZI_B |
| 201347420U, // ASR_ZZI_D |
| 239628636U, // ASR_ZZI_H |
| 268472668U, // ASR_ZZI_S |
| 2248196751U, // AUTDA |
| 2248197244U, // AUTDB |
| 6341460U, // AUTDZA |
| 6342386U, // AUTDZB |
| 2248196772U, // AUTIA |
| 5806U, // AUTIA1716 |
| 5935U, // AUTIASP |
| 5989U, // AUTIAZ |
| 2248197264U, // AUTIB |
| 5826U, // AUTIB1716 |
| 5951U, // AUTIBSP |
| 6003U, // AUTIBZ |
| 6341476U, // AUTIZA |
| 6342402U, // AUTIZB |
| 66415U, // B |
| 68203857U, // BCAX |
| 369151650U, // BFMWri |
| 369151650U, // BFMXri |
| 0U, // BICSWrr |
| 100717084U, // BICSWrs |
| 0U, // BICSXrr |
| 100717084U, // BICSXrs |
| 302002716U, // BICS_PPzPP |
| 0U, // BICWrr |
| 100714267U, // BICWrs |
| 0U, // BICXrr |
| 100714267U, // BICXrs |
| 301999899U, // BIC_PPzPP |
| 301999899U, // BIC_ZPmZ_B |
| 302008091U, // BIC_ZPmZ_D |
| 2186307355U, // BIC_ZPmZ_H |
| 302024475U, // BIC_ZPmZ_S |
| 201344795U, // BIC_ZZZ |
| 68200219U, // BICv16i8 |
| 404285211U, // BICv2i32 |
| 405333787U, // BICv4i16 |
| 405858075U, // BICv4i32 |
| 406382363U, // BICv8i16 |
| 2218829595U, // BICv8i8 |
| 68200698U, // BIFv16i8 |
| 2218830074U, // BIFv8i8 |
| 135328513U, // BITv16i8 |
| 2285957889U, // BITv8i8 |
| 68906U, // BL |
| 6344980U, // BLR |
| 2248196710U, // BLRAA |
| 6346175U, // BLRAAZ |
| 2248197127U, // BLRAB |
| 6346190U, // BLRABZ |
| 6344926U, // BR |
| 2248196697U, // BRAA |
| 6346168U, // BRAAZ |
| 2248197114U, // BRAB |
| 6346183U, // BRABZ |
| 76951U, // BRK |
| 302002647U, // BRKAS_PPzP |
| 8875U, // BRKA_PPmP |
| 301998763U, // BRKA_PPzP |
| 302002683U, // BRKBS_PPzP |
| 9367U, // BRKB_PPmP |
| 301999255U, // BRKB_PPzP |
| 302002803U, // BRKNS_PPzP |
| 302001918U, // BRKN_PPzP |
| 302002654U, // BRKPAS_PPzPP |
| 301998807U, // BRKPA_PPzPP |
| 302002690U, // BRKPBS_PPzPP |
| 301999474U, // BRKPB_PPzPP |
| 135327279U, // BSLv16i8 |
| 2285956655U, // BSLv8i8 |
| 87596U, // Bcc |
| 2516673568U, // CASAB |
| 2516675032U, // CASAH |
| 2516673753U, // CASALB |
| 2516675183U, // CASALH |
| 2516675845U, // CASALW |
| 2516675845U, // CASALX |
| 2516673308U, // CASAW |
| 2516673308U, // CASAX |
| 2516674100U, // CASB |
| 2516675551U, // CASH |
| 2516673847U, // CASLB |
| 2516675277U, // CASLH |
| 2516676137U, // CASLW |
| 2516676137U, // CASLX |
| 101604U, // CASPALW |
| 109796U, // CASPALX |
| 99038U, // CASPAW |
| 107230U, // CASPAX |
| 101900U, // CASPLW |
| 110092U, // CASPLX |
| 102471U, // CASPW |
| 110663U, // CASPX |
| 2516677074U, // CASW |
| 2516677074U, // CASX |
| 436262373U, // CBNZW |
| 436262373U, // CBNZX |
| 436262358U, // CBZW |
| 436262358U, // CBZX |
| 100716292U, // CCMNWi |
| 100716292U, // CCMNWr |
| 100716292U, // CCMNXi |
| 100716292U, // CCMNXr |
| 100716546U, // CCMPWi |
| 100716546U, // CCMPWr |
| 100716546U, // CCMPXi |
| 100716546U, // CCMPXr |
| 5976U, // CFINV |
| 302039858U, // CLASTA_RPZ_B |
| 302039858U, // CLASTA_RPZ_D |
| 302039858U, // CLASTA_RPZ_H |
| 302039858U, // CLASTA_RPZ_S |
| 302039858U, // CLASTA_VPZ_B |
| 302039858U, // CLASTA_VPZ_D |
| 302039858U, // CLASTA_VPZ_H |
| 302039858U, // CLASTA_VPZ_S |
| 301998898U, // CLASTA_ZPZ_B |
| 302007090U, // CLASTA_ZPZ_D |
| 2387632946U, // CLASTA_ZPZ_H |
| 302023474U, // CLASTA_ZPZ_S |
| 302040717U, // CLASTB_RPZ_B |
| 302040717U, // CLASTB_RPZ_D |
| 302040717U, // CLASTB_RPZ_H |
| 302040717U, // CLASTB_RPZ_S |
| 302040717U, // CLASTB_VPZ_B |
| 302040717U, // CLASTB_VPZ_D |
| 302040717U, // CLASTB_VPZ_H |
| 302040717U, // CLASTB_VPZ_S |
| 301999757U, // CLASTB_ZPZ_B |
| 302007949U, // CLASTB_ZPZ_D |
| 2387633805U, // CLASTB_ZPZ_H |
| 302024333U, // CLASTB_ZPZ_S |
| 6346114U, // CLREX |
| 2248200772U, // CLSWr |
| 2248200772U, // CLSXr |
| 12868U, // CLS_ZPmZ_B |
| 21060U, // CLS_ZPmZ_D |
| 2181591620U, // CLS_ZPmZ_H |
| 37444U, // CLS_ZPmZ_S |
| 68203076U, // CLSv16i8 |
| 68727364U, // CLSv2i32 |
| 69775940U, // CLSv4i16 |
| 2217783876U, // CLSv4i32 |
| 70824516U, // CLSv8i16 |
| 2218832452U, // CLSv8i8 |
| 2248201696U, // CLZWr |
| 2248201696U, // CLZXr |
| 13792U, // CLZ_ZPmZ_B |
| 21984U, // CLZ_ZPmZ_D |
| 2181592544U, // CLZ_ZPmZ_H |
| 38368U, // CLZ_ZPmZ_S |
| 68204000U, // CLZv16i8 |
| 68728288U, // CLZv2i32 |
| 69776864U, // CLZv4i16 |
| 2217784800U, // CLZv4i32 |
| 70825440U, // CLZv8i16 |
| 2218833376U, // CLZv8i8 |
| 68202651U, // CMEQv16i8 |
| 68202651U, // CMEQv16i8rz |
| 100716699U, // CMEQv1i64 |
| 2248200347U, // CMEQv1i64rz |
| 2216210587U, // CMEQv2i32 |
| 68726939U, // CMEQv2i32rz |
| 2216734875U, // CMEQv2i64 |
| 2216734875U, // CMEQv2i64rz |
| 69775515U, // CMEQv4i16 |
| 69775515U, // CMEQv4i16rz |
| 70299803U, // CMEQv4i32 |
| 2217783451U, // CMEQv4i32rz |
| 2218307739U, // CMEQv8i16 |
| 70824091U, // CMEQv8i16rz |
| 2218832027U, // CMEQv8i8 |
| 2218832027U, // CMEQv8i8rz |
| 68200561U, // CMGEv16i8 |
| 68200561U, // CMGEv16i8rz |
| 100714609U, // CMGEv1i64 |
| 2248198257U, // CMGEv1i64rz |
| 2216208497U, // CMGEv2i32 |
| 68724849U, // CMGEv2i32rz |
| 2216732785U, // CMGEv2i64 |
| 2216732785U, // CMGEv2i64rz |
| 69773425U, // CMGEv4i16 |
| 69773425U, // CMGEv4i16rz |
| 70297713U, // CMGEv4i32 |
| 2217781361U, // CMGEv4i32rz |
| 2218305649U, // CMGEv8i16 |
| 70822001U, // CMGEv8i16rz |
| 2218829937U, // CMGEv8i8 |
| 2218829937U, // CMGEv8i8rz |
| 68203251U, // CMGTv16i8 |
| 68203251U, // CMGTv16i8rz |
| 100717299U, // CMGTv1i64 |
| 2248200947U, // CMGTv1i64rz |
| 2216211187U, // CMGTv2i32 |
| 68727539U, // CMGTv2i32rz |
| 2216735475U, // CMGTv2i64 |
| 2216735475U, // CMGTv2i64rz |
| 69776115U, // CMGTv4i16 |
| 69776115U, // CMGTv4i16rz |
| 70300403U, // CMGTv4i32 |
| 2217784051U, // CMGTv4i32rz |
| 2218308339U, // CMGTv8i16 |
| 70824691U, // CMGTv8i16rz |
| 2218832627U, // CMGTv8i8 |
| 2218832627U, // CMGTv8i8rz |
| 68201580U, // CMHIv16i8 |
| 100715628U, // CMHIv1i64 |
| 2216209516U, // CMHIv2i32 |
| 2216733804U, // CMHIv2i64 |
| 69774444U, // CMHIv4i16 |
| 70298732U, // CMHIv4i32 |
| 2218306668U, // CMHIv8i16 |
| 2218830956U, // CMHIv8i8 |
| 68203063U, // CMHSv16i8 |
| 100717111U, // CMHSv1i64 |
| 2216210999U, // CMHSv2i32 |
| 2216735287U, // CMHSv2i64 |
| 69775927U, // CMHSv4i16 |
| 70300215U, // CMHSv4i32 |
| 2218308151U, // CMHSv8i16 |
| 2218832439U, // CMHSv8i8 |
| 68200592U, // CMLEv16i8rz |
| 2248198288U, // CMLEv1i64rz |
| 68724880U, // CMLEv2i32rz |
| 2216732816U, // CMLEv2i64rz |
| 69773456U, // CMLEv4i16rz |
| 2217781392U, // CMLEv4i32rz |
| 70822032U, // CMLEv8i16rz |
| 2218829968U, // CMLEv8i8rz |
| 68203285U, // CMLTv16i8rz |
| 2248200981U, // CMLTv1i64rz |
| 68727573U, // CMLTv2i32rz |
| 2216735509U, // CMLTv2i64rz |
| 69776149U, // CMLTv4i16rz |
| 2217784085U, // CMLTv4i32rz |
| 70824725U, // CMLTv8i16rz |
| 2218832661U, // CMLTv8i8rz |
| 302002346U, // CMPEQ_PPzZI_B |
| 302010538U, // CMPEQ_PPzZI_D |
| 2622517418U, // CMPEQ_PPzZI_H |
| 302026922U, // CMPEQ_PPzZI_S |
| 302002346U, // CMPEQ_PPzZZ_B |
| 302010538U, // CMPEQ_PPzZZ_D |
| 2622517418U, // CMPEQ_PPzZZ_H |
| 302026922U, // CMPEQ_PPzZZ_S |
| 302002346U, // CMPEQ_WIDE_PPzZZ_B |
| 2622517418U, // CMPEQ_WIDE_PPzZZ_H |
| 302026922U, // CMPEQ_WIDE_PPzZZ_S |
| 302000247U, // CMPGE_PPzZI_B |
| 302008439U, // CMPGE_PPzZI_D |
| 2622515319U, // CMPGE_PPzZI_H |
| 302024823U, // CMPGE_PPzZI_S |
| 302000247U, // CMPGE_PPzZZ_B |
| 302008439U, // CMPGE_PPzZZ_D |
| 2622515319U, // CMPGE_PPzZZ_H |
| 302024823U, // CMPGE_PPzZZ_S |
| 302000247U, // CMPGE_WIDE_PPzZZ_B |
| 2622515319U, // CMPGE_WIDE_PPzZZ_H |
| 302024823U, // CMPGE_WIDE_PPzZZ_S |
| 302002937U, // CMPGT_PPzZI_B |
| 302011129U, // CMPGT_PPzZI_D |
| 2622518009U, // CMPGT_PPzZI_H |
| 302027513U, // CMPGT_PPzZI_S |
| 302002937U, // CMPGT_PPzZZ_B |
| 302011129U, // CMPGT_PPzZZ_D |
| 2622518009U, // CMPGT_PPzZZ_H |
| 302027513U, // CMPGT_PPzZZ_S |
| 302002937U, // CMPGT_WIDE_PPzZZ_B |
| 2622518009U, // CMPGT_WIDE_PPzZZ_H |
| 302027513U, // CMPGT_WIDE_PPzZZ_S |
| 302001266U, // CMPHI_PPzZI_B |
| 302009458U, // CMPHI_PPzZI_D |
| 2622516338U, // CMPHI_PPzZI_H |
| 302025842U, // CMPHI_PPzZI_S |
| 302001266U, // CMPHI_PPzZZ_B |
| 302009458U, // CMPHI_PPzZZ_D |
| 2622516338U, // CMPHI_PPzZZ_H |
| 302025842U, // CMPHI_PPzZZ_S |
| 302001266U, // CMPHI_WIDE_PPzZZ_B |
| 2622516338U, // CMPHI_WIDE_PPzZZ_H |
| 302025842U, // CMPHI_WIDE_PPzZZ_S |
| 302002749U, // CMPHS_PPzZI_B |
| 302010941U, // CMPHS_PPzZI_D |
| 2622517821U, // CMPHS_PPzZI_H |
| 302027325U, // CMPHS_PPzZI_S |
| 302002749U, // CMPHS_PPzZZ_B |
| 302010941U, // CMPHS_PPzZZ_D |
| 2622517821U, // CMPHS_PPzZZ_H |
| 302027325U, // CMPHS_PPzZZ_S |
| 302002749U, // CMPHS_WIDE_PPzZZ_B |
| 2622517821U, // CMPHS_WIDE_PPzZZ_H |
| 302027325U, // CMPHS_WIDE_PPzZZ_S |
| 302000278U, // CMPLE_PPzZI_B |
| 302008470U, // CMPLE_PPzZI_D |
| 2622515350U, // CMPLE_PPzZI_H |
| 302024854U, // CMPLE_PPzZI_S |
| 302000278U, // CMPLE_WIDE_PPzZZ_B |
| 2622515350U, // CMPLE_WIDE_PPzZZ_H |
| 302024854U, // CMPLE_WIDE_PPzZZ_S |
| 302002080U, // CMPLO_PPzZI_B |
| 302010272U, // CMPLO_PPzZI_D |
| 2622517152U, // CMPLO_PPzZI_H |
| 302026656U, // CMPLO_PPzZI_S |
| 302002080U, // CMPLO_WIDE_PPzZZ_B |
| 2622517152U, // CMPLO_WIDE_PPzZZ_H |
| 302026656U, // CMPLO_WIDE_PPzZZ_S |
| 302002783U, // CMPLS_PPzZI_B |
| 302010975U, // CMPLS_PPzZI_D |
| 2622517855U, // CMPLS_PPzZI_H |
| 302027359U, // CMPLS_PPzZI_S |
| 302002783U, // CMPLS_WIDE_PPzZZ_B |
| 2622517855U, // CMPLS_WIDE_PPzZZ_H |
| 302027359U, // CMPLS_WIDE_PPzZZ_S |
| 302002971U, // CMPLT_PPzZI_B |
| 302011163U, // CMPLT_PPzZI_D |
| 2622518043U, // CMPLT_PPzZI_H |
| 302027547U, // CMPLT_PPzZI_S |
| 302002971U, // CMPLT_WIDE_PPzZZ_B |
| 2622518043U, // CMPLT_WIDE_PPzZZ_H |
| 302027547U, // CMPLT_WIDE_PPzZZ_S |
| 302000301U, // CMPNE_PPzZI_B |
| 302008493U, // CMPNE_PPzZI_D |
| 2622515373U, // CMPNE_PPzZI_H |
| 302024877U, // CMPNE_PPzZI_S |
| 302000301U, // CMPNE_PPzZZ_B |
| 302008493U, // CMPNE_PPzZZ_D |
| 2622515373U, // CMPNE_PPzZZ_H |
| 302024877U, // CMPNE_PPzZZ_S |
| 302000301U, // CMPNE_WIDE_PPzZZ_B |
| 2622515373U, // CMPNE_WIDE_PPzZZ_H |
| 302024877U, // CMPNE_WIDE_PPzZZ_S |
| 0U, // CMP_SWAP_128 |
| 0U, // CMP_SWAP_16 |
| 0U, // CMP_SWAP_32 |
| 0U, // CMP_SWAP_64 |
| 0U, // CMP_SWAP_8 |
| 68203349U, // CMTSTv16i8 |
| 100717397U, // CMTSTv1i64 |
| 2216211285U, // CMTSTv2i32 |
| 2216735573U, // CMTSTv2i64 |
| 69776213U, // CMTSTv4i16 |
| 70300501U, // CMTSTv4i32 |
| 2218308437U, // CMTSTv8i16 |
| 2218832725U, // CMTSTv8i8 |
| 13113U, // CNOT_ZPmZ_B |
| 21305U, // CNOT_ZPmZ_D |
| 2181591865U, // CNOT_ZPmZ_H |
| 37689U, // CNOT_ZPmZ_S |
| 503367303U, // CNTB_XPiI |
| 503367765U, // CNTD_XPiI |
| 503368736U, // CNTH_XPiI |
| 302043213U, // CNTP_XPP_B |
| 302043213U, // CNTP_XPP_D |
| 302043213U, // CNTP_XPP_H |
| 302043213U, // CNTP_XPP_S |
| 503371057U, // CNTW_XPiI |
| 13090U, // CNT_ZPmZ_B |
| 21282U, // CNT_ZPmZ_D |
| 2181591842U, // CNT_ZPmZ_H |
| 37666U, // CNT_ZPmZ_S |
| 68203298U, // CNTv16i8 |
| 2218832674U, // CNTv8i8 |
| 302011094U, // COMPACT_ZPZ_D |
| 302027478U, // COMPACT_ZPZ_S |
| 13747U, // CPY_ZPmI_B |
| 21939U, // CPY_ZPmI_D |
| 2181592499U, // CPY_ZPmI_H |
| 38323U, // CPY_ZPmI_S |
| 13747U, // CPY_ZPmR_B |
| 21939U, // CPY_ZPmR_D |
| 34108851U, // CPY_ZPmR_H |
| 38323U, // CPY_ZPmR_S |
| 13747U, // CPY_ZPmV_B |
| 21939U, // CPY_ZPmV_D |
| 34108851U, // CPY_ZPmV_H |
| 38323U, // CPY_ZPmV_S |
| 302003635U, // CPY_ZPzI_B |
| 302011827U, // CPY_ZPzI_D |
| 2622518707U, // CPY_ZPzI_H |
| 302028211U, // CPY_ZPzI_S |
| 67163146U, // CPYi16 |
| 2214646794U, // CPYi32 |
| 67163146U, // CPYi64 |
| 2214646794U, // CPYi8 |
| 100713377U, // CRC32Brr |
| 100713540U, // CRC32CBrr |
| 100715004U, // CRC32CHrr |
| 100717724U, // CRC32CWrr |
| 100717938U, // CRC32CXrr |
| 100714851U, // CRC32Hrr |
| 100717666U, // CRC32Wrr |
| 100717897U, // CRC32Xrr |
| 100715905U, // CSELWr |
| 100715905U, // CSELXr |
| 100714287U, // CSINCWr |
| 100714287U, // CSINCXr |
| 100717570U, // CSINVWr |
| 100717570U, // CSINVXr |
| 100714784U, // CSNEGWr |
| 100714784U, // CSNEGXr |
| 2248200353U, // CTERMEQ_WW |
| 2248200353U, // CTERMEQ_XX |
| 2248198308U, // CTERMNE_WW |
| 2248198308U, // CTERMNE_XX |
| 0U, // CompilerBarrier |
| 73783U, // DCPS1 |
| 74194U, // DCPS2 |
| 74260U, // DCPS3 |
| 536921167U, // DECB_XPiI |
| 536922047U, // DECD_XPiI |
| 536889279U, // DECD_ZPiI |
| 536922631U, // DECH_XPiI |
| 6842887U, // DECH_ZPiI |
| 2315308983U, // DECP_XP_B |
| 2348863415U, // DECP_XP_D |
| 2717962167U, // DECP_XP_H |
| 2415972279U, // DECP_XP_S |
| 2147504055U, // DECP_ZP_D |
| 604532663U, // DECP_ZP_H |
| 2147520439U, // DECP_ZP_S |
| 536925351U, // DECW_XPiI |
| 536908967U, // DECW_ZPiI |
| 116059U, // DMB |
| 5966U, // DRPS |
| 116282U, // DSB |
| 637554371U, // DUPM_ZI |
| 671101025U, // DUP_ZI_B |
| 704663649U, // DUP_ZI_D |
| 7368801U, // DUP_ZI_H |
| 738234465U, // DUP_ZI_S |
| 2248159329U, // DUP_ZR_B |
| 2248167521U, // DUP_ZR_D |
| 611872865U, // DUP_ZR_H |
| 2248183905U, // DUP_ZR_S |
| 167784545U, // DUP_ZZI_B |
| 201347169U, // DUP_ZZI_D |
| 776499297U, // DUP_ZZI_H |
| 127073U, // DUP_ZZI_Q |
| 268472417U, // DUP_ZZI_S |
| 2249240673U, // DUPv16i8gpr |
| 2215686241U, // DUPv16i8lane |
| 2249764961U, // DUPv2i32gpr |
| 2216210529U, // DUPv2i32lane |
| 2250289249U, // DUPv2i64gpr |
| 69251169U, // DUPv2i64lane |
| 2250813537U, // DUPv4i16gpr |
| 69775457U, // DUPv4i16lane |
| 2251337825U, // DUPv4i32gpr |
| 2217783393U, // DUPv4i32lane |
| 2251862113U, // DUPv8i16gpr |
| 70824033U, // DUPv8i16lane |
| 2252386401U, // DUPv8i8gpr |
| 2218831969U, // DUPv8i8lane |
| 0U, // EONWrr |
| 100716298U, // EONWrs |
| 0U, // EONXrr |
| 100716298U, // EONXrs |
| 68198926U, // EOR3 |
| 302002853U, // EORS_PPzPP |
| 302044187U, // EORV_VPZ_B |
| 302044187U, // EORV_VPZ_D |
| 302044187U, // EORV_VPZ_H |
| 302044187U, // EORV_VPZ_S |
| 100716853U, // EORWri |
| 0U, // EORWrr |
| 100716853U, // EORWrs |
| 100716853U, // EORXri |
| 0U, // EORXrr |
| 100716853U, // EORXrs |
| 302002485U, // EOR_PPzPP |
| 201347381U, // EOR_ZI |
| 302002485U, // EOR_ZPmZ_B |
| 302010677U, // EOR_ZPmZ_D |
| 2186309941U, // EOR_ZPmZ_H |
| 302027061U, // EOR_ZPmZ_S |
| 201347381U, // EOR_ZZZ |
| 68202805U, // EORv16i8 |
| 2218832181U, // EORv8i8 |
| 5971U, // ERET |
| 5891U, // ERETAA |
| 5898U, // ERETAB |
| 100716930U, // EXTRWrri |
| 100716930U, // EXTRXrri |
| 167785316U, // EXT_ZZI |
| 68203364U, // EXTv16i8 |
| 2218832740U, // EXTv8i8 |
| 0U, // F128CSEL |
| 100714404U, // FABD16 |
| 100714404U, // FABD32 |
| 100714404U, // FABD64 |
| 302008228U, // FABD_ZPmZ_D |
| 2186307492U, // FABD_ZPmZ_H |
| 302024612U, // FABD_ZPmZ_S |
| 2216208292U, // FABDv2f32 |
| 2216732580U, // FABDv2f64 |
| 69773220U, // FABDv4f16 |
| 70297508U, // FABDv4f32 |
| 2218305444U, // FABDv8f16 |
| 2248200686U, // FABSDr |
| 2248200686U, // FABSHr |
| 2248200686U, // FABSSr |
| 20974U, // FABS_ZPmZ_D |
| 2181591534U, // FABS_ZPmZ_H |
| 37358U, // FABS_ZPmZ_S |
| 68727278U, // FABSv2f32 |
| 2216735214U, // FABSv2f64 |
| 69775854U, // FABSv4f16 |
| 2217783790U, // FABSv4f32 |
| 70824430U, // FABSv8f16 |
| 100714601U, // FACGE16 |
| 100714601U, // FACGE32 |
| 100714601U, // FACGE64 |
| 302008425U, // FACGE_PPzZZ_D |
| 2622515305U, // FACGE_PPzZZ_H |
| 302024809U, // FACGE_PPzZZ_S |
| 2216208489U, // FACGEv2f32 |
| 2216732777U, // FACGEv2f64 |
| 69773417U, // FACGEv4f16 |
| 70297705U, // FACGEv4f32 |
| 2218305641U, // FACGEv8f16 |
| 100717291U, // FACGT16 |
| 100717291U, // FACGT32 |
| 100717291U, // FACGT64 |
| 302011115U, // FACGT_PPzZZ_D |
| 2622517995U, // FACGT_PPzZZ_H |
| 302027499U, // FACGT_PPzZZ_S |
| 2216211179U, // FACGTv2f32 |
| 2216735467U, // FACGTv2f64 |
| 69776107U, // FACGTv4f16 |
| 70300395U, // FACGTv4f32 |
| 2218308331U, // FACGTv8f16 |
| 302039688U, // FADDA_VPZ_D |
| 302039688U, // FADDA_VPZ_H |
| 302039688U, // FADDA_VPZ_S |
| 100714475U, // FADDDrr |
| 100714475U, // FADDHrr |
| 2216210389U, // FADDPv2f32 |
| 2216734677U, // FADDPv2f64 |
| 2214645717U, // FADDPv2i16p |
| 67162069U, // FADDPv2i32p |
| 2214645717U, // FADDPv2i64p |
| 69775317U, // FADDPv4f16 |
| 70299605U, // FADDPv4f32 |
| 2218307541U, // FADDPv8f16 |
| 100714475U, // FADDSrr |
| 302044057U, // FADDV_VPZ_D |
| 302044057U, // FADDV_VPZ_H |
| 302044057U, // FADDV_VPZ_S |
| 302008299U, // FADD_ZPmI_D |
| 2186307563U, // FADD_ZPmI_H |
| 302024683U, // FADD_ZPmI_S |
| 302008299U, // FADD_ZPmZ_D |
| 2186307563U, // FADD_ZPmZ_H |
| 302024683U, // FADD_ZPmZ_S |
| 201345003U, // FADD_ZZZ_D |
| 2387109867U, // FADD_ZZZ_H |
| 268470251U, // FADD_ZZZ_S |
| 2216208363U, // FADDv2f32 |
| 2216732651U, // FADDv2f64 |
| 69773291U, // FADDv4f16 |
| 70297579U, // FADDv4f32 |
| 2218305515U, // FADDv8f16 |
| 302008285U, // FCADD_ZPmZ_D |
| 2186307549U, // FCADD_ZPmZ_H |
| 302024669U, // FCADD_ZPmZ_S |
| 2216208349U, // FCADDv2f32 |
| 2216732637U, // FCADDv2f64 |
| 69773277U, // FCADDv4f16 |
| 70297565U, // FCADDv4f32 |
| 2218305501U, // FCADDv8f16 |
| 100716545U, // FCCMPDrr |
| 100714692U, // FCCMPEDrr |
| 100714692U, // FCCMPEHrr |
| 100714692U, // FCCMPESrr |
| 100716545U, // FCCMPHrr |
| 100716545U, // FCCMPSrr |
| 100716698U, // FCMEQ16 |
| 100716698U, // FCMEQ32 |
| 100716698U, // FCMEQ64 |
| 302010522U, // FCMEQ_PPzZ0_D |
| 2622517402U, // FCMEQ_PPzZ0_H |
| 302026906U, // FCMEQ_PPzZ0_S |
| 302010522U, // FCMEQ_PPzZZ_D |
| 2622517402U, // FCMEQ_PPzZZ_H |
| 302026906U, // FCMEQ_PPzZZ_S |
| 100716698U, // FCMEQv1i16rz |
| 100716698U, // FCMEQv1i32rz |
| 100716698U, // FCMEQv1i64rz |
| 2216210586U, // FCMEQv2f32 |
| 2216734874U, // FCMEQv2f64 |
| 2216210586U, // FCMEQv2i32rz |
| 69251226U, // FCMEQv2i64rz |
| 69775514U, // FCMEQv4f16 |
| 70299802U, // FCMEQv4f32 |
| 2217259162U, // FCMEQv4i16rz |
| 70299802U, // FCMEQv4i32rz |
| 2218307738U, // FCMEQv8f16 |
| 2218307738U, // FCMEQv8i16rz |
| 100714608U, // FCMGE16 |
| 100714608U, // FCMGE32 |
| 100714608U, // FCMGE64 |
| 302008432U, // FCMGE_PPzZ0_D |
| 2622515312U, // FCMGE_PPzZ0_H |
| 302024816U, // FCMGE_PPzZ0_S |
| 302008432U, // FCMGE_PPzZZ_D |
| 2622515312U, // FCMGE_PPzZZ_H |
| 302024816U, // FCMGE_PPzZZ_S |
| 100714608U, // FCMGEv1i16rz |
| 100714608U, // FCMGEv1i32rz |
| 100714608U, // FCMGEv1i64rz |
| 2216208496U, // FCMGEv2f32 |
| 2216732784U, // FCMGEv2f64 |
| 2216208496U, // FCMGEv2i32rz |
| 69249136U, // FCMGEv2i64rz |
| 69773424U, // FCMGEv4f16 |
| 70297712U, // FCMGEv4f32 |
| 2217257072U, // FCMGEv4i16rz |
| 70297712U, // FCMGEv4i32rz |
| 2218305648U, // FCMGEv8f16 |
| 2218305648U, // FCMGEv8i16rz |
| 100717298U, // FCMGT16 |
| 100717298U, // FCMGT32 |
| 100717298U, // FCMGT64 |
| 302011122U, // FCMGT_PPzZ0_D |
| 2622518002U, // FCMGT_PPzZ0_H |
| 302027506U, // FCMGT_PPzZ0_S |
| 302011122U, // FCMGT_PPzZZ_D |
| 2622518002U, // FCMGT_PPzZZ_H |
| 302027506U, // FCMGT_PPzZZ_S |
| 100717298U, // FCMGTv1i16rz |
| 100717298U, // FCMGTv1i32rz |
| 100717298U, // FCMGTv1i64rz |
| 2216211186U, // FCMGTv2f32 |
| 2216735474U, // FCMGTv2f64 |
| 2216211186U, // FCMGTv2i32rz |
| 69251826U, // FCMGTv2i64rz |
| 69776114U, // FCMGTv4f16 |
| 70300402U, // FCMGTv4f32 |
| 2217259762U, // FCMGTv4i16rz |
| 70300402U, // FCMGTv4i32rz |
| 2218308338U, // FCMGTv8f16 |
| 2218308338U, // FCMGTv8i16rz |
| 302006961U, // FCMLA_ZPmZZ_D |
| 2186306225U, // FCMLA_ZPmZZ_H |
| 302023345U, // FCMLA_ZPmZZ_S |
| 243294897U, // FCMLA_ZZZI_H |
| 2952823473U, // FCMLA_ZZZI_S |
| 2283332273U, // FCMLAv2f32 |
| 2283856561U, // FCMLAv2f64 |
| 136897201U, // FCMLAv4f16 |
| 136897201U, // FCMLAv4f16_indexed |
| 137421489U, // FCMLAv4f32 |
| 137421489U, // FCMLAv4f32_indexed |
| 2285429425U, // FCMLAv8f16 |
| 2285429425U, // FCMLAv8f16_indexed |
| 302008463U, // FCMLE_PPzZ0_D |
| 2622515343U, // FCMLE_PPzZ0_H |
| 302024847U, // FCMLE_PPzZ0_S |
| 100714639U, // FCMLEv1i16rz |
| 100714639U, // FCMLEv1i32rz |
| 100714639U, // FCMLEv1i64rz |
| 2216208527U, // FCMLEv2i32rz |
| 69249167U, // FCMLEv2i64rz |
| 2217257103U, // FCMLEv4i16rz |
| 70297743U, // FCMLEv4i32rz |
| 2218305679U, // FCMLEv8i16rz |
| 302011156U, // FCMLT_PPzZ0_D |
| 2622518036U, // FCMLT_PPzZ0_H |
| 302027540U, // FCMLT_PPzZ0_S |
| 100717332U, // FCMLTv1i16rz |
| 100717332U, // FCMLTv1i32rz |
| 100717332U, // FCMLTv1i64rz |
| 2216211220U, // FCMLTv2i32rz |
| 69251860U, // FCMLTv2i64rz |
| 2217259796U, // FCMLTv4i16rz |
| 70300436U, // FCMLTv4i32rz |
| 2218308372U, // FCMLTv8i16rz |
| 302008477U, // FCMNE_PPzZ0_D |
| 2622515357U, // FCMNE_PPzZ0_H |
| 302024861U, // FCMNE_PPzZ0_S |
| 302008477U, // FCMNE_PPzZZ_D |
| 2622515357U, // FCMNE_PPzZZ_H |
| 302024861U, // FCMNE_PPzZZ_S |
| 8966152U, // FCMPDri |
| 2248200200U, // FCMPDrr |
| 8964300U, // FCMPEDri |
| 2248198348U, // FCMPEDrr |
| 8964300U, // FCMPEHri |
| 2248198348U, // FCMPEHrr |
| 8964300U, // FCMPESri |
| 2248198348U, // FCMPESrr |
| 8966152U, // FCMPHri |
| 2248200200U, // FCMPHrr |
| 8966152U, // FCMPSri |
| 2248200200U, // FCMPSrr |
| 302010279U, // FCMUO_PPzZZ_D |
| 2622517159U, // FCMUO_PPzZZ_H |
| 302026663U, // FCMUO_PPzZZ_S |
| 21938U, // FCPY_ZPmI_D |
| 34108850U, // FCPY_ZPmI_H |
| 38322U, // FCPY_ZPmI_S |
| 100715904U, // FCSELDrrr |
| 100715904U, // FCSELHrrr |
| 100715904U, // FCSELSrrr |
| 2248200678U, // FCVTASUWDr |
| 2248200678U, // FCVTASUWHr |
| 2248200678U, // FCVTASUWSr |
| 2248200678U, // FCVTASUXDr |
| 2248200678U, // FCVTASUXHr |
| 2248200678U, // FCVTASUXSr |
| 2248200678U, // FCVTASv1f16 |
| 2248200678U, // FCVTASv1i32 |
| 2248200678U, // FCVTASv1i64 |
| 68727270U, // FCVTASv2f32 |
| 2216735206U, // FCVTASv2f64 |
| 69775846U, // FCVTASv4f16 |
| 2217783782U, // FCVTASv4f32 |
| 70824422U, // FCVTASv8f16 |
| 2248201065U, // FCVTAUUWDr |
| 2248201065U, // FCVTAUUWHr |
| 2248201065U, // FCVTAUUWSr |
| 2248201065U, // FCVTAUUXDr |
| 2248201065U, // FCVTAUUXHr |
| 2248201065U, // FCVTAUUXSr |
| 2248201065U, // FCVTAUv1f16 |
| 2248201065U, // FCVTAUv1i32 |
| 2248201065U, // FCVTAUv1i64 |
| 68727657U, // FCVTAUv2f32 |
| 2216735593U, // FCVTAUv2f64 |
| 69776233U, // FCVTAUv4f16 |
| 2217784169U, // FCVTAUv4f32 |
| 70824809U, // FCVTAUv8f16 |
| 2248201052U, // FCVTDHr |
| 2248201052U, // FCVTDSr |
| 2248201052U, // FCVTHDr |
| 2248201052U, // FCVTHSr |
| 69250649U, // FCVTLv2i32 |
| 70299225U, // FCVTLv4i16 |
| 2216730945U, // FCVTLv4i32 |
| 70295873U, // FCVTLv8i16 |
| 2248200806U, // FCVTMSUWDr |
| 2248200806U, // FCVTMSUWHr |
| 2248200806U, // FCVTMSUWSr |
| 2248200806U, // FCVTMSUXDr |
| 2248200806U, // FCVTMSUXHr |
| 2248200806U, // FCVTMSUXSr |
| 2248200806U, // FCVTMSv1f16 |
| 2248200806U, // FCVTMSv1i32 |
| 2248200806U, // FCVTMSv1i64 |
| 68727398U, // FCVTMSv2f32 |
| 2216735334U, // FCVTMSv2f64 |
| 69775974U, // FCVTMSv4f16 |
| 2217783910U, // FCVTMSv4f32 |
| 70824550U, // FCVTMSv8f16 |
| 2248201081U, // FCVTMUUWDr |
| 2248201081U, // FCVTMUUWHr |
| 2248201081U, // FCVTMUUWSr |
| 2248201081U, // FCVTMUUXDr |
| 2248201081U, // FCVTMUUXHr |
| 2248201081U, // FCVTMUUXSr |
| 2248201081U, // FCVTMUv1f16 |
| 2248201081U, // FCVTMUv1i32 |
| 2248201081U, // FCVTMUv1i64 |
| 68727673U, // FCVTMUv2f32 |
| 2216735609U, // FCVTMUv2f64 |
| 69776249U, // FCVTMUv4f16 |
| 2217784185U, // FCVTMUv4f32 |
| 70824825U, // FCVTMUv8f16 |
| 2248200832U, // FCVTNSUWDr |
| 2248200832U, // FCVTNSUWHr |
| 2248200832U, // FCVTNSUWSr |
| 2248200832U, // FCVTNSUXDr |
| 2248200832U, // FCVTNSUXHr |
| 2248200832U, // FCVTNSUXSr |
| 2248200832U, // FCVTNSv1f16 |
| 2248200832U, // FCVTNSv1i32 |
| 2248200832U, // FCVTNSv1i64 |
| 68727424U, // FCVTNSv2f32 |
| 2216735360U, // FCVTNSv2f64 |
| 69776000U, // FCVTNSv4f16 |
| 2217783936U, // FCVTNSv4f32 |
| 70824576U, // FCVTNSv8f16 |
| 2248201089U, // FCVTNUUWDr |
| 2248201089U, // FCVTNUUWHr |
| 2248201089U, // FCVTNUUWSr |
| 2248201089U, // FCVTNUUXDr |
| 2248201089U, // FCVTNUUXHr |
| 2248201089U, // FCVTNUUXSr |
| 2248201089U, // FCVTNUv1f16 |
| 2248201089U, // FCVTNUv1i32 |
| 2248201089U, // FCVTNUv1i64 |
| 68727681U, // FCVTNUv2f32 |
| 2216735617U, // FCVTNUv2f64 |
| 69776257U, // FCVTNUv4f16 |
| 2217784193U, // FCVTNUv4f32 |
| 70824833U, // FCVTNUv8f16 |
| 2216210238U, // FCVTNv2i32 |
| 2217258814U, // FCVTNv4i16 |
| 2284904839U, // FCVTNv4i32 |
| 2285429127U, // FCVTNv8i16 |
| 2248200848U, // FCVTPSUWDr |
| 2248200848U, // FCVTPSUWHr |
| 2248200848U, // FCVTPSUWSr |
| 2248200848U, // FCVTPSUXDr |
| 2248200848U, // FCVTPSUXHr |
| 2248200848U, // FCVTPSUXSr |
| 2248200848U, // FCVTPSv1f16 |
| 2248200848U, // FCVTPSv1i32 |
| 2248200848U, // FCVTPSv1i64 |
| 68727440U, // FCVTPSv2f32 |
| 2216735376U, // FCVTPSv2f64 |
| 69776016U, // FCVTPSv4f16 |
| 2217783952U, // FCVTPSv4f32 |
| 70824592U, // FCVTPSv8f16 |
| 2248201097U, // FCVTPUUWDr |
| 2248201097U, // FCVTPUUWHr |
| 2248201097U, // FCVTPUUWSr |
| 2248201097U, // FCVTPUUXDr |
| 2248201097U, // FCVTPUUXHr |
| 2248201097U, // FCVTPUUXSr |
| 2248201097U, // FCVTPUv1f16 |
| 2248201097U, // FCVTPUv1i32 |
| 2248201097U, // FCVTPUv1i64 |
| 68727689U, // FCVTPUv2f32 |
| 2216735625U, // FCVTPUv2f64 |
| 69776265U, // FCVTPUv4f16 |
| 2217784201U, // FCVTPUv4f32 |
| 70824841U, // FCVTPUv8f16 |
| 2248201052U, // FCVTSDr |
| 2248201052U, // FCVTSHr |
| 2248200052U, // FCVTXNv1i64 |
| 2216210292U, // FCVTXNv2f32 |
| 2284904893U, // FCVTXNv4f32 |
| 100717253U, // FCVTZSSWDri |
| 100717253U, // FCVTZSSWHri |
| 100717253U, // FCVTZSSWSri |
| 100717253U, // FCVTZSSXDri |
| 100717253U, // FCVTZSSXHri |
| 100717253U, // FCVTZSSXSri |
| 2248200901U, // FCVTZSUWDr |
| 2248200901U, // FCVTZSUWHr |
| 2248200901U, // FCVTZSUWSr |
| 2248200901U, // FCVTZSUXDr |
| 2248200901U, // FCVTZSUXHr |
| 2248200901U, // FCVTZSUXSr |
| 21189U, // FCVTZS_ZPmZ_DtoD |
| 37573U, // FCVTZS_ZPmZ_DtoS |
| 21189U, // FCVTZS_ZPmZ_HtoD |
| 2181591749U, // FCVTZS_ZPmZ_HtoH |
| 37573U, // FCVTZS_ZPmZ_HtoS |
| 21189U, // FCVTZS_ZPmZ_StoD |
| 37573U, // FCVTZS_ZPmZ_StoS |
| 100717253U, // FCVTZSd |
| 100717253U, // FCVTZSh |
| 100717253U, // FCVTZSs |
| 2248200901U, // FCVTZSv1f16 |
| 2248200901U, // FCVTZSv1i32 |
| 2248200901U, // FCVTZSv1i64 |
| 68727493U, // FCVTZSv2f32 |
| 2216735429U, // FCVTZSv2f64 |
| 2216211141U, // FCVTZSv2i32_shift |
| 2216735429U, // FCVTZSv2i64_shift |
| 69776069U, // FCVTZSv4f16 |
| 2217784005U, // FCVTZSv4f32 |
| 69776069U, // FCVTZSv4i16_shift |
| 70300357U, // FCVTZSv4i32_shift |
| 70824645U, // FCVTZSv8f16 |
| 2218308293U, // FCVTZSv8i16_shift |
| 100717457U, // FCVTZUSWDri |
| 100717457U, // FCVTZUSWHri |
| 100717457U, // FCVTZUSWSri |
| 100717457U, // FCVTZUSXDri |
| 100717457U, // FCVTZUSXHri |
| 100717457U, // FCVTZUSXSri |
| 2248201105U, // FCVTZUUWDr |
| 2248201105U, // FCVTZUUWHr |
| 2248201105U, // FCVTZUUWSr |
| 2248201105U, // FCVTZUUXDr |
| 2248201105U, // FCVTZUUXHr |
| 2248201105U, // FCVTZUUXSr |
| 21393U, // FCVTZU_ZPmZ_DtoD |
| 37777U, // FCVTZU_ZPmZ_DtoS |
| 21393U, // FCVTZU_ZPmZ_HtoD |
| 2181591953U, // FCVTZU_ZPmZ_HtoH |
| 37777U, // FCVTZU_ZPmZ_HtoS |
| 21393U, // FCVTZU_ZPmZ_StoD |
| 37777U, // FCVTZU_ZPmZ_StoS |
| 100717457U, // FCVTZUd |
| 100717457U, // FCVTZUh |
| 100717457U, // FCVTZUs |
| 2248201105U, // FCVTZUv1f16 |
| 2248201105U, // FCVTZUv1i32 |
| 2248201105U, // FCVTZUv1i64 |
| 68727697U, // FCVTZUv2f32 |
| 2216735633U, // FCVTZUv2f64 |
| 2216211345U, // FCVTZUv2i32_shift |
| 2216735633U, // FCVTZUv2i64_shift |
| 69776273U, // FCVTZUv4f16 |
| 2217784209U, // FCVTZUv4f32 |
| 69776273U, // FCVTZUv4i16_shift |
| 70300561U, // FCVTZUv4i32_shift |
| 70824849U, // FCVTZUv8f16 |
| 2218308497U, // FCVTZUv8i16_shift |
| 2181591900U, // FCVT_ZPmZ_DtoH |
| 37724U, // FCVT_ZPmZ_DtoS |
| 21340U, // FCVT_ZPmZ_HtoD |
| 37724U, // FCVT_ZPmZ_HtoS |
| 21340U, // FCVT_ZPmZ_StoD |
| 2181591900U, // FCVT_ZPmZ_StoH |
| 100717497U, // FDIVDrr |
| 100717497U, // FDIVHrr |
| 302010787U, // FDIVR_ZPmZ_D |
| 2186310051U, // FDIVR_ZPmZ_H |
| 302027171U, // FDIVR_ZPmZ_S |
| 100717497U, // FDIVSrr |
| 302011321U, // FDIV_ZPmZ_D |
| 2186310585U, // FDIV_ZPmZ_H |
| 302027705U, // FDIV_ZPmZ_S |
| 2216211385U, // FDIVv2f32 |
| 2216735673U, // FDIVv2f64 |
| 69776313U, // FDIVv4f16 |
| 70300601U, // FDIVv4f32 |
| 2218308537U, // FDIVv8f16 |
| 838881376U, // FDUP_ZI_D |
| 9465952U, // FDUP_ZI_H |
| 838897760U, // FDUP_ZI_S |
| 2348827371U, // FEXPA_ZZ_D |
| 608723691U, // FEXPA_ZZ_H |
| 2415952619U, // FEXPA_ZZ_S |
| 2248200909U, // FJCVTZS |
| 100714511U, // FMADDDrrr |
| 100714511U, // FMADDHrrr |
| 100714511U, // FMADDSrrr |
| 302008208U, // FMAD_ZPmZZ_D |
| 2186307472U, // FMAD_ZPmZZ_H |
| 302024592U, // FMAD_ZPmZZ_S |
| 100717911U, // FMAXDrr |
| 100717911U, // FMAXHrr |
| 100716219U, // FMAXNMDrr |
| 100716219U, // FMAXNMHrr |
| 2216210455U, // FMAXNMPv2f32 |
| 2216734743U, // FMAXNMPv2f64 |
| 2214645783U, // FMAXNMPv2i16p |
| 67162135U, // FMAXNMPv2i32p |
| 2214645783U, // FMAXNMPv2i64p |
| 69775383U, // FMAXNMPv4f16 |
| 70299671U, // FMAXNMPv4f32 |
| 2218307607U, // FMAXNMPv8f16 |
| 100716219U, // FMAXNMSrr |
| 302044132U, // FMAXNMV_VPZ_D |
| 302044132U, // FMAXNMV_VPZ_H |
| 302044132U, // FMAXNMV_VPZ_S |
| 67163108U, // FMAXNMVv4i16v |
| 2214646756U, // FMAXNMVv4i32v |
| 67163108U, // FMAXNMVv8i16v |
| 302010043U, // FMAXNM_ZPmI_D |
| 2186309307U, // FMAXNM_ZPmI_H |
| 302026427U, // FMAXNM_ZPmI_S |
| 302010043U, // FMAXNM_ZPmZ_D |
| 2186309307U, // FMAXNM_ZPmZ_H |
| 302026427U, // FMAXNM_ZPmZ_S |
| 2216210107U, // FMAXNMv2f32 |
| 2216734395U, // FMAXNMv2f64 |
| 69775035U, // FMAXNMv4f16 |
| 70299323U, // FMAXNMv4f32 |
| 2218307259U, // FMAXNMv8f16 |
| 2216210546U, // FMAXPv2f32 |
| 2216734834U, // FMAXPv2f64 |
| 2214645874U, // FMAXPv2i16p |
| 67162226U, // FMAXPv2i32p |
| 2214645874U, // FMAXPv2i64p |
| 69775474U, // FMAXPv4f16 |
| 70299762U, // FMAXPv4f32 |
| 2218307698U, // FMAXPv8f16 |
| 100717911U, // FMAXSrr |
| 302044193U, // FMAXV_VPZ_D |
| 302044193U, // FMAXV_VPZ_H |
| 302044193U, // FMAXV_VPZ_S |
| 67163169U, // FMAXVv4i16v |
| 2214646817U, // FMAXVv4i32v |
| 67163169U, // FMAXVv8i16v |
| 302011735U, // FMAX_ZPmI_D |
| 2186310999U, // FMAX_ZPmI_H |
| 302028119U, // FMAX_ZPmI_S |
| 302011735U, // FMAX_ZPmZ_D |
| 2186310999U, // FMAX_ZPmZ_H |
| 302028119U, // FMAX_ZPmZ_S |
| 2216211799U, // FMAXv2f32 |
| 2216736087U, // FMAXv2f64 |
| 69776727U, // FMAXv4f16 |
| 70301015U, // FMAXv4f32 |
| 2218308951U, // FMAXv8f16 |
| 100716264U, // FMINDrr |
| 100716264U, // FMINHrr |
| 100716211U, // FMINNMDrr |
| 100716211U, // FMINNMHrr |
| 2216210446U, // FMINNMPv2f32 |
| 2216734734U, // FMINNMPv2f64 |
| 2214645774U, // FMINNMPv2i16p |
| 67162126U, // FMINNMPv2i32p |
| 2214645774U, // FMINNMPv2i64p |
| 69775374U, // FMINNMPv4f16 |
| 70299662U, // FMINNMPv4f32 |
| 2218307598U, // FMINNMPv8f16 |
| 100716211U, // FMINNMSrr |
| 302044123U, // FMINNMV_VPZ_D |
| 302044123U, // FMINNMV_VPZ_H |
| 302044123U, // FMINNMV_VPZ_S |
| 67163099U, // FMINNMVv4i16v |
| 2214646747U, // FMINNMVv4i32v |
| 67163099U, // FMINNMVv8i16v |
| 302010035U, // FMINNM_ZPmI_D |
| 2186309299U, // FMINNM_ZPmI_H |
| 302026419U, // FMINNM_ZPmI_S |
| 302010035U, // FMINNM_ZPmZ_D |
| 2186309299U, // FMINNM_ZPmZ_H |
| 302026419U, // FMINNM_ZPmZ_S |
| 2216210099U, // FMINNMv2f32 |
| 2216734387U, // FMINNMv2f64 |
| 69775027U, // FMINNMv4f16 |
| 70299315U, // FMINNMv4f32 |
| 2218307251U, // FMINNMv8f16 |
| 2216210470U, // FMINPv2f32 |
| 2216734758U, // FMINPv2f64 |
| 2214645798U, // FMINPv2i16p |
| 67162150U, // FMINPv2i32p |
| 2214645798U, // FMINPv2i64p |
| 69775398U, // FMINPv4f16 |
| 70299686U, // FMINPv4f32 |
| 2218307622U, // FMINPv8f16 |
| 100716264U, // FMINSrr |
| 302044141U, // FMINV_VPZ_D |
| 302044141U, // FMINV_VPZ_H |
| 302044141U, // FMINV_VPZ_S |
| 67163117U, // FMINVv4i16v |
| 2214646765U, // FMINVv4i32v |
| 67163117U, // FMINVv8i16v |
| 302010088U, // FMIN_ZPmI_D |
| 2186309352U, // FMIN_ZPmI_H |
| 302026472U, // FMIN_ZPmI_S |
| 302010088U, // FMIN_ZPmZ_D |
| 2186309352U, // FMIN_ZPmZ_H |
| 302026472U, // FMIN_ZPmZ_S |
| 2216210152U, // FMINv2f32 |
| 2216734440U, // FMINv2f64 |
| 69775080U, // FMINv4f16 |
| 70299368U, // FMINv4f32 |
| 2218307304U, // FMINv8f16 |
| 302006968U, // FMLA_ZPmZZ_D |
| 2186306232U, // FMLA_ZPmZZ_H |
| 302023352U, // FMLA_ZPmZZ_S |
| 3019915960U, // FMLA_ZZZI_D |
| 612393656U, // FMLA_ZZZI_H |
| 2952823480U, // FMLA_ZZZI_S |
| 369189560U, // FMLAv1i16_indexed |
| 369189560U, // FMLAv1i32_indexed |
| 369189560U, // FMLAv1i64_indexed |
| 2283332280U, // FMLAv2f32 |
| 2283856568U, // FMLAv2f64 |
| 2283332280U, // FMLAv2i32_indexed |
| 2283856568U, // FMLAv2i64_indexed |
| 136897208U, // FMLAv4f16 |
| 137421496U, // FMLAv4f32 |
| 136897208U, // FMLAv4i16_indexed |
| 137421496U, // FMLAv4i32_indexed |
| 2285429432U, // FMLAv8f16 |
| 2285429432U, // FMLAv8i16_indexed |
| 302010962U, // FMLS_ZPmZZ_D |
| 2186310226U, // FMLS_ZPmZZ_H |
| 302027346U, // FMLS_ZPmZZ_S |
| 3019919954U, // FMLS_ZZZI_D |
| 612397650U, // FMLS_ZZZI_H |
| 2952827474U, // FMLS_ZZZI_S |
| 369193554U, // FMLSv1i16_indexed |
| 369193554U, // FMLSv1i32_indexed |
| 369193554U, // FMLSv1i64_indexed |
| 2283336274U, // FMLSv2f32 |
| 2283860562U, // FMLSv2f64 |
| 2283336274U, // FMLSv2i32_indexed |
| 2283860562U, // FMLSv2i64_indexed |
| 136901202U, // FMLSv4f16 |
| 137425490U, // FMLSv4f32 |
| 136901202U, // FMLSv4i16_indexed |
| 137425490U, // FMLSv4i32_indexed |
| 2285433426U, // FMLSv8f16 |
| 2285433426U, // FMLSv8i16_indexed |
| 0U, // FMOVD0 |
| 67163145U, // FMOVDXHighr |
| 2248201225U, // FMOVDXr |
| 838915081U, // FMOVDi |
| 2248201225U, // FMOVDr |
| 0U, // FMOVH0 |
| 2248201225U, // FMOVHWr |
| 2248201225U, // FMOVHXr |
| 838915081U, // FMOVHi |
| 2248201225U, // FMOVHr |
| 0U, // FMOVS0 |
| 2248201225U, // FMOVSWr |
| 838915081U, // FMOVSi |
| 2248201225U, // FMOVSr |
| 2248201225U, // FMOVWHr |
| 2248201225U, // FMOVWSr |
| 2258154505U, // FMOVXDHighr |
| 2248201225U, // FMOVXDr |
| 2248201225U, // FMOVXHr |
| 840479753U, // FMOVv2f32_ns |
| 841004041U, // FMOVv2f64_ns |
| 841528329U, // FMOVv4f16_ns |
| 842052617U, // FMOVv4f32_ns |
| 842576905U, // FMOVv8f16_ns |
| 302007876U, // FMSB_ZPmZZ_D |
| 2186307140U, // FMSB_ZPmZZ_H |
| 302024260U, // FMSB_ZPmZZ_S |
| 100714165U, // FMSUBDrrr |
| 100714165U, // FMSUBHrrr |
| 100714165U, // FMSUBSrrr |
| 100716128U, // FMULDrr |
| 100716128U, // FMULHrr |
| 100716128U, // FMULSrr |
| 100717970U, // FMULX16 |
| 100717970U, // FMULX32 |
| 100717970U, // FMULX64 |
| 302011794U, // FMULX_ZPmZ_D |
| 2186311058U, // FMULX_ZPmZ_H |
| 302028178U, // FMULX_ZPmZ_S |
| 100717970U, // FMULXv1i16_indexed |
| 100717970U, // FMULXv1i32_indexed |
| 100717970U, // FMULXv1i64_indexed |
| 2216211858U, // FMULXv2f32 |
| 2216736146U, // FMULXv2f64 |
| 2216211858U, // FMULXv2i32_indexed |
| 2216736146U, // FMULXv2i64_indexed |
| 69776786U, // FMULXv4f16 |
| 70301074U, // FMULXv4f32 |
| 69776786U, // FMULXv4i16_indexed |
| 70301074U, // FMULXv4i32_indexed |
| 2218309010U, // FMULXv8f16 |
| 2218309010U, // FMULXv8i16_indexed |
| 302009952U, // FMUL_ZPmI_D |
| 2186309216U, // FMUL_ZPmI_H |
| 302026336U, // FMUL_ZPmI_S |
| 302009952U, // FMUL_ZPmZ_D |
| 2186309216U, // FMUL_ZPmZ_H |
| 302026336U, // FMUL_ZPmZ_S |
| 201346656U, // FMUL_ZZZI_D |
| 2387111520U, // FMUL_ZZZI_H |
| 268471904U, // FMUL_ZZZI_S |
| 201346656U, // FMUL_ZZZ_D |
| 2387111520U, // FMUL_ZZZ_H |
| 268471904U, // FMUL_ZZZ_S |
| 100716128U, // FMULv1i16_indexed |
| 100716128U, // FMULv1i32_indexed |
| 100716128U, // FMULv1i64_indexed |
| 2216210016U, // FMULv2f32 |
| 2216734304U, // FMULv2f64 |
| 2216210016U, // FMULv2i32_indexed |
| 2216734304U, // FMULv2i64_indexed |
| 69774944U, // FMULv4f16 |
| 70299232U, // FMULv4f32 |
| 69774944U, // FMULv4i16_indexed |
| 70299232U, // FMULv4i32_indexed |
| 2218307168U, // FMULv8f16 |
| 2218307168U, // FMULv8i16_indexed |
| 2248198419U, // FNEGDr |
| 2248198419U, // FNEGHr |
| 2248198419U, // FNEGSr |
| 18707U, // FNEG_ZPmZ_D |
| 2181589267U, // FNEG_ZPmZ_H |
| 35091U, // FNEG_ZPmZ_S |
| 68725011U, // FNEGv2f32 |
| 2216732947U, // FNEGv2f64 |
| 69773587U, // FNEGv4f16 |
| 2217781523U, // FNEGv4f32 |
| 70822163U, // FNEGv8f16 |
| 100714518U, // FNMADDDrrr |
| 100714518U, // FNMADDHrrr |
| 100714518U, // FNMADDSrrr |
| 302008214U, // FNMAD_ZPmZZ_D |
| 2186307478U, // FNMAD_ZPmZZ_H |
| 302024598U, // FNMAD_ZPmZZ_S |
| 302006974U, // FNMLA_ZPmZZ_D |
| 2186306238U, // FNMLA_ZPmZZ_H |
| 302023358U, // FNMLA_ZPmZZ_S |
| 302010968U, // FNMLS_ZPmZZ_D |
| 2186310232U, // FNMLS_ZPmZZ_H |
| 302027352U, // FNMLS_ZPmZZ_S |
| 302007882U, // FNMSB_ZPmZZ_D |
| 2186307146U, // FNMSB_ZPmZZ_H |
| 302024266U, // FNMSB_ZPmZZ_S |
| 100714172U, // FNMSUBDrrr |
| 100714172U, // FNMSUBHrrr |
| 100714172U, // FNMSUBSrrr |
| 100716134U, // FNMULDrr |
| 100716134U, // FNMULHrr |
| 100716134U, // FNMULSrr |
| 2348828852U, // FRECPE_ZZ_D |
| 608725172U, // FRECPE_ZZ_H |
| 2415954100U, // FRECPE_ZZ_S |
| 2248198324U, // FRECPEv1f16 |
| 2248198324U, // FRECPEv1i32 |
| 2248198324U, // FRECPEv1i64 |
| 68724916U, // FRECPEv2f32 |
| 2216732852U, // FRECPEv2f64 |
| 69773492U, // FRECPEv4f16 |
| 2217781428U, // FRECPEv4f32 |
| 70822068U, // FRECPEv8f16 |
| 100717192U, // FRECPS16 |
| 100717192U, // FRECPS32 |
| 100717192U, // FRECPS64 |
| 201347720U, // FRECPS_ZZZ_D |
| 2387112584U, // FRECPS_ZZZ_H |
| 268472968U, // FRECPS_ZZZ_S |
| 2216211080U, // FRECPSv2f32 |
| 2216735368U, // FRECPSv2f64 |
| 69776008U, // FRECPSv4f16 |
| 70300296U, // FRECPSv4f32 |
| 2218308232U, // FRECPSv8f16 |
| 21913U, // FRECPX_ZPmZ_D |
| 2181592473U, // FRECPX_ZPmZ_H |
| 38297U, // FRECPX_ZPmZ_S |
| 2248201625U, // FRECPXv1f16 |
| 2248201625U, // FRECPXv1i32 |
| 2248201625U, // FRECPXv1i64 |
| 2248196906U, // FRINTADr |
| 2248196906U, // FRINTAHr |
| 2248196906U, // FRINTASr |
| 17194U, // FRINTA_ZPmZ_D |
| 2181587754U, // FRINTA_ZPmZ_H |
| 33578U, // FRINTA_ZPmZ_S |
| 68723498U, // FRINTAv2f32 |
| 2216731434U, // FRINTAv2f64 |
| 69772074U, // FRINTAv4f16 |
| 2217780010U, // FRINTAv4f32 |
| 70820650U, // FRINTAv8f16 |
| 2248199305U, // FRINTIDr |
| 2248199305U, // FRINTIHr |
| 2248199305U, // FRINTISr |
| 19593U, // FRINTI_ZPmZ_D |
| 2181590153U, // FRINTI_ZPmZ_H |
| 35977U, // FRINTI_ZPmZ_S |
| 68725897U, // FRINTIv2f32 |
| 2216733833U, // FRINTIv2f64 |
| 69774473U, // FRINTIv4f16 |
| 2217782409U, // FRINTIv4f32 |
| 70823049U, // FRINTIv8f16 |
| 2248199881U, // FRINTMDr |
| 2248199881U, // FRINTMHr |
| 2248199881U, // FRINTMSr |
| 20169U, // FRINTM_ZPmZ_D |
| 2181590729U, // FRINTM_ZPmZ_H |
| 36553U, // FRINTM_ZPmZ_S |
| 68726473U, // FRINTMv2f32 |
| 2216734409U, // FRINTMv2f64 |
| 69775049U, // FRINTMv4f16 |
| 2217782985U, // FRINTMv4f32 |
| 70823625U, // FRINTMv8f16 |
| 2248199990U, // FRINTNDr |
| 2248199990U, // FRINTNHr |
| 2248199990U, // FRINTNSr |
| 20278U, // FRINTN_ZPmZ_D |
| 2181590838U, // FRINTN_ZPmZ_H |
| 36662U, // FRINTN_ZPmZ_S |
| 68726582U, // FRINTNv2f32 |
| 2216734518U, // FRINTNv2f64 |
| 69775158U, // FRINTNv4f16 |
| 2217783094U, // FRINTNv4f32 |
| 70823734U, // FRINTNv8f16 |
| 2248200275U, // FRINTPDr |
| 2248200275U, // FRINTPHr |
| 2248200275U, // FRINTPSr |
| 20563U, // FRINTP_ZPmZ_D |
| 2181591123U, // FRINTP_ZPmZ_H |
| 36947U, // FRINTP_ZPmZ_S |
| 68726867U, // FRINTPv2f32 |
| 2216734803U, // FRINTPv2f64 |
| 69775443U, // FRINTPv4f16 |
| 2217783379U, // FRINTPv4f32 |
| 70824019U, // FRINTPv8f16 |
| 2248201633U, // FRINTXDr |
| 2248201633U, // FRINTXHr |
| 2248201633U, // FRINTXSr |
| 21921U, // FRINTX_ZPmZ_D |
| 2181592481U, // FRINTX_ZPmZ_H |
| 38305U, // FRINTX_ZPmZ_S |
| 68728225U, // FRINTXv2f32 |
| 2216736161U, // FRINTXv2f64 |
| 69776801U, // FRINTXv4f16 |
| 2217784737U, // FRINTXv4f32 |
| 70825377U, // FRINTXv8f16 |
| 2248201713U, // FRINTZDr |
| 2248201713U, // FRINTZHr |
| 2248201713U, // FRINTZSr |
| 22001U, // FRINTZ_ZPmZ_D |
| 2181592561U, // FRINTZ_ZPmZ_H |
| 38385U, // FRINTZ_ZPmZ_S |
| 68728305U, // FRINTZv2f32 |
| 2216736241U, // FRINTZv2f64 |
| 69776881U, // FRINTZv4f16 |
| 2217784817U, // FRINTZv4f32 |
| 70825457U, // FRINTZv8f16 |
| 2348828897U, // FRSQRTE_ZZ_D |
| 608725217U, // FRSQRTE_ZZ_H |
| 2415954145U, // FRSQRTE_ZZ_S |
| 2248198369U, // FRSQRTEv1f16 |
| 2248198369U, // FRSQRTEv1i32 |
| 2248198369U, // FRSQRTEv1i64 |
| 68724961U, // FRSQRTEv2f32 |
| 2216732897U, // FRSQRTEv2f64 |
| 69773537U, // FRSQRTEv4f16 |
| 2217781473U, // FRSQRTEv4f32 |
| 70822113U, // FRSQRTEv8f16 |
| 100717239U, // FRSQRTS16 |
| 100717239U, // FRSQRTS32 |
| 100717239U, // FRSQRTS64 |
| 201347767U, // FRSQRTS_ZZZ_D |
| 2387112631U, // FRSQRTS_ZZZ_H |
| 268473015U, // FRSQRTS_ZZZ_S |
| 2216211127U, // FRSQRTSv2f32 |
| 2216735415U, // FRSQRTSv2f64 |
| 69776055U, // FRSQRTSv4f16 |
| 70300343U, // FRSQRTSv4f32 |
| 2218308279U, // FRSQRTSv8f16 |
| 302008446U, // FSCALE_ZPmZ_D |
| 2186307710U, // FSCALE_ZPmZ_H |
| 302024830U, // FSCALE_ZPmZ_S |
| 2248201023U, // FSQRTDr |
| 2248201023U, // FSQRTHr |
| 2248201023U, // FSQRTSr |
| 21311U, // FSQRT_ZPmZ_D |
| 2181591871U, // FSQRT_ZPmZ_H |
| 37695U, // FSQRT_ZPmZ_S |
| 68727615U, // FSQRTv2f32 |
| 2216735551U, // FSQRTv2f64 |
| 69776191U, // FSQRTv4f16 |
| 2217784127U, // FSQRTv4f32 |
| 70824767U, // FSQRTv8f16 |
| 100714145U, // FSUBDrr |
| 100714145U, // FSUBHrr |
| 302010587U, // FSUBR_ZPmI_D |
| 2186309851U, // FSUBR_ZPmI_H |
| 302026971U, // FSUBR_ZPmI_S |
| 302010587U, // FSUBR_ZPmZ_D |
| 2186309851U, // FSUBR_ZPmZ_H |
| 302026971U, // FSUBR_ZPmZ_S |
| 100714145U, // FSUBSrr |
| 302007969U, // FSUB_ZPmI_D |
| 2186307233U, // FSUB_ZPmI_H |
| 302024353U, // FSUB_ZPmI_S |
| 302007969U, // FSUB_ZPmZ_D |
| 2186307233U, // FSUB_ZPmZ_H |
| 302024353U, // FSUB_ZPmZ_S |
| 201344673U, // FSUB_ZZZ_D |
| 2387109537U, // FSUB_ZZZ_H |
| 268469921U, // FSUB_ZZZ_S |
| 2216208033U, // FSUBv2f32 |
| 2216732321U, // FSUBv2f64 |
| 69772961U, // FSUBv4f16 |
| 70297249U, // FSUBv4f32 |
| 2218305185U, // FSUBv8f16 |
| 201344925U, // FTMAD_ZZI_D |
| 2387109789U, // FTMAD_ZZI_H |
| 268470173U, // FTMAD_ZZI_S |
| 201346675U, // FTSMUL_ZZZ_D |
| 2387111539U, // FTSMUL_ZZZ_H |
| 268471923U, // FTSMUL_ZZZ_S |
| 201346439U, // FTSSEL_ZZZ_D |
| 2387111303U, // FTSSEL_ZZZ_H |
| 268471687U, // FTSSEL_ZZZ_S |
| 883032940U, // GLD1B_D_IMM_REAL |
| 379716460U, // GLD1B_D_REAL |
| 379716460U, // GLD1B_D_SXTW_REAL |
| 379716460U, // GLD1B_D_UXTW_REAL |
| 815932268U, // GLD1B_S_IMM_REAL |
| 379724652U, // GLD1B_S_SXTW_REAL |
| 379724652U, // GLD1B_S_UXTW_REAL |
| 883033920U, // GLD1D_IMM_REAL |
| 379717440U, // GLD1D_REAL |
| 379717440U, // GLD1D_SCALED_REAL |
| 379717440U, // GLD1D_SXTW_REAL |
| 379717440U, // GLD1D_SXTW_SCALED_REAL |
| 379717440U, // GLD1D_UXTW_REAL |
| 379717440U, // GLD1D_UXTW_SCALED_REAL |
| 3030518062U, // GLD1H_D_IMM_REAL |
| 379717934U, // GLD1H_D_REAL |
| 379717934U, // GLD1H_D_SCALED_REAL |
| 379717934U, // GLD1H_D_SXTW_REAL |
| 379717934U, // GLD1H_D_SXTW_SCALED_REAL |
| 379717934U, // GLD1H_D_UXTW_REAL |
| 379717934U, // GLD1H_D_UXTW_SCALED_REAL |
| 2963417390U, // GLD1H_S_IMM_REAL |
| 379726126U, // GLD1H_S_SXTW_REAL |
| 379726126U, // GLD1H_S_SXTW_SCALED_REAL |
| 379726126U, // GLD1H_S_UXTW_REAL |
| 379726126U, // GLD1H_S_UXTW_SCALED_REAL |
| 883033627U, // GLD1SB_D_IMM_REAL |
| 379717147U, // GLD1SB_D_REAL |
| 379717147U, // GLD1SB_D_SXTW_REAL |
| 379717147U, // GLD1SB_D_UXTW_REAL |
| 815932955U, // GLD1SB_S_IMM_REAL |
| 379725339U, // GLD1SB_S_SXTW_REAL |
| 379725339U, // GLD1SB_S_UXTW_REAL |
| 3030518726U, // GLD1SH_D_IMM_REAL |
| 379718598U, // GLD1SH_D_REAL |
| 379718598U, // GLD1SH_D_SCALED_REAL |
| 379718598U, // GLD1SH_D_SXTW_REAL |
| 379718598U, // GLD1SH_D_SXTW_SCALED_REAL |
| 379718598U, // GLD1SH_D_UXTW_REAL |
| 379718598U, // GLD1SH_D_UXTW_SCALED_REAL |
| 2963418054U, // GLD1SH_S_IMM_REAL |
| 379726790U, // GLD1SH_S_SXTW_REAL |
| 379726790U, // GLD1SH_S_SXTW_SCALED_REAL |
| 379726790U, // GLD1SH_S_UXTW_REAL |
| 379726790U, // GLD1SH_S_UXTW_SCALED_REAL |
| 883037416U, // GLD1SW_D_IMM_REAL |
| 379720936U, // GLD1SW_D_REAL |
| 379720936U, // GLD1SW_D_SCALED_REAL |
| 379720936U, // GLD1SW_D_SXTW_REAL |
| 379720936U, // GLD1SW_D_SXTW_SCALED_REAL |
| 379720936U, // GLD1SW_D_UXTW_REAL |
| 379720936U, // GLD1SW_D_UXTW_SCALED_REAL |
| 883037238U, // GLD1W_D_IMM_REAL |
| 379720758U, // GLD1W_D_REAL |
| 379720758U, // GLD1W_D_SCALED_REAL |
| 379720758U, // GLD1W_D_SXTW_REAL |
| 379720758U, // GLD1W_D_SXTW_SCALED_REAL |
| 379720758U, // GLD1W_D_UXTW_REAL |
| 379720758U, // GLD1W_D_UXTW_SCALED_REAL |
| 815936566U, // GLD1W_IMM_REAL |
| 379728950U, // GLD1W_SXTW_REAL |
| 379728950U, // GLD1W_SXTW_SCALED_REAL |
| 379728950U, // GLD1W_UXTW_REAL |
| 379728950U, // GLD1W_UXTW_SCALED_REAL |
| 883032946U, // GLDFF1B_D_IMM_REAL |
| 379716466U, // GLDFF1B_D_REAL |
| 379716466U, // GLDFF1B_D_SXTW_REAL |
| 379716466U, // GLDFF1B_D_UXTW_REAL |
| 815932274U, // GLDFF1B_S_IMM_REAL |
| 379724658U, // GLDFF1B_S_SXTW_REAL |
| 379724658U, // GLDFF1B_S_UXTW_REAL |
| 883033926U, // GLDFF1D_IMM_REAL |
| 379717446U, // GLDFF1D_REAL |
| 379717446U, // GLDFF1D_SCALED_REAL |
| 379717446U, // GLDFF1D_SXTW_REAL |
| 379717446U, // GLDFF1D_SXTW_SCALED_REAL |
| 379717446U, // GLDFF1D_UXTW_REAL |
| 379717446U, // GLDFF1D_UXTW_SCALED_REAL |
| 3030518068U, // GLDFF1H_D_IMM_REAL |
| 379717940U, // GLDFF1H_D_REAL |
| 379717940U, // GLDFF1H_D_SCALED_REAL |
| 379717940U, // GLDFF1H_D_SXTW_REAL |
| 379717940U, // GLDFF1H_D_SXTW_SCALED_REAL |
| 379717940U, // GLDFF1H_D_UXTW_REAL |
| 379717940U, // GLDFF1H_D_UXTW_SCALED_REAL |
| 2963417396U, // GLDFF1H_S_IMM_REAL |
| 379726132U, // GLDFF1H_S_SXTW_REAL |
| 379726132U, // GLDFF1H_S_SXTW_SCALED_REAL |
| 379726132U, // GLDFF1H_S_UXTW_REAL |
| 379726132U, // GLDFF1H_S_UXTW_SCALED_REAL |
| 883033634U, // GLDFF1SB_D_IMM_REAL |
| 379717154U, // GLDFF1SB_D_REAL |
| 379717154U, // GLDFF1SB_D_SXTW_REAL |
| 379717154U, // GLDFF1SB_D_UXTW_REAL |
| 815932962U, // GLDFF1SB_S_IMM_REAL |
| 379725346U, // GLDFF1SB_S_SXTW_REAL |
| 379725346U, // GLDFF1SB_S_UXTW_REAL |
| 3030518733U, // GLDFF1SH_D_IMM_REAL |
| 379718605U, // GLDFF1SH_D_REAL |
| 379718605U, // GLDFF1SH_D_SCALED_REAL |
| 379718605U, // GLDFF1SH_D_SXTW_REAL |
| 379718605U, // GLDFF1SH_D_SXTW_SCALED_REAL |
| 379718605U, // GLDFF1SH_D_UXTW_REAL |
| 379718605U, // GLDFF1SH_D_UXTW_SCALED_REAL |
| 2963418061U, // GLDFF1SH_S_IMM_REAL |
| 379726797U, // GLDFF1SH_S_SXTW_REAL |
| 379726797U, // GLDFF1SH_S_SXTW_SCALED_REAL |
| 379726797U, // GLDFF1SH_S_UXTW_REAL |
| 379726797U, // GLDFF1SH_S_UXTW_SCALED_REAL |
| 883037423U, // GLDFF1SW_D_IMM_REAL |
| 379720943U, // GLDFF1SW_D_REAL |
| 379720943U, // GLDFF1SW_D_SCALED_REAL |
| 379720943U, // GLDFF1SW_D_SXTW_REAL |
| 379720943U, // GLDFF1SW_D_SXTW_SCALED_REAL |
| 379720943U, // GLDFF1SW_D_UXTW_REAL |
| 379720943U, // GLDFF1SW_D_UXTW_SCALED_REAL |
| 883037244U, // GLDFF1W_D_IMM_REAL |
| 379720764U, // GLDFF1W_D_REAL |
| 379720764U, // GLDFF1W_D_SCALED_REAL |
| 379720764U, // GLDFF1W_D_SXTW_REAL |
| 379720764U, // GLDFF1W_D_SXTW_SCALED_REAL |
| 379720764U, // GLDFF1W_D_UXTW_REAL |
| 379720764U, // GLDFF1W_D_UXTW_SCALED_REAL |
| 815936572U, // GLDFF1W_IMM_REAL |
| 379728956U, // GLDFF1W_SXTW_REAL |
| 379728956U, // GLDFF1W_SXTW_SCALED_REAL |
| 379728956U, // GLDFF1W_UXTW_REAL |
| 379728956U, // GLDFF1W_UXTW_SCALED_REAL |
| 152359U, // HINT |
| 78607U, // HLT |
| 75574U, // HVC |
| 536921183U, // INCB_XPiI |
| 536922063U, // INCD_XPiI |
| 536889295U, // INCD_ZPiI |
| 536922647U, // INCH_XPiI |
| 6842903U, // INCH_ZPiI |
| 2315308999U, // INCP_XP_B |
| 2348863431U, // INCP_XP_D |
| 2717962183U, // INCP_XP_H |
| 2415972295U, // INCP_XP_S |
| 2147504071U, // INCP_ZP_D |
| 604532679U, // INCP_ZP_H |
| 2147520455U, // INCP_ZP_S |
| 536925367U, // INCW_XPiI |
| 536908983U, // INCW_ZPiI |
| 100676987U, // INDEX_II_B |
| 100685179U, // INDEX_II_D |
| 242775419U, // INDEX_II_H |
| 100701563U, // INDEX_II_S |
| 100676987U, // INDEX_IR_B |
| 100685179U, // INDEX_IR_D |
| 242775419U, // INDEX_IR_H |
| 100701563U, // INDEX_IR_S |
| 100676987U, // INDEX_RI_B |
| 100685179U, // INDEX_RI_D |
| 242775419U, // INDEX_RI_H |
| 100701563U, // INDEX_RI_S |
| 100676987U, // INDEX_RR_B |
| 100685179U, // INDEX_RR_D |
| 242775419U, // INDEX_RR_H |
| 100701563U, // INDEX_RR_S |
| 2516595051U, // INSR_ZR_B |
| 2516603243U, // INSR_ZR_D |
| 615018859U, // INSR_ZR_H |
| 2516619627U, // INSR_ZR_S |
| 2516595051U, // INSR_ZV_B |
| 2516603243U, // INSR_ZV_D |
| 615018859U, // INSR_ZV_H |
| 2516619627U, // INSR_ZV_S |
| 3065049710U, // INSvi16gpr |
| 951120494U, // INSvi16lane |
| 3065573998U, // INSvi32gpr |
| 3099128430U, // INSvi32lane |
| 3063476846U, // INSvi64gpr |
| 949547630U, // INSvi64lane |
| 3066098286U, // INSvi8gpr |
| 3099652718U, // INSvi8lane |
| 116287U, // ISB |
| 302039859U, // LASTA_RPZ_B |
| 302039859U, // LASTA_RPZ_D |
| 302039859U, // LASTA_RPZ_H |
| 302039859U, // LASTA_RPZ_S |
| 302039859U, // LASTA_VPZ_B |
| 302039859U, // LASTA_VPZ_D |
| 302039859U, // LASTA_VPZ_H |
| 302039859U, // LASTA_VPZ_S |
| 302040718U, // LASTB_RPZ_B |
| 302040718U, // LASTB_RPZ_D |
| 302040718U, // LASTB_RPZ_H |
| 302040718U, // LASTB_RPZ_S |
| 302040718U, // LASTB_VPZ_B |
| 302040718U, // LASTB_VPZ_D |
| 302040718U, // LASTB_VPZ_H |
| 302040718U, // LASTB_VPZ_S |
| 379741036U, // LD1B |
| 379716460U, // LD1B_D |
| 379716460U, // LD1B_D_IMM_REAL |
| 379749228U, // LD1B_H |
| 379749228U, // LD1B_H_IMM_REAL |
| 379741036U, // LD1B_IMM_REAL |
| 379724652U, // LD1B_S |
| 379724652U, // LD1B_S_IMM_REAL |
| 379717440U, // LD1D |
| 379717440U, // LD1D_IMM_REAL |
| 172064U, // LD1Fourv16b |
| 13287456U, // LD1Fourv16b_POST |
| 188448U, // LD1Fourv1d |
| 13828128U, // LD1Fourv1d_POST |
| 204832U, // LD1Fourv2d |
| 13320224U, // LD1Fourv2d_POST |
| 221216U, // LD1Fourv2s |
| 13860896U, // LD1Fourv2s_POST |
| 237600U, // LD1Fourv4h |
| 13877280U, // LD1Fourv4h_POST |
| 253984U, // LD1Fourv4s |
| 13369376U, // LD1Fourv4s_POST |
| 270368U, // LD1Fourv8b |
| 13910048U, // LD1Fourv8b_POST |
| 286752U, // LD1Fourv8h |
| 13402144U, // LD1Fourv8h_POST |
| 379750702U, // LD1H |
| 379717934U, // LD1H_D |
| 379717934U, // LD1H_D_IMM_REAL |
| 379750702U, // LD1H_IMM_REAL |
| 379726126U, // LD1H_S |
| 379726126U, // LD1H_S_IMM_REAL |
| 172064U, // LD1Onev16b |
| 14336032U, // LD1Onev16b_POST |
| 188448U, // LD1Onev1d |
| 14876704U, // LD1Onev1d_POST |
| 204832U, // LD1Onev2d |
| 14368800U, // LD1Onev2d_POST |
| 221216U, // LD1Onev2s |
| 14909472U, // LD1Onev2s_POST |
| 237600U, // LD1Onev4h |
| 14925856U, // LD1Onev4h_POST |
| 253984U, // LD1Onev4s |
| 14417952U, // LD1Onev4s_POST |
| 270368U, // LD1Onev8b |
| 14958624U, // LD1Onev8b_POST |
| 286752U, // LD1Onev8h |
| 14450720U, // LD1Onev8h_POST |
| 379716999U, // LD1RB_D_IMM |
| 379749767U, // LD1RB_H_IMM |
| 379741575U, // LD1RB_IMM |
| 379725191U, // LD1RB_S_IMM |
| 379717698U, // LD1RD_IMM |
| 379718450U, // LD1RH_D_IMM |
| 379751218U, // LD1RH_IMM |
| 379726642U, // LD1RH_S_IMM |
| 379741567U, // LD1RQ_B |
| 379741567U, // LD1RQ_B_IMM |
| 379717690U, // LD1RQ_D |
| 379717690U, // LD1RQ_D_IMM |
| 379751210U, // LD1RQ_H |
| 379751210U, // LD1RQ_H_IMM |
| 379729113U, // LD1RQ_W |
| 379729113U, // LD1RQ_W_IMM |
| 379717201U, // LD1RSB_D_IMM |
| 379749969U, // LD1RSB_H_IMM |
| 379725393U, // LD1RSB_S_IMM |
| 379718639U, // LD1RSH_D_IMM |
| 379726831U, // LD1RSH_S_IMM |
| 379720968U, // LD1RSW_IMM |
| 379720929U, // LD1RW_D_IMM |
| 379729121U, // LD1RW_IMM |
| 176305U, // LD1Rv16b |
| 15388849U, // LD1Rv16b_POST |
| 192689U, // LD1Rv1d |
| 14880945U, // LD1Rv1d_POST |
| 209073U, // LD1Rv2d |
| 14897329U, // LD1Rv2d_POST |
| 225457U, // LD1Rv2s |
| 15962289U, // LD1Rv2s_POST |
| 241841U, // LD1Rv4h |
| 16502961U, // LD1Rv4h_POST |
| 258225U, // LD1Rv4s |
| 15995057U, // LD1Rv4s_POST |
| 274609U, // LD1Rv8b |
| 15487153U, // LD1Rv8b_POST |
| 290993U, // LD1Rv8h |
| 16552113U, // LD1Rv8h_POST |
| 379717147U, // LD1SB_D |
| 379717147U, // LD1SB_D_IMM_REAL |
| 379749915U, // LD1SB_H |
| 379749915U, // LD1SB_H_IMM_REAL |
| 379725339U, // LD1SB_S |
| 379725339U, // LD1SB_S_IMM_REAL |
| 379718598U, // LD1SH_D |
| 379718598U, // LD1SH_D_IMM_REAL |
| 379726790U, // LD1SH_S |
| 379726790U, // LD1SH_S_IMM_REAL |
| 379720936U, // LD1SW_D |
| 379720936U, // LD1SW_D_IMM_REAL |
| 172064U, // LD1Threev16b |
| 16957472U, // LD1Threev16b_POST |
| 188448U, // LD1Threev1d |
| 17498144U, // LD1Threev1d_POST |
| 204832U, // LD1Threev2d |
| 16990240U, // LD1Threev2d_POST |
| 221216U, // LD1Threev2s |
| 17530912U, // LD1Threev2s_POST |
| 237600U, // LD1Threev4h |
| 17547296U, // LD1Threev4h_POST |
| 253984U, // LD1Threev4s |
| 17039392U, // LD1Threev4s_POST |
| 270368U, // LD1Threev8b |
| 17580064U, // LD1Threev8b_POST |
| 286752U, // LD1Threev8h |
| 17072160U, // LD1Threev8h_POST |
| 172064U, // LD1Twov16b |
| 13811744U, // LD1Twov16b_POST |
| 188448U, // LD1Twov1d |
| 14352416U, // LD1Twov1d_POST |
| 204832U, // LD1Twov2d |
| 13844512U, // LD1Twov2d_POST |
| 221216U, // LD1Twov2s |
| 14385184U, // LD1Twov2s_POST |
| 237600U, // LD1Twov4h |
| 14401568U, // LD1Twov4h_POST |
| 253984U, // LD1Twov4s |
| 13893664U, // LD1Twov4s_POST |
| 270368U, // LD1Twov8b |
| 14434336U, // LD1Twov8b_POST |
| 286752U, // LD1Twov8h |
| 13926432U, // LD1Twov8h_POST |
| 379728950U, // LD1W |
| 379720758U, // LD1W_D |
| 379720758U, // LD1W_D_IMM_REAL |
| 379728950U, // LD1W_IMM_REAL |
| 18128928U, // LD1i16 |
| 18661408U, // LD1i16_POST |
| 18145312U, // LD1i32 |
| 19202080U, // LD1i32_POST |
| 18161696U, // LD1i64 |
| 19742752U, // LD1i64_POST |
| 18178080U, // LD1i8 |
| 20283424U, // LD1i8_POST |
| 379741097U, // LD2B |
| 379741097U, // LD2B_IMM |
| 379717484U, // LD2D |
| 379717484U, // LD2D_IMM |
| 379750763U, // LD2H |
| 379750763U, // LD2H_IMM |
| 176311U, // LD2Rv16b |
| 16437431U, // LD2Rv16b_POST |
| 192695U, // LD2Rv1d |
| 14356663U, // LD2Rv1d_POST |
| 209079U, // LD2Rv2d |
| 14373047U, // LD2Rv2d_POST |
| 225463U, // LD2Rv2s |
| 14913719U, // LD2Rv2s_POST |
| 241847U, // LD2Rv4h |
| 15978679U, // LD2Rv4h_POST |
| 258231U, // LD2Rv4s |
| 14946487U, // LD2Rv4s_POST |
| 274615U, // LD2Rv8b |
| 16535735U, // LD2Rv8b_POST |
| 290999U, // LD2Rv8h |
| 16027831U, // LD2Rv8h_POST |
| 172162U, // LD2Twov16b |
| 13811842U, // LD2Twov16b_POST |
| 204930U, // LD2Twov2d |
| 13844610U, // LD2Twov2d_POST |
| 221314U, // LD2Twov2s |
| 14385282U, // LD2Twov2s_POST |
| 237698U, // LD2Twov4h |
| 14401666U, // LD2Twov4h_POST |
| 254082U, // LD2Twov4s |
| 13893762U, // LD2Twov4s_POST |
| 270466U, // LD2Twov8b |
| 14434434U, // LD2Twov8b_POST |
| 286850U, // LD2Twov8h |
| 13926530U, // LD2Twov8h_POST |
| 379729002U, // LD2W |
| 379729002U, // LD2W_IMM |
| 18129026U, // LD2i16 |
| 19185794U, // LD2i16_POST |
| 18145410U, // LD2i32 |
| 19726466U, // LD2i32_POST |
| 18161794U, // LD2i64 |
| 20791426U, // LD2i64_POST |
| 18178178U, // LD2i8 |
| 18710658U, // LD2i8_POST |
| 379741118U, // LD3B |
| 379741118U, // LD3B_IMM |
| 379717496U, // LD3D |
| 379717496U, // LD3D_IMM |
| 379750775U, // LD3H |
| 379750775U, // LD3H_IMM |
| 176317U, // LD3Rv16b |
| 21156029U, // LD3Rv16b_POST |
| 192701U, // LD3Rv1d |
| 17502397U, // LD3Rv1d_POST |
| 209085U, // LD3Rv2d |
| 17518781U, // LD3Rv2d_POST |
| 225469U, // LD3Rv2s |
| 21729469U, // LD3Rv2s_POST |
| 241853U, // LD3Rv4h |
| 22270141U, // LD3Rv4h_POST |
| 258237U, // LD3Rv4s |
| 21762237U, // LD3Rv4s_POST |
| 274621U, // LD3Rv8b |
| 21254333U, // LD3Rv8b_POST |
| 291005U, // LD3Rv8h |
| 22319293U, // LD3Rv8h_POST |
| 172553U, // LD3Threev16b |
| 16957961U, // LD3Threev16b_POST |
| 205321U, // LD3Threev2d |
| 16990729U, // LD3Threev2d_POST |
| 221705U, // LD3Threev2s |
| 17531401U, // LD3Threev2s_POST |
| 238089U, // LD3Threev4h |
| 17547785U, // LD3Threev4h_POST |
| 254473U, // LD3Threev4s |
| 17039881U, // LD3Threev4s_POST |
| 270857U, // LD3Threev8b |
| 17580553U, // LD3Threev8b_POST |
| 287241U, // LD3Threev8h |
| 17072649U, // LD3Threev8h_POST |
| 379729014U, // LD3W |
| 379729014U, // LD3W_IMM |
| 18129417U, // LD3i16 |
| 22856201U, // LD3i16_POST |
| 18145801U, // LD3i32 |
| 23396873U, // LD3i32_POST |
| 18162185U, // LD3i64 |
| 23937545U, // LD3i64_POST |
| 18178569U, // LD3i8 |
| 24478217U, // LD3i8_POST |
| 379741130U, // LD4B |
| 379741130U, // LD4B_IMM |
| 379717508U, // LD4D |
| 379717508U, // LD4D_IMM |
| 172583U, // LD4Fourv16b |
| 13287975U, // LD4Fourv16b_POST |
| 205351U, // LD4Fourv2d |
| 13320743U, // LD4Fourv2d_POST |
| 221735U, // LD4Fourv2s |
| 13861415U, // LD4Fourv2s_POST |
| 238119U, // LD4Fourv4h |
| 13877799U, // LD4Fourv4h_POST |
| 254503U, // LD4Fourv4s |
| 13369895U, // LD4Fourv4s_POST |
| 270887U, // LD4Fourv8b |
| 13910567U, // LD4Fourv8b_POST |
| 287271U, // LD4Fourv8h |
| 13402663U, // LD4Fourv8h_POST |
| 379750787U, // LD4H |
| 379750787U, // LD4H_IMM |
| 176323U, // LD4Rv16b |
| 15913155U, // LD4Rv16b_POST |
| 192707U, // LD4Rv1d |
| 13832387U, // LD4Rv1d_POST |
| 209091U, // LD4Rv2d |
| 13848771U, // LD4Rv2d_POST |
| 225475U, // LD4Rv2s |
| 14389443U, // LD4Rv2s_POST |
| 241859U, // LD4Rv4h |
| 14930115U, // LD4Rv4h_POST |
| 258243U, // LD4Rv4s |
| 14422211U, // LD4Rv4s_POST |
| 274627U, // LD4Rv8b |
| 16011459U, // LD4Rv8b_POST |
| 291011U, // LD4Rv8h |
| 14979267U, // LD4Rv8h_POST |
| 379729026U, // LD4W |
| 379729026U, // LD4W_IMM |
| 18129447U, // LD4i16 |
| 19710503U, // LD4i16_POST |
| 18145831U, // LD4i32 |
| 20775463U, // LD4i32_POST |
| 18162215U, // LD4i64 |
| 24986151U, // LD4i64_POST |
| 18178599U, // LD4i8 |
| 19235367U, // LD4i8_POST |
| 973169622U, // LDADDAB |
| 973171096U, // LDADDAH |
| 973169821U, // LDADDALB |
| 973171251U, // LDADDALH |
| 973171888U, // LDADDALW |
| 973171888U, // LDADDALX |
| 973169280U, // LDADDAW |
| 973169280U, // LDADDAX |
| 973169780U, // LDADDB |
| 973171237U, // LDADDH |
| 973169921U, // LDADDLB |
| 973171351U, // LDADDLH |
| 973172058U, // LDADDLW |
| 973172058U, // LDADDLX |
| 973170660U, // LDADDW |
| 973170660U, // LDADDX |
| 2253964738U, // LDAPRB |
| 2253966189U, // LDAPRH |
| 2253967684U, // LDAPRW |
| 2253967684U, // LDAPRX |
| 106481133U, // LDAPURBi |
| 106482584U, // LDAPURHi |
| 106481264U, // LDAPURSBWi |
| 106481264U, // LDAPURSBXi |
| 106482702U, // LDAPURSHWi |
| 106482702U, // LDAPURSHXi |
| 106485031U, // LDAPURSWi |
| 106484117U, // LDAPURXi |
| 106484117U, // LDAPURi |
| 2253964686U, // LDARB |
| 2253966137U, // LDARH |
| 2253967561U, // LDARW |
| 2253967561U, // LDARX |
| 2248200299U, // LDAXPW |
| 2248200299U, // LDAXPX |
| 2253964797U, // LDAXRB |
| 2253966248U, // LDAXRH |
| 2253967800U, // LDAXRW |
| 2253967800U, // LDAXRX |
| 973169678U, // LDCLRAB |
| 973171142U, // LDCLRAH |
| 973169861U, // LDCLRALB |
| 973171291U, // LDCLRALH |
| 973171955U, // LDCLRALW |
| 973171955U, // LDCLRALX |
| 973169394U, // LDCLRAW |
| 973169394U, // LDCLRAX |
| 973170083U, // LDCLRB |
| 973171534U, // LDCLRH |
| 973169957U, // LDCLRLB |
| 973171387U, // LDCLRLH |
| 973172249U, // LDCLRLW |
| 973172249U, // LDCLRLX |
| 973173017U, // LDCLRW |
| 973173017U, // LDCLRX |
| 973169687U, // LDEORAB |
| 973171151U, // LDEORAH |
| 973169871U, // LDEORALB |
| 973171301U, // LDEORALH |
| 973171964U, // LDEORALW |
| 973171964U, // LDEORALX |
| 973169402U, // LDEORAW |
| 973169402U, // LDEORAX |
| 973170106U, // LDEORB |
| 973171557U, // LDEORH |
| 973169966U, // LDEORLB |
| 973171396U, // LDEORLH |
| 973172257U, // LDEORLW |
| 973172257U, // LDEORLX |
| 973173043U, // LDEORW |
| 973173043U, // LDEORX |
| 379716466U, // LDFF1B_D_REAL |
| 379749234U, // LDFF1B_H_REAL |
| 379741042U, // LDFF1B_REAL |
| 379724658U, // LDFF1B_S_REAL |
| 379717446U, // LDFF1D_REAL |
| 379717940U, // LDFF1H_D_REAL |
| 379750708U, // LDFF1H_REAL |
| 379726132U, // LDFF1H_S_REAL |
| 379717154U, // LDFF1SB_D_REAL |
| 379749922U, // LDFF1SB_H_REAL |
| 379725346U, // LDFF1SB_S_REAL |
| 379718605U, // LDFF1SH_D_REAL |
| 379726797U, // LDFF1SH_S_REAL |
| 379720943U, // LDFF1SW_D_REAL |
| 379720764U, // LDFF1W_D_REAL |
| 379728956U, // LDFF1W_REAL |
| 2253964693U, // LDLARB |
| 2253966144U, // LDLARH |
| 2253967567U, // LDLARW |
| 2253967567U, // LDLARX |
| 379716474U, // LDNF1B_D_IMM_REAL |
| 379749242U, // LDNF1B_H_IMM_REAL |
| 379741050U, // LDNF1B_IMM_REAL |
| 379724666U, // LDNF1B_S_IMM_REAL |
| 379717454U, // LDNF1D_IMM_REAL |
| 379717948U, // LDNF1H_D_IMM_REAL |
| 379750716U, // LDNF1H_IMM_REAL |
| 379726140U, // LDNF1H_S_IMM_REAL |
| 379717163U, // LDNF1SB_D_IMM_REAL |
| 379749931U, // LDNF1SB_H_IMM_REAL |
| 379725355U, // LDNF1SB_S_IMM_REAL |
| 379718614U, // LDNF1SH_D_IMM_REAL |
| 379726806U, // LDNF1SH_S_IMM_REAL |
| 379720952U, // LDNF1SW_D_IMM_REAL |
| 379720772U, // LDNF1W_D_IMM_REAL |
| 379728964U, // LDNF1W_IMM_REAL |
| 2248200224U, // LDNPDi |
| 2248200224U, // LDNPQi |
| 2248200224U, // LDNPSi |
| 2248200224U, // LDNPWi |
| 2248200224U, // LDNPXi |
| 379741058U, // LDNT1B_ZRI |
| 379741058U, // LDNT1B_ZRR |
| 379717462U, // LDNT1D_ZRI |
| 379717462U, // LDNT1D_ZRR |
| 379750724U, // LDNT1H_ZRI |
| 379750724U, // LDNT1H_ZRR |
| 379728972U, // LDNT1W_ZRI |
| 379728972U, // LDNT1W_ZRR |
| 2248200156U, // LDPDi |
| 2516676572U, // LDPDpost |
| 2516676572U, // LDPDpre |
| 2248200156U, // LDPQi |
| 2516676572U, // LDPQpost |
| 2516676572U, // LDPQpre |
| 2248201473U, // LDPSWi |
| 2516677889U, // LDPSWpost |
| 2516677889U, // LDPSWpre |
| 2248200156U, // LDPSi |
| 2516676572U, // LDPSpost |
| 2516676572U, // LDPSpre |
| 2248200156U, // LDPWi |
| 2516676572U, // LDPWpost |
| 2516676572U, // LDPWpre |
| 2248200156U, // LDPXi |
| 2516676572U, // LDPXpost |
| 2516676572U, // LDPXpre |
| 106480223U, // LDRAAindexed |
| 374956639U, // LDRAAwriteback |
| 106480640U, // LDRABindexed |
| 374957056U, // LDRABwriteback |
| 374957469U, // LDRBBpost |
| 374957469U, // LDRBBpre |
| 106481053U, // LDRBBroW |
| 106481053U, // LDRBBroX |
| 106481053U, // LDRBBui |
| 374960359U, // LDRBpost |
| 374960359U, // LDRBpre |
| 106483943U, // LDRBroW |
| 106483943U, // LDRBroX |
| 106483943U, // LDRBui |
| 436261095U, // LDRDl |
| 374960359U, // LDRDpost |
| 374960359U, // LDRDpre |
| 106483943U, // LDRDroW |
| 106483943U, // LDRDroX |
| 106483943U, // LDRDui |
| 374958920U, // LDRHHpost |
| 374958920U, // LDRHHpre |
| 106482504U, // LDRHHroW |
| 106482504U, // LDRHHroX |
| 106482504U, // LDRHHui |
| 374960359U, // LDRHpost |
| 374960359U, // LDRHpre |
| 106483943U, // LDRHroW |
| 106483943U, // LDRHroX |
| 106483943U, // LDRHui |
| 436261095U, // LDRQl |
| 374960359U, // LDRQpost |
| 374960359U, // LDRQpre |
| 106483943U, // LDRQroW |
| 106483943U, // LDRQroX |
| 106483943U, // LDRQui |
| 374957657U, // LDRSBWpost |
| 374957657U, // LDRSBWpre |
| 106481241U, // LDRSBWroW |
| 106481241U, // LDRSBWroX |
| 106481241U, // LDRSBWui |
| 374957657U, // LDRSBXpost |
| 374957657U, // LDRSBXpre |
| 106481241U, // LDRSBXroW |
| 106481241U, // LDRSBXroX |
| 106481241U, // LDRSBXui |
| 374959095U, // LDRSHWpost |
| 374959095U, // LDRSHWpre |
| 106482679U, // LDRSHWroW |
| 106482679U, // LDRSHWroX |
| 106482679U, // LDRSHWui |
| 374959095U, // LDRSHXpost |
| 374959095U, // LDRSHXpre |
| 106482679U, // LDRSHXroW |
| 106482679U, // LDRSHXroX |
| 106482679U, // LDRSHXui |
| 436262160U, // LDRSWl |
| 374961424U, // LDRSWpost |
| 374961424U, // LDRSWpre |
| 106485008U, // LDRSWroW |
| 106485008U, // LDRSWroX |
| 106485008U, // LDRSWui |
| 436261095U, // LDRSl |
| 374960359U, // LDRSpost |
| 374960359U, // LDRSpre |
| 106483943U, // LDRSroW |
| 106483943U, // LDRSroX |
| 106483943U, // LDRSui |
| 436261095U, // LDRWl |
| 374960359U, // LDRWpost |
| 374960359U, // LDRWpre |
| 106483943U, // LDRWroW |
| 106483943U, // LDRWroX |
| 106483943U, // LDRWui |
| 436261095U, // LDRXl |
| 374960359U, // LDRXpost |
| 374960359U, // LDRXpre |
| 106483943U, // LDRXroW |
| 106483943U, // LDRXroX |
| 106483943U, // LDRXui |
| 106803431U, // LDR_PXI |
| 106803431U, // LDR_ZXI |
| 973169703U, // LDSETAB |
| 973171167U, // LDSETAH |
| 973169889U, // LDSETALB |
| 973171319U, // LDSETALH |
| 973171980U, // LDSETALW |
| 973171980U, // LDSETALX |
| 973169442U, // LDSETAW |
| 973169442U, // LDSETAX |
| 973170303U, // LDSETB |
| 973171736U, // LDSETH |
| 973169982U, // LDSETLB |
| 973171412U, // LDSETLH |
| 973172305U, // LDSETLW |
| 973172305U, // LDSETLX |
| 973173476U, // LDSETW |
| 973173476U, // LDSETX |
| 973169712U, // LDSMAXAB |
| 973171176U, // LDSMAXAH |
| 973169899U, // LDSMAXALB |
| 973171329U, // LDSMAXALH |
| 973171989U, // LDSMAXALW |
| 973171989U, // LDSMAXALX |
| 973169466U, // LDSMAXAW |
| 973169466U, // LDSMAXAX |
| 973170392U, // LDSMAXB |
| 973171768U, // LDSMAXH |
| 973169991U, // LDSMAXLB |
| 973171454U, // LDSMAXLH |
| 973172360U, // LDSMAXLW |
| 973172360U, // LDSMAXLX |
| 973174109U, // LDSMAXW |
| 973174109U, // LDSMAXX |
| 973169631U, // LDSMINAB |
| 973171115U, // LDSMINAH |
| 973169831U, // LDSMINALB |
| 973171261U, // LDSMINALH |
| 973171920U, // LDSMINALW |
| 973171920U, // LDSMINALX |
| 973169349U, // LDSMINAW |
| 973169349U, // LDSMINAX |
| 973170016U, // LDSMINB |
| 973171474U, // LDSMINH |
| 973169930U, // LDSMINLB |
| 973171360U, // LDSMINLH |
| 973172211U, // LDSMINLW |
| 973172211U, // LDSMINLX |
| 973172462U, // LDSMINW |
| 973172462U, // LDSMINX |
| 106481098U, // LDTRBi |
| 106482549U, // LDTRHi |
| 106481248U, // LDTRSBWi |
| 106481248U, // LDTRSBXi |
| 106482686U, // LDTRSHWi |
| 106482686U, // LDTRSHXi |
| 106485015U, // LDTRSWi |
| 106484081U, // LDTRWi |
| 106484081U, // LDTRXi |
| 973169722U, // LDUMAXAB |
| 973171186U, // LDUMAXAH |
| 973169910U, // LDUMAXALB |
| 973171340U, // LDUMAXALH |
| 973171999U, // LDUMAXALW |
| 973171999U, // LDUMAXALX |
| 973169475U, // LDUMAXAW |
| 973169475U, // LDUMAXAX |
| 973170401U, // LDUMAXB |
| 973171777U, // LDUMAXH |
| 973170001U, // LDUMAXLB |
| 973171464U, // LDUMAXLH |
| 973172369U, // LDUMAXLW |
| 973172369U, // LDUMAXLX |
| 973174117U, // LDUMAXW |
| 973174117U, // LDUMAXX |
| 973169641U, // LDUMINAB |
| 973171125U, // LDUMINAH |
| 973169842U, // LDUMINALB |
| 973171272U, // LDUMINALH |
| 973171930U, // LDUMINALW |
| 973171930U, // LDUMINALX |
| 973169358U, // LDUMINAW |
| 973169358U, // LDUMINAX |
| 973170025U, // LDUMINB |
| 973171483U, // LDUMINH |
| 973169940U, // LDUMINLB |
| 973171370U, // LDUMINLH |
| 973172220U, // LDUMINLW |
| 973172220U, // LDUMINLX |
| 973172470U, // LDUMINW |
| 973172470U, // LDUMINX |
| 106481118U, // LDURBBi |
| 106484104U, // LDURBi |
| 106484104U, // LDURDi |
| 106482569U, // LDURHHi |
| 106484104U, // LDURHi |
| 106484104U, // LDURQi |
| 106481256U, // LDURSBWi |
| 106481256U, // LDURSBXi |
| 106482694U, // LDURSHWi |
| 106482694U, // LDURSHXi |
| 106485023U, // LDURSWi |
| 106484104U, // LDURSi |
| 106484104U, // LDURWi |
| 106484104U, // LDURXi |
| 2248200327U, // LDXPW |
| 2248200327U, // LDXPX |
| 2253964805U, // LDXRB |
| 2253966256U, // LDXRH |
| 2253967807U, // LDXRW |
| 2253967807U, // LDXRX |
| 0U, // LOADgot |
| 302002471U, // LSLR_ZPmZ_B |
| 302010663U, // LSLR_ZPmZ_D |
| 2186309927U, // LSLR_ZPmZ_H |
| 302027047U, // LSLR_ZPmZ_S |
| 100716088U, // LSLVWr |
| 100716088U, // LSLVXr |
| 302001720U, // LSL_WIDE_ZPmZ_B |
| 2186309176U, // LSL_WIDE_ZPmZ_H |
| 302026296U, // LSL_WIDE_ZPmZ_S |
| 167783992U, // LSL_WIDE_ZZZ_B |
| 2387111480U, // LSL_WIDE_ZZZ_H |
| 268471864U, // LSL_WIDE_ZZZ_S |
| 302001720U, // LSL_ZPmI_B |
| 302009912U, // LSL_ZPmI_D |
| 2186309176U, // LSL_ZPmI_H |
| 302026296U, // LSL_ZPmI_S |
| 302001720U, // LSL_ZPmZ_B |
| 302009912U, // LSL_ZPmZ_D |
| 2186309176U, // LSL_ZPmZ_H |
| 302026296U, // LSL_ZPmZ_S |
| 167783992U, // LSL_ZZI_B |
| 201346616U, // LSL_ZZI_D |
| 239627832U, // LSL_ZZI_H |
| 268471864U, // LSL_ZZI_S |
| 302002518U, // LSRR_ZPmZ_B |
| 302010710U, // LSRR_ZPmZ_D |
| 2186309974U, // LSRR_ZPmZ_H |
| 302027094U, // LSRR_ZPmZ_S |
| 100716897U, // LSRVWr |
| 100716897U, // LSRVXr |
| 302002529U, // LSR_WIDE_ZPmZ_B |
| 2186309985U, // LSR_WIDE_ZPmZ_H |
| 302027105U, // LSR_WIDE_ZPmZ_S |
| 167784801U, // LSR_WIDE_ZZZ_B |
| 2387112289U, // LSR_WIDE_ZZZ_H |
| 268472673U, // LSR_WIDE_ZZZ_S |
| 302002529U, // LSR_ZPmI_B |
| 302010721U, // LSR_ZPmI_D |
| 2186309985U, // LSR_ZPmI_H |
| 302027105U, // LSR_ZPmI_S |
| 302002529U, // LSR_ZPmZ_B |
| 302010721U, // LSR_ZPmZ_D |
| 2186309985U, // LSR_ZPmZ_H |
| 302027105U, // LSR_ZPmZ_S |
| 167784801U, // LSR_ZZI_B |
| 201347425U, // LSR_ZZI_D |
| 239628641U, // LSR_ZZI_H |
| 268472673U, // LSR_ZZI_S |
| 100714512U, // MADDWrrr |
| 100714512U, // MADDXrrr |
| 302000017U, // MAD_ZPmZZ_B |
| 302008209U, // MAD_ZPmZZ_D |
| 2186307473U, // MAD_ZPmZZ_H |
| 302024593U, // MAD_ZPmZZ_S |
| 301998771U, // MLA_ZPmZZ_B |
| 302006963U, // MLA_ZPmZZ_D |
| 2186306227U, // MLA_ZPmZZ_H |
| 302023347U, // MLA_ZPmZZ_S |
| 135324339U, // MLAv16i8 |
| 2283332275U, // MLAv2i32 |
| 2283332275U, // MLAv2i32_indexed |
| 136897203U, // MLAv4i16 |
| 136897203U, // MLAv4i16_indexed |
| 137421491U, // MLAv4i32 |
| 137421491U, // MLAv4i32_indexed |
| 2285429427U, // MLAv8i16 |
| 2285429427U, // MLAv8i16_indexed |
| 2285953715U, // MLAv8i8 |
| 302002771U, // MLS_ZPmZZ_B |
| 302010963U, // MLS_ZPmZZ_D |
| 2186310227U, // MLS_ZPmZZ_H |
| 302027347U, // MLS_ZPmZZ_S |
| 135328339U, // MLSv16i8 |
| 2283336275U, // MLSv2i32 |
| 2283336275U, // MLSv2i32_indexed |
| 136901203U, // MLSv4i16 |
| 136901203U, // MLSv4i16_indexed |
| 137425491U, // MLSv4i32 |
| 137425491U, // MLSv4i32_indexed |
| 2285433427U, // MLSv8i16 |
| 2285433427U, // MLSv8i16_indexed |
| 2285957715U, // MLSv8i8 |
| 1006685329U, // MOVID |
| 3188763793U, // MOVIv16b_ns |
| 1008774289U, // MOVIv2d_ns |
| 3189288081U, // MOVIv2i32 |
| 3189288081U, // MOVIv2s_msl |
| 3190336657U, // MOVIv4i16 |
| 3190860945U, // MOVIv4i32 |
| 3190860945U, // MOVIv4s_msl |
| 3191909521U, // MOVIv8b_ns |
| 3191385233U, // MOVIv8i16 |
| 402705564U, // MOVKWi |
| 402705564U, // MOVKXi |
| 3187724142U, // MOVNWi |
| 3187724142U, // MOVNXi |
| 13705U, // MOVPRFX_ZPmZ_B |
| 21897U, // MOVPRFX_ZPmZ_D |
| 2181592457U, // MOVPRFX_ZPmZ_H |
| 38281U, // MOVPRFX_ZPmZ_S |
| 302003593U, // MOVPRFX_ZPzZ_B |
| 302011785U, // MOVPRFX_ZPzZ_D |
| 2622518665U, // MOVPRFX_ZPzZ_H |
| 302028169U, // MOVPRFX_ZPzZ_S |
| 2449847689U, // MOVPRFX_ZZ |
| 3187725817U, // MOVZWi |
| 3187725817U, // MOVZXi |
| 0U, // MOVaddr |
| 0U, // MOVaddrBA |
| 0U, // MOVaddrCP |
| 0U, // MOVaddrEXT |
| 0U, // MOVaddrJT |
| 0U, // MOVaddrTLS |
| 0U, // MOVbaseTLS |
| 0U, // MOVi32imm |
| 0U, // MOVi64imm |
| 1073795744U, // MRS |
| 301999685U, // MSB_ZPmZZ_B |
| 302007877U, // MSB_ZPmZZ_D |
| 2186307141U, // MSB_ZPmZZ_H |
| 302024261U, // MSB_ZPmZZ_S |
| 381286U, // MSR |
| 389478U, // MSRpstateImm1 |
| 389478U, // MSRpstateImm4 |
| 100714166U, // MSUBWrrr |
| 100714166U, // MSUBXrrr |
| 167784033U, // MUL_ZI_B |
| 201346657U, // MUL_ZI_D |
| 239627873U, // MUL_ZI_H |
| 268471905U, // MUL_ZI_S |
| 302001761U, // MUL_ZPmZ_B |
| 302009953U, // MUL_ZPmZ_D |
| 2186309217U, // MUL_ZPmZ_H |
| 302026337U, // MUL_ZPmZ_S |
| 68202081U, // MULv16i8 |
| 2216210017U, // MULv2i32 |
| 2216210017U, // MULv2i32_indexed |
| 69774945U, // MULv4i16 |
| 69774945U, // MULv4i16_indexed |
| 70299233U, // MULv4i32 |
| 70299233U, // MULv4i32_indexed |
| 2218307169U, // MULv8i16 |
| 2218307169U, // MULv8i16_indexed |
| 2218831457U, // MULv8i8 |
| 3189288062U, // MVNIv2i32 |
| 3189288062U, // MVNIv2s_msl |
| 3190336638U, // MVNIv4i16 |
| 3190860926U, // MVNIv4i32 |
| 3190860926U, // MVNIv4s_msl |
| 3191385214U, // MVNIv8i16 |
| 302002728U, // NANDS_PPzPP |
| 302000180U, // NAND_PPzPP |
| 10516U, // NEG_ZPmZ_B |
| 18708U, // NEG_ZPmZ_D |
| 2181589268U, // NEG_ZPmZ_H |
| 35092U, // NEG_ZPmZ_S |
| 68200724U, // NEGv16i8 |
| 2248198420U, // NEGv1i64 |
| 68725012U, // NEGv2i32 |
| 2216732948U, // NEGv2i64 |
| 69773588U, // NEGv4i16 |
| 2217781524U, // NEGv4i32 |
| 70822164U, // NEGv8i16 |
| 2218830100U, // NEGv8i8 |
| 302002859U, // NORS_PPzPP |
| 302002490U, // NOR_PPzPP |
| 13114U, // NOT_ZPmZ_B |
| 21306U, // NOT_ZPmZ_D |
| 2181591866U, // NOT_ZPmZ_H |
| 37690U, // NOT_ZPmZ_S |
| 68203322U, // NOTv16i8 |
| 2218832698U, // NOTv8i8 |
| 302002810U, // ORNS_PPzPP |
| 0U, // ORNWrr |
| 100716337U, // ORNWrs |
| 0U, // ORNXrr |
| 100716337U, // ORNXrs |
| 302001969U, // ORN_PPzPP |
| 68202289U, // ORNv16i8 |
| 2218831665U, // ORNv8i8 |
| 302002865U, // ORRS_PPzPP |
| 100716875U, // ORRWri |
| 0U, // ORRWrr |
| 100716875U, // ORRWrs |
| 100716875U, // ORRXri |
| 0U, // ORRXrr |
| 100716875U, // ORRXrs |
| 302002507U, // ORR_PPzPP |
| 201347403U, // ORR_ZI |
| 302002507U, // ORR_ZPmZ_B |
| 302010699U, // ORR_ZPmZ_D |
| 2186309963U, // ORR_ZPmZ_H |
| 302027083U, // ORR_ZPmZ_S |
| 201347403U, // ORR_ZZZ |
| 68202827U, // ORRv16i8 |
| 404287819U, // ORRv2i32 |
| 405336395U, // ORRv4i16 |
| 405860683U, // ORRv4i32 |
| 406384971U, // ORRv8i16 |
| 2218832203U, // ORRv8i8 |
| 302044188U, // ORV_VPZ_B |
| 302044188U, // ORV_VPZ_D |
| 302044188U, // ORV_VPZ_H |
| 302044188U, // ORV_VPZ_S |
| 2248196729U, // PACDA |
| 2248197229U, // PACDB |
| 6341452U, // PACDZA |
| 6342378U, // PACDZB |
| 100713110U, // PACGA |
| 2248196765U, // PACIA |
| 5796U, // PACIA1716 |
| 5927U, // PACIASP |
| 5982U, // PACIAZ |
| 2248197257U, // PACIB |
| 5816U, // PACIB1716 |
| 5943U, // PACIBSP |
| 5996U, // PACIBZ |
| 6341468U, // PACIZA |
| 6342394U, // PACIZB |
| 6301913U, // PFALSE |
| 70820111U, // PMULLv16i8 |
| 1132506590U, // PMULLv1i64 |
| 1166057743U, // PMULLv2i64 |
| 2218307038U, // PMULLv8i8 |
| 68202093U, // PMULv16i8 |
| 2218831469U, // PMULv8i8 |
| 302003042U, // PNEXT_B |
| 302011234U, // PNEXT_D |
| 2387637090U, // PNEXT_H |
| 302027618U, // PNEXT_S |
| 3079537795U, // PRFB_D_PZI |
| 246285443U, // PRFB_D_SCALED |
| 2393769091U, // PRFB_D_SXTW_SCALED |
| 246285443U, // PRFB_D_UXTW_SCALED |
| 246285443U, // PRFB_PRI |
| 2393769091U, // PRFB_PRR |
| 3080062083U, // PRFB_S_PZI |
| 246285443U, // PRFB_S_SXTW_SCALED |
| 2393769091U, // PRFB_S_UXTW_SCALED |
| 1200490542U, // PRFD_D_PZI |
| 246286382U, // PRFD_D_SCALED |
| 2393770030U, // PRFD_D_SXTW_SCALED |
| 246286382U, // PRFD_D_UXTW_SCALED |
| 246286382U, // PRFD_PRI |
| 2393770030U, // PRFD_PRR |
| 1201014830U, // PRFD_S_PZI |
| 246286382U, // PRFD_S_SXTW_SCALED |
| 2393770030U, // PRFD_S_UXTW_SCALED |
| 1234045485U, // PRFH_D_PZI |
| 246286893U, // PRFH_D_SCALED |
| 2393770541U, // PRFH_D_SXTW_SCALED |
| 246286893U, // PRFH_D_UXTW_SCALED |
| 246286893U, // PRFH_PRI |
| 2393770541U, // PRFH_PRR |
| 1234569773U, // PRFH_S_PZI |
| 246286893U, // PRFH_S_SXTW_SCALED |
| 2393770541U, // PRFH_S_UXTW_SCALED |
| 436612781U, // PRFMl |
| 106835629U, // PRFMroW |
| 106835629U, // PRFMroX |
| 106835629U, // PRFMui |
| 246289619U, // PRFS_PRR |
| 106835665U, // PRFUMi |
| 1267602643U, // PRFW_D_PZI |
| 2393773267U, // PRFW_D_SCALED |
| 246289619U, // PRFW_D_SXTW_SCALED |
| 2393773267U, // PRFW_D_UXTW_SCALED |
| 246289619U, // PRFW_PRI |
| 1268126931U, // PRFW_S_PZI |
| 246289619U, // PRFW_S_SXTW_SCALED |
| 2393773267U, // PRFW_S_UXTW_SCALED |
| 2315629382U, // PTEST_PP |
| 2650812975U, // PTRUES_B |
| 2650821167U, // PTRUES_D |
| 26767919U, // PTRUES_H |
| 2650837551U, // PTRUES_S |
| 2650810611U, // PTRUE_B |
| 2650818803U, // PTRUE_D |
| 26765555U, // PTRUE_H |
| 2650835187U, // PTRUE_S |
| 27290705U, // PUNPKHI_PP |
| 27291525U, // PUNPKLO_PP |
| 2216210144U, // RADDHNv2i64_v2i32 |
| 2284904786U, // RADDHNv2i64_v4i32 |
| 69775072U, // RADDHNv4i32_v4i16 |
| 137945426U, // RADDHNv4i32_v8i16 |
| 2282807634U, // RADDHNv8i16_v16i8 |
| 2218831584U, // RADDHNv8i16_v8i8 |
| 2216730741U, // RAX1 |
| 2248200960U, // RBITWr |
| 2248200960U, // RBITXr |
| 13056U, // RBIT_ZPmZ_B |
| 21248U, // RBIT_ZPmZ_D |
| 2181591808U, // RBIT_ZPmZ_H |
| 37632U, // RBIT_ZPmZ_S |
| 68203264U, // RBITv16i8 |
| 2218832640U, // RBITv8i8 |
| 302002840U, // RDFFRS_PPz |
| 6303980U, // RDFFR_P |
| 302002412U, // RDFFR_PPz |
| 2248199810U, // RDVLI_XI |
| 6345439U, // RET |
| 5892U, // RETAA |
| 5899U, // RETAB |
| 0U, // RET_ReallyLR |
| 2248196665U, // REV16Wr |
| 2248196665U, // REV16Xr |
| 68198969U, // REV16v16i8 |
| 2218828345U, // REV16v8i8 |
| 2248196219U, // REV32Xr |
| 68198523U, // REV32v16i8 |
| 69771387U, // REV32v4i16 |
| 70819963U, // REV32v8i16 |
| 2218827899U, // REV32v8i8 |
| 68198944U, // REV64v16i8 |
| 68723232U, // REV64v2i32 |
| 69771808U, // REV64v4i16 |
| 2217779744U, // REV64v4i32 |
| 70820384U, // REV64v8i16 |
| 2218828320U, // REV64v8i8 |
| 18130U, // REVB_ZPmZ_D |
| 2181588690U, // REVB_ZPmZ_H |
| 34514U, // REVB_ZPmZ_S |
| 19506U, // REVH_ZPmZ_D |
| 35890U, // REVH_ZPmZ_S |
| 21827U, // REVW_ZPmZ_D |
| 2248201140U, // REVWr |
| 2248201140U, // REVXr |
| 2315269044U, // REV_PP_B |
| 2348831668U, // REV_PP_D |
| 608727988U, // REV_PP_H |
| 2415956916U, // REV_PP_S |
| 2315269044U, // REV_ZZ_B |
| 2348831668U, // REV_ZZ_D |
| 608727988U, // REV_ZZ_H |
| 2415956916U, // REV_ZZ_S |
| 100714751U, // RMIF |
| 100716863U, // RORVWr |
| 100716863U, // RORVXr |
| 2282807663U, // RSHRNv16i8_shift |
| 2216210209U, // RSHRNv2i32_shift |
| 69775137U, // RSHRNv4i16_shift |
| 2284904815U, // RSHRNv4i32_shift |
| 137945455U, // RSHRNv8i16_shift |
| 2218831649U, // RSHRNv8i8_shift |
| 2216210136U, // RSUBHNv2i64_v2i32 |
| 2284904777U, // RSUBHNv2i64_v4i32 |
| 69775064U, // RSUBHNv4i32_v4i16 |
| 137945417U, // RSUBHNv4i32_v8i16 |
| 2282807625U, // RSUBHNv8i16_v16i8 |
| 2218831576U, // RSUBHNv8i16_v8i8 |
| 137945243U, // SABALv16i8_v8i16 |
| 2283859106U, // SABALv2i32_v2i64 |
| 137424034U, // SABALv4i16_v4i32 |
| 136372379U, // SABALv4i32_v2i64 |
| 2284904603U, // SABALv8i16_v4i32 |
| 2285431970U, // SABALv8i8_v8i16 |
| 135324269U, // SABAv16i8 |
| 2283332205U, // SABAv2i32 |
| 136897133U, // SABAv4i16 |
| 137421421U, // SABAv4i32 |
| 2285429357U, // SABAv8i16 |
| 2285953645U, // SABAv8i8 |
| 70820053U, // SABDLv16i8_v8i16 |
| 2216734028U, // SABDLv2i32_v2i64 |
| 70298956U, // SABDLv4i16_v4i32 |
| 69247189U, // SABDLv4i32_v2i64 |
| 2217779413U, // SABDLv8i16_v4i32 |
| 2218306892U, // SABDLv8i8_v8i16 |
| 302000042U, // SABD_ZPmZ_B |
| 302008234U, // SABD_ZPmZ_D |
| 2186307498U, // SABD_ZPmZ_H |
| 302024618U, // SABD_ZPmZ_S |
| 68200362U, // SABDv16i8 |
| 2216208298U, // SABDv2i32 |
| 69773226U, // SABDv4i16 |
| 70297514U, // SABDv4i32 |
| 2218305450U, // SABDv8i16 |
| 2218829738U, // SABDv8i8 |
| 137949153U, // SADALPv16i8_v8i16 |
| 162066401U, // SADALPv2i32_v1i64 |
| 135852001U, // SADALPv4i16_v2i32 |
| 2283859937U, // SADALPv4i32_v2i64 |
| 137424865U, // SADALPv8i16_v4i32 |
| 2284384225U, // SADALPv8i8_v4i16 |
| 70823921U, // SADDLPv16i8_v8i16 |
| 94941169U, // SADDLPv2i32_v1i64 |
| 68726769U, // SADDLPv4i16_v2i32 |
| 2216734705U, // SADDLPv4i32_v2i64 |
| 70299633U, // SADDLPv8i16_v4i32 |
| 2217258993U, // SADDLPv8i8_v4i16 |
| 67163083U, // SADDLVv16i8v |
| 67163083U, // SADDLVv4i16v |
| 2214646731U, // SADDLVv4i32v |
| 67163083U, // SADDLVv8i16v |
| 2214646731U, // SADDLVv8i8v |
| 70820069U, // SADDLv16i8_v8i16 |
| 2216734066U, // SADDLv2i32_v2i64 |
| 70298994U, // SADDLv4i16_v4i32 |
| 69247205U, // SADDLv4i32_v2i64 |
| 2217779429U, // SADDLv8i16_v4i32 |
| 2218306930U, // SADDLv8i8_v8i16 |
| 302044064U, // SADDV_VPZ_B |
| 302044064U, // SADDV_VPZ_H |
| 302044064U, // SADDV_VPZ_S |
| 2218303982U, // SADDWv16i8_v8i16 |
| 2216735941U, // SADDWv2i32_v2i64 |
| 70300869U, // SADDWv4i16_v4i32 |
| 2216731118U, // SADDWv4i32_v2i64 |
| 70296046U, // SADDWv8i16_v4i32 |
| 2218308805U, // SADDWv8i8_v8i16 |
| 100717072U, // SBCSWr |
| 100717072U, // SBCSXr |
| 100714257U, // SBCWr |
| 100714257U, // SBCXr |
| 100716193U, // SBFMWri |
| 100716193U, // SBFMXri |
| 100714757U, // SCVTFSWDri |
| 100714757U, // SCVTFSWHri |
| 100714757U, // SCVTFSWSri |
| 100714757U, // SCVTFSXDri |
| 100714757U, // SCVTFSXHri |
| 100714757U, // SCVTFSXSri |
| 2248198405U, // SCVTFUWDri |
| 2248198405U, // SCVTFUWHri |
| 2248198405U, // SCVTFUWSri |
| 2248198405U, // SCVTFUXDri |
| 2248198405U, // SCVTFUXHri |
| 2248198405U, // SCVTFUXSri |
| 18693U, // SCVTF_ZPmZ_DtoD |
| 2181589253U, // SCVTF_ZPmZ_DtoH |
| 35077U, // SCVTF_ZPmZ_DtoS |
| 2181589253U, // SCVTF_ZPmZ_HtoH |
| 18693U, // SCVTF_ZPmZ_StoD |
| 2181589253U, // SCVTF_ZPmZ_StoH |
| 35077U, // SCVTF_ZPmZ_StoS |
| 100714757U, // SCVTFd |
| 100714757U, // SCVTFh |
| 100714757U, // SCVTFs |
| 2248198405U, // SCVTFv1i16 |
| 2248198405U, // SCVTFv1i32 |
| 2248198405U, // SCVTFv1i64 |
| 68724997U, // SCVTFv2f32 |
| 2216732933U, // SCVTFv2f64 |
| 2216208645U, // SCVTFv2i32_shift |
| 2216732933U, // SCVTFv2i64_shift |
| 69773573U, // SCVTFv4f16 |
| 2217781509U, // SCVTFv4f32 |
| 69773573U, // SCVTFv4i16_shift |
| 70297861U, // SCVTFv4i32_shift |
| 70822149U, // SCVTFv8f16 |
| 2218305797U, // SCVTFv8i16_shift |
| 302010794U, // SDIVR_ZPmZ_D |
| 302027178U, // SDIVR_ZPmZ_S |
| 100717503U, // SDIVWr |
| 100717503U, // SDIVXr |
| 302011327U, // SDIV_ZPmZ_D |
| 302027711U, // SDIV_ZPmZ_S |
| 3422573357U, // SDOT_ZZZI_D |
| 3456144173U, // SDOT_ZZZI_S |
| 3422573357U, // SDOT_ZZZ_D |
| 3456144173U, // SDOT_ZZZ_S |
| 137425709U, // SDOTlanev16i8 |
| 2283336493U, // SDOTlanev8i8 |
| 137425709U, // SDOTv16i8 |
| 2283336493U, // SDOTv8i8 |
| 302001538U, // SEL_PPPP |
| 302001538U, // SEL_ZPZZ_B |
| 302009730U, // SEL_ZPZZ_D |
| 2387635586U, // SEL_ZPZZ_H |
| 302026114U, // SEL_ZPZZ_S |
| 6341169U, // SETF16 |
| 6341184U, // SETF8 |
| 5959U, // SETFFR |
| 369190666U, // SHA1Crrr |
| 2248198439U, // SHA1Hrr |
| 369192602U, // SHA1Mrrr |
| 369192878U, // SHA1Prrr |
| 137420801U, // SHA1SU0rrr |
| 2284904523U, // SHA1SU1rr |
| 369189009U, // SHA256H2rrr |
| 369191311U, // SHA256Hrrr |
| 2284904469U, // SHA256SU0rr |
| 137420895U, // SHA256SU1rrr |
| 369191258U, // SHA512H |
| 369188999U, // SHA512H2 |
| 2216730634U, // SHA512SU0 |
| 2283855956U, // SHA512SU1 |
| 68200449U, // SHADDv16i8 |
| 2216208385U, // SHADDv2i32 |
| 69773313U, // SHADDv4i16 |
| 70297601U, // SHADDv4i32 |
| 2218305537U, // SHADDv8i16 |
| 2218829825U, // SHADDv8i8 |
| 70820086U, // SHLLv16i8 |
| 2216734152U, // SHLLv2i32 |
| 70299080U, // SHLLv4i16 |
| 2216730870U, // SHLLv4i32 |
| 70295798U, // SHLLv8i16 |
| 2218307016U, // SHLLv8i8 |
| 100715921U, // SHLd |
| 68201873U, // SHLv16i8_shift |
| 2216209809U, // SHLv2i32_shift |
| 2216734097U, // SHLv2i64_shift |
| 69774737U, // SHLv4i16_shift |
| 70299025U, // SHLv4i32_shift |
| 2218306961U, // SHLv8i16_shift |
| 2218831249U, // SHLv8i8_shift |
| 2282807645U, // SHRNv16i8_shift |
| 2216210193U, // SHRNv2i32_shift |
| 69775121U, // SHRNv4i16_shift |
| 2284904797U, // SHRNv4i32_shift |
| 137945437U, // SHRNv8i16_shift |
| 2218831633U, // SHRNv8i8_shift |
| 68200103U, // SHSUBv16i8 |
| 2216208039U, // SHSUBv2i32 |
| 69772967U, // SHSUBv4i16 |
| 70297255U, // SHSUBv4i32 |
| 2218305191U, // SHSUBv8i16 |
| 2218829479U, // SHSUBv8i8 |
| 369192057U, // SLId |
| 135326841U, // SLIv16i8_shift |
| 2283334777U, // SLIv2i32_shift |
| 2283859065U, // SLIv2i64_shift |
| 136899705U, // SLIv4i16_shift |
| 137423993U, // SLIv4i32_shift |
| 2285431929U, // SLIv8i16_shift |
| 2285956217U, // SLIv8i8_shift |
| 137420906U, // SM3PARTW1 |
| 137421310U, // SM3PARTW2 |
| 70295614U, // SM3SS1 |
| 137421383U, // SM3TT1A |
| 137421720U, // SM3TT1B |
| 137421392U, // SM3TT2A |
| 137421749U, // SM3TT2B |
| 2217781339U, // SM4E |
| 70301097U, // SM4ENCKEY |
| 100715874U, // SMADDLrrr |
| 68202617U, // SMAXPv16i8 |
| 2216210553U, // SMAXPv2i32 |
| 69775481U, // SMAXPv4i16 |
| 70299769U, // SMAXPv4i32 |
| 2218307705U, // SMAXPv8i16 |
| 2218831993U, // SMAXPv8i8 |
| 302044200U, // SMAXV_VPZ_B |
| 302044200U, // SMAXV_VPZ_D |
| 302044200U, // SMAXV_VPZ_H |
| 302044200U, // SMAXV_VPZ_S |
| 67163176U, // SMAXVv16i8v |
| 67163176U, // SMAXVv4i16v |
| 2214646824U, // SMAXVv4i32v |
| 67163176U, // SMAXVv8i16v |
| 2214646824U, // SMAXVv8i8v |
| 167785823U, // SMAX_ZI_B |
| 201348447U, // SMAX_ZI_D |
| 239629663U, // SMAX_ZI_H |
| 268473695U, // SMAX_ZI_S |
| 302003551U, // SMAX_ZPmZ_B |
| 302011743U, // SMAX_ZPmZ_D |
| 2186311007U, // SMAX_ZPmZ_H |
| 302028127U, // SMAX_ZPmZ_S |
| 68203871U, // SMAXv16i8 |
| 2216211807U, // SMAXv2i32 |
| 69776735U, // SMAXv4i16 |
| 70301023U, // SMAXv4i32 |
| 2218308959U, // SMAXv8i16 |
| 2218833247U, // SMAXv8i8 |
| 75562U, // SMC |
| 68202541U, // SMINPv16i8 |
| 2216210477U, // SMINPv2i32 |
| 69775405U, // SMINPv4i16 |
| 70299693U, // SMINPv4i32 |
| 2218307629U, // SMINPv8i16 |
| 2218831917U, // SMINPv8i8 |
| 302044148U, // SMINV_VPZ_B |
| 302044148U, // SMINV_VPZ_D |
| 302044148U, // SMINV_VPZ_H |
| 302044148U, // SMINV_VPZ_S |
| 67163124U, // SMINVv16i8v |
| 67163124U, // SMINVv4i16v |
| 2214646772U, // SMINVv4i32v |
| 67163124U, // SMINVv8i16v |
| 2214646772U, // SMINVv8i8v |
| 167784176U, // SMIN_ZI_B |
| 201346800U, // SMIN_ZI_D |
| 239628016U, // SMIN_ZI_H |
| 268472048U, // SMIN_ZI_S |
| 302001904U, // SMIN_ZPmZ_B |
| 302010096U, // SMIN_ZPmZ_D |
| 2186309360U, // SMIN_ZPmZ_H |
| 302026480U, // SMIN_ZPmZ_S |
| 68202224U, // SMINv16i8 |
| 2216210160U, // SMINv2i32 |
| 69775088U, // SMINv4i16 |
| 70299376U, // SMINv4i32 |
| 2218307312U, // SMINv8i16 |
| 2218831600U, // SMINv8i8 |
| 137945269U, // SMLALv16i8_v8i16 |
| 2283859138U, // SMLALv2i32_indexed |
| 2283859138U, // SMLALv2i32_v2i64 |
| 137424066U, // SMLALv4i16_indexed |
| 137424066U, // SMLALv4i16_v4i32 |
| 136372405U, // SMLALv4i32_indexed |
| 136372405U, // SMLALv4i32_v2i64 |
| 2284904629U, // SMLALv8i16_indexed |
| 2284904629U, // SMLALv8i16_v4i32 |
| 2285432002U, // SMLALv8i8_v8i16 |
| 137945393U, // SMLSLv16i8_v8i16 |
| 2283859517U, // SMLSLv2i32_indexed |
| 2283859517U, // SMLSLv2i32_v2i64 |
| 137424445U, // SMLSLv4i16_indexed |
| 137424445U, // SMLSLv4i16_v4i32 |
| 136372529U, // SMLSLv4i32_indexed |
| 136372529U, // SMLSLv4i32_v2i64 |
| 2284904753U, // SMLSLv8i16_indexed |
| 2284904753U, // SMLSLv8i16_v4i32 |
| 2285432381U, // SMLSLv8i8_v8i16 |
| 67163151U, // SMOVvi16to32 |
| 67163151U, // SMOVvi16to64 |
| 2214646799U, // SMOVvi32to64 |
| 2214646799U, // SMOVvi8to32 |
| 2214646799U, // SMOVvi8to64 |
| 100715822U, // SMSUBLrrr |
| 302000880U, // SMULH_ZPmZ_B |
| 302009072U, // SMULH_ZPmZ_D |
| 2186308336U, // SMULH_ZPmZ_H |
| 302025456U, // SMULH_ZPmZ_S |
| 100715248U, // SMULHrr |
| 70820119U, // SMULLv16i8_v8i16 |
| 2216734181U, // SMULLv2i32_indexed |
| 2216734181U, // SMULLv2i32_v2i64 |
| 70299109U, // SMULLv4i16_indexed |
| 70299109U, // SMULLv4i16_v4i32 |
| 69247255U, // SMULLv4i32_indexed |
| 69247255U, // SMULLv4i32_v2i64 |
| 2217779479U, // SMULLv8i16_indexed |
| 2217779479U, // SMULLv8i16_v4i32 |
| 2218307045U, // SMULLv8i8_v8i16 |
| 302000225U, // SPLICE_ZPZ_B |
| 302008417U, // SPLICE_ZPZ_D |
| 2387634273U, // SPLICE_ZPZ_H |
| 302024801U, // SPLICE_ZPZ_S |
| 68202996U, // SQABSv16i8 |
| 2248200692U, // SQABSv1i16 |
| 2248200692U, // SQABSv1i32 |
| 2248200692U, // SQABSv1i64 |
| 2248200692U, // SQABSv1i8 |
| 68727284U, // SQABSv2i32 |
| 2216735220U, // SQABSv2i64 |
| 69775860U, // SQABSv4i16 |
| 2217783796U, // SQABSv4i32 |
| 70824436U, // SQABSv8i16 |
| 2218832372U, // SQABSv8i8 |
| 167782431U, // SQADD_ZI_B |
| 201345055U, // SQADD_ZI_D |
| 239626271U, // SQADD_ZI_H |
| 268470303U, // SQADD_ZI_S |
| 167782431U, // SQADD_ZZZ_B |
| 201345055U, // SQADD_ZZZ_D |
| 2387109919U, // SQADD_ZZZ_H |
| 268470303U, // SQADD_ZZZ_S |
| 68200479U, // SQADDv16i8 |
| 100714527U, // SQADDv1i16 |
| 100714527U, // SQADDv1i32 |
| 100714527U, // SQADDv1i64 |
| 100714527U, // SQADDv1i8 |
| 2216208415U, // SQADDv2i32 |
| 2216732703U, // SQADDv2i64 |
| 69773343U, // SQADDv4i16 |
| 70297631U, // SQADDv4i32 |
| 2218305567U, // SQADDv8i16 |
| 2218829855U, // SQADDv8i8 |
| 536921165U, // SQDECB_XPiI |
| 1342227533U, // SQDECB_XPiWdI |
| 536922045U, // SQDECD_XPiI |
| 1342228413U, // SQDECD_XPiWdI |
| 536889277U, // SQDECD_ZPiI |
| 536922629U, // SQDECH_XPiI |
| 1342228997U, // SQDECH_XPiWdI |
| 6842885U, // SQDECH_ZPiI |
| 167825333U, // SQDECP_XPWd_B |
| 201379765U, // SQDECP_XPWd_D |
| 570478517U, // SQDECP_XPWd_H |
| 268488629U, // SQDECP_XPWd_S |
| 2315308981U, // SQDECP_XP_B |
| 2348863413U, // SQDECP_XP_D |
| 2717962165U, // SQDECP_XP_H |
| 2415972277U, // SQDECP_XP_S |
| 2147504053U, // SQDECP_ZP_D |
| 604532661U, // SQDECP_ZP_H |
| 2147520437U, // SQDECP_ZP_S |
| 536925349U, // SQDECW_XPiI |
| 1342231717U, // SQDECW_XPiWdI |
| 536908965U, // SQDECW_ZPiI |
| 369192121U, // SQDMLALi16 |
| 369192121U, // SQDMLALi32 |
| 369192121U, // SQDMLALv1i32_indexed |
| 369192121U, // SQDMLALv1i64_indexed |
| 2283859129U, // SQDMLALv2i32_indexed |
| 2283859129U, // SQDMLALv2i32_v2i64 |
| 137424057U, // SQDMLALv4i16_indexed |
| 137424057U, // SQDMLALv4i16_v4i32 |
| 136372395U, // SQDMLALv4i32_indexed |
| 136372395U, // SQDMLALv4i32_v2i64 |
| 2284904619U, // SQDMLALv8i16_indexed |
| 2284904619U, // SQDMLALv8i16_v4i32 |
| 369192500U, // SQDMLSLi16 |
| 369192500U, // SQDMLSLi32 |
| 369192500U, // SQDMLSLv1i32_indexed |
| 369192500U, // SQDMLSLv1i64_indexed |
| 2283859508U, // SQDMLSLv2i32_indexed |
| 2283859508U, // SQDMLSLv2i32_v2i64 |
| 137424436U, // SQDMLSLv4i16_indexed |
| 137424436U, // SQDMLSLv4i16_v4i32 |
| 136372519U, // SQDMLSLv4i32_indexed |
| 136372519U, // SQDMLSLv4i32_v2i64 |
| 2284904743U, // SQDMLSLv8i16_indexed |
| 2284904743U, // SQDMLSLv8i16_v4i32 |
| 100715229U, // SQDMULHv1i16 |
| 100715229U, // SQDMULHv1i16_indexed |
| 100715229U, // SQDMULHv1i32 |
| 100715229U, // SQDMULHv1i32_indexed |
| 2216209117U, // SQDMULHv2i32 |
| 2216209117U, // SQDMULHv2i32_indexed |
| 69774045U, // SQDMULHv4i16 |
| 69774045U, // SQDMULHv4i16_indexed |
| 70298333U, // SQDMULHv4i32 |
| 70298333U, // SQDMULHv4i32_indexed |
| 2218306269U, // SQDMULHv8i16 |
| 2218306269U, // SQDMULHv8i16_indexed |
| 100715989U, // SQDMULLi16 |
| 100715989U, // SQDMULLi32 |
| 100715989U, // SQDMULLv1i32_indexed |
| 100715989U, // SQDMULLv1i64_indexed |
| 2216734165U, // SQDMULLv2i32_indexed |
| 2216734165U, // SQDMULLv2i32_v2i64 |
| 70299093U, // SQDMULLv4i16_indexed |
| 70299093U, // SQDMULLv4i16_v4i32 |
| 69247237U, // SQDMULLv4i32_indexed |
| 69247237U, // SQDMULLv4i32_v2i64 |
| 2217779461U, // SQDMULLv8i16_indexed |
| 2217779461U, // SQDMULLv8i16_v4i32 |
| 536921181U, // SQINCB_XPiI |
| 1342227549U, // SQINCB_XPiWdI |
| 536922061U, // SQINCD_XPiI |
| 1342228429U, // SQINCD_XPiWdI |
| 536889293U, // SQINCD_ZPiI |
| 536922645U, // SQINCH_XPiI |
| 1342229013U, // SQINCH_XPiWdI |
| 6842901U, // SQINCH_ZPiI |
| 167825349U, // SQINCP_XPWd_B |
| 201379781U, // SQINCP_XPWd_D |
| 570478533U, // SQINCP_XPWd_H |
| 268488645U, // SQINCP_XPWd_S |
| 2315308997U, // SQINCP_XP_B |
| 2348863429U, // SQINCP_XP_D |
| 2717962181U, // SQINCP_XP_H |
| 2415972293U, // SQINCP_XP_S |
| 2147504069U, // SQINCP_ZP_D |
| 604532677U, // SQINCP_ZP_H |
| 2147520453U, // SQINCP_ZP_S |
| 536925365U, // SQINCW_XPiI |
| 1342231733U, // SQINCW_XPiWdI |
| 536908981U, // SQINCW_ZPiI |
| 68200729U, // SQNEGv16i8 |
| 2248198425U, // SQNEGv1i16 |
| 2248198425U, // SQNEGv1i32 |
| 2248198425U, // SQNEGv1i64 |
| 2248198425U, // SQNEGv1i8 |
| 68725017U, // SQNEGv2i32 |
| 2216732953U, // SQNEGv2i64 |
| 69773593U, // SQNEGv4i16 |
| 2217781529U, // SQNEGv4i32 |
| 70822169U, // SQNEGv8i16 |
| 2218830105U, // SQNEGv8i8 |
| 369191329U, // SQRDMLAHi16_indexed |
| 369191329U, // SQRDMLAHi32_indexed |
| 369191329U, // SQRDMLAHv1i16 |
| 369191329U, // SQRDMLAHv1i32 |
| 2283334049U, // SQRDMLAHv2i32 |
| 2283334049U, // SQRDMLAHv2i32_indexed |
| 136898977U, // SQRDMLAHv4i16 |
| 136898977U, // SQRDMLAHv4i16_indexed |
| 137423265U, // SQRDMLAHv4i32 |
| 137423265U, // SQRDMLAHv4i32_indexed |
| 2285431201U, // SQRDMLAHv8i16 |
| 2285431201U, // SQRDMLAHv8i16_indexed |
| 369191909U, // SQRDMLSHi16_indexed |
| 369191909U, // SQRDMLSHi32_indexed |
| 369191909U, // SQRDMLSHv1i16 |
| 369191909U, // SQRDMLSHv1i32 |
| 2283334629U, // SQRDMLSHv2i32 |
| 2283334629U, // SQRDMLSHv2i32_indexed |
| 136899557U, // SQRDMLSHv4i16 |
| 136899557U, // SQRDMLSHv4i16_indexed |
| 137423845U, // SQRDMLSHv4i32 |
| 137423845U, // SQRDMLSHv4i32_indexed |
| 2285431781U, // SQRDMLSHv8i16 |
| 2285431781U, // SQRDMLSHv8i16_indexed |
| 100715238U, // SQRDMULHv1i16 |
| 100715238U, // SQRDMULHv1i16_indexed |
| 100715238U, // SQRDMULHv1i32 |
| 100715238U, // SQRDMULHv1i32_indexed |
| 2216209126U, // SQRDMULHv2i32 |
| 2216209126U, // SQRDMULHv2i32_indexed |
| 69774054U, // SQRDMULHv4i16 |
| 69774054U, // SQRDMULHv4i16_indexed |
| 70298342U, // SQRDMULHv4i32 |
| 70298342U, // SQRDMULHv4i32_indexed |
| 2218306278U, // SQRDMULHv8i16 |
| 2218306278U, // SQRDMULHv8i16_indexed |
| 68201885U, // SQRSHLv16i8 |
| 100715933U, // SQRSHLv1i16 |
| 100715933U, // SQRSHLv1i32 |
| 100715933U, // SQRSHLv1i64 |
| 100715933U, // SQRSHLv1i8 |
| 2216209821U, // SQRSHLv2i32 |
| 2216734109U, // SQRSHLv2i64 |
| 69774749U, // SQRSHLv4i16 |
| 70299037U, // SQRSHLv4i32 |
| 2218306973U, // SQRSHLv8i16 |
| 2218831261U, // SQRSHLv8i8 |
| 100716319U, // SQRSHRNb |
| 100716319U, // SQRSHRNh |
| 100716319U, // SQRSHRNs |
| 2282807661U, // SQRSHRNv16i8_shift |
| 2216210207U, // SQRSHRNv2i32_shift |
| 69775135U, // SQRSHRNv4i16_shift |
| 2284904813U, // SQRSHRNv4i32_shift |
| 137945453U, // SQRSHRNv8i16_shift |
| 2218831647U, // SQRSHRNv8i8_shift |
| 100716380U, // SQRSHRUNb |
| 100716380U, // SQRSHRUNh |
| 100716380U, // SQRSHRUNs |
| 2282807721U, // SQRSHRUNv16i8_shift |
| 2216210268U, // SQRSHRUNv2i32_shift |
| 69775196U, // SQRSHRUNv4i16_shift |
| 2284904873U, // SQRSHRUNv4i32_shift |
| 137945513U, // SQRSHRUNv8i16_shift |
| 2218831708U, // SQRSHRUNv8i8_shift |
| 100717425U, // SQSHLUb |
| 100717425U, // SQSHLUd |
| 100717425U, // SQSHLUh |
| 100717425U, // SQSHLUs |
| 68203377U, // SQSHLUv16i8_shift |
| 2216211313U, // SQSHLUv2i32_shift |
| 2216735601U, // SQSHLUv2i64_shift |
| 69776241U, // SQSHLUv4i16_shift |
| 70300529U, // SQSHLUv4i32_shift |
| 2218308465U, // SQSHLUv8i16_shift |
| 2218832753U, // SQSHLUv8i8_shift |
| 100715919U, // SQSHLb |
| 100715919U, // SQSHLd |
| 100715919U, // SQSHLh |
| 100715919U, // SQSHLs |
| 68201871U, // SQSHLv16i8 |
| 68201871U, // SQSHLv16i8_shift |
| 100715919U, // SQSHLv1i16 |
| 100715919U, // SQSHLv1i32 |
| 100715919U, // SQSHLv1i64 |
| 100715919U, // SQSHLv1i8 |
| 2216209807U, // SQSHLv2i32 |
| 2216209807U, // SQSHLv2i32_shift |
| 2216734095U, // SQSHLv2i64 |
| 2216734095U, // SQSHLv2i64_shift |
| 69774735U, // SQSHLv4i16 |
| 69774735U, // SQSHLv4i16_shift |
| 70299023U, // SQSHLv4i32 |
| 70299023U, // SQSHLv4i32_shift |
| 2218306959U, // SQSHLv8i16 |
| 2218306959U, // SQSHLv8i16_shift |
| 2218831247U, // SQSHLv8i8 |
| 2218831247U, // SQSHLv8i8_shift |
| 100716303U, // SQSHRNb |
| 100716303U, // SQSHRNh |
| 100716303U, // SQSHRNs |
| 2282807643U, // SQSHRNv16i8_shift |
| 2216210191U, // SQSHRNv2i32_shift |
| 69775119U, // SQSHRNv4i16_shift |
| 2284904795U, // SQSHRNv4i32_shift |
| 137945435U, // SQSHRNv8i16_shift |
| 2218831631U, // SQSHRNv8i8_shift |
| 100716371U, // SQSHRUNb |
| 100716371U, // SQSHRUNh |
| 100716371U, // SQSHRUNs |
| 2282807711U, // SQSHRUNv16i8_shift |
| 2216210259U, // SQSHRUNv2i32_shift |
| 69775187U, // SQSHRUNv4i16_shift |
| 2284904863U, // SQSHRUNv4i32_shift |
| 137945503U, // SQSHRUNv8i16_shift |
| 2218831699U, // SQSHRUNv8i8_shift |
| 167782084U, // SQSUB_ZI_B |
| 201344708U, // SQSUB_ZI_D |
| 239625924U, // SQSUB_ZI_H |
| 268469956U, // SQSUB_ZI_S |
| 167782084U, // SQSUB_ZZZ_B |
| 201344708U, // SQSUB_ZZZ_D |
| 2387109572U, // SQSUB_ZZZ_H |
| 268469956U, // SQSUB_ZZZ_S |
| 68200132U, // SQSUBv16i8 |
| 100714180U, // SQSUBv1i16 |
| 100714180U, // SQSUBv1i32 |
| 100714180U, // SQSUBv1i64 |
| 100714180U, // SQSUBv1i8 |
| 2216208068U, // SQSUBv2i32 |
| 2216732356U, // SQSUBv2i64 |
| 69772996U, // SQSUBv4i16 |
| 70297284U, // SQSUBv4i32 |
| 2218305220U, // SQSUBv8i16 |
| 2218829508U, // SQSUBv8i8 |
| 135324047U, // SQXTNv16i8 |
| 2248200005U, // SQXTNv1i16 |
| 2248200005U, // SQXTNv1i32 |
| 2248200005U, // SQXTNv1i8 |
| 2216210245U, // SQXTNv2i32 |
| 2217258821U, // SQXTNv4i16 |
| 2284904847U, // SQXTNv4i32 |
| 2285429135U, // SQXTNv8i16 |
| 71348037U, // SQXTNv8i8 |
| 135324084U, // SQXTUNv16i8 |
| 2248200038U, // SQXTUNv1i16 |
| 2248200038U, // SQXTUNv1i32 |
| 2248200038U, // SQXTUNv1i8 |
| 2216210278U, // SQXTUNv2i32 |
| 2217258854U, // SQXTUNv4i16 |
| 2284904884U, // SQXTUNv4i32 |
| 2285429172U, // SQXTUNv8i16 |
| 71348070U, // SQXTUNv8i8 |
| 68200433U, // SRHADDv16i8 |
| 2216208369U, // SRHADDv2i32 |
| 69773297U, // SRHADDv4i16 |
| 70297585U, // SRHADDv4i32 |
| 2218305521U, // SRHADDv8i16 |
| 2218829809U, // SRHADDv8i8 |
| 369192068U, // SRId |
| 135326852U, // SRIv16i8_shift |
| 2283334788U, // SRIv2i32_shift |
| 2283859076U, // SRIv2i64_shift |
| 136899716U, // SRIv4i16_shift |
| 137424004U, // SRIv4i32_shift |
| 2285431940U, // SRIv8i16_shift |
| 2285956228U, // SRIv8i8_shift |
| 68201901U, // SRSHLv16i8 |
| 100715949U, // SRSHLv1i64 |
| 2216209837U, // SRSHLv2i32 |
| 2216734125U, // SRSHLv2i64 |
| 69774765U, // SRSHLv4i16 |
| 70299053U, // SRSHLv4i32 |
| 2218306989U, // SRSHLv8i16 |
| 2218831277U, // SRSHLv8i8 |
| 100716794U, // SRSHRd |
| 68202746U, // SRSHRv16i8_shift |
| 2216210682U, // SRSHRv2i32_shift |
| 2216734970U, // SRSHRv2i64_shift |
| 69775610U, // SRSHRv4i16_shift |
| 70299898U, // SRSHRv4i32_shift |
| 2218307834U, // SRSHRv8i16_shift |
| 2218832122U, // SRSHRv8i8_shift |
| 369189634U, // SRSRAd |
| 135324418U, // SRSRAv16i8_shift |
| 2283332354U, // SRSRAv2i32_shift |
| 2283856642U, // SRSRAv2i64_shift |
| 136897282U, // SRSRAv4i16_shift |
| 137421570U, // SRSRAv4i32_shift |
| 2285429506U, // SRSRAv8i16_shift |
| 2285953794U, // SRSRAv8i8_shift |
| 70820085U, // SSHLLv16i8_shift |
| 2216734151U, // SSHLLv2i32_shift |
| 70299079U, // SSHLLv4i16_shift |
| 69247221U, // SSHLLv4i32_shift |
| 2217779445U, // SSHLLv8i16_shift |
| 2218307015U, // SSHLLv8i8_shift |
| 68201915U, // SSHLv16i8 |
| 100715963U, // SSHLv1i64 |
| 2216209851U, // SSHLv2i32 |
| 2216734139U, // SSHLv2i64 |
| 69774779U, // SSHLv4i16 |
| 70299067U, // SSHLv4i32 |
| 2218307003U, // SSHLv8i16 |
| 2218831291U, // SSHLv8i8 |
| 100716808U, // SSHRd |
| 68202760U, // SSHRv16i8_shift |
| 2216210696U, // SSHRv2i32_shift |
| 2216734984U, // SSHRv2i64_shift |
| 69775624U, // SSHRv4i16_shift |
| 70299912U, // SSHRv4i32_shift |
| 2218307848U, // SSHRv8i16_shift |
| 2218832136U, // SSHRv8i8_shift |
| 369189648U, // SSRAd |
| 135324432U, // SSRAv16i8_shift |
| 2283332368U, // SSRAv2i32_shift |
| 2283856656U, // SSRAv2i64_shift |
| 136897296U, // SSRAv4i16_shift |
| 137421584U, // SSRAv4i32_shift |
| 2285429520U, // SSRAv8i16_shift |
| 2285953808U, // SSRAv8i8_shift |
| 374997906U, // SST1B_D |
| 878314386U, // SST1B_D_IMM |
| 374997906U, // SST1B_D_SXTW |
| 374997906U, // SST1B_D_UXTW |
| 811213714U, // SST1B_S_IMM |
| 375006098U, // SST1B_S_SXTW |
| 375006098U, // SST1B_S_UXTW |
| 374998886U, // SST1D |
| 878315366U, // SST1D_IMM |
| 374998886U, // SST1D_SCALED |
| 374998886U, // SST1D_SXTW |
| 374998886U, // SST1D_SXTW_SCALED |
| 374998886U, // SST1D_UXTW |
| 374998886U, // SST1D_UXTW_SCALED |
| 374999380U, // SST1H_D |
| 3025799508U, // SST1H_D_IMM |
| 374999380U, // SST1H_D_SCALED |
| 374999380U, // SST1H_D_SXTW |
| 374999380U, // SST1H_D_SXTW_SCALED |
| 374999380U, // SST1H_D_UXTW |
| 374999380U, // SST1H_D_UXTW_SCALED |
| 2958698836U, // SST1H_S_IMM |
| 375007572U, // SST1H_S_SXTW |
| 375007572U, // SST1H_S_SXTW_SCALED |
| 375007572U, // SST1H_S_UXTW |
| 375007572U, // SST1H_S_UXTW_SCALED |
| 375002204U, // SST1W_D |
| 878318684U, // SST1W_D_IMM |
| 375002204U, // SST1W_D_SCALED |
| 375002204U, // SST1W_D_SXTW |
| 375002204U, // SST1W_D_SXTW_SCALED |
| 375002204U, // SST1W_D_UXTW |
| 375002204U, // SST1W_D_UXTW_SCALED |
| 811218012U, // SST1W_IMM |
| 375010396U, // SST1W_SXTW |
| 375010396U, // SST1W_SXTW_SCALED |
| 375010396U, // SST1W_UXTW |
| 375010396U, // SST1W_UXTW_SCALED |
| 70820037U, // SSUBLv16i8_v8i16 |
| 2216734014U, // SSUBLv2i32_v2i64 |
| 70298942U, // SSUBLv4i16_v4i32 |
| 69247173U, // SSUBLv4i32_v2i64 |
| 2217779397U, // SSUBLv8i16_v4i32 |
| 2218306878U, // SSUBLv8i8_v8i16 |
| 2218303966U, // SSUBWv16i8_v8i16 |
| 2216735886U, // SSUBWv2i32_v2i64 |
| 70300814U, // SSUBWv4i16_v4i32 |
| 2216731102U, // SSUBWv4i32_v2i64 |
| 70296030U, // SSUBWv8i16_v4i32 |
| 2218308750U, // SSUBWv8i8_v8i16 |
| 375022482U, // ST1B |
| 374997906U, // ST1B_D |
| 374997906U, // ST1B_D_IMM |
| 375030674U, // ST1B_H |
| 375030674U, // ST1B_H_IMM |
| 375022482U, // ST1B_IMM |
| 375006098U, // ST1B_S |
| 375006098U, // ST1B_S_IMM |
| 374998886U, // ST1D |
| 374998886U, // ST1D_IMM |
| 172102U, // ST1Fourv16b |
| 13287494U, // ST1Fourv16b_POST |
| 188486U, // ST1Fourv1d |
| 13828166U, // ST1Fourv1d_POST |
| 204870U, // ST1Fourv2d |
| 13320262U, // ST1Fourv2d_POST |
| 221254U, // ST1Fourv2s |
| 13860934U, // ST1Fourv2s_POST |
| 237638U, // ST1Fourv4h |
| 13877318U, // ST1Fourv4h_POST |
| 254022U, // ST1Fourv4s |
| 13369414U, // ST1Fourv4s_POST |
| 270406U, // ST1Fourv8b |
| 13910086U, // ST1Fourv8b_POST |
| 286790U, // ST1Fourv8h |
| 13402182U, // ST1Fourv8h_POST |
| 375032148U, // ST1H |
| 374999380U, // ST1H_D |
| 374999380U, // ST1H_D_IMM |
| 375032148U, // ST1H_IMM |
| 375007572U, // ST1H_S |
| 375007572U, // ST1H_S_IMM |
| 172102U, // ST1Onev16b |
| 14336070U, // ST1Onev16b_POST |
| 188486U, // ST1Onev1d |
| 14876742U, // ST1Onev1d_POST |
| 204870U, // ST1Onev2d |
| 14368838U, // ST1Onev2d_POST |
| 221254U, // ST1Onev2s |
| 14909510U, // ST1Onev2s_POST |
| 237638U, // ST1Onev4h |
| 14925894U, // ST1Onev4h_POST |
| 254022U, // ST1Onev4s |
| 14417990U, // ST1Onev4s_POST |
| 270406U, // ST1Onev8b |
| 14958662U, // ST1Onev8b_POST |
| 286790U, // ST1Onev8h |
| 14450758U, // ST1Onev8h_POST |
| 172102U, // ST1Threev16b |
| 16957510U, // ST1Threev16b_POST |
| 188486U, // ST1Threev1d |
| 17498182U, // ST1Threev1d_POST |
| 204870U, // ST1Threev2d |
| 16990278U, // ST1Threev2d_POST |
| 221254U, // ST1Threev2s |
| 17530950U, // ST1Threev2s_POST |
| 237638U, // ST1Threev4h |
| 17547334U, // ST1Threev4h_POST |
| 254022U, // ST1Threev4s |
| 17039430U, // ST1Threev4s_POST |
| 270406U, // ST1Threev8b |
| 17580102U, // ST1Threev8b_POST |
| 286790U, // ST1Threev8h |
| 17072198U, // ST1Threev8h_POST |
| 172102U, // ST1Twov16b |
| 13811782U, // ST1Twov16b_POST |
| 188486U, // ST1Twov1d |
| 14352454U, // ST1Twov1d_POST |
| 204870U, // ST1Twov2d |
| 13844550U, // ST1Twov2d_POST |
| 221254U, // ST1Twov2s |
| 14385222U, // ST1Twov2s_POST |
| 237638U, // ST1Twov4h |
| 14401606U, // ST1Twov4h_POST |
| 254022U, // ST1Twov4s |
| 13893702U, // ST1Twov4s_POST |
| 270406U, // ST1Twov8b |
| 14434374U, // ST1Twov8b_POST |
| 286790U, // ST1Twov8h |
| 13926470U, // ST1Twov8h_POST |
| 375010396U, // ST1W |
| 375002204U, // ST1W_D |
| 375002204U, // ST1W_D_IMM |
| 375010396U, // ST1W_IMM |
| 409670U, // ST1i16 |
| 1404346438U, // ST1i16_POST |
| 417862U, // ST1i32 |
| 1437917254U, // ST1i32_POST |
| 426054U, // ST1i64 |
| 1471488070U, // ST1i64_POST |
| 434246U, // ST1i8 |
| 1505058886U, // ST1i8_POST |
| 375022511U, // ST2B |
| 375022511U, // ST2B_IMM |
| 374998898U, // ST2D |
| 374998898U, // ST2D_IMM |
| 375032177U, // ST2H |
| 375032177U, // ST2H_IMM |
| 172505U, // ST2Twov16b |
| 13812185U, // ST2Twov16b_POST |
| 205273U, // ST2Twov2d |
| 13844953U, // ST2Twov2d_POST |
| 221657U, // ST2Twov2s |
| 14385625U, // ST2Twov2s_POST |
| 238041U, // ST2Twov4h |
| 14402009U, // ST2Twov4h_POST |
| 254425U, // ST2Twov4s |
| 13894105U, // ST2Twov4s_POST |
| 270809U, // ST2Twov8b |
| 14434777U, // ST2Twov8b_POST |
| 287193U, // ST2Twov8h |
| 13926873U, // ST2Twov8h_POST |
| 375010416U, // ST2W |
| 375010416U, // ST2W_IMM |
| 410073U, // ST2i16 |
| 1437901273U, // ST2i16_POST |
| 418265U, // ST2i32 |
| 1471472089U, // ST2i32_POST |
| 426457U, // ST2i64 |
| 1538597337U, // ST2i64_POST |
| 434649U, // ST2i8 |
| 1404395993U, // ST2i8_POST |
| 375022532U, // ST3B |
| 375022532U, // ST3B_IMM |
| 374998910U, // ST3D |
| 374998910U, // ST3D_IMM |
| 375032189U, // ST3H |
| 375032189U, // ST3H_IMM |
| 172571U, // ST3Threev16b |
| 16957979U, // ST3Threev16b_POST |
| 205339U, // ST3Threev2d |
| 16990747U, // ST3Threev2d_POST |
| 221723U, // ST3Threev2s |
| 17531419U, // ST3Threev2s_POST |
| 238107U, // ST3Threev4h |
| 17547803U, // ST3Threev4h_POST |
| 254491U, // ST3Threev4s |
| 17039899U, // ST3Threev4s_POST |
| 270875U, // ST3Threev8b |
| 17580571U, // ST3Threev8b_POST |
| 287259U, // ST3Threev8h |
| 17072667U, // ST3Threev8h_POST |
| 375010428U, // ST3W |
| 375010428U, // ST3W_IMM |
| 410139U, // ST3i16 |
| 1572119067U, // ST3i16_POST |
| 418331U, // ST3i32 |
| 1605689883U, // ST3i32_POST |
| 426523U, // ST3i64 |
| 1639260699U, // ST3i64_POST |
| 434715U, // ST3i8 |
| 1672831515U, // ST3i8_POST |
| 375022544U, // ST4B |
| 375022544U, // ST4B_IMM |
| 374998922U, // ST4D |
| 374998922U, // ST4D_IMM |
| 172588U, // ST4Fourv16b |
| 13287980U, // ST4Fourv16b_POST |
| 205356U, // ST4Fourv2d |
| 13320748U, // ST4Fourv2d_POST |
| 221740U, // ST4Fourv2s |
| 13861420U, // ST4Fourv2s_POST |
| 238124U, // ST4Fourv4h |
| 13877804U, // ST4Fourv4h_POST |
| 254508U, // ST4Fourv4s |
| 13369900U, // ST4Fourv4s_POST |
| 270892U, // ST4Fourv8b |
| 13910572U, // ST4Fourv8b_POST |
| 287276U, // ST4Fourv8h |
| 13402668U, // ST4Fourv8h_POST |
| 375032201U, // ST4H |
| 375032201U, // ST4H_IMM |
| 375010440U, // ST4W |
| 375010440U, // ST4W_IMM |
| 410156U, // ST4i16 |
| 1471455788U, // ST4i16_POST |
| 418348U, // ST4i32 |
| 1538581036U, // ST4i32_POST |
| 426540U, // ST4i64 |
| 1706369580U, // ST4i64_POST |
| 434732U, // ST4i8 |
| 1437950508U, // ST4i8_POST |
| 2253964715U, // STLLRB |
| 2253966166U, // STLLRH |
| 2253967648U, // STLLRW |
| 2253967648U, // STLLRX |
| 2253964723U, // STLRB |
| 2253966174U, // STLRH |
| 2253967661U, // STLRW |
| 2253967661U, // STLRX |
| 106481125U, // STLURBi |
| 106482576U, // STLURHi |
| 106484110U, // STLURWi |
| 106484110U, // STLURXi |
| 100716685U, // STLXPW |
| 100716685U, // STLXPX |
| 2248197644U, // STLXRB |
| 2248199095U, // STLXRH |
| 2248200645U, // STLXRW |
| 2248200645U, // STLXRX |
| 2248200251U, // STNPDi |
| 2248200251U, // STNPQi |
| 2248200251U, // STNPSi |
| 2248200251U, // STNPWi |
| 2248200251U, // STNPXi |
| 375022474U, // STNT1B_ZRI |
| 375022474U, // STNT1B_ZRR |
| 374998878U, // STNT1D_ZRI |
| 374998878U, // STNT1D_ZRR |
| 375032140U, // STNT1H_ZRI |
| 375032140U, // STNT1H_ZRR |
| 375010388U, // STNT1W_ZRI |
| 375010388U, // STNT1W_ZRR |
| 2248200283U, // STPDi |
| 2516676699U, // STPDpost |
| 2516676699U, // STPDpre |
| 2248200283U, // STPQi |
| 2516676699U, // STPQpost |
| 2516676699U, // STPQpre |
| 2248200283U, // STPSi |
| 2516676699U, // STPSpost |
| 2516676699U, // STPSpre |
| 2248200283U, // STPWi |
| 2516676699U, // STPWpost |
| 2516676699U, // STPWpre |
| 2248200283U, // STPXi |
| 2516676699U, // STPXpost |
| 2516676699U, // STPXpre |
| 374957521U, // STRBBpost |
| 374957521U, // STRBBpre |
| 106481105U, // STRBBroW |
| 106481105U, // STRBBroX |
| 106481105U, // STRBBui |
| 374960503U, // STRBpost |
| 374960503U, // STRBpre |
| 106484087U, // STRBroW |
| 106484087U, // STRBroX |
| 106484087U, // STRBui |
| 374960503U, // STRDpost |
| 374960503U, // STRDpre |
| 106484087U, // STRDroW |
| 106484087U, // STRDroX |
| 106484087U, // STRDui |
| 374958972U, // STRHHpost |
| 374958972U, // STRHHpre |
| 106482556U, // STRHHroW |
| 106482556U, // STRHHroX |
| 106482556U, // STRHHui |
| 374960503U, // STRHpost |
| 374960503U, // STRHpre |
| 106484087U, // STRHroW |
| 106484087U, // STRHroX |
| 106484087U, // STRHui |
| 374960503U, // STRQpost |
| 374960503U, // STRQpre |
| 106484087U, // STRQroW |
| 106484087U, // STRQroX |
| 106484087U, // STRQui |
| 374960503U, // STRSpost |
| 374960503U, // STRSpre |
| 106484087U, // STRSroW |
| 106484087U, // STRSroX |
| 106484087U, // STRSui |
| 374960503U, // STRWpost |
| 374960503U, // STRWpre |
| 106484087U, // STRWroW |
| 106484087U, // STRWroX |
| 106484087U, // STRWui |
| 374960503U, // STRXpost |
| 374960503U, // STRXpre |
| 106484087U, // STRXroW |
| 106484087U, // STRXroX |
| 106484087U, // STRXui |
| 106803575U, // STR_PXI |
| 106803575U, // STR_ZXI |
| 106481111U, // STTRBi |
| 106482562U, // STTRHi |
| 106484092U, // STTRWi |
| 106484092U, // STTRXi |
| 106481142U, // STURBBi |
| 106484125U, // STURBi |
| 106484125U, // STURDi |
| 106482593U, // STURHHi |
| 106484125U, // STURHi |
| 106484125U, // STURQi |
| 106484125U, // STURSi |
| 106484125U, // STURWi |
| 106484125U, // STURXi |
| 100716692U, // STXPW |
| 100716692U, // STXPX |
| 2248197652U, // STXRB |
| 2248199103U, // STXRH |
| 2248200652U, // STXRW |
| 2248200652U, // STXRX |
| 2216210137U, // SUBHNv2i64_v2i32 |
| 2284904778U, // SUBHNv2i64_v4i32 |
| 69775065U, // SUBHNv4i32_v4i16 |
| 137945418U, // SUBHNv4i32_v8i16 |
| 2282807626U, // SUBHNv8i16_v16i8 |
| 2218831577U, // SUBHNv8i16_v8i8 |
| 167784668U, // SUBR_ZI_B |
| 201347292U, // SUBR_ZI_D |
| 239628508U, // SUBR_ZI_H |
| 268472540U, // SUBR_ZI_S |
| 302002396U, // SUBR_ZPmZ_B |
| 302010588U, // SUBR_ZPmZ_D |
| 2186309852U, // SUBR_ZPmZ_H |
| 302026972U, // SUBR_ZPmZ_S |
| 100717066U, // SUBSWri |
| 0U, // SUBSWrr |
| 100717066U, // SUBSWrs |
| 100717066U, // SUBSWrx |
| 100717066U, // SUBSXri |
| 0U, // SUBSXrr |
| 100717066U, // SUBSXrs |
| 100717066U, // SUBSXrx |
| 100717066U, // SUBSXrx64 |
| 100714146U, // SUBWri |
| 0U, // SUBWrr |
| 100714146U, // SUBWrs |
| 100714146U, // SUBWrx |
| 100714146U, // SUBXri |
| 0U, // SUBXrr |
| 100714146U, // SUBXrs |
| 100714146U, // SUBXrx |
| 100714146U, // SUBXrx64 |
| 167782050U, // SUB_ZI_B |
| 201344674U, // SUB_ZI_D |
| 239625890U, // SUB_ZI_H |
| 268469922U, // SUB_ZI_S |
| 301999778U, // SUB_ZPmZ_B |
| 302007970U, // SUB_ZPmZ_D |
| 2186307234U, // SUB_ZPmZ_H |
| 302024354U, // SUB_ZPmZ_S |
| 167782050U, // SUB_ZZZ_B |
| 201344674U, // SUB_ZZZ_D |
| 2387109538U, // SUB_ZZZ_H |
| 268469922U, // SUB_ZZZ_S |
| 68200098U, // SUBv16i8 |
| 100714146U, // SUBv1i64 |
| 2216208034U, // SUBv2i32 |
| 2216732322U, // SUBv2i64 |
| 69772962U, // SUBv4i16 |
| 70297250U, // SUBv4i32 |
| 2218305186U, // SUBv8i16 |
| 2218829474U, // SUBv8i8 |
| 2415938650U, // SUNPKHI_ZZ_D |
| 27290714U, // SUNPKHI_ZZ_H |
| 2717944922U, // SUNPKHI_ZZ_S |
| 2415939470U, // SUNPKLO_ZZ_D |
| 27291534U, // SUNPKLO_ZZ_H |
| 2717945742U, // SUNPKLO_ZZ_S |
| 135325734U, // SUQADDv16i8 |
| 2516674598U, // SUQADDv1i16 |
| 2516674598U, // SUQADDv1i32 |
| 2516674598U, // SUQADDv1i64 |
| 2516674598U, // SUQADDv1i8 |
| 135850022U, // SUQADDv2i32 |
| 2283857958U, // SUQADDv2i64 |
| 136898598U, // SUQADDv4i16 |
| 2284906534U, // SUQADDv4i32 |
| 137947174U, // SUQADDv8i16 |
| 2285955110U, // SUQADDv8i8 |
| 75579U, // SVC |
| 973169651U, // SWPAB |
| 973171135U, // SWPAH |
| 973169853U, // SWPALB |
| 973171283U, // SWPALH |
| 973171948U, // SWPALW |
| 973171948U, // SWPALX |
| 973169381U, // SWPAW |
| 973169381U, // SWPAX |
| 973170041U, // SWPB |
| 973171492U, // SWPH |
| 973169950U, // SWPLB |
| 973171380U, // SWPLH |
| 973172243U, // SWPLW |
| 973172243U, // SWPLX |
| 973172838U, // SWPW |
| 973172838U, // SWPX |
| 18069U, // SXTB_ZPmZ_D |
| 2181588629U, // SXTB_ZPmZ_H |
| 34453U, // SXTB_ZPmZ_S |
| 19494U, // SXTH_ZPmZ_D |
| 35878U, // SXTH_ZPmZ_S |
| 21815U, // SXTW_ZPmZ_D |
| 100716107U, // SYSLxt |
| 1711329984U, // SYSxt |
| 1744842025U, // TBL_ZZZ_B |
| 1778404649U, // TBL_ZZZ_D |
| 28863785U, // TBL_ZZZ_H |
| 1811975465U, // TBL_ZZZ_S |
| 1846586665U, // TBLv16i8Four |
| 1846586665U, // TBLv16i8One |
| 1846586665U, // TBLv16i8Three |
| 1846586665U, // TBLv16i8Two |
| 3997216041U, // TBLv8i8Four |
| 3997216041U, // TBLv8i8One |
| 3997216041U, // TBLv8i8Three |
| 3997216041U, // TBLv8i8Two |
| 100718059U, // TBNZW |
| 100718059U, // TBNZX |
| 1880159597U, // TBXv16i8Four |
| 1880159597U, // TBXv16i8One |
| 1880159597U, // TBXv16i8Three |
| 1880159597U, // TBXv16i8Two |
| 4030788973U, // TBXv8i8Four |
| 4030788973U, // TBXv8i8One |
| 4030788973U, // TBXv8i8Three |
| 4030788973U, // TBXv8i8Two |
| 100718043U, // TBZW |
| 100718043U, // TBZX |
| 0U, // TCRETURNdi |
| 0U, // TCRETURNri |
| 6346239U, // TLSDESCCALL |
| 0U, // TLSDESC_CALLSEQ |
| 167780389U, // TRN1_PPP_B |
| 201343013U, // TRN1_PPP_D |
| 2387107877U, // TRN1_PPP_H |
| 268468261U, // TRN1_PPP_S |
| 167780389U, // TRN1_ZZZ_B |
| 201343013U, // TRN1_ZZZ_D |
| 2387107877U, // TRN1_ZZZ_H |
| 268468261U, // TRN1_ZZZ_S |
| 68198437U, // TRN1v16i8 |
| 2216206373U, // TRN1v2i32 |
| 2216730661U, // TRN1v2i64 |
| 69771301U, // TRN1v4i16 |
| 70295589U, // TRN1v4i32 |
| 2218303525U, // TRN1v8i16 |
| 2218827813U, // TRN1v8i8 |
| 167780737U, // TRN2_PPP_B |
| 201343361U, // TRN2_PPP_D |
| 2387108225U, // TRN2_PPP_H |
| 268468609U, // TRN2_PPP_S |
| 167780737U, // TRN2_ZZZ_B |
| 201343361U, // TRN2_ZZZ_D |
| 2387108225U, // TRN2_ZZZ_H |
| 268468609U, // TRN2_ZZZ_S |
| 68198785U, // TRN2v16i8 |
| 2216206721U, // TRN2v2i32 |
| 2216731009U, // TRN2v2i64 |
| 69771649U, // TRN2v4i16 |
| 70295937U, // TRN2v4i32 |
| 2218303873U, // TRN2v8i16 |
| 2218828161U, // TRN2v8i8 |
| 116346U, // TSB |
| 137945251U, // UABALv16i8_v8i16 |
| 2283859113U, // UABALv2i32_v2i64 |
| 137424041U, // UABALv4i16_v4i32 |
| 136372387U, // UABALv4i32_v2i64 |
| 2284904611U, // UABALv8i16_v4i32 |
| 2285431977U, // UABALv8i8_v8i16 |
| 135324275U, // UABAv16i8 |
| 2283332211U, // UABAv2i32 |
| 136897139U, // UABAv4i16 |
| 137421427U, // UABAv4i32 |
| 2285429363U, // UABAv8i16 |
| 2285953651U, // UABAv8i8 |
| 70820061U, // UABDLv16i8_v8i16 |
| 2216734035U, // UABDLv2i32_v2i64 |
| 70298963U, // UABDLv4i16_v4i32 |
| 69247197U, // UABDLv4i32_v2i64 |
| 2217779421U, // UABDLv8i16_v4i32 |
| 2218306899U, // UABDLv8i8_v8i16 |
| 302000048U, // UABD_ZPmZ_B |
| 302008240U, // UABD_ZPmZ_D |
| 2186307504U, // UABD_ZPmZ_H |
| 302024624U, // UABD_ZPmZ_S |
| 68200368U, // UABDv16i8 |
| 2216208304U, // UABDv2i32 |
| 69773232U, // UABDv4i16 |
| 70297520U, // UABDv4i32 |
| 2218305456U, // UABDv8i16 |
| 2218829744U, // UABDv8i8 |
| 137949161U, // UADALPv16i8_v8i16 |
| 162066409U, // UADALPv2i32_v1i64 |
| 135852009U, // UADALPv4i16_v2i32 |
| 2283859945U, // UADALPv4i32_v2i64 |
| 137424873U, // UADALPv8i16_v4i32 |
| 2284384233U, // UADALPv8i8_v4i16 |
| 70823929U, // UADDLPv16i8_v8i16 |
| 94941177U, // UADDLPv2i32_v1i64 |
| 68726777U, // UADDLPv4i16_v2i32 |
| 2216734713U, // UADDLPv4i32_v2i64 |
| 70299641U, // UADDLPv8i16_v4i32 |
| 2217259001U, // UADDLPv8i8_v4i16 |
| 67163091U, // UADDLVv16i8v |
| 67163091U, // UADDLVv4i16v |
| 2214646739U, // UADDLVv4i32v |
| 67163091U, // UADDLVv8i16v |
| 2214646739U, // UADDLVv8i8v |
| 70820077U, // UADDLv16i8_v8i16 |
| 2216734073U, // UADDLv2i32_v2i64 |
| 70299001U, // UADDLv4i16_v4i32 |
| 69247213U, // UADDLv4i32_v2i64 |
| 2217779437U, // UADDLv8i16_v4i32 |
| 2218306937U, // UADDLv8i8_v8i16 |
| 302044071U, // UADDV_VPZ_B |
| 302044071U, // UADDV_VPZ_D |
| 302044071U, // UADDV_VPZ_H |
| 302044071U, // UADDV_VPZ_S |
| 2218303990U, // UADDWv16i8_v8i16 |
| 2216735948U, // UADDWv2i32_v2i64 |
| 70300876U, // UADDWv4i16_v4i32 |
| 2216731126U, // UADDWv4i32_v2i64 |
| 70296054U, // UADDWv8i16_v4i32 |
| 2218308812U, // UADDWv8i8_v8i16 |
| 100716199U, // UBFMWri |
| 100716199U, // UBFMXri |
| 100714764U, // UCVTFSWDri |
| 100714764U, // UCVTFSWHri |
| 100714764U, // UCVTFSWSri |
| 100714764U, // UCVTFSXDri |
| 100714764U, // UCVTFSXHri |
| 100714764U, // UCVTFSXSri |
| 2248198412U, // UCVTFUWDri |
| 2248198412U, // UCVTFUWHri |
| 2248198412U, // UCVTFUWSri |
| 2248198412U, // UCVTFUXDri |
| 2248198412U, // UCVTFUXHri |
| 2248198412U, // UCVTFUXSri |
| 18700U, // UCVTF_ZPmZ_DtoD |
| 2181589260U, // UCVTF_ZPmZ_DtoH |
| 35084U, // UCVTF_ZPmZ_DtoS |
| 2181589260U, // UCVTF_ZPmZ_HtoH |
| 18700U, // UCVTF_ZPmZ_StoD |
| 2181589260U, // UCVTF_ZPmZ_StoH |
| 35084U, // UCVTF_ZPmZ_StoS |
| 100714764U, // UCVTFd |
| 100714764U, // UCVTFh |
| 100714764U, // UCVTFs |
| 2248198412U, // UCVTFv1i16 |
| 2248198412U, // UCVTFv1i32 |
| 2248198412U, // UCVTFv1i64 |
| 68725004U, // UCVTFv2f32 |
| 2216732940U, // UCVTFv2f64 |
| 2216208652U, // UCVTFv2i32_shift |
| 2216732940U, // UCVTFv2i64_shift |
| 69773580U, // UCVTFv4f16 |
| 2217781516U, // UCVTFv4f32 |
| 69773580U, // UCVTFv4i16_shift |
| 70297868U, // UCVTFv4i32_shift |
| 70822156U, // UCVTFv8f16 |
| 2218305804U, // UCVTFv8i16_shift |
| 302010801U, // UDIVR_ZPmZ_D |
| 302027185U, // UDIVR_ZPmZ_S |
| 100717509U, // UDIVWr |
| 100717509U, // UDIVXr |
| 302011333U, // UDIV_ZPmZ_D |
| 302027717U, // UDIV_ZPmZ_S |
| 3422573363U, // UDOT_ZZZI_D |
| 3456144179U, // UDOT_ZZZI_S |
| 3422573363U, // UDOT_ZZZ_D |
| 3456144179U, // UDOT_ZZZ_S |
| 137425715U, // UDOTlanev16i8 |
| 2283336499U, // UDOTlanev8i8 |
| 137425715U, // UDOTv16i8 |
| 2283336499U, // UDOTv8i8 |
| 68200456U, // UHADDv16i8 |
| 2216208392U, // UHADDv2i32 |
| 69773320U, // UHADDv4i16 |
| 70297608U, // UHADDv4i32 |
| 2218305544U, // UHADDv8i16 |
| 2218829832U, // UHADDv8i8 |
| 68200110U, // UHSUBv16i8 |
| 2216208046U, // UHSUBv2i32 |
| 69772974U, // UHSUBv4i16 |
| 70297262U, // UHSUBv4i32 |
| 2218305198U, // UHSUBv8i16 |
| 2218829486U, // UHSUBv8i8 |
| 100715882U, // UMADDLrrr |
| 68202624U, // UMAXPv16i8 |
| 2216210560U, // UMAXPv2i32 |
| 69775488U, // UMAXPv4i16 |
| 70299776U, // UMAXPv4i32 |
| 2218307712U, // UMAXPv8i16 |
| 2218832000U, // UMAXPv8i8 |
| 302044207U, // UMAXV_VPZ_B |
| 302044207U, // UMAXV_VPZ_D |
| 302044207U, // UMAXV_VPZ_H |
| 302044207U, // UMAXV_VPZ_S |
| 67163183U, // UMAXVv16i8v |
| 67163183U, // UMAXVv4i16v |
| 2214646831U, // UMAXVv4i32v |
| 67163183U, // UMAXVv8i16v |
| 2214646831U, // UMAXVv8i8v |
| 167785831U, // UMAX_ZI_B |
| 201348455U, // UMAX_ZI_D |
| 239629671U, // UMAX_ZI_H |
| 268473703U, // UMAX_ZI_S |
| 302003559U, // UMAX_ZPmZ_B |
| 302011751U, // UMAX_ZPmZ_D |
| 2186311015U, // UMAX_ZPmZ_H |
| 302028135U, // UMAX_ZPmZ_S |
| 68203879U, // UMAXv16i8 |
| 2216211815U, // UMAXv2i32 |
| 69776743U, // UMAXv4i16 |
| 70301031U, // UMAXv4i32 |
| 2218308967U, // UMAXv8i16 |
| 2218833255U, // UMAXv8i8 |
| 68202548U, // UMINPv16i8 |
| 2216210484U, // UMINPv2i32 |
| 69775412U, // UMINPv4i16 |
| 70299700U, // UMINPv4i32 |
| 2218307636U, // UMINPv8i16 |
| 2218831924U, // UMINPv8i8 |
| 302044155U, // UMINV_VPZ_B |
| 302044155U, // UMINV_VPZ_D |
| 302044155U, // UMINV_VPZ_H |
| 302044155U, // UMINV_VPZ_S |
| 67163131U, // UMINVv16i8v |
| 67163131U, // UMINVv4i16v |
| 2214646779U, // UMINVv4i32v |
| 67163131U, // UMINVv8i16v |
| 2214646779U, // UMINVv8i8v |
| 167784184U, // UMIN_ZI_B |
| 201346808U, // UMIN_ZI_D |
| 239628024U, // UMIN_ZI_H |
| 268472056U, // UMIN_ZI_S |
| 302001912U, // UMIN_ZPmZ_B |
| 302010104U, // UMIN_ZPmZ_D |
| 2186309368U, // UMIN_ZPmZ_H |
| 302026488U, // UMIN_ZPmZ_S |
| 68202232U, // UMINv16i8 |
| 2216210168U, // UMINv2i32 |
| 69775096U, // UMINv4i16 |
| 70299384U, // UMINv4i32 |
| 2218307320U, // UMINv8i16 |
| 2218831608U, // UMINv8i8 |
| 137945277U, // UMLALv16i8_v8i16 |
| 2283859145U, // UMLALv2i32_indexed |
| 2283859145U, // UMLALv2i32_v2i64 |
| 137424073U, // UMLALv4i16_indexed |
| 137424073U, // UMLALv4i16_v4i32 |
| 136372413U, // UMLALv4i32_indexed |
| 136372413U, // UMLALv4i32_v2i64 |
| 2284904637U, // UMLALv8i16_indexed |
| 2284904637U, // UMLALv8i16_v4i32 |
| 2285432009U, // UMLALv8i8_v8i16 |
| 137945401U, // UMLSLv16i8_v8i16 |
| 2283859524U, // UMLSLv2i32_indexed |
| 2283859524U, // UMLSLv2i32_v2i64 |
| 137424452U, // UMLSLv4i16_indexed |
| 137424452U, // UMLSLv4i16_v4i32 |
| 136372537U, // UMLSLv4i32_indexed |
| 136372537U, // UMLSLv4i32_v2i64 |
| 2284904761U, // UMLSLv8i16_indexed |
| 2284904761U, // UMLSLv8i16_v4i32 |
| 2285432388U, // UMLSLv8i8_v8i16 |
| 67163157U, // UMOVvi16 |
| 2214646805U, // UMOVvi32 |
| 67163157U, // UMOVvi64 |
| 2214646805U, // UMOVvi8 |
| 100715830U, // UMSUBLrrr |
| 302000887U, // UMULH_ZPmZ_B |
| 302009079U, // UMULH_ZPmZ_D |
| 2186308343U, // UMULH_ZPmZ_H |
| 302025463U, // UMULH_ZPmZ_S |
| 100715255U, // UMULHrr |
| 70820127U, // UMULLv16i8_v8i16 |
| 2216734188U, // UMULLv2i32_indexed |
| 2216734188U, // UMULLv2i32_v2i64 |
| 70299116U, // UMULLv4i16_indexed |
| 70299116U, // UMULLv4i16_v4i32 |
| 69247263U, // UMULLv4i32_indexed |
| 69247263U, // UMULLv4i32_v2i64 |
| 2217779487U, // UMULLv8i16_indexed |
| 2217779487U, // UMULLv8i16_v4i32 |
| 2218307052U, // UMULLv8i8_v8i16 |
| 167782439U, // UQADD_ZI_B |
| 201345063U, // UQADD_ZI_D |
| 239626279U, // UQADD_ZI_H |
| 268470311U, // UQADD_ZI_S |
| 167782439U, // UQADD_ZZZ_B |
| 201345063U, // UQADD_ZZZ_D |
| 2387109927U, // UQADD_ZZZ_H |
| 268470311U, // UQADD_ZZZ_S |
| 68200487U, // UQADDv16i8 |
| 100714535U, // UQADDv1i16 |
| 100714535U, // UQADDv1i32 |
| 100714535U, // UQADDv1i64 |
| 100714535U, // UQADDv1i8 |
| 2216208423U, // UQADDv2i32 |
| 2216732711U, // UQADDv2i64 |
| 69773351U, // UQADDv4i16 |
| 70297639U, // UQADDv4i32 |
| 2218305575U, // UQADDv8i16 |
| 2218829863U, // UQADDv8i8 |
| 536921173U, // UQDECB_WPiI |
| 536921173U, // UQDECB_XPiI |
| 536922053U, // UQDECD_WPiI |
| 536922053U, // UQDECD_XPiI |
| 536889285U, // UQDECD_ZPiI |
| 536922637U, // UQDECH_WPiI |
| 536922637U, // UQDECH_XPiI |
| 6842893U, // UQDECH_ZPiI |
| 2315308989U, // UQDECP_WP_B |
| 2348863421U, // UQDECP_WP_D |
| 2717962173U, // UQDECP_WP_H |
| 2415972285U, // UQDECP_WP_S |
| 2315308989U, // UQDECP_XP_B |
| 2348863421U, // UQDECP_XP_D |
| 2717962173U, // UQDECP_XP_H |
| 2415972285U, // UQDECP_XP_S |
| 2147504061U, // UQDECP_ZP_D |
| 604532669U, // UQDECP_ZP_H |
| 2147520445U, // UQDECP_ZP_S |
| 536925357U, // UQDECW_WPiI |
| 536925357U, // UQDECW_XPiI |
| 536908973U, // UQDECW_ZPiI |
| 536921189U, // UQINCB_WPiI |
| 536921189U, // UQINCB_XPiI |
| 536922069U, // UQINCD_WPiI |
| 536922069U, // UQINCD_XPiI |
| 536889301U, // UQINCD_ZPiI |
| 536922653U, // UQINCH_WPiI |
| 536922653U, // UQINCH_XPiI |
| 6842909U, // UQINCH_ZPiI |
| 2315309005U, // UQINCP_WP_B |
| 2348863437U, // UQINCP_WP_D |
| 2717962189U, // UQINCP_WP_H |
| 2415972301U, // UQINCP_WP_S |
| 2315309005U, // UQINCP_XP_B |
| 2348863437U, // UQINCP_XP_D |
| 2717962189U, // UQINCP_XP_H |
| 2415972301U, // UQINCP_XP_S |
| 2147504077U, // UQINCP_ZP_D |
| 604532685U, // UQINCP_ZP_H |
| 2147520461U, // UQINCP_ZP_S |
| 536925373U, // UQINCW_WPiI |
| 536925373U, // UQINCW_XPiI |
| 536908989U, // UQINCW_ZPiI |
| 68201893U, // UQRSHLv16i8 |
| 100715941U, // UQRSHLv1i16 |
| 100715941U, // UQRSHLv1i32 |
| 100715941U, // UQRSHLv1i64 |
| 100715941U, // UQRSHLv1i8 |
| 2216209829U, // UQRSHLv2i32 |
| 2216734117U, // UQRSHLv2i64 |
| 69774757U, // UQRSHLv4i16 |
| 70299045U, // UQRSHLv4i32 |
| 2218306981U, // UQRSHLv8i16 |
| 2218831269U, // UQRSHLv8i8 |
| 100716328U, // UQRSHRNb |
| 100716328U, // UQRSHRNh |
| 100716328U, // UQRSHRNs |
| 2282807671U, // UQRSHRNv16i8_shift |
| 2216210216U, // UQRSHRNv2i32_shift |
| 69775144U, // UQRSHRNv4i16_shift |
| 2284904823U, // UQRSHRNv4i32_shift |
| 137945463U, // UQRSHRNv8i16_shift |
| 2218831656U, // UQRSHRNv8i8_shift |
| 100715926U, // UQSHLb |
| 100715926U, // UQSHLd |
| 100715926U, // UQSHLh |
| 100715926U, // UQSHLs |
| 68201878U, // UQSHLv16i8 |
| 68201878U, // UQSHLv16i8_shift |
| 100715926U, // UQSHLv1i16 |
| 100715926U, // UQSHLv1i32 |
| 100715926U, // UQSHLv1i64 |
| 100715926U, // UQSHLv1i8 |
| 2216209814U, // UQSHLv2i32 |
| 2216209814U, // UQSHLv2i32_shift |
| 2216734102U, // UQSHLv2i64 |
| 2216734102U, // UQSHLv2i64_shift |
| 69774742U, // UQSHLv4i16 |
| 69774742U, // UQSHLv4i16_shift |
| 70299030U, // UQSHLv4i32 |
| 70299030U, // UQSHLv4i32_shift |
| 2218306966U, // UQSHLv8i16 |
| 2218306966U, // UQSHLv8i16_shift |
| 2218831254U, // UQSHLv8i8 |
| 2218831254U, // UQSHLv8i8_shift |
| 100716311U, // UQSHRNb |
| 100716311U, // UQSHRNh |
| 100716311U, // UQSHRNs |
| 2282807652U, // UQSHRNv16i8_shift |
| 2216210199U, // UQSHRNv2i32_shift |
| 69775127U, // UQSHRNv4i16_shift |
| 2284904804U, // UQSHRNv4i32_shift |
| 137945444U, // UQSHRNv8i16_shift |
| 2218831639U, // UQSHRNv8i8_shift |
| 167782091U, // UQSUB_ZI_B |
| 201344715U, // UQSUB_ZI_D |
| 239625931U, // UQSUB_ZI_H |
| 268469963U, // UQSUB_ZI_S |
| 167782091U, // UQSUB_ZZZ_B |
| 201344715U, // UQSUB_ZZZ_D |
| 2387109579U, // UQSUB_ZZZ_H |
| 268469963U, // UQSUB_ZZZ_S |
| 68200139U, // UQSUBv16i8 |
| 100714187U, // UQSUBv1i16 |
| 100714187U, // UQSUBv1i32 |
| 100714187U, // UQSUBv1i64 |
| 100714187U, // UQSUBv1i8 |
| 2216208075U, // UQSUBv2i32 |
| 2216732363U, // UQSUBv2i64 |
| 69773003U, // UQSUBv4i16 |
| 70297291U, // UQSUBv4i32 |
| 2218305227U, // UQSUBv8i16 |
| 2218829515U, // UQSUBv8i8 |
| 135324055U, // UQXTNv16i8 |
| 2248200012U, // UQXTNv1i16 |
| 2248200012U, // UQXTNv1i32 |
| 2248200012U, // UQXTNv1i8 |
| 2216210252U, // UQXTNv2i32 |
| 2217258828U, // UQXTNv4i16 |
| 2284904855U, // UQXTNv4i32 |
| 2285429143U, // UQXTNv8i16 |
| 71348044U, // UQXTNv8i8 |
| 68724924U, // URECPEv2i32 |
| 2217781436U, // URECPEv4i32 |
| 68200441U, // URHADDv16i8 |
| 2216208377U, // URHADDv2i32 |
| 69773305U, // URHADDv4i16 |
| 70297593U, // URHADDv4i32 |
| 2218305529U, // URHADDv8i16 |
| 2218829817U, // URHADDv8i8 |
| 68201908U, // URSHLv16i8 |
| 100715956U, // URSHLv1i64 |
| 2216209844U, // URSHLv2i32 |
| 2216734132U, // URSHLv2i64 |
| 69774772U, // URSHLv4i16 |
| 70299060U, // URSHLv4i32 |
| 2218306996U, // URSHLv8i16 |
| 2218831284U, // URSHLv8i8 |
| 100716801U, // URSHRd |
| 68202753U, // URSHRv16i8_shift |
| 2216210689U, // URSHRv2i32_shift |
| 2216734977U, // URSHRv2i64_shift |
| 69775617U, // URSHRv4i16_shift |
| 70299905U, // URSHRv4i32_shift |
| 2218307841U, // URSHRv8i16_shift |
| 2218832129U, // URSHRv8i8_shift |
| 68724970U, // URSQRTEv2i32 |
| 2217781482U, // URSQRTEv4i32 |
| 369189641U, // URSRAd |
| 135324425U, // URSRAv16i8_shift |
| 2283332361U, // URSRAv2i32_shift |
| 2283856649U, // URSRAv2i64_shift |
| 136897289U, // URSRAv4i16_shift |
| 137421577U, // URSRAv4i32_shift |
| 2285429513U, // URSRAv8i16_shift |
| 2285953801U, // URSRAv8i8_shift |
| 70820093U, // USHLLv16i8_shift |
| 2216734158U, // USHLLv2i32_shift |
| 70299086U, // USHLLv4i16_shift |
| 69247229U, // USHLLv4i32_shift |
| 2217779453U, // USHLLv8i16_shift |
| 2218307022U, // USHLLv8i8_shift |
| 68201921U, // USHLv16i8 |
| 100715969U, // USHLv1i64 |
| 2216209857U, // USHLv2i32 |
| 2216734145U, // USHLv2i64 |
| 69774785U, // USHLv4i16 |
| 70299073U, // USHLv4i32 |
| 2218307009U, // USHLv8i16 |
| 2218831297U, // USHLv8i8 |
| 100716814U, // USHRd |
| 68202766U, // USHRv16i8_shift |
| 2216210702U, // USHRv2i32_shift |
| 2216734990U, // USHRv2i64_shift |
| 69775630U, // USHRv4i16_shift |
| 70299918U, // USHRv4i32_shift |
| 2218307854U, // USHRv8i16_shift |
| 2218832142U, // USHRv8i8_shift |
| 135325726U, // USQADDv16i8 |
| 2516674590U, // USQADDv1i16 |
| 2516674590U, // USQADDv1i32 |
| 2516674590U, // USQADDv1i64 |
| 2516674590U, // USQADDv1i8 |
| 135850014U, // USQADDv2i32 |
| 2283857950U, // USQADDv2i64 |
| 136898590U, // USQADDv4i16 |
| 2284906526U, // USQADDv4i32 |
| 137947166U, // USQADDv8i16 |
| 2285955102U, // USQADDv8i8 |
| 369189654U, // USRAd |
| 135324438U, // USRAv16i8_shift |
| 2283332374U, // USRAv2i32_shift |
| 2283856662U, // USRAv2i64_shift |
| 136897302U, // USRAv4i16_shift |
| 137421590U, // USRAv4i32_shift |
| 2285429526U, // USRAv8i16_shift |
| 2285953814U, // USRAv8i8_shift |
| 70820045U, // USUBLv16i8_v8i16 |
| 2216734021U, // USUBLv2i32_v2i64 |
| 70298949U, // USUBLv4i16_v4i32 |
| 69247181U, // USUBLv4i32_v2i64 |
| 2217779405U, // USUBLv8i16_v4i32 |
| 2218306885U, // USUBLv8i8_v8i16 |
| 2218303974U, // USUBWv16i8_v8i16 |
| 2216735893U, // USUBWv2i32_v2i64 |
| 70300821U, // USUBWv4i16_v4i32 |
| 2216731110U, // USUBWv4i32_v2i64 |
| 70296038U, // USUBWv8i16_v4i32 |
| 2218308757U, // USUBWv8i8_v8i16 |
| 2415938659U, // UUNPKHI_ZZ_D |
| 27290723U, // UUNPKHI_ZZ_H |
| 2717944931U, // UUNPKHI_ZZ_S |
| 2415939479U, // UUNPKLO_ZZ_D |
| 27291543U, // UUNPKLO_ZZ_H |
| 2717945751U, // UUNPKLO_ZZ_S |
| 18075U, // UXTB_ZPmZ_D |
| 2181588635U, // UXTB_ZPmZ_H |
| 34459U, // UXTB_ZPmZ_S |
| 19500U, // UXTH_ZPmZ_D |
| 35884U, // UXTH_ZPmZ_S |
| 21821U, // UXTW_ZPmZ_D |
| 167780401U, // UZP1_PPP_B |
| 201343025U, // UZP1_PPP_D |
| 2387107889U, // UZP1_PPP_H |
| 268468273U, // UZP1_PPP_S |
| 167780401U, // UZP1_ZZZ_B |
| 201343025U, // UZP1_ZZZ_D |
| 2387107889U, // UZP1_ZZZ_H |
| 268468273U, // UZP1_ZZZ_S |
| 68198449U, // UZP1v16i8 |
| 2216206385U, // UZP1v2i32 |
| 2216730673U, // UZP1v2i64 |
| 69771313U, // UZP1v4i16 |
| 70295601U, // UZP1v4i32 |
| 2218303537U, // UZP1v8i16 |
| 2218827825U, // UZP1v8i8 |
| 167780812U, // UZP2_PPP_B |
| 201343436U, // UZP2_PPP_D |
| 2387108300U, // UZP2_PPP_H |
| 268468684U, // UZP2_PPP_S |
| 167780812U, // UZP2_ZZZ_B |
| 201343436U, // UZP2_ZZZ_D |
| 2387108300U, // UZP2_ZZZ_H |
| 268468684U, // UZP2_ZZZ_S |
| 68198860U, // UZP2v16i8 |
| 2216206796U, // UZP2v2i32 |
| 2216731084U, // UZP2v2i64 |
| 69771724U, // UZP2v4i16 |
| 70296012U, // UZP2v4i32 |
| 2218303948U, // UZP2v8i16 |
| 2218828236U, // UZP2v8i8 |
| 100673670U, // WHILELE_PWW_B |
| 100681862U, // WHILELE_PWW_D |
| 242772102U, // WHILELE_PWW_H |
| 100698246U, // WHILELE_PWW_S |
| 100673670U, // WHILELE_PXX_B |
| 100681862U, // WHILELE_PXX_D |
| 242772102U, // WHILELE_PXX_H |
| 100698246U, // WHILELE_PXX_S |
| 100675452U, // WHILELO_PWW_B |
| 100683644U, // WHILELO_PWW_D |
| 242773884U, // WHILELO_PWW_H |
| 100700028U, // WHILELO_PWW_S |
| 100675452U, // WHILELO_PXX_B |
| 100683644U, // WHILELO_PXX_D |
| 242773884U, // WHILELO_PXX_H |
| 100700028U, // WHILELO_PXX_S |
| 100676169U, // WHILELS_PWW_B |
| 100684361U, // WHILELS_PWW_D |
| 242774601U, // WHILELS_PWW_H |
| 100700745U, // WHILELS_PWW_S |
| 100676169U, // WHILELS_PXX_B |
| 100684361U, // WHILELS_PXX_D |
| 242774601U, // WHILELS_PXX_H |
| 100700745U, // WHILELS_PXX_S |
| 100676358U, // WHILELT_PWW_B |
| 100684550U, // WHILELT_PWW_D |
| 242774790U, // WHILELT_PWW_H |
| 100700934U, // WHILELT_PWW_S |
| 100676358U, // WHILELT_PXX_B |
| 100684550U, // WHILELT_PXX_D |
| 242774790U, // WHILELT_PXX_H |
| 100700934U, // WHILELT_PXX_S |
| 6303987U, // WRFFR |
| 2216734934U, // XAR |
| 6342582U, // XPACD |
| 6343754U, // XPACI |
| 5905U, // XPACLRI |
| 135324049U, // XTNv16i8 |
| 2216210247U, // XTNv2i32 |
| 2217258823U, // XTNv4i16 |
| 2284904849U, // XTNv4i32 |
| 2285429137U, // XTNv8i16 |
| 71348039U, // XTNv8i8 |
| 167780395U, // ZIP1_PPP_B |
| 201343019U, // ZIP1_PPP_D |
| 2387107883U, // ZIP1_PPP_H |
| 268468267U, // ZIP1_PPP_S |
| 167780395U, // ZIP1_ZZZ_B |
| 201343019U, // ZIP1_ZZZ_D |
| 2387107883U, // ZIP1_ZZZ_H |
| 268468267U, // ZIP1_ZZZ_S |
| 68198443U, // ZIP1v16i8 |
| 2216206379U, // ZIP1v2i32 |
| 2216730667U, // ZIP1v2i64 |
| 69771307U, // ZIP1v4i16 |
| 70295595U, // ZIP1v4i32 |
| 2218303531U, // ZIP1v8i16 |
| 2218827819U, // ZIP1v8i8 |
| 167780806U, // ZIP2_PPP_B |
| 201343430U, // ZIP2_PPP_D |
| 2387108294U, // ZIP2_PPP_H |
| 268468678U, // ZIP2_PPP_S |
| 167780806U, // ZIP2_ZZZ_B |
| 201343430U, // ZIP2_ZZZ_D |
| 2387108294U, // ZIP2_ZZZ_H |
| 268468678U, // ZIP2_ZZZ_S |
| 68198854U, // ZIP2v16i8 |
| 2216206790U, // ZIP2v2i32 |
| 2216731078U, // ZIP2v2i64 |
| 69771718U, // ZIP2v4i16 |
| 70296006U, // ZIP2v4i32 |
| 2218303942U, // ZIP2v8i16 |
| 2218828230U, // ZIP2v8i8 |
| 302003021U, // anonymous_1349 |
| }; |
| |
| static const uint32_t OpInfo1[] = { |
| 0U, // PHI |
| 0U, // INLINEASM |
| 0U, // CFI_INSTRUCTION |
| 0U, // EH_LABEL |
| 0U, // GC_LABEL |
| 0U, // ANNOTATION_LABEL |
| 0U, // KILL |
| 0U, // EXTRACT_SUBREG |
| 0U, // INSERT_SUBREG |
| 0U, // IMPLICIT_DEF |
| 0U, // SUBREG_TO_REG |
| 0U, // COPY_TO_REGCLASS |
| 0U, // DBG_VALUE |
| 0U, // DBG_LABEL |
| 0U, // REG_SEQUENCE |
| 0U, // COPY |
| 0U, // BUNDLE |
| 0U, // LIFETIME_START |
| 0U, // LIFETIME_END |
| 0U, // STACKMAP |
| 0U, // FENTRY_CALL |
| 0U, // PATCHPOINT |
| 0U, // LOAD_STACK_GUARD |
| 0U, // STATEPOINT |
| 0U, // LOCAL_ESCAPE |
| 0U, // FAULTING_OP |
| 0U, // PATCHABLE_OP |
| 0U, // PATCHABLE_FUNCTION_ENTER |
| 0U, // PATCHABLE_RET |
| 0U, // PATCHABLE_FUNCTION_EXIT |
| 0U, // PATCHABLE_TAIL_CALL |
| 0U, // PATCHABLE_EVENT_CALL |
| 0U, // PATCHABLE_TYPED_EVENT_CALL |
| 0U, // ICALL_BRANCH_FUNNEL |
| 0U, // G_ADD |
| 0U, // G_SUB |
| 0U, // G_MUL |
| 0U, // G_SDIV |
| 0U, // G_UDIV |
| 0U, // G_SREM |
| 0U, // G_UREM |
| 0U, // G_AND |
| 0U, // G_OR |
| 0U, // G_XOR |
| 0U, // G_IMPLICIT_DEF |
| 0U, // G_PHI |
| 0U, // G_FRAME_INDEX |
| 0U, // G_GLOBAL_VALUE |
| 0U, // G_EXTRACT |
| 0U, // G_UNMERGE_VALUES |
| 0U, // G_INSERT |
| 0U, // G_MERGE_VALUES |
| 0U, // G_PTRTOINT |
| 0U, // G_INTTOPTR |
| 0U, // G_BITCAST |
| 0U, // G_LOAD |
| 0U, // G_SEXTLOAD |
| 0U, // G_ZEXTLOAD |
| 0U, // G_STORE |
| 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 0U, // G_ATOMIC_CMPXCHG |
| 0U, // G_ATOMICRMW_XCHG |
| 0U, // G_ATOMICRMW_ADD |
| 0U, // G_ATOMICRMW_SUB |
| 0U, // G_ATOMICRMW_AND |
| 0U, // G_ATOMICRMW_NAND |
| 0U, // G_ATOMICRMW_OR |
| 0U, // G_ATOMICRMW_XOR |
| 0U, // G_ATOMICRMW_MAX |
| 0U, // G_ATOMICRMW_MIN |
| 0U, // G_ATOMICRMW_UMAX |
| 0U, // G_ATOMICRMW_UMIN |
| 0U, // G_BRCOND |
| 0U, // G_BRINDIRECT |
| 0U, // G_INTRINSIC |
| 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
| 0U, // G_ANYEXT |
| 0U, // G_TRUNC |
| 0U, // G_CONSTANT |
| 0U, // G_FCONSTANT |
| 0U, // G_VASTART |
| 0U, // G_VAARG |
| 0U, // G_SEXT |
| 0U, // G_ZEXT |
| 0U, // G_SHL |
| 0U, // G_LSHR |
| 0U, // G_ASHR |
| 0U, // G_ICMP |
| 0U, // G_FCMP |
| 0U, // G_SELECT |
| 0U, // G_UADDE |
| 0U, // G_USUBE |
| 0U, // G_SADDO |
| 0U, // G_SSUBO |
| 0U, // G_UMULO |
| 0U, // G_SMULO |
| 0U, // G_UMULH |
| 0U, // G_SMULH |
| 0U, // G_FADD |
| 0U, // G_FSUB |
| 0U, // G_FMUL |
| 0U, // G_FMA |
| 0U, // G_FDIV |
| 0U, // G_FREM |
| 0U, // G_FPOW |
| 0U, // G_FEXP |
| 0U, // G_FEXP2 |
| 0U, // G_FLOG |
| 0U, // G_FLOG2 |
| 0U, // G_FNEG |
| 0U, // G_FPEXT |
| 0U, // G_FPTRUNC |
| 0U, // G_FPTOSI |
| 0U, // G_FPTOUI |
| 0U, // G_SITOFP |
| 0U, // G_UITOFP |
| 0U, // G_FABS |
| 0U, // G_GEP |
| 0U, // G_PTR_MASK |
| 0U, // G_BR |
| 0U, // G_INSERT_VECTOR_ELT |
| 0U, // G_EXTRACT_VECTOR_ELT |
| 0U, // G_SHUFFLE_VECTOR |
| 0U, // G_BSWAP |
| 0U, // G_ADDRSPACE_CAST |
| 0U, // G_BLOCK_ADDR |
| 0U, // ABS_ZPmZ_B |
| 64U, // ABS_ZPmZ_D |
| 128U, // ABS_ZPmZ_H |
| 192U, // ABS_ZPmZ_S |
| 1U, // ABSv16i8 |
| 1U, // ABSv1i64 |
| 2U, // ABSv2i32 |
| 2U, // ABSv2i64 |
| 3U, // ABSv4i16 |
| 3U, // ABSv4i32 |
| 4U, // ABSv8i16 |
| 4U, // ABSv8i8 |
| 261U, // ADCSWr |
| 261U, // ADCSXr |
| 261U, // ADCWr |
| 261U, // ADCXr |
| 8517U, // ADDHNv2i64_v2i32 |
| 8581U, // ADDHNv2i64_v4i32 |
| 16710U, // ADDHNv4i32_v4i16 |
| 16774U, // ADDHNv4i32_v8i16 |
| 24966U, // ADDHNv8i16_v16i8 |
| 24902U, // ADDHNv8i16_v8i8 |
| 261U, // ADDPL_XXI |
| 33095U, // ADDPv16i8 |
| 41287U, // ADDPv2i32 |
| 8517U, // ADDPv2i64 |
| 2U, // ADDPv2i64p |
| 49480U, // ADDPv4i16 |
| 16710U, // ADDPv4i32 |
| 24902U, // ADDPv8i16 |
| 57672U, // ADDPv8i8 |
| 453U, // ADDSWri |
| 0U, // ADDSWrr |
| 517U, // ADDSWrs |
| 581U, // ADDSWrx |
| 453U, // ADDSXri |
| 0U, // ADDSXrr |
| 517U, // ADDSXrs |
| 581U, // ADDSXrx |
| 65797U, // ADDSXrx64 |
| 261U, // ADDVL_XXI |
| 1U, // ADDVv16i8v |
| 3U, // ADDVv4i16v |
| 3U, // ADDVv4i32v |
| 4U, // ADDVv8i16v |
| 4U, // ADDVv8i8v |
| 453U, // ADDWri |
| 0U, // ADDWrr |
| 517U, // ADDWrs |
| 581U, // ADDWrx |
| 453U, // ADDXri |
| 0U, // ADDXrr |
| 517U, // ADDXrs |
| 581U, // ADDXrx |
| 65797U, // ADDXrx64 |
| 645U, // ADD_ZI_B |
| 709U, // ADD_ZI_D |
| 9U, // ADD_ZI_H |
| 773U, // ADD_ZI_S |
| 74560U, // ADD_ZPmZ_B |
| 598912U, // ADD_ZPmZ_D |
| 1131465U, // ADD_ZPmZ_H |
| 1647616U, // ADD_ZPmZ_S |
| 837U, // ADD_ZZZ_B |
| 901U, // ADD_ZZZ_D |
| 137U, // ADD_ZZZ_H |
| 1029U, // ADD_ZZZ_S |
| 0U, // ADDlowTLS |
| 33095U, // ADDv16i8 |
| 261U, // ADDv1i64 |
| 41287U, // ADDv2i32 |
| 8517U, // ADDv2i64 |
| 49480U, // ADDv4i16 |
| 16710U, // ADDv4i32 |
| 24902U, // ADDv8i16 |
| 57672U, // ADDv8i8 |
| 0U, // ADJCALLSTACKDOWN |
| 0U, // ADJCALLSTACKUP |
| 1U, // ADR |
| 0U, // ADRP |
| 1093U, // ADR_LSL_ZZZ_D_0 |
| 1157U, // ADR_LSL_ZZZ_D_1 |
| 1221U, // ADR_LSL_ZZZ_D_2 |
| 1285U, // ADR_LSL_ZZZ_D_3 |
| 1349U, // ADR_LSL_ZZZ_S_0 |
| 1413U, // ADR_LSL_ZZZ_S_1 |
| 1477U, // ADR_LSL_ZZZ_S_2 |
| 1541U, // ADR_LSL_ZZZ_S_3 |
| 1605U, // ADR_SXTW_ZZZ_D_0 |
| 1669U, // ADR_SXTW_ZZZ_D_1 |
| 1733U, // ADR_SXTW_ZZZ_D_2 |
| 1797U, // ADR_SXTW_ZZZ_D_3 |
| 1861U, // ADR_UXTW_ZZZ_D_0 |
| 1925U, // ADR_UXTW_ZZZ_D_1 |
| 1989U, // ADR_UXTW_ZZZ_D_2 |
| 2053U, // ADR_UXTW_ZZZ_D_3 |
| 1U, // AESDrr |
| 1U, // AESErr |
| 1U, // AESIMCrr |
| 0U, // AESIMCrrTied |
| 1U, // AESMCrr |
| 0U, // AESMCrrTied |
| 2117U, // ANDSWri |
| 0U, // ANDSWrr |
| 517U, // ANDSWrs |
| 2181U, // ANDSXri |
| 0U, // ANDSXrr |
| 517U, // ANDSXrs |
| 74570U, // ANDS_PPzPP |
| 837U, // ANDV_VPZ_B |
| 901U, // ANDV_VPZ_D |
| 2245U, // ANDV_VPZ_H |
| 1029U, // ANDV_VPZ_S |
| 2117U, // ANDWri |
| 0U, // ANDWrr |
| 517U, // ANDWrs |
| 2181U, // ANDXri |
| 0U, // ANDXrr |
| 517U, // ANDXrs |
| 74570U, // AND_PPzPP |
| 2181U, // AND_ZI |
| 74560U, // AND_ZPmZ_B |
| 598912U, // AND_ZPmZ_D |
| 1131465U, // AND_ZPmZ_H |
| 1647616U, // AND_ZPmZ_S |
| 901U, // AND_ZZZ |
| 33095U, // ANDv16i8 |
| 57672U, // ANDv8i8 |
| 2171712U, // ASRD_ZPmI_B |
| 2171776U, // ASRD_ZPmI_D |
| 91081U, // ASRD_ZPmI_H |
| 2171904U, // ASRD_ZPmI_S |
| 74560U, // ASRR_ZPmZ_B |
| 598912U, // ASRR_ZPmZ_D |
| 1131465U, // ASRR_ZPmZ_H |
| 1647616U, // ASRR_ZPmZ_S |
| 261U, // ASRVWr |
| 261U, // ASRVXr |
| 598848U, // ASR_WIDE_ZPmZ_B |
| 99273U, // ASR_WIDE_ZPmZ_H |
| 599040U, // ASR_WIDE_ZPmZ_S |
| 901U, // ASR_WIDE_ZZZ_B |
| 10U, // ASR_WIDE_ZZZ_H |
| 901U, // ASR_WIDE_ZZZ_S |
| 2171712U, // ASR_ZPmI_B |
| 2171776U, // ASR_ZPmI_D |
| 91081U, // ASR_ZPmI_H |
| 2171904U, // ASR_ZPmI_S |
| 74560U, // ASR_ZPmZ_B |
| 598912U, // ASR_ZPmZ_D |
| 1131465U, // ASR_ZPmZ_H |
| 1647616U, // ASR_ZPmZ_S |
| 261U, // ASR_ZZI_B |
| 261U, // ASR_ZZI_D |
| 11U, // ASR_ZZI_H |
| 261U, // ASR_ZZI_S |
| 1U, // AUTDA |
| 1U, // AUTDB |
| 0U, // AUTDZA |
| 0U, // AUTDZB |
| 1U, // AUTIA |
| 0U, // AUTIA1716 |
| 0U, // AUTIASP |
| 0U, // AUTIAZ |
| 1U, // AUTIB |
| 0U, // AUTIB1716 |
| 0U, // AUTIBSP |
| 0U, // AUTIBZ |
| 0U, // AUTIZA |
| 0U, // AUTIZB |
| 0U, // B |
| 36282695U, // BCAX |
| 3221765U, // BFMWri |
| 3221765U, // BFMXri |
| 0U, // BICSWrr |
| 517U, // BICSWrs |
| 0U, // BICSXrr |
| 517U, // BICSXrs |
| 74570U, // BICS_PPzPP |
| 0U, // BICWrr |
| 517U, // BICWrs |
| 0U, // BICXrr |
| 517U, // BICXrs |
| 74570U, // BIC_PPzPP |
| 74560U, // BIC_ZPmZ_B |
| 598912U, // BIC_ZPmZ_D |
| 1131465U, // BIC_ZPmZ_H |
| 1647616U, // BIC_ZPmZ_S |
| 901U, // BIC_ZZZ |
| 33095U, // BICv16i8 |
| 0U, // BICv2i32 |
| 0U, // BICv4i16 |
| 0U, // BICv4i32 |
| 0U, // BICv8i16 |
| 57672U, // BICv8i8 |
| 33095U, // BIFv16i8 |
| 57672U, // BIFv8i8 |
| 33159U, // BITv16i8 |
| 57736U, // BITv8i8 |
| 0U, // BL |
| 0U, // BLR |
| 1U, // BLRAA |
| 0U, // BLRAAZ |
| 1U, // BLRAB |
| 0U, // BLRABZ |
| 0U, // BR |
| 1U, // BRAA |
| 0U, // BRAAZ |
| 1U, // BRAB |
| 0U, // BRABZ |
| 0U, // BRK |
| 842U, // BRKAS_PPzP |
| 0U, // BRKA_PPmP |
| 842U, // BRKA_PPzP |
| 842U, // BRKBS_PPzP |
| 0U, // BRKB_PPmP |
| 842U, // BRKB_PPzP |
| 74570U, // BRKNS_PPzP |
| 74570U, // BRKN_PPzP |
| 74570U, // BRKPAS_PPzPP |
| 74570U, // BRKPA_PPzPP |
| 74570U, // BRKPBS_PPzPP |
| 74570U, // BRKPB_PPzPP |
| 33159U, // BSLv16i8 |
| 57736U, // BSLv8i8 |
| 0U, // Bcc |
| 117003U, // CASAB |
| 117003U, // CASAH |
| 117003U, // CASALB |
| 117003U, // CASALH |
| 117003U, // CASALW |
| 117003U, // CASALX |
| 117003U, // CASAW |
| 117003U, // CASAX |
| 117003U, // CASB |
| 117003U, // CASH |
| 117003U, // CASLB |
| 117003U, // CASLH |
| 117003U, // CASLW |
| 117003U, // CASLX |
| 0U, // CASPALW |
| 0U, // CASPALX |
| 0U, // CASPAW |
| 0U, // CASPAX |
| 0U, // CASPLW |
| 0U, // CASPLX |
| 0U, // CASPW |
| 0U, // CASPX |
| 117003U, // CASW |
| 117003U, // CASX |
| 0U, // CBNZW |
| 0U, // CBNZX |
| 0U, // CBZW |
| 0U, // CBZX |
| 3744005U, // CCMNWi |
| 3744005U, // CCMNWr |
| 3744005U, // CCMNXi |
| 3744005U, // CCMNXr |
| 3744005U, // CCMPWi |
| 3744005U, // CCMPWr |
| 3744005U, // CCMPXi |
| 3744005U, // CCMPXr |
| 0U, // CFINV |
| 73989U, // CLASTA_RPZ_B |
| 598277U, // CLASTA_RPZ_D |
| 4268293U, // CLASTA_RPZ_H |
| 1646853U, // CLASTA_RPZ_S |
| 73989U, // CLASTA_VPZ_B |
| 598277U, // CLASTA_VPZ_D |
| 4268293U, // CLASTA_VPZ_H |
| 1646853U, // CLASTA_VPZ_S |
| 74565U, // CLASTA_ZPZ_B |
| 598917U, // CLASTA_ZPZ_D |
| 1131465U, // CLASTA_ZPZ_H |
| 1647621U, // CLASTA_ZPZ_S |
| 73989U, // CLASTB_RPZ_B |
| 598277U, // CLASTB_RPZ_D |
| 4268293U, // CLASTB_RPZ_H |
| 1646853U, // CLASTB_RPZ_S |
| 73989U, // CLASTB_VPZ_B |
| 598277U, // CLASTB_VPZ_D |
| 4268293U, // CLASTB_VPZ_H |
| 1646853U, // CLASTB_VPZ_S |
| 74565U, // CLASTB_ZPZ_B |
| 598917U, // CLASTB_ZPZ_D |
| 1131465U, // CLASTB_ZPZ_H |
| 1647621U, // CLASTB_ZPZ_S |
| 0U, // CLREX |
| 1U, // CLSWr |
| 1U, // CLSXr |
| 0U, // CLS_ZPmZ_B |
| 64U, // CLS_ZPmZ_D |
| 128U, // CLS_ZPmZ_H |
| 192U, // CLS_ZPmZ_S |
| 1U, // CLSv16i8 |
| 2U, // CLSv2i32 |
| 3U, // CLSv4i16 |
| 3U, // CLSv4i32 |
| 4U, // CLSv8i16 |
| 4U, // CLSv8i8 |
| 1U, // CLZWr |
| 1U, // CLZXr |
| 0U, // CLZ_ZPmZ_B |
| 64U, // CLZ_ZPmZ_D |
| 128U, // CLZ_ZPmZ_H |
| 192U, // CLZ_ZPmZ_S |
| 1U, // CLZv16i8 |
| 2U, // CLZv2i32 |
| 3U, // CLZv4i16 |
| 3U, // CLZv4i32 |
| 4U, // CLZv8i16 |
| 4U, // CLZv8i8 |
| 33095U, // CMEQv16i8 |
| 12U, // CMEQv16i8rz |
| 261U, // CMEQv1i64 |
| 12U, // CMEQv1i64rz |
| 41287U, // CMEQv2i32 |
| 13U, // CMEQv2i32rz |
| 8517U, // CMEQv2i64 |
| 13U, // CMEQv2i64rz |
| 49480U, // CMEQv4i16 |
| 14U, // CMEQv4i16rz |
| 16710U, // CMEQv4i32 |
| 14U, // CMEQv4i32rz |
| 24902U, // CMEQv8i16 |
| 15U, // CMEQv8i16rz |
| 57672U, // CMEQv8i8 |
| 15U, // CMEQv8i8rz |
| 33095U, // CMGEv16i8 |
| 12U, // CMGEv16i8rz |
| 261U, // CMGEv1i64 |
| 12U, // CMGEv1i64rz |
| 41287U, // CMGEv2i32 |
| 13U, // CMGEv2i32rz |
| 8517U, // CMGEv2i64 |
| 13U, // CMGEv2i64rz |
| 49480U, // CMGEv4i16 |
| 14U, // CMGEv4i16rz |
| 16710U, // CMGEv4i32 |
| 14U, // CMGEv4i32rz |
| 24902U, // CMGEv8i16 |
| 15U, // CMGEv8i16rz |
| 57672U, // CMGEv8i8 |
| 15U, // CMGEv8i8rz |
| 33095U, // CMGTv16i8 |
| 12U, // CMGTv16i8rz |
| 261U, // CMGTv1i64 |
| 12U, // CMGTv1i64rz |
| 41287U, // CMGTv2i32 |
| 13U, // CMGTv2i32rz |
| 8517U, // CMGTv2i64 |
| 13U, // CMGTv2i64rz |
| 49480U, // CMGTv4i16 |
| 14U, // CMGTv4i16rz |
| 16710U, // CMGTv4i32 |
| 14U, // CMGTv4i32rz |
| 24902U, // CMGTv8i16 |
| 15U, // CMGTv8i16rz |
| 57672U, // CMGTv8i8 |
| 15U, // CMGTv8i8rz |
| 33095U, // CMHIv16i8 |
| 261U, // CMHIv1i64 |
| 41287U, // CMHIv2i32 |
| 8517U, // CMHIv2i64 |
| 49480U, // CMHIv4i16 |
| 16710U, // CMHIv4i32 |
| 24902U, // CMHIv8i16 |
| 57672U, // CMHIv8i8 |
| 33095U, // CMHSv16i8 |
| 261U, // CMHSv1i64 |
| 41287U, // CMHSv2i32 |
| 8517U, // CMHSv2i64 |
| 49480U, // CMHSv4i16 |
| 16710U, // CMHSv4i32 |
| 24902U, // CMHSv8i16 |
| 57672U, // CMHSv8i8 |
| 12U, // CMLEv16i8rz |
| 12U, // CMLEv1i64rz |
| 13U, // CMLEv2i32rz |
| 13U, // CMLEv2i64rz |
| 14U, // CMLEv4i16rz |
| 14U, // CMLEv4i32rz |
| 15U, // CMLEv8i16rz |
| 15U, // CMLEv8i8rz |
| 12U, // CMLTv16i8rz |
| 12U, // CMLTv1i64rz |
| 13U, // CMLTv2i32rz |
| 13U, // CMLTv2i64rz |
| 14U, // CMLTv4i16rz |
| 14U, // CMLTv4i32rz |
| 15U, // CMLTv8i16rz |
| 15U, // CMLTv8i8rz |
| 2171722U, // CMPEQ_PPzZI_B |
| 2171786U, // CMPEQ_PPzZI_D |
| 91081U, // CMPEQ_PPzZI_H |
| 2171914U, // CMPEQ_PPzZI_S |
| 74570U, // CMPEQ_PPzZZ_B |
| 598922U, // CMPEQ_PPzZZ_D |
| 1131465U, // CMPEQ_PPzZZ_H |
| 1647626U, // CMPEQ_PPzZZ_S |
| 598858U, // CMPEQ_WIDE_PPzZZ_B |
| 99273U, // CMPEQ_WIDE_PPzZZ_H |
| 599050U, // CMPEQ_WIDE_PPzZZ_S |
| 2171722U, // CMPGE_PPzZI_B |
| 2171786U, // CMPGE_PPzZI_D |
| 91081U, // CMPGE_PPzZI_H |
| 2171914U, // CMPGE_PPzZI_S |
| 74570U, // CMPGE_PPzZZ_B |
| 598922U, // CMPGE_PPzZZ_D |
| 1131465U, // CMPGE_PPzZZ_H |
| 1647626U, // CMPGE_PPzZZ_S |
| 598858U, // CMPGE_WIDE_PPzZZ_B |
| 99273U, // CMPGE_WIDE_PPzZZ_H |
| 599050U, // CMPGE_WIDE_PPzZZ_S |
| 2171722U, // CMPGT_PPzZI_B |
| 2171786U, // CMPGT_PPzZI_D |
| 91081U, // CMPGT_PPzZI_H |
| 2171914U, // CMPGT_PPzZI_S |
| 74570U, // CMPGT_PPzZZ_B |
| 598922U, // CMPGT_PPzZZ_D |
| 1131465U, // CMPGT_PPzZZ_H |
| 1647626U, // CMPGT_PPzZZ_S |
| 598858U, // CMPGT_WIDE_PPzZZ_B |
| 99273U, // CMPGT_WIDE_PPzZZ_H |
| 599050U, // CMPGT_WIDE_PPzZZ_S |
| 4793162U, // CMPHI_PPzZI_B |
| 4793226U, // CMPHI_PPzZI_D |
| 123849U, // CMPHI_PPzZI_H |
| 4793354U, // CMPHI_PPzZI_S |
| 74570U, // CMPHI_PPzZZ_B |
| 598922U, // CMPHI_PPzZZ_D |
| 1131465U, // CMPHI_PPzZZ_H |
| 1647626U, // CMPHI_PPzZZ_S |
| 598858U, // CMPHI_WIDE_PPzZZ_B |
| 99273U, // CMPHI_WIDE_PPzZZ_H |
| 599050U, // CMPHI_WIDE_PPzZZ_S |
| 4793162U, // CMPHS_PPzZI_B |
| 4793226U, // CMPHS_PPzZI_D |
| 123849U, // CMPHS_PPzZI_H |
| 4793354U, // CMPHS_PPzZI_S |
| 74570U, // CMPHS_PPzZZ_B |
| 598922U, // CMPHS_PPzZZ_D |
| 1131465U, // CMPHS_PPzZZ_H |
| 1647626U, // CMPHS_PPzZZ_S |
| 598858U, // CMPHS_WIDE_PPzZZ_B |
| 99273U, // CMPHS_WIDE_PPzZZ_H |
| 599050U, // CMPHS_WIDE_PPzZZ_S |
| 2171722U, // CMPLE_PPzZI_B |
| 2171786U, // CMPLE_PPzZI_D |
| 91081U, // CMPLE_PPzZI_H |
| 2171914U, // CMPLE_PPzZI_S |
| 598858U, // CMPLE_WIDE_PPzZZ_B |
| 99273U, // CMPLE_WIDE_PPzZZ_H |
| 599050U, // CMPLE_WIDE_PPzZZ_S |
| 4793162U, // CMPLO_PPzZI_B |
| 4793226U, // CMPLO_PPzZI_D |
| 123849U, // CMPLO_PPzZI_H |
| 4793354U, // CMPLO_PPzZI_S |
| 598858U, // CMPLO_WIDE_PPzZZ_B |
| 99273U, // CMPLO_WIDE_PPzZZ_H |
| 599050U, // CMPLO_WIDE_PPzZZ_S |
| 4793162U, // CMPLS_PPzZI_B |
| 4793226U, // CMPLS_PPzZI_D |
| 123849U, // CMPLS_PPzZI_H |
| 4793354U, // CMPLS_PPzZI_S |
| 598858U, // CMPLS_WIDE_PPzZZ_B |
| 99273U, // CMPLS_WIDE_PPzZZ_H |
| 599050U, // CMPLS_WIDE_PPzZZ_S |
| 2171722U, // CMPLT_PPzZI_B |
| 2171786U, // CMPLT_PPzZI_D |
| 91081U, // CMPLT_PPzZI_H |
| 2171914U, // CMPLT_PPzZI_S |
| 598858U, // CMPLT_WIDE_PPzZZ_B |
| 99273U, // CMPLT_WIDE_PPzZZ_H |
| 599050U, // CMPLT_WIDE_PPzZZ_S |
| 2171722U, // CMPNE_PPzZI_B |
| 2171786U, // CMPNE_PPzZI_D |
| 91081U, // CMPNE_PPzZI_H |
| 2171914U, // CMPNE_PPzZI_S |
| 74570U, // CMPNE_PPzZZ_B |
| 598922U, // CMPNE_PPzZZ_D |
| 1131465U, // CMPNE_PPzZZ_H |
| 1647626U, // CMPNE_PPzZZ_S |
| 598858U, // CMPNE_WIDE_PPzZZ_B |
| 99273U, // CMPNE_WIDE_PPzZZ_H |
| 599050U, // CMPNE_WIDE_PPzZZ_S |
| 0U, // CMP_SWAP_128 |
| 0U, // CMP_SWAP_16 |
| 0U, // CMP_SWAP_32 |
| 0U, // CMP_SWAP_64 |
| 0U, // CMP_SWAP_8 |
| 33095U, // CMTSTv16i8 |
| 261U, // CMTSTv1i64 |
| 41287U, // CMTSTv2i32 |
| 8517U, // CMTSTv2i64 |
| 49480U, // CMTSTv4i16 |
| 16710U, // CMTSTv4i32 |
| 24902U, // CMTSTv8i16 |
| 57672U, // CMTSTv8i8 |
| 0U, // CNOT_ZPmZ_B |
| 64U, // CNOT_ZPmZ_D |
| 128U, // CNOT_ZPmZ_H |
| 192U, // CNOT_ZPmZ_S |
| 16U, // CNTB_XPiI |
| 16U, // CNTD_XPiI |
| 16U, // CNTH_XPiI |
| 837U, // CNTP_XPP_B |
| 901U, // CNTP_XPP_D |
| 2245U, // CNTP_XPP_H |
| 1029U, // CNTP_XPP_S |
| 16U, // CNTW_XPiI |
| 0U, // CNT_ZPmZ_B |
| 64U, // CNT_ZPmZ_D |
| 128U, // CNT_ZPmZ_H |
| 192U, // CNT_ZPmZ_S |
| 1U, // CNTv16i8 |
| 4U, // CNTv8i8 |
| 901U, // COMPACT_ZPZ_D |
| 1029U, // COMPACT_ZPZ_S |
| 2368U, // CPY_ZPmI_B |
| 2432U, // CPY_ZPmI_D |
| 16U, // CPY_ZPmI_H |
| 2496U, // CPY_ZPmI_S |
| 2304U, // CPY_ZPmR_B |
| 2304U, // CPY_ZPmR_D |
| 145U, // CPY_ZPmR_H |
| 2304U, // CPY_ZPmR_S |
| 2304U, // CPY_ZPmV_B |
| 2304U, // CPY_ZPmV_D |
| 145U, // CPY_ZPmV_H |
| 2304U, // CPY_ZPmV_S |
| 2570U, // CPY_ZPzI_B |
| 2634U, // CPY_ZPzI_D |
| 17U, // CPY_ZPzI_H |
| 2698U, // CPY_ZPzI_S |
| 2770U, // CPYi16 |
| 2770U, // CPYi32 |
| 2771U, // CPYi64 |
| 2771U, // CPYi8 |
| 261U, // CRC32Brr |
| 261U, // CRC32CBrr |
| 261U, // CRC32CHrr |
| 261U, // CRC32CWrr |
| 261U, // CRC32CXrr |
| 261U, // CRC32Hrr |
| 261U, // CRC32Wrr |
| 261U, // CRC32Xrr |
| 3744005U, // CSELWr |
| 3744005U, // CSELXr |
| 3744005U, // CSINCWr |
| 3744005U, // CSINCXr |
| 3744005U, // CSINVWr |
| 3744005U, // CSINVXr |
| 3744005U, // CSNEGWr |
| 3744005U, // CSNEGXr |
| 1U, // CTERMEQ_WW |
| 1U, // CTERMEQ_XX |
| 1U, // CTERMNE_WW |
| 1U, // CTERMNE_XX |
| 0U, // CompilerBarrier |
| 0U, // DCPS1 |
| 0U, // DCPS2 |
| 0U, // DCPS3 |
| 0U, // DECB_XPiI |
| 0U, // DECD_XPiI |
| 0U, // DECD_ZPiI |
| 0U, // DECH_XPiI |
| 0U, // DECH_ZPiI |
| 1U, // DECP_XP_B |
| 1U, // DECP_XP_D |
| 1U, // DECP_XP_H |
| 1U, // DECP_XP_S |
| 1U, // DECP_ZP_D |
| 0U, // DECP_ZP_H |
| 1U, // DECP_ZP_S |
| 0U, // DECW_XPiI |
| 0U, // DECW_ZPiI |
| 0U, // DMB |
| 0U, // DRPS |
| 0U, // DSB |
| 0U, // DUPM_ZI |
| 0U, // DUP_ZI_B |
| 0U, // DUP_ZI_D |
| 0U, // DUP_ZI_H |
| 0U, // DUP_ZI_S |
| 1U, // DUP_ZR_B |
| 1U, // DUP_ZR_D |
| 0U, // DUP_ZR_H |
| 1U, // DUP_ZR_S |
| 20U, // DUP_ZZI_B |
| 20U, // DUP_ZZI_D |
| 0U, // DUP_ZZI_H |
| 0U, // DUP_ZZI_Q |
| 20U, // DUP_ZZI_S |
| 1U, // DUPv16i8gpr |
| 2771U, // DUPv16i8lane |
| 1U, // DUPv2i32gpr |
| 2770U, // DUPv2i32lane |
| 1U, // DUPv2i64gpr |
| 2771U, // DUPv2i64lane |
| 1U, // DUPv4i16gpr |
| 2770U, // DUPv4i16lane |
| 1U, // DUPv4i32gpr |
| 2770U, // DUPv4i32lane |
| 1U, // DUPv8i16gpr |
| 2770U, // DUPv8i16lane |
| 1U, // DUPv8i8gpr |
| 2771U, // DUPv8i8lane |
| 0U, // EONWrr |
| 517U, // EONWrs |
| 0U, // EONXrr |
| 517U, // EONXrs |
| 36282695U, // EOR3 |
| 74570U, // EORS_PPzPP |
| 837U, // EORV_VPZ_B |
| 901U, // EORV_VPZ_D |
| 2245U, // EORV_VPZ_H |
| 1029U, // EORV_VPZ_S |
| 2117U, // EORWri |
| 0U, // EORWrr |
| 517U, // EORWrs |
| 2181U, // EORXri |
| 0U, // EORXrr |
| 517U, // EORXrs |
| 74570U, // EOR_PPzPP |
| 2181U, // EOR_ZI |
| 74560U, // EOR_ZPmZ_B |
| 598912U, // EOR_ZPmZ_D |
| 1131465U, // EOR_ZPmZ_H |
| 1647616U, // EOR_ZPmZ_S |
| 901U, // EOR_ZZZ |
| 33095U, // EORv16i8 |
| 57672U, // EORv8i8 |
| 0U, // ERET |
| 0U, // ERETAA |
| 0U, // ERETAB |
| 2171141U, // EXTRWrri |
| 2171141U, // EXTRXrri |
| 4793157U, // EXT_ZZI |
| 2203975U, // EXTv16i8 |
| 131400U, // EXTv8i8 |
| 0U, // F128CSEL |
| 261U, // FABD16 |
| 261U, // FABD32 |
| 261U, // FABD64 |
| 598912U, // FABD_ZPmZ_D |
| 1131465U, // FABD_ZPmZ_H |
| 1647616U, // FABD_ZPmZ_S |
| 41287U, // FABDv2f32 |
| 8517U, // FABDv2f64 |
| 49480U, // FABDv4f16 |
| 16710U, // FABDv4f32 |
| 24902U, // FABDv8f16 |
| 1U, // FABSDr |
| 1U, // FABSHr |
| 1U, // FABSSr |
| 64U, // FABS_ZPmZ_D |
| 128U, // FABS_ZPmZ_H |
| 192U, // FABS_ZPmZ_S |
| 2U, // FABSv2f32 |
| 2U, // FABSv2f64 |
| 3U, // FABSv4f16 |
| 3U, // FABSv4f32 |
| 4U, // FABSv8f16 |
| 261U, // FACGE16 |
| 261U, // FACGE32 |
| 261U, // FACGE64 |
| 598922U, // FACGE_PPzZZ_D |
| 1131465U, // FACGE_PPzZZ_H |
| 1647626U, // FACGE_PPzZZ_S |
| 41287U, // FACGEv2f32 |
| 8517U, // FACGEv2f64 |
| 49480U, // FACGEv4f16 |
| 16710U, // FACGEv4f32 |
| 24902U, // FACGEv8f16 |
| 261U, // FACGT16 |
| 261U, // FACGT32 |
| 261U, // FACGT64 |
| 598922U, // FACGT_PPzZZ_D |
| 1131465U, // FACGT_PPzZZ_H |
| 1647626U, // FACGT_PPzZZ_S |
| 41287U, // FACGTv2f32 |
| 8517U, // FACGTv2f64 |
| 49480U, // FACGTv4f16 |
| 16710U, // FACGTv4f32 |
| 24902U, // FACGTv8f16 |
| 598277U, // FADDA_VPZ_D |
| 4268293U, // FADDA_VPZ_H |
| 1646853U, // FADDA_VPZ_S |
| 261U, // FADDDrr |
| 261U, // FADDHrr |
| 41287U, // FADDPv2f32 |
| 8517U, // FADDPv2f64 |
| 20U, // FADDPv2i16p |
| 2U, // FADDPv2i32p |
| 2U, // FADDPv2i64p |
| 49480U, // FADDPv4f16 |
| 16710U, // FADDPv4f32 |
| 24902U, // FADDPv8f16 |
| 261U, // FADDSrr |
| 901U, // FADDV_VPZ_D |
| 2245U, // FADDV_VPZ_H |
| 1029U, // FADDV_VPZ_S |
| 5317504U, // FADD_ZPmI_D |
| 140233U, // FADD_ZPmI_H |
| 5317632U, // FADD_ZPmI_S |
| 598912U, // FADD_ZPmZ_D |
| 1131465U, // FADD_ZPmZ_H |
| 1647616U, // FADD_ZPmZ_S |
| 901U, // FADD_ZZZ_D |
| 137U, // FADD_ZZZ_H |
| 1029U, // FADD_ZZZ_S |
| 41287U, // FADDv2f32 |
| 8517U, // FADDv2f64 |
| 49480U, // FADDv4f16 |
| 16710U, // FADDv4f32 |
| 24902U, // FADDv8f16 |
| 67707776U, // FCADD_ZPmZ_D |
| 106513353U, // FCADD_ZPmZ_H |
| 68756480U, // FCADD_ZPmZ_S |
| 6439239U, // FCADDv2f32 |
| 6447429U, // FCADDv2f64 |
| 6455624U, // FCADDv4f16 |
| 6463814U, // FCADDv4f32 |
| 6472006U, // FCADDv8f16 |
| 3744005U, // FCCMPDrr |
| 3744005U, // FCCMPEDrr |
| 3744005U, // FCCMPEHrr |
| 3744005U, // FCCMPESrr |
| 3744005U, // FCCMPHrr |
| 3744005U, // FCCMPSrr |
| 261U, // FCMEQ16 |
| 261U, // FCMEQ32 |
| 261U, // FCMEQ64 |
| 189322U, // FCMEQ_PPzZ0_D |
| 2825U, // FCMEQ_PPzZ0_H |
| 189450U, // FCMEQ_PPzZ0_S |
| 598922U, // FCMEQ_PPzZZ_D |
| 1131465U, // FCMEQ_PPzZZ_H |
| 1647626U, // FCMEQ_PPzZZ_S |
| 21U, // FCMEQv1i16rz |
| 21U, // FCMEQv1i32rz |
| 21U, // FCMEQv1i64rz |
| 41287U, // FCMEQv2f32 |
| 8517U, // FCMEQv2f64 |
| 21U, // FCMEQv2i32rz |
| 22U, // FCMEQv2i64rz |
| 49480U, // FCMEQv4f16 |
| 16710U, // FCMEQv4f32 |
| 22U, // FCMEQv4i16rz |
| 23U, // FCMEQv4i32rz |
| 24902U, // FCMEQv8f16 |
| 23U, // FCMEQv8i16rz |
| 261U, // FCMGE16 |
| 261U, // FCMGE32 |
| 261U, // FCMGE64 |
| 189322U, // FCMGE_PPzZ0_D |
| 2825U, // FCMGE_PPzZ0_H |
| 189450U, // FCMGE_PPzZ0_S |
| 598922U, // FCMGE_PPzZZ_D |
| 1131465U, // FCMGE_PPzZZ_H |
| 1647626U, // FCMGE_PPzZZ_S |
| 21U, // FCMGEv1i16rz |
| 21U, // FCMGEv1i32rz |
| 21U, // FCMGEv1i64rz |
| 41287U, // FCMGEv2f32 |
| 8517U, // FCMGEv2f64 |
| 21U, // FCMGEv2i32rz |
| 22U, // FCMGEv2i64rz |
| 49480U, // FCMGEv4f16 |
| 16710U, // FCMGEv4f32 |
| 22U, // FCMGEv4i16rz |
| 23U, // FCMGEv4i32rz |
| 24902U, // FCMGEv8f16 |
| 23U, // FCMGEv8i16rz |
| 261U, // FCMGT16 |
| 261U, // FCMGT32 |
| 261U, // FCMGT64 |
| 189322U, // FCMGT_PPzZ0_D |
| 2825U, // FCMGT_PPzZ0_H |
| 189450U, // FCMGT_PPzZ0_S |
| 598922U, // FCMGT_PPzZZ_D |
| 1131465U, // FCMGT_PPzZZ_H |
| 1647626U, // FCMGT_PPzZZ_S |
| 21U, // FCMGTv1i16rz |
| 21U, // FCMGTv1i32rz |
| 21U, // FCMGTv1i64rz |
| 41287U, // FCMGTv2f32 |
| 8517U, // FCMGTv2f64 |
| 21U, // FCMGTv2i32rz |
| 22U, // FCMGTv2i64rz |
| 49480U, // FCMGTv4f16 |
| 16710U, // FCMGTv4f32 |
| 22U, // FCMGTv4i16rz |
| 23U, // FCMGTv4i32rz |
| 24902U, // FCMGTv8f16 |
| 23U, // FCMGTv8i16rz |
| 342433856U, // FCMLA_ZPmZZ_D |
| 140182464U, // FCMLA_ZPmZZ_H |
| 342958272U, // FCMLA_ZPmZZ_S |
| 24U, // FCMLA_ZZZI_H |
| 7940952U, // FCMLA_ZZZI_S |
| 8536455U, // FCMLAv2f32 |
| 8544645U, // FCMLAv2f64 |
| 8552840U, // FCMLAv4f16 |
| 344662408U, // FCMLAv4f16_indexed |
| 8561030U, // FCMLAv4f32 |
| 344670598U, // FCMLAv4f32_indexed |
| 8569222U, // FCMLAv8f16 |
| 344662406U, // FCMLAv8f16_indexed |
| 189322U, // FCMLE_PPzZ0_D |
| 2825U, // FCMLE_PPzZ0_H |
| 189450U, // FCMLE_PPzZ0_S |
| 21U, // FCMLEv1i16rz |
| 21U, // FCMLEv1i32rz |
| 21U, // FCMLEv1i64rz |
| 21U, // FCMLEv2i32rz |
| 22U, // FCMLEv2i64rz |
| 22U, // FCMLEv4i16rz |
| 23U, // FCMLEv4i32rz |
| 23U, // FCMLEv8i16rz |
| 189322U, // FCMLT_PPzZ0_D |
| 2825U, // FCMLT_PPzZ0_H |
| 189450U, // FCMLT_PPzZ0_S |
| 21U, // FCMLTv1i16rz |
| 21U, // FCMLTv1i32rz |
| 21U, // FCMLTv1i64rz |
| 21U, // FCMLTv2i32rz |
| 22U, // FCMLTv2i64rz |
| 22U, // FCMLTv4i16rz |
| 23U, // FCMLTv4i32rz |
| 23U, // FCMLTv8i16rz |
| 189322U, // FCMNE_PPzZ0_D |
| 2825U, // FCMNE_PPzZ0_H |
| 189450U, // FCMNE_PPzZ0_S |
| 598922U, // FCMNE_PPzZZ_D |
| 1131465U, // FCMNE_PPzZZ_H |
| 1647626U, // FCMNE_PPzZZ_S |
| 0U, // FCMPDri |
| 1U, // FCMPDrr |
| 0U, // FCMPEDri |
| 1U, // FCMPEDrr |
| 0U, // FCMPEHri |
| 1U, // FCMPEHrr |
| 0U, // FCMPESri |
| 1U, // FCMPESrr |
| 0U, // FCMPHri |
| 1U, // FCMPHrr |
| 0U, // FCMPSri |
| 1U, // FCMPSrr |
| 598922U, // FCMUO_PPzZZ_D |
| 1131465U, // FCMUO_PPzZZ_H |
| 1647626U, // FCMUO_PPzZZ_S |
| 2944U, // FCPY_ZPmI_D |
| 25U, // FCPY_ZPmI_H |
| 2944U, // FCPY_ZPmI_S |
| 3744005U, // FCSELDrrr |
| 3744005U, // FCSELHrrr |
| 3744005U, // FCSELSrrr |
| 1U, // FCVTASUWDr |
| 1U, // FCVTASUWHr |
| 1U, // FCVTASUWSr |
| 1U, // FCVTASUXDr |
| 1U, // FCVTASUXHr |
| 1U, // FCVTASUXSr |
| 1U, // FCVTASv1f16 |
| 1U, // FCVTASv1i32 |
| 1U, // FCVTASv1i64 |
| 2U, // FCVTASv2f32 |
| 2U, // FCVTASv2f64 |
| 3U, // FCVTASv4f16 |
| 3U, // FCVTASv4f32 |
| 4U, // FCVTASv8f16 |
| 1U, // FCVTAUUWDr |
| 1U, // FCVTAUUWHr |
| 1U, // FCVTAUUWSr |
| 1U, // FCVTAUUXDr |
| 1U, // FCVTAUUXHr |
| 1U, // FCVTAUUXSr |
| 1U, // FCVTAUv1f16 |
| 1U, // FCVTAUv1i32 |
| 1U, // FCVTAUv1i64 |
| 2U, // FCVTAUv2f32 |
| 2U, // FCVTAUv2f64 |
| 3U, // FCVTAUv4f16 |
| 3U, // FCVTAUv4f32 |
| 4U, // FCVTAUv8f16 |
| 1U, // FCVTDHr |
| 1U, // FCVTDSr |
| 1U, // FCVTHDr |
| 1U, // FCVTHSr |
| 2U, // FCVTLv2i32 |
| 3U, // FCVTLv4i16 |
| 3U, // FCVTLv4i32 |
| 4U, // FCVTLv8i16 |
| 1U, // FCVTMSUWDr |
| 1U, // FCVTMSUWHr |
| 1U, // FCVTMSUWSr |
| 1U, // FCVTMSUXDr |
| 1U, // FCVTMSUXHr |
| 1U, // FCVTMSUXSr |
| 1U, // FCVTMSv1f16 |
| 1U, // FCVTMSv1i32 |
| 1U, // FCVTMSv1i64 |
| 2U, // FCVTMSv2f32 |
| 2U, // FCVTMSv2f64 |
| 3U, // FCVTMSv4f16 |
| 3U, // FCVTMSv4f32 |
| 4U, // FCVTMSv8f16 |
| 1U, // FCVTMUUWDr |
| 1U, // FCVTMUUWHr |
| 1U, // FCVTMUUWSr |
| 1U, // FCVTMUUXDr |
| 1U, // FCVTMUUXHr |
| 1U, // FCVTMUUXSr |
| 1U, // FCVTMUv1f16 |
| 1U, // FCVTMUv1i32 |
| 1U, // FCVTMUv1i64 |
| 2U, // FCVTMUv2f32 |
| 2U, // FCVTMUv2f64 |
| 3U, // FCVTMUv4f16 |
| 3U, // FCVTMUv4f32 |
| 4U, // FCVTMUv8f16 |
| 1U, // FCVTNSUWDr |
| 1U, // FCVTNSUWHr |
| 1U, // FCVTNSUWSr |
| 1U, // FCVTNSUXDr |
| 1U, // FCVTNSUXHr |
| 1U, // FCVTNSUXSr |
| 1U, // FCVTNSv1f16 |
| 1U, // FCVTNSv1i32 |
| 1U, // FCVTNSv1i64 |
| 2U, // FCVTNSv2f32 |
| 2U, // FCVTNSv2f64 |
| 3U, // FCVTNSv4f16 |
| 3U, // FCVTNSv4f32 |
| 4U, // FCVTNSv8f16 |
| 1U, // FCVTNUUWDr |
| 1U, // FCVTNUUWHr |
| 1U, // FCVTNUUWSr |
| 1U, // FCVTNUUXDr |
| 1U, // FCVTNUUXHr |
| 1U, // FCVTNUUXSr |
| 1U, // FCVTNUv1f16 |
| 1U, // FCVTNUv1i32 |
| 1U, // FCVTNUv1i64 |
| 2U, // FCVTNUv2f32 |
| 2U, // FCVTNUv2f64 |
| 3U, // FCVTNUv4f16 |
| 3U, // FCVTNUv4f32 |
| 4U, // FCVTNUv8f16 |
| 2U, // FCVTNv2i32 |
| 3U, // FCVTNv4i16 |
| 2U, // FCVTNv4i32 |
| 3U, // FCVTNv8i16 |
| 1U, // FCVTPSUWDr |
| 1U, // FCVTPSUWHr |
| 1U, // FCVTPSUWSr |
| 1U, // FCVTPSUXDr |
| 1U, // FCVTPSUXHr |
| 1U, // FCVTPSUXSr |
| 1U, // FCVTPSv1f16 |
| 1U, // FCVTPSv1i32 |
| 1U, // FCVTPSv1i64 |
| 2U, // FCVTPSv2f32 |
| 2U, // FCVTPSv2f64 |
| 3U, // FCVTPSv4f16 |
| 3U, // FCVTPSv4f32 |
| 4U, // FCVTPSv8f16 |
| 1U, // FCVTPUUWDr |
| 1U, // FCVTPUUWHr |
| 1U, // FCVTPUUWSr |
| 1U, // FCVTPUUXDr |
| 1U, // FCVTPUUXHr |
| 1U, // FCVTPUUXSr |
| 1U, // FCVTPUv1f16 |
| 1U, // FCVTPUv1i32 |
| 1U, // FCVTPUv1i64 |
| 2U, // FCVTPUv2f32 |
| 2U, // FCVTPUv2f64 |
| 3U, // FCVTPUv4f16 |
| 3U, // FCVTPUv4f32 |
| 4U, // FCVTPUv8f16 |
| 1U, // FCVTSDr |
| 1U, // FCVTSHr |
| 1U, // FCVTXNv1i64 |
| 2U, // FCVTXNv2f32 |
| 2U, // FCVTXNv4f32 |
| 261U, // FCVTZSSWDri |
| 261U, // FCVTZSSWHri |
| 261U, // FCVTZSSWSri |
| 261U, // FCVTZSSXDri |
| 261U, // FCVTZSSXHri |
| 261U, // FCVTZSSXSri |
| 1U, // FCVTZSUWDr |
| 1U, // FCVTZSUWHr |
| 1U, // FCVTZSUWSr |
| 1U, // FCVTZSUXDr |
| 1U, // FCVTZSUXHr |
| 1U, // FCVTZSUXSr |
| 64U, // FCVTZS_ZPmZ_DtoD |
| 64U, // FCVTZS_ZPmZ_DtoS |
| 3008U, // FCVTZS_ZPmZ_HtoD |
| 128U, // FCVTZS_ZPmZ_HtoH |
| 3008U, // FCVTZS_ZPmZ_HtoS |
| 192U, // FCVTZS_ZPmZ_StoD |
| 192U, // FCVTZS_ZPmZ_StoS |
| 261U, // FCVTZSd |
| 261U, // FCVTZSh |
| 261U, // FCVTZSs |
| 1U, // FCVTZSv1f16 |
| 1U, // FCVTZSv1i32 |
| 1U, // FCVTZSv1i64 |
| 2U, // FCVTZSv2f32 |
| 2U, // FCVTZSv2f64 |
| 263U, // FCVTZSv2i32_shift |
| 261U, // FCVTZSv2i64_shift |
| 3U, // FCVTZSv4f16 |
| 3U, // FCVTZSv4f32 |
| 264U, // FCVTZSv4i16_shift |
| 262U, // FCVTZSv4i32_shift |
| 4U, // FCVTZSv8f16 |
| 262U, // FCVTZSv8i16_shift |
| 261U, // FCVTZUSWDri |
| 261U, // FCVTZUSWHri |
| 261U, // FCVTZUSWSri |
| 261U, // FCVTZUSXDri |
| 261U, // FCVTZUSXHri |
| 261U, // FCVTZUSXSri |
| 1U, // FCVTZUUWDr |
| 1U, // FCVTZUUWHr |
| 1U, // FCVTZUUWSr |
| 1U, // FCVTZUUXDr |
| 1U, // FCVTZUUXHr |
| 1U, // FCVTZUUXSr |
| 64U, // FCVTZU_ZPmZ_DtoD |
| 64U, // FCVTZU_ZPmZ_DtoS |
| 3008U, // FCVTZU_ZPmZ_HtoD |
| 128U, // FCVTZU_ZPmZ_HtoH |
| 3008U, // FCVTZU_ZPmZ_HtoS |
| 192U, // FCVTZU_ZPmZ_StoD |
| 192U, // FCVTZU_ZPmZ_StoS |
| 261U, // FCVTZUd |
| 261U, // FCVTZUh |
| 261U, // FCVTZUs |
| 1U, // FCVTZUv1f16 |
| 1U, // FCVTZUv1i32 |
| 1U, // FCVTZUv1i64 |
| 2U, // FCVTZUv2f32 |
| 2U, // FCVTZUv2f64 |
| 263U, // FCVTZUv2i32_shift |
| 261U, // FCVTZUv2i64_shift |
| 3U, // FCVTZUv4f16 |
| 3U, // FCVTZUv4f32 |
| 264U, // FCVTZUv4i16_shift |
| 262U, // FCVTZUv4i32_shift |
| 4U, // FCVTZUv8f16 |
| 262U, // FCVTZUv8i16_shift |
| 153U, // FCVT_ZPmZ_DtoH |
| 64U, // FCVT_ZPmZ_DtoS |
| 3008U, // FCVT_ZPmZ_HtoD |
| 3008U, // FCVT_ZPmZ_HtoS |
| 192U, // FCVT_ZPmZ_StoD |
| 152U, // FCVT_ZPmZ_StoH |
| 261U, // FDIVDrr |
| 261U, // FDIVHrr |
| 598912U, // FDIVR_ZPmZ_D |
| 1131465U, // FDIVR_ZPmZ_H |
| 1647616U, // FDIVR_ZPmZ_S |
| 261U, // FDIVSrr |
| 598912U, // FDIV_ZPmZ_D |
| 1131465U, // FDIV_ZPmZ_H |
| 1647616U, // FDIV_ZPmZ_S |
| 41287U, // FDIVv2f32 |
| 8517U, // FDIVv2f64 |
| 49480U, // FDIVv4f16 |
| 16710U, // FDIVv4f32 |
| 24902U, // FDIVv8f16 |
| 0U, // FDUP_ZI_D |
| 0U, // FDUP_ZI_H |
| 0U, // FDUP_ZI_S |
| 1U, // FEXPA_ZZ_D |
| 0U, // FEXPA_ZZ_H |
| 1U, // FEXPA_ZZ_S |
| 1U, // FJCVTZS |
| 2171141U, // FMADDDrrr |
| 2171141U, // FMADDHrrr |
| 2171141U, // FMADDSrrr |
| 6889536U, // FMAD_ZPmZZ_D |
| 1246144U, // FMAD_ZPmZZ_H |
| 7413952U, // FMAD_ZPmZZ_S |
| 261U, // FMAXDrr |
| 261U, // FMAXHrr |
| 261U, // FMAXNMDrr |
| 261U, // FMAXNMHrr |
| 41287U, // FMAXNMPv2f32 |
| 8517U, // FMAXNMPv2f64 |
| 20U, // FMAXNMPv2i16p |
| 2U, // FMAXNMPv2i32p |
| 2U, // FMAXNMPv2i64p |
| 49480U, // FMAXNMPv4f16 |
| 16710U, // FMAXNMPv4f32 |
| 24902U, // FMAXNMPv8f16 |
| 261U, // FMAXNMSrr |
| 901U, // FMAXNMV_VPZ_D |
| 2245U, // FMAXNMV_VPZ_H |
| 1029U, // FMAXNMV_VPZ_S |
| 3U, // FMAXNMVv4i16v |
| 3U, // FMAXNMVv4i32v |
| 4U, // FMAXNMVv8i16v |
| 9511808U, // FMAXNM_ZPmI_D |
| 222153U, // FMAXNM_ZPmI_H |
| 9511936U, // FMAXNM_ZPmI_S |
| 598912U, // FMAXNM_ZPmZ_D |
| 1131465U, // FMAXNM_ZPmZ_H |
| 1647616U, // FMAXNM_ZPmZ_S |
| 41287U, // FMAXNMv2f32 |
| 8517U, // FMAXNMv2f64 |
| 49480U, // FMAXNMv4f16 |
| 16710U, // FMAXNMv4f32 |
| 24902U, // FMAXNMv8f16 |
| 41287U, // FMAXPv2f32 |
| 8517U, // FMAXPv2f64 |
| 20U, // FMAXPv2i16p |
| 2U, // FMAXPv2i32p |
| 2U, // FMAXPv2i64p |
| 49480U, // FMAXPv4f16 |
| 16710U, // FMAXPv4f32 |
| 24902U, // FMAXPv8f16 |
| 261U, // FMAXSrr |
| 901U, // FMAXV_VPZ_D |
| 2245U, // FMAXV_VPZ_H |
| 1029U, // FMAXV_VPZ_S |
| 3U, // FMAXVv4i16v |
| 3U, // FMAXVv4i32v |
| 4U, // FMAXVv8i16v |
| 9511808U, // FMAX_ZPmI_D |
| 222153U, // FMAX_ZPmI_H |
| 9511936U, // FMAX_ZPmI_S |
| 598912U, // FMAX_ZPmZ_D |
| 1131465U, // FMAX_ZPmZ_H |
| 1647616U, // FMAX_ZPmZ_S |
| 41287U, // FMAXv2f32 |
| 8517U, // FMAXv2f64 |
| 49480U, // FMAXv4f16 |
| 16710U, // FMAXv4f32 |
| 24902U, // FMAXv8f16 |
| 261U, // FMINDrr |
| 261U, // FMINHrr |
| 261U, // FMINNMDrr |
| 261U, // FMINNMHrr |
| 41287U, // FMINNMPv2f32 |
| 8517U, // FMINNMPv2f64 |
| 20U, // FMINNMPv2i16p |
| 2U, // FMINNMPv2i32p |
| 2U, // FMINNMPv2i64p |
| 49480U, // FMINNMPv4f16 |
| 16710U, // FMINNMPv4f32 |
| 24902U, // FMINNMPv8f16 |
| 261U, // FMINNMSrr |
| 901U, // FMINNMV_VPZ_D |
| 2245U, // FMINNMV_VPZ_H |
| 1029U, // FMINNMV_VPZ_S |
| 3U, // FMINNMVv4i16v |
| 3U, // FMINNMVv4i32v |
| 4U, // FMINNMVv8i16v |
| 9511808U, // FMINNM_ZPmI_D |
| 222153U, // FMINNM_ZPmI_H |
| 9511936U, // FMINNM_ZPmI_S |
| 598912U, // FMINNM_ZPmZ_D |
| 1131465U, // FMINNM_ZPmZ_H |
| 1647616U, // FMINNM_ZPmZ_S |
| 41287U, // FMINNMv2f32 |
| 8517U, // FMINNMv2f64 |
| 49480U, // FMINNMv4f16 |
| 16710U, // FMINNMv4f32 |
| 24902U, // FMINNMv8f16 |
| 41287U, // FMINPv2f32 |
| 8517U, // FMINPv2f64 |
| 20U, // FMINPv2i16p |
| 2U, // FMINPv2i32p |
| 2U, // FMINPv2i64p |
| 49480U, // FMINPv4f16 |
| 16710U, // FMINPv4f32 |
| 24902U, // FMINPv8f16 |
| 261U, // FMINSrr |
| 901U, // FMINV_VPZ_D |
| 2245U, // FMINV_VPZ_H |
| 1029U, // FMINV_VPZ_S |
| 3U, // FMINVv4i16v |
| 3U, // FMINVv4i32v |
| 4U, // FMINVv8i16v |
| 9511808U, // FMIN_ZPmI_D |
| 222153U, // FMIN_ZPmI_H |
| 9511936U, // FMIN_ZPmI_S |
| 598912U, // FMIN_ZPmZ_D |
| 1131465U, // FMIN_ZPmZ_H |
| 1647616U, // FMIN_ZPmZ_S |
| 41287U, // FMINv2f32 |
| 8517U, // FMINv2f64 |
| 49480U, // FMINv4f16 |
| 16710U, // FMINv4f32 |
| 24902U, // FMINv8f16 |
| 6889536U, // FMLA_ZPmZZ_D |
| 1246144U, // FMLA_ZPmZZ_H |
| 7413952U, // FMLA_ZPmZZ_S |
| 2905U, // FMLA_ZZZI_D |
| 0U, // FMLA_ZZZI_H |
| 2904U, // FMLA_ZZZI_S |
| 9118085U, // FMLAv1i16_indexed |
| 9126277U, // FMLAv1i32_indexed |
| 9142661U, // FMLAv1i64_indexed |
| 41351U, // FMLAv2f32 |
| 8581U, // FMLAv2f64 |
| 9126279U, // FMLAv2i32_indexed |
| 9142661U, // FMLAv2i64_indexed |
| 49544U, // FMLAv4f16 |
| 16774U, // FMLAv4f32 |
| 9118088U, // FMLAv4i16_indexed |
| 9126278U, // FMLAv4i32_indexed |
| 24966U, // FMLAv8f16 |
| 9118086U, // FMLAv8i16_indexed |
| 6889536U, // FMLS_ZPmZZ_D |
| 1246144U, // FMLS_ZPmZZ_H |
| 7413952U, // FMLS_ZPmZZ_S |
| 2905U, // FMLS_ZZZI_D |
| 0U, // FMLS_ZZZI_H |
| 2904U, // FMLS_ZZZI_S |
| 9118085U, // FMLSv1i16_indexed |
| 9126277U, // FMLSv1i32_indexed |
| 9142661U, // FMLSv1i64_indexed |
| 41351U, // FMLSv2f32 |
| 8581U, // FMLSv2f64 |
| 9126279U, // FMLSv2i32_indexed |
| 9142661U, // FMLSv2i64_indexed |
| 49544U, // FMLSv4f16 |
| 16774U, // FMLSv4f32 |
| 9118088U, // FMLSv4i16_indexed |
| 9126278U, // FMLSv4i32_indexed |
| 24966U, // FMLSv8f16 |
| 9118086U, // FMLSv8i16_indexed |
| 0U, // FMOVD0 |
| 2771U, // FMOVDXHighr |
| 1U, // FMOVDXr |
| 0U, // FMOVDi |
| 1U, // FMOVDr |
| 0U, // FMOVH0 |
| 1U, // FMOVHWr |
| 1U, // FMOVHXr |
| 0U, // FMOVHi |
| 1U, // FMOVHr |
| 0U, // FMOVS0 |
| 1U, // FMOVSWr |
| 0U, // FMOVSi |
| 1U, // FMOVSr |
| 1U, // FMOVWHr |
| 1U, // FMOVWSr |
| 1U, // FMOVXDHighr |
| 1U, // FMOVXDr |
| 1U, // FMOVXHr |
| 0U, // FMOVv2f32_ns |
| 0U, // FMOVv2f64_ns |
| 0U, // FMOVv4f16_ns |
| 0U, // FMOVv4f32_ns |
| 0U, // FMOVv8f16_ns |
| 6889536U, // FMSB_ZPmZZ_D |
| 1246144U, // FMSB_ZPmZZ_H |
| 7413952U, // FMSB_ZPmZZ_S |
| 2171141U, // FMSUBDrrr |
| 2171141U, // FMSUBHrrr |
| 2171141U, // FMSUBSrrr |
| 261U, // FMULDrr |
| 261U, // FMULHrr |
| 261U, // FMULSrr |
| 261U, // FMULX16 |
| 261U, // FMULX32 |
| 261U, // FMULX64 |
| 598912U, // FMULX_ZPmZ_D |
| 1131465U, // FMULX_ZPmZ_H |
| 1647616U, // FMULX_ZPmZ_S |
| 10166597U, // FMULXv1i16_indexed |
| 10174789U, // FMULXv1i32_indexed |
| 10191173U, // FMULXv1i64_indexed |
| 41287U, // FMULXv2f32 |
| 8517U, // FMULXv2f64 |
| 10174791U, // FMULXv2i32_indexed |
| 10191173U, // FMULXv2i64_indexed |
| 49480U, // FMULXv4f16 |
| 16710U, // FMULXv4f32 |
| 10166600U, // FMULXv4i16_indexed |
| 10174790U, // FMULXv4i32_indexed |
| 24902U, // FMULXv8f16 |
| 10166598U, // FMULXv8i16_indexed |
| 10560384U, // FMUL_ZPmI_D |
| 238537U, // FMUL_ZPmI_H |
| 10560512U, // FMUL_ZPmI_S |
| 598912U, // FMUL_ZPmZ_D |
| 1131465U, // FMUL_ZPmZ_H |
| 1647616U, // FMUL_ZPmZ_S |
| 246661U, // FMUL_ZZZI_D |
| 3081U, // FMUL_ZZZI_H |
| 246789U, // FMUL_ZZZI_S |
| 901U, // FMUL_ZZZ_D |
| 137U, // FMUL_ZZZ_H |
| 1029U, // FMUL_ZZZ_S |
| 10166597U, // FMULv1i16_indexed |
| 10174789U, // FMULv1i32_indexed |
| 10191173U, // FMULv1i64_indexed |
| 41287U, // FMULv2f32 |
| 8517U, // FMULv2f64 |
| 10174791U, // FMULv2i32_indexed |
| 10191173U, // FMULv2i64_indexed |
| 49480U, // FMULv4f16 |
| 16710U, // FMULv4f32 |
| 10166600U, // FMULv4i16_indexed |
| 10174790U, // FMULv4i32_indexed |
| 24902U, // FMULv8f16 |
| 10166598U, // FMULv8i16_indexed |
| 1U, // FNEGDr |
| 1U, // FNEGHr |
| 1U, // FNEGSr |
| 64U, // FNEG_ZPmZ_D |
| 128U, // FNEG_ZPmZ_H |
| 192U, // FNEG_ZPmZ_S |
| 2U, // FNEGv2f32 |
| 2U, // FNEGv2f64 |
| 3U, // FNEGv4f16 |
| 3U, // FNEGv4f32 |
| 4U, // FNEGv8f16 |
| 2171141U, // FNMADDDrrr |
| 2171141U, // FNMADDHrrr |
| 2171141U, // FNMADDSrrr |
| 6889536U, // FNMAD_ZPmZZ_D |
| 1246144U, // FNMAD_ZPmZZ_H |
| 7413952U, // FNMAD_ZPmZZ_S |
| 6889536U, // FNMLA_ZPmZZ_D |
| 1246144U, // FNMLA_ZPmZZ_H |
| 7413952U, // FNMLA_ZPmZZ_S |
| 6889536U, // FNMLS_ZPmZZ_D |
| 1246144U, // FNMLS_ZPmZZ_H |
| 7413952U, // FNMLS_ZPmZZ_S |
| 6889536U, // FNMSB_ZPmZZ_D |
| 1246144U, // FNMSB_ZPmZZ_H |
| 7413952U, // FNMSB_ZPmZZ_S |
| 2171141U, // FNMSUBDrrr |
| 2171141U, // FNMSUBHrrr |
| 2171141U, // FNMSUBSrrr |
| 261U, // FNMULDrr |
| 261U, // FNMULHrr |
| 261U, // FNMULSrr |
| 1U, // FRECPE_ZZ_D |
| 0U, // FRECPE_ZZ_H |
| 1U, // FRECPE_ZZ_S |
| 1U, // FRECPEv1f16 |
| 1U, // FRECPEv1i32 |
| 1U, // FRECPEv1i64 |
| 2U, // FRECPEv2f32 |
| 2U, // FRECPEv2f64 |
| 3U, // FRECPEv4f16 |
| 3U, // FRECPEv4f32 |
| 4U, // FRECPEv8f16 |
| 261U, // FRECPS16 |
| 261U, // FRECPS32 |
| 261U, // FRECPS64 |
| 901U, // FRECPS_ZZZ_D |
| 137U, // FRECPS_ZZZ_H |
| 1029U, // FRECPS_ZZZ_S |
| 41287U, // FRECPSv2f32 |
| 8517U, // FRECPSv2f64 |
| 49480U, // FRECPSv4f16 |
| 16710U, // FRECPSv4f32 |
| 24902U, // FRECPSv8f16 |
| 64U, // FRECPX_ZPmZ_D |
| 128U, // FRECPX_ZPmZ_H |
| 192U, // FRECPX_ZPmZ_S |
| 1U, // FRECPXv1f16 |
| 1U, // FRECPXv1i32 |
| 1U, // FRECPXv1i64 |
| 1U, // FRINTADr |
| 1U, // FRINTAHr |
| 1U, // FRINTASr |
| 64U, // FRINTA_ZPmZ_D |
| 128U, // FRINTA_ZPmZ_H |
| 192U, // FRINTA_ZPmZ_S |
| 2U, // FRINTAv2f32 |
| 2U, // FRINTAv2f64 |
| 3U, // FRINTAv4f16 |
| 3U, // FRINTAv4f32 |
| 4U, // FRINTAv8f16 |
| 1U, // FRINTIDr |
| 1U, // FRINTIHr |
| 1U, // FRINTISr |
| 64U, // FRINTI_ZPmZ_D |
| 128U, // FRINTI_ZPmZ_H |
| 192U, // FRINTI_ZPmZ_S |
| 2U, // FRINTIv2f32 |
| 2U, // FRINTIv2f64 |
| 3U, // FRINTIv4f16 |
| 3U, // FRINTIv4f32 |
| 4U, // FRINTIv8f16 |
| 1U, // FRINTMDr |
| 1U, // FRINTMHr |
| 1U, // FRINTMSr |
| 64U, // FRINTM_ZPmZ_D |
| 128U, // FRINTM_ZPmZ_H |
| 192U, // FRINTM_ZPmZ_S |
| 2U, // FRINTMv2f32 |
| 2U, // FRINTMv2f64 |
| 3U, // FRINTMv4f16 |
| 3U, // FRINTMv4f32 |
| 4U, // FRINTMv8f16 |
| 1U, // FRINTNDr |
| 1U, // FRINTNHr |
| 1U, // FRINTNSr |
| 64U, // FRINTN_ZPmZ_D |
| 128U, // FRINTN_ZPmZ_H |
| 192U, // FRINTN_ZPmZ_S |
| 2U, // FRINTNv2f32 |
| 2U, // FRINTNv2f64 |
| 3U, // FRINTNv4f16 |
| 3U, // FRINTNv4f32 |
| 4U, // FRINTNv8f16 |
| 1U, // FRINTPDr |
| 1U, // FRINTPHr |
| 1U, // FRINTPSr |
| 64U, // FRINTP_ZPmZ_D |
| 128U, // FRINTP_ZPmZ_H |
| 192U, // FRINTP_ZPmZ_S |
| 2U, // FRINTPv2f32 |
| 2U, // FRINTPv2f64 |
| 3U, // FRINTPv4f16 |
| 3U, // FRINTPv4f32 |
| 4U, // FRINTPv8f16 |
| 1U, // FRINTXDr |
| 1U, // FRINTXHr |
| 1U, // FRINTXSr |
| 64U, // FRINTX_ZPmZ_D |
| 128U, // FRINTX_ZPmZ_H |
| 192U, // FRINTX_ZPmZ_S |
| 2U, // FRINTXv2f32 |
| 2U, // FRINTXv2f64 |
| 3U, // FRINTXv4f16 |
| 3U, // FRINTXv4f32 |
| 4U, // FRINTXv8f16 |
| 1U, // FRINTZDr |
| 1U, // FRINTZHr |
| 1U, // FRINTZSr |
| 64U, // FRINTZ_ZPmZ_D |
| 128U, // FRINTZ_ZPmZ_H |
| 192U, // FRINTZ_ZPmZ_S |
| 2U, // FRINTZv2f32 |
| 2U, // FRINTZv2f64 |
| 3U, // FRINTZv4f16 |
| 3U, // FRINTZv4f32 |
| 4U, // FRINTZv8f16 |
| 1U, // FRSQRTE_ZZ_D |
| 0U, // FRSQRTE_ZZ_H |
| 1U, // FRSQRTE_ZZ_S |
| 1U, // FRSQRTEv1f16 |
| 1U, // FRSQRTEv1i32 |
| 1U, // FRSQRTEv1i64 |
| 2U, // FRSQRTEv2f32 |
| 2U, // FRSQRTEv2f64 |
| 3U, // FRSQRTEv4f16 |
| 3U, // FRSQRTEv4f32 |
| 4U, // FRSQRTEv8f16 |
| 261U, // FRSQRTS16 |
| 261U, // FRSQRTS32 |
| 261U, // FRSQRTS64 |
| 901U, // FRSQRTS_ZZZ_D |
| 137U, // FRSQRTS_ZZZ_H |
| 1029U, // FRSQRTS_ZZZ_S |
| 41287U, // FRSQRTSv2f32 |
| 8517U, // FRSQRTSv2f64 |
| 49480U, // FRSQRTSv4f16 |
| 16710U, // FRSQRTSv4f32 |
| 24902U, // FRSQRTSv8f16 |
| 598912U, // FSCALE_ZPmZ_D |
| 1131465U, // FSCALE_ZPmZ_H |
| 1647616U, // FSCALE_ZPmZ_S |
| 1U, // FSQRTDr |
| 1U, // FSQRTHr |
| 1U, // FSQRTSr |
| 64U, // FSQRT_ZPmZ_D |
| 128U, // FSQRT_ZPmZ_H |
| 192U, // FSQRT_ZPmZ_S |
| 2U, // FSQRTv2f32 |
| 2U, // FSQRTv2f64 |
| 3U, // FSQRTv4f16 |
| 3U, // FSQRTv4f32 |
| 4U, // FSQRTv8f16 |
| 261U, // FSUBDrr |
| 261U, // FSUBHrr |
| 5317504U, // FSUBR_ZPmI_D |
| 140233U, // FSUBR_ZPmI_H |
| 5317632U, // FSUBR_ZPmI_S |
| 598912U, // FSUBR_ZPmZ_D |
| 1131465U, // FSUBR_ZPmZ_H |
| 1647616U, // FSUBR_ZPmZ_S |
| 261U, // FSUBSrr |
| 5317504U, // FSUB_ZPmI_D |
| 140233U, // FSUB_ZPmI_H |
| 5317632U, // FSUB_ZPmI_S |
| 598912U, // FSUB_ZPmZ_D |
| 1131465U, // FSUB_ZPmZ_H |
| 1647616U, // FSUB_ZPmZ_S |
| 901U, // FSUB_ZZZ_D |
| 137U, // FSUB_ZZZ_H |
| 1029U, // FSUB_ZZZ_S |
| 41287U, // FSUBv2f32 |
| 8517U, // FSUBv2f64 |
| 49480U, // FSUBv4f16 |
| 16710U, // FSUBv4f32 |
| 24902U, // FSUBv8f16 |
| 2171781U, // FTMAD_ZZI_D |
| 91081U, // FTMAD_ZZI_H |
| 2171909U, // FTMAD_ZZI_S |
| 901U, // FTSMUL_ZZZ_D |
| 137U, // FTSMUL_ZZZ_H |
| 1029U, // FTSMUL_ZZZ_S |
| 901U, // FTSSEL_ZZZ_D |
| 137U, // FTSSEL_ZZZ_H |
| 1029U, // FTSSEL_ZZZ_S |
| 3153U, // GLD1B_D_IMM_REAL |
| 3205U, // GLD1B_D_REAL |
| 3269U, // GLD1B_D_SXTW_REAL |
| 3333U, // GLD1B_D_UXTW_REAL |
| 3153U, // GLD1B_S_IMM_REAL |
| 3397U, // GLD1B_S_SXTW_REAL |
| 3461U, // GLD1B_S_UXTW_REAL |
| 26U, // GLD1D_IMM_REAL |
| 3205U, // GLD1D_REAL |
| 3525U, // GLD1D_SCALED_REAL |
| 3269U, // GLD1D_SXTW_REAL |
| 3589U, // GLD1D_SXTW_SCALED_REAL |
| 3333U, // GLD1D_UXTW_REAL |
| 3653U, // GLD1D_UXTW_SCALED_REAL |
| 26U, // GLD1H_D_IMM_REAL |
| 3205U, // GLD1H_D_REAL |
| 3717U, // GLD1H_D_SCALED_REAL |
| 3269U, // GLD1H_D_SXTW_REAL |
| 3781U, // GLD1H_D_SXTW_SCALED_REAL |
| 3333U, // GLD1H_D_UXTW_REAL |
| 3845U, // GLD1H_D_UXTW_SCALED_REAL |
| 26U, // GLD1H_S_IMM_REAL |
| 3397U, // GLD1H_S_SXTW_REAL |
| 3909U, // GLD1H_S_SXTW_SCALED_REAL |
| 3461U, // GLD1H_S_UXTW_REAL |
| 3973U, // GLD1H_S_UXTW_SCALED_REAL |
| 3153U, // GLD1SB_D_IMM_REAL |
| 3205U, // GLD1SB_D_REAL |
| 3269U, // GLD1SB_D_SXTW_REAL |
| 3333U, // GLD1SB_D_UXTW_REAL |
| 3153U, // GLD1SB_S_IMM_REAL |
| 3397U, // GLD1SB_S_SXTW_REAL |
| 3461U, // GLD1SB_S_UXTW_REAL |
| 26U, // GLD1SH_D_IMM_REAL |
| 3205U, // GLD1SH_D_REAL |
| 3717U, // GLD1SH_D_SCALED_REAL |
| 3269U, // GLD1SH_D_SXTW_REAL |
| 3781U, // GLD1SH_D_SXTW_SCALED_REAL |
| 3333U, // GLD1SH_D_UXTW_REAL |
| 3845U, // GLD1SH_D_UXTW_SCALED_REAL |
| 26U, // GLD1SH_S_IMM_REAL |
| 3397U, // GLD1SH_S_SXTW_REAL |
| 3909U, // GLD1SH_S_SXTW_SCALED_REAL |
| 3461U, // GLD1SH_S_UXTW_REAL |
| 3973U, // GLD1SH_S_UXTW_SCALED_REAL |
| 27U, // GLD1SW_D_IMM_REAL |
| 3205U, // GLD1SW_D_REAL |
| 4037U, // GLD1SW_D_SCALED_REAL |
| 3269U, // GLD1SW_D_SXTW_REAL |
| 4101U, // GLD1SW_D_SXTW_SCALED_REAL |
| 3333U, // GLD1SW_D_UXTW_REAL |
| 4165U, // GLD1SW_D_UXTW_SCALED_REAL |
| 27U, // GLD1W_D_IMM_REAL |
| 3205U, // GLD1W_D_REAL |
| 4037U, // GLD1W_D_SCALED_REAL |
| 3269U, // GLD1W_D_SXTW_REAL |
| 4101U, // GLD1W_D_SXTW_SCALED_REAL |
| 3333U, // GLD1W_D_UXTW_REAL |
| 4165U, // GLD1W_D_UXTW_SCALED_REAL |
| 27U, // GLD1W_IMM_REAL |
| 3397U, // GLD1W_SXTW_REAL |
| 4229U, // GLD1W_SXTW_SCALED_REAL |
| 3461U, // GLD1W_UXTW_REAL |
| 4293U, // GLD1W_UXTW_SCALED_REAL |
| 3153U, // GLDFF1B_D_IMM_REAL |
| 3205U, // GLDFF1B_D_REAL |
| 3269U, // GLDFF1B_D_SXTW_REAL |
| 3333U, // GLDFF1B_D_UXTW_REAL |
| 3153U, // GLDFF1B_S_IMM_REAL |
| 3397U, // GLDFF1B_S_SXTW_REAL |
| 3461U, // GLDFF1B_S_UXTW_REAL |
| 26U, // GLDFF1D_IMM_REAL |
| 3205U, // GLDFF1D_REAL |
| 3525U, // GLDFF1D_SCALED_REAL |
| 3269U, // GLDFF1D_SXTW_REAL |
| 3589U, // GLDFF1D_SXTW_SCALED_REAL |
| 3333U, // GLDFF1D_UXTW_REAL |
| 3653U, // GLDFF1D_UXTW_SCALED_REAL |
| 26U, // GLDFF1H_D_IMM_REAL |
| 3205U, // GLDFF1H_D_REAL |
| 3717U, // GLDFF1H_D_SCALED_REAL |
| 3269U, // GLDFF1H_D_SXTW_REAL |
| 3781U, // GLDFF1H_D_SXTW_SCALED_REAL |
| 3333U, // GLDFF1H_D_UXTW_REAL |
| 3845U, // GLDFF1H_D_UXTW_SCALED_REAL |
| 26U, // GLDFF1H_S_IMM_REAL |
| 3397U, // GLDFF1H_S_SXTW_REAL |
| 3909U, // GLDFF1H_S_SXTW_SCALED_REAL |
| 3461U, // GLDFF1H_S_UXTW_REAL |
| 3973U, // GLDFF1H_S_UXTW_SCALED_REAL |
| 3153U, // GLDFF1SB_D_IMM_REAL |
| 3205U, // GLDFF1SB_D_REAL |
| 3269U, // GLDFF1SB_D_SXTW_REAL |
| 3333U, // GLDFF1SB_D_UXTW_REAL |
| 3153U, // GLDFF1SB_S_IMM_REAL |
| 3397U, // GLDFF1SB_S_SXTW_REAL |
| 3461U, // GLDFF1SB_S_UXTW_REAL |
| 26U, // GLDFF1SH_D_IMM_REAL |
| 3205U, // GLDFF1SH_D_REAL |
| 3717U, // GLDFF1SH_D_SCALED_REAL |
| 3269U, // GLDFF1SH_D_SXTW_REAL |
| 3781U, // GLDFF1SH_D_SXTW_SCALED_REAL |
| 3333U, // GLDFF1SH_D_UXTW_REAL |
| 3845U, // GLDFF1SH_D_UXTW_SCALED_REAL |
| 26U, // GLDFF1SH_S_IMM_REAL |
| 3397U, // GLDFF1SH_S_SXTW_REAL |
| 3909U, // GLDFF1SH_S_SXTW_SCALED_REAL |
| 3461U, // GLDFF1SH_S_UXTW_REAL |
| 3973U, // GLDFF1SH_S_UXTW_SCALED_REAL |
| 27U, // GLDFF1SW_D_IMM_REAL |
| 3205U, // GLDFF1SW_D_REAL |
| 4037U, // GLDFF1SW_D_SCALED_REAL |
| 3269U, // GLDFF1SW_D_SXTW_REAL |
| 4101U, // GLDFF1SW_D_SXTW_SCALED_REAL |
| 3333U, // GLDFF1SW_D_UXTW_REAL |
| 4165U, // GLDFF1SW_D_UXTW_SCALED_REAL |
| 27U, // GLDFF1W_D_IMM_REAL |
| 3205U, // GLDFF1W_D_REAL |
| 4037U, // GLDFF1W_D_SCALED_REAL |
| 3269U, // GLDFF1W_D_SXTW_REAL |
| 4101U, // GLDFF1W_D_SXTW_SCALED_REAL |
| 3333U, // GLDFF1W_D_UXTW_REAL |
| 4165U, // GLDFF1W_D_UXTW_SCALED_REAL |
| 27U, // GLDFF1W_IMM_REAL |
| 3397U, // GLDFF1W_SXTW_REAL |
| 4229U, // GLDFF1W_SXTW_SCALED_REAL |
| 3461U, // GLDFF1W_UXTW_REAL |
| 4293U, // GLDFF1W_UXTW_SCALED_REAL |
| 0U, // HINT |
| 0U, // HLT |
| 0U, // HVC |
| 0U, // INCB_XPiI |
| 0U, // INCD_XPiI |
| 0U, // INCD_ZPiI |
| 0U, // INCH_XPiI |
| 0U, // INCH_ZPiI |
| 1U, // INCP_XP_B |
| 1U, // INCP_XP_D |
| 1U, // INCP_XP_H |
| 1U, // INCP_XP_S |
| 1U, // INCP_ZP_D |
| 0U, // INCP_ZP_H |
| 1U, // INCP_ZP_S |
| 0U, // INCW_XPiI |
| 0U, // INCW_ZPiI |
| 261U, // INDEX_II_B |
| 261U, // INDEX_II_D |
| 11U, // INDEX_II_H |
| 261U, // INDEX_II_S |
| 261U, // INDEX_IR_B |
| 261U, // INDEX_IR_D |
| 11U, // INDEX_IR_H |
| 261U, // INDEX_IR_S |
| 261U, // INDEX_RI_B |
| 261U, // INDEX_RI_D |
| 11U, // INDEX_RI_H |
| 261U, // INDEX_RI_S |
| 261U, // INDEX_RR_B |
| 261U, // INDEX_RR_D |
| 11U, // INDEX_RR_H |
| 261U, // INDEX_RR_S |
| 1U, // INSR_ZR_B |
| 1U, // INSR_ZR_D |
| 0U, // INSR_ZR_H |
| 1U, // INSR_ZR_S |
| 1U, // INSR_ZV_B |
| 1U, // INSR_ZV_D |
| 0U, // INSR_ZV_H |
| 1U, // INSR_ZV_S |
| 1U, // INSvi16gpr |
| 2898U, // INSvi16lane |
| 1U, // INSvi32gpr |
| 2898U, // INSvi32lane |
| 1U, // INSvi64gpr |
| 2899U, // INSvi64lane |
| 1U, // INSvi8gpr |
| 2899U, // INSvi8lane |
| 0U, // ISB |
| 837U, // LASTA_RPZ_B |
| 901U, // LASTA_RPZ_D |
| 2245U, // LASTA_RPZ_H |
| 1029U, // LASTA_RPZ_S |
| 837U, // LASTA_VPZ_B |
| 901U, // LASTA_VPZ_D |
| 2245U, // LASTA_VPZ_H |
| 1029U, // LASTA_VPZ_S |
| 837U, // LASTB_RPZ_B |
| 901U, // LASTB_RPZ_D |
| 2245U, // LASTB_RPZ_H |
| 1029U, // LASTB_RPZ_S |
| 837U, // LASTB_VPZ_B |
| 901U, // LASTB_VPZ_D |
| 2245U, // LASTB_VPZ_H |
| 1029U, // LASTB_VPZ_S |
| 4357U, // LD1B |
| 4357U, // LD1B_D |
| 256261U, // LD1B_D_IMM_REAL |
| 4357U, // LD1B_H |
| 256261U, // LD1B_H_IMM_REAL |
| 256261U, // LD1B_IMM_REAL |
| 4357U, // LD1B_S |
| 256261U, // LD1B_S_IMM_REAL |
| 4421U, // LD1D |
| 256261U, // LD1D_IMM_REAL |
| 0U, // LD1Fourv16b |
| 0U, // LD1Fourv16b_POST |
| 0U, // LD1Fourv1d |
| 0U, // LD1Fourv1d_POST |
| 0U, // LD1Fourv2d |
| 0U, // LD1Fourv2d_POST |
| 0U, // LD1Fourv2s |
| 0U, // LD1Fourv2s_POST |
| 0U, // LD1Fourv4h |
| 0U, // LD1Fourv4h_POST |
| 0U, // LD1Fourv4s |
| 0U, // LD1Fourv4s_POST |
| 0U, // LD1Fourv8b |
| 0U, // LD1Fourv8b_POST |
| 0U, // LD1Fourv8h |
| 0U, // LD1Fourv8h_POST |
| 4485U, // LD1H |
| 4485U, // LD1H_D |
| 256261U, // LD1H_D_IMM_REAL |
| 256261U, // LD1H_IMM_REAL |
| 4485U, // LD1H_S |
| 256261U, // LD1H_S_IMM_REAL |
| 0U, // LD1Onev16b |
| 0U, // LD1Onev16b_POST |
| 0U, // LD1Onev1d |
| 0U, // LD1Onev1d_POST |
| 0U, // LD1Onev2d |
| 0U, // LD1Onev2d_POST |
| 0U, // LD1Onev2s |
| 0U, // LD1Onev2s_POST |
| 0U, // LD1Onev4h |
| 0U, // LD1Onev4h_POST |
| 0U, // LD1Onev4s |
| 0U, // LD1Onev4s_POST |
| 0U, // LD1Onev8b |
| 0U, // LD1Onev8b_POST |
| 0U, // LD1Onev8h |
| 0U, // LD1Onev8h_POST |
| 116997U, // LD1RB_D_IMM |
| 116997U, // LD1RB_H_IMM |
| 116997U, // LD1RB_IMM |
| 116997U, // LD1RB_S_IMM |
| 119237U, // LD1RD_IMM |
| 119301U, // LD1RH_D_IMM |
| 119301U, // LD1RH_IMM |
| 119301U, // LD1RH_S_IMM |
| 4357U, // LD1RQ_B |
| 4677U, // LD1RQ_B_IMM |
| 4421U, // LD1RQ_D |
| 4677U, // LD1RQ_D_IMM |
| 4485U, // LD1RQ_H |
| 4677U, // LD1RQ_H_IMM |
| 4741U, // LD1RQ_W |
| 4677U, // LD1RQ_W_IMM |
| 116997U, // LD1RSB_D_IMM |
| 116997U, // LD1RSB_H_IMM |
| 116997U, // LD1RSB_S_IMM |
| 119301U, // LD1RSH_D_IMM |
| 119301U, // LD1RSH_S_IMM |
| 119493U, // LD1RSW_IMM |
| 119493U, // LD1RW_D_IMM |
| 119493U, // LD1RW_IMM |
| 0U, // LD1Rv16b |
| 0U, // LD1Rv16b_POST |
| 0U, // LD1Rv1d |
| 0U, // LD1Rv1d_POST |
| 0U, // LD1Rv2d |
| 0U, // LD1Rv2d_POST |
| 0U, // LD1Rv2s |
| 0U, // LD1Rv2s_POST |
| 0U, // LD1Rv4h |
| 0U, // LD1Rv4h_POST |
| 0U, // LD1Rv4s |
| 0U, // LD1Rv4s_POST |
| 0U, // LD1Rv8b |
| 0U, // LD1Rv8b_POST |
| 0U, // LD1Rv8h |
| 0U, // LD1Rv8h_POST |
| 4357U, // LD1SB_D |
| 256261U, // LD1SB_D_IMM_REAL |
| 4357U, // LD1SB_H |
| 256261U, // LD1SB_H_IMM_REAL |
| 4357U, // LD1SB_S |
| 256261U, // LD1SB_S_IMM_REAL |
| 4485U, // LD1SH_D |
| 256261U, // LD1SH_D_IMM_REAL |
| 4485U, // LD1SH_S |
| 256261U, // LD1SH_S_IMM_REAL |
| 4741U, // LD1SW_D |
| 256261U, // LD1SW_D_IMM_REAL |
| 0U, // LD1Threev16b |
| 0U, // LD1Threev16b_POST |
| 0U, // LD1Threev1d |
| 0U, // LD1Threev1d_POST |
| 0U, // LD1Threev2d |
| 0U, // LD1Threev2d_POST |
| 0U, // LD1Threev2s |
| 0U, // LD1Threev2s_POST |
| 0U, // LD1Threev4h |
| 0U, // LD1Threev4h_POST |
| 0U, // LD1Threev4s |
| 0U, // LD1Threev4s_POST |
| 0U, // LD1Threev8b |
| 0U, // LD1Threev8b_POST |
| 0U, // LD1Threev8h |
| 0U, // LD1Threev8h_POST |
| 0U, // LD1Twov16b |
| 0U, // LD1Twov16b_POST |
| 0U, // LD1Twov1d |
| 0U, // LD1Twov1d_POST |
| 0U, // LD1Twov2d |
| 0U, // LD1Twov2d_POST |
| 0U, // LD1Twov2s |
| 0U, // LD1Twov2s_POST |
| 0U, // LD1Twov4h |
| 0U, // LD1Twov4h_POST |
| 0U, // LD1Twov4s |
| 0U, // LD1Twov4s_POST |
| 0U, // LD1Twov8b |
| 0U, // LD1Twov8b_POST |
| 0U, // LD1Twov8h |
| 0U, // LD1Twov8h_POST |
| 4741U, // LD1W |
| 4741U, // LD1W_D |
| 256261U, // LD1W_D_IMM_REAL |
| 256261U, // LD1W_IMM_REAL |
| 0U, // LD1i16 |
| 0U, // LD1i16_POST |
| 0U, // LD1i32 |
| 0U, // LD1i32_POST |
| 0U, // LD1i64 |
| 0U, // LD1i64_POST |
| 0U, // LD1i8 |
| 0U, // LD1i8_POST |
| 4357U, // LD2B |
| 258565U, // LD2B_IMM |
| 4421U, // LD2D |
| 258565U, // LD2D_IMM |
| 4485U, // LD2H |
| 258565U, // LD2H_IMM |
| 0U, // LD2Rv16b |
| 0U, // LD2Rv16b_POST |
| 0U, // LD2Rv1d |
| 0U, // LD2Rv1d_POST |
| 0U, // LD2Rv2d |
| 0U, // LD2Rv2d_POST |
| 0U, // LD2Rv2s |
| 0U, // LD2Rv2s_POST |
| 0U, // LD2Rv4h |
| 0U, // LD2Rv4h_POST |
| 0U, // LD2Rv4s |
| 0U, // LD2Rv4s_POST |
| 0U, // LD2Rv8b |
| 0U, // LD2Rv8b_POST |
| 0U, // LD2Rv8h |
| 0U, // LD2Rv8h_POST |
| 0U, // LD2Twov16b |
| 0U, // LD2Twov16b_POST |
| 0U, // LD2Twov2d |
| 0U, // LD2Twov2d_POST |
| 0U, // LD2Twov2s |
| 0U, // LD2Twov2s_POST |
| 0U, // LD2Twov4h |
| 0U, // LD2Twov4h_POST |
| 0U, // LD2Twov4s |
| 0U, // LD2Twov4s_POST |
| 0U, // LD2Twov8b |
| 0U, // LD2Twov8b_POST |
| 0U, // LD2Twov8h |
| 0U, // LD2Twov8h_POST |
| 4741U, // LD2W |
| 258565U, // LD2W_IMM |
| 0U, // LD2i16 |
| 0U, // LD2i16_POST |
| 0U, // LD2i32 |
| 0U, // LD2i32_POST |
| 0U, // LD2i64 |
| 0U, // LD2i64_POST |
| 0U, // LD2i8 |
| 0U, // LD2i8_POST |
| 4357U, // LD3B |
| 4869U, // LD3B_IMM |
| 4421U, // LD3D |
| 4869U, // LD3D_IMM |
| 4485U, // LD3H |
| 4869U, // LD3H_IMM |
| 0U, // LD3Rv16b |
| 0U, // LD3Rv16b_POST |
| 0U, // LD3Rv1d |
| 0U, // LD3Rv1d_POST |
| 0U, // LD3Rv2d |
| 0U, // LD3Rv2d_POST |
| 0U, // LD3Rv2s |
| 0U, // LD3Rv2s_POST |
| 0U, // LD3Rv4h |
| 0U, // LD3Rv4h_POST |
| 0U, // LD3Rv4s |
| 0U, // LD3Rv4s_POST |
| 0U, // LD3Rv8b |
| 0U, // LD3Rv8b_POST |
| 0U, // LD3Rv8h |
| 0U, // LD3Rv8h_POST |
| 0U, // LD3Threev16b |
| 0U, // LD3Threev16b_POST |
| 0U, // LD3Threev2d |
| 0U, // LD3Threev2d_POST |
| 0U, // LD3Threev2s |
| 0U, // LD3Threev2s_POST |
| 0U, // LD3Threev4h |
| 0U, // LD3Threev4h_POST |
| 0U, // LD3Threev4s |
| 0U, // LD3Threev4s_POST |
| 0U, // LD3Threev8b |
| 0U, // LD3Threev8b_POST |
| 0U, // LD3Threev8h |
| 0U, // LD3Threev8h_POST |
| 4741U, // LD3W |
| 4869U, // LD3W_IMM |
| 0U, // LD3i16 |
| 0U, // LD3i16_POST |
| 0U, // LD3i32 |
| 0U, // LD3i32_POST |
| 0U, // LD3i64 |
| 0U, // LD3i64_POST |
| 0U, // LD3i8 |
| 0U, // LD3i8_POST |
| 4357U, // LD4B |
| 258757U, // LD4B_IMM |
| 4421U, // LD4D |
| 258757U, // LD4D_IMM |
| 0U, // LD4Fourv16b |
| 0U, // LD4Fourv16b_POST |
| 0U, // LD4Fourv2d |
| 0U, // LD4Fourv2d_POST |
| 0U, // LD4Fourv2s |
| 0U, // LD4Fourv2s_POST |
| 0U, // LD4Fourv4h |
| 0U, // LD4Fourv4h_POST |
| 0U, // LD4Fourv4s |
| 0U, // LD4Fourv4s_POST |
| 0U, // LD4Fourv8b |
| 0U, // LD4Fourv8b_POST |
| 0U, // LD4Fourv8h |
| 0U, // LD4Fourv8h_POST |
| 4485U, // LD4H |
| 258757U, // LD4H_IMM |
| 0U, // LD4Rv16b |
| 0U, // LD4Rv16b_POST |
| 0U, // LD4Rv1d |
| 0U, // LD4Rv1d_POST |
| 0U, // LD4Rv2d |
| 0U, // LD4Rv2d_POST |
| 0U, // LD4Rv2s |
| 0U, // LD4Rv2s_POST |
| 0U, // LD4Rv4h |
| 0U, // LD4Rv4h_POST |
| 0U, // LD4Rv4s |
| 0U, // LD4Rv4s_POST |
| 0U, // LD4Rv8b |
| 0U, // LD4Rv8b_POST |
| 0U, // LD4Rv8h |
| 0U, // LD4Rv8h_POST |
| 4741U, // LD4W |
| 258757U, // LD4W_IMM |
| 0U, // LD4i16 |
| 0U, // LD4i16_POST |
| 0U, // LD4i32 |
| 0U, // LD4i32_POST |
| 0U, // LD4i64 |
| 0U, // LD4i64_POST |
| 0U, // LD4i8 |
| 0U, // LD4i8_POST |
| 0U, // LDADDAB |
| 0U, // LDADDAH |
| 0U, // LDADDALB |
| 0U, // LDADDALH |
| 0U, // LDADDALW |
| 0U, // LDADDALX |
| 0U, // LDADDAW |
| 0U, // LDADDAX |
| 0U, // LDADDB |
| 0U, // LDADDH |
| 0U, // LDADDLB |
| 0U, // LDADDLH |
| 0U, // LDADDLW |
| 0U, // LDADDLX |
| 0U, // LDADDW |
| 0U, // LDADDX |
| 27U, // LDAPRB |
| 27U, // LDAPRH |
| 27U, // LDAPRW |
| 27U, // LDAPRX |
| 114949U, // LDAPURBi |
| 114949U, // LDAPURHi |
| 114949U, // LDAPURSBWi |
| 114949U, // LDAPURSBXi |
| 114949U, // LDAPURSHWi |
| 114949U, // LDAPURSHXi |
| 114949U, // LDAPURSWi |
| 114949U, // LDAPURXi |
| 114949U, // LDAPURi |
| 27U, // LDARB |
| 27U, // LDARH |
| 27U, // LDARW |
| 27U, // LDARX |
| 114955U, // LDAXPW |
| 114955U, // LDAXPX |
| 27U, // LDAXRB |
| 27U, // LDAXRH |
| 27U, // LDAXRW |
| 27U, // LDAXRX |
| 0U, // LDCLRAB |
| 0U, // LDCLRAH |
| 0U, // LDCLRALB |
| 0U, // LDCLRALH |
| 0U, // LDCLRALW |
| 0U, // LDCLRALX |
| 0U, // LDCLRAW |
| 0U, // LDCLRAX |
| 0U, // LDCLRB |
| 0U, // LDCLRH |
| 0U, // LDCLRLB |
| 0U, // LDCLRLH |
| 0U, // LDCLRLW |
| 0U, // LDCLRLX |
| 0U, // LDCLRW |
| 0U, // LDCLRX |
| 0U, // LDEORAB |
| 0U, // LDEORAH |
| 0U, // LDEORALB |
| 0U, // LDEORALH |
| 0U, // LDEORALW |
| 0U, // LDEORALX |
| 0U, // LDEORAW |
| 0U, // LDEORAX |
| 0U, // LDEORB |
| 0U, // LDEORH |
| 0U, // LDEORLB |
| 0U, // LDEORLH |
| 0U, // LDEORLW |
| 0U, // LDEORLX |
| 0U, // LDEORW |
| 0U, // LDEORX |
| 4357U, // LDFF1B_D_REAL |
| 4357U, // LDFF1B_H_REAL |
| 4357U, // LDFF1B_REAL |
| 4357U, // LDFF1B_S_REAL |
| 4421U, // LDFF1D_REAL |
| 4485U, // LDFF1H_D_REAL |
| 4485U, // LDFF1H_REAL |
| 4485U, // LDFF1H_S_REAL |
| 4357U, // LDFF1SB_D_REAL |
| 4357U, // LDFF1SB_H_REAL |
| 4357U, // LDFF1SB_S_REAL |
| 4485U, // LDFF1SH_D_REAL |
| 4485U, // LDFF1SH_S_REAL |
| 4741U, // LDFF1SW_D_REAL |
| 4741U, // LDFF1W_D_REAL |
| 4741U, // LDFF1W_REAL |
| 27U, // LDLARB |
| 27U, // LDLARH |
| 27U, // LDLARW |
| 27U, // LDLARX |
| 256261U, // LDNF1B_D_IMM_REAL |
| 256261U, // LDNF1B_H_IMM_REAL |
| 256261U, // LDNF1B_IMM_REAL |
| 256261U, // LDNF1B_S_IMM_REAL |
| 256261U, // LDNF1D_IMM_REAL |
| 256261U, // LDNF1H_D_IMM_REAL |
| 256261U, // LDNF1H_IMM_REAL |
| 256261U, // LDNF1H_S_IMM_REAL |
| 256261U, // LDNF1SB_D_IMM_REAL |
| 256261U, // LDNF1SB_H_IMM_REAL |
| 256261U, // LDNF1SB_S_IMM_REAL |
| 256261U, // LDNF1SH_D_IMM_REAL |
| 256261U, // LDNF1SH_S_IMM_REAL |
| 256261U, // LDNF1SW_D_IMM_REAL |
| 256261U, // LDNF1W_D_IMM_REAL |
| 256261U, // LDNF1W_IMM_REAL |
| 11084043U, // LDNPDi |
| 11608331U, // LDNPQi |
| 12132619U, // LDNPSi |
| 12132619U, // LDNPWi |
| 11084043U, // LDNPXi |
| 256261U, // LDNT1B_ZRI |
| 4357U, // LDNT1B_ZRR |
| 256261U, // LDNT1D_ZRI |
| 4421U, // LDNT1D_ZRR |
| 256261U, // LDNT1H_ZRI |
| 4485U, // LDNT1H_ZRR |
| 256261U, // LDNT1W_ZRI |
| 4741U, // LDNT1W_ZRR |
| 11084043U, // LDPDi |
| 12847371U, // LDPDpost |
| 180431115U, // LDPDpre |
| 11608331U, // LDPQi |
| 13371659U, // LDPQpost |
| 180955403U, // LDPQpre |
| 12132619U, // LDPSWi |
| 13895947U, // LDPSWpost |
| 181479691U, // LDPSWpre |
| 12132619U, // LDPSi |
| 13895947U, // LDPSpost |
| 181479691U, // LDPSpre |
| 12132619U, // LDPWi |
| 13895947U, // LDPWpost |
| 181479691U, // LDPWpre |
| 11084043U, // LDPXi |
| 12847371U, // LDPXpost |
| 180431115U, // LDPXpre |
| 4933U, // LDRAAindexed |
| 274885U, // LDRAAwriteback |
| 4933U, // LDRABindexed |
| 274885U, // LDRABwriteback |
| 28U, // LDRBBpost |
| 272645U, // LDRBBpre |
| 14229765U, // LDRBBroW |
| 14754053U, // LDRBBroX |
| 4997U, // LDRBBui |
| 28U, // LDRBpost |
| 272645U, // LDRBpre |
| 14229765U, // LDRBroW |
| 14754053U, // LDRBroX |
| 4997U, // LDRBui |
| 0U, // LDRDl |
| 28U, // LDRDpost |
| 272645U, // LDRDpre |
| 15278341U, // LDRDroW |
| 15802629U, // LDRDroX |
| 5061U, // LDRDui |
| 28U, // LDRHHpost |
| 272645U, // LDRHHpre |
| 16326917U, // LDRHHroW |
| 16851205U, // LDRHHroX |
| 5125U, // LDRHHui |
| 28U, // LDRHpost |
| 272645U, // LDRHpre |
| 16326917U, // LDRHroW |
| 16851205U, // LDRHroX |
| 5125U, // LDRHui |
| 0U, // LDRQl |
| 28U, // LDRQpost |
| 272645U, // LDRQpre |
| 17375493U, // LDRQroW |
| 17899781U, // LDRQroX |
| 5189U, // LDRQui |
| 28U, // LDRSBWpost |
| 272645U, // LDRSBWpre |
| 14229765U, // LDRSBWroW |
| 14754053U, // LDRSBWroX |
| 4997U, // LDRSBWui |
| 28U, // LDRSBXpost |
| 272645U, // LDRSBXpre |
| 14229765U, // LDRSBXroW |
| 14754053U, // LDRSBXroX |
| 4997U, // LDRSBXui |
| 28U, // LDRSHWpost |
| 272645U, // LDRSHWpre |
| 16326917U, // LDRSHWroW |
| 16851205U, // LDRSHWroX |
| 5125U, // LDRSHWui |
| 28U, // LDRSHXpost |
| 272645U, // LDRSHXpre |
| 16326917U, // LDRSHXroW |
| 16851205U, // LDRSHXroX |
| 5125U, // LDRSHXui |
| 0U, // LDRSWl |
| 28U, // LDRSWpost |
| 272645U, // LDRSWpre |
| 18424069U, // LDRSWroW |
| 18948357U, // LDRSWroX |
| 5253U, // LDRSWui |
| 0U, // LDRSl |
| 28U, // LDRSpost |
| 272645U, // LDRSpre |
| 18424069U, // LDRSroW |
| 18948357U, // LDRSroX |
| 5253U, // LDRSui |
| 0U, // LDRWl |
| 28U, // LDRWpost |
| 272645U, // LDRWpre |
| 18424069U, // LDRWroW |
| 18948357U, // LDRWroX |
| 5253U, // LDRWui |
| 0U, // LDRXl |
| 28U, // LDRXpost |
| 272645U, // LDRXpre |
| 15278341U, // LDRXroW |
| 15802629U, // LDRXroX |
| 5061U, // LDRXui |
| 254213U, // LDR_PXI |
| 254213U, // LDR_ZXI |
| 0U, // LDSETAB |
| 0U, // LDSETAH |
| 0U, // LDSETALB |
| 0U, // LDSETALH |
| 0U, // LDSETALW |
| 0U, // LDSETALX |
| 0U, // LDSETAW |
| 0U, // LDSETAX |
| 0U, // LDSETB |
| 0U, // LDSETH |
| 0U, // LDSETLB |
| 0U, // LDSETLH |
| 0U, // LDSETLW |
| 0U, // LDSETLX |
| 0U, // LDSETW |
| 0U, // LDSETX |
| 0U, // LDSMAXAB |
| 0U, // LDSMAXAH |
| 0U, // LDSMAXALB |
| 0U, // LDSMAXALH |
| 0U, // LDSMAXALW |
| 0U, // LDSMAXALX |
| 0U, // LDSMAXAW |
| 0U, // LDSMAXAX |
| 0U, // LDSMAXB |
| 0U, // LDSMAXH |
| 0U, // LDSMAXLB |
| 0U, // LDSMAXLH |
| 0U, // LDSMAXLW |
| 0U, // LDSMAXLX |
| 0U, // LDSMAXW |
| 0U, // LDSMAXX |
| 0U, // LDSMINAB |
| 0U, // LDSMINAH |
| 0U, // LDSMINALB |
| 0U, // LDSMINALH |
| 0U, // LDSMINALW |
| 0U, // LDSMINALX |
| 0U, // LDSMINAW |
| 0U, // LDSMINAX |
| 0U, // LDSMINB |
| 0U, // LDSMINH |
| 0U, // LDSMINLB |
| 0U, // LDSMINLH |
| 0U, // LDSMINLW |
| 0U, // LDSMINLX |
| 0U, // LDSMINW |
| 0U, // LDSMINX |
| 114949U, // LDTRBi |
| 114949U, // LDTRHi |
| 114949U, // LDTRSBWi |
| 114949U, // LDTRSBXi |
| 114949U, // LDTRSHWi |
| 114949U, // LDTRSHXi |
| 114949U, // LDTRSWi |
| 114949U, // LDTRWi |
| 114949U, // LDTRXi |
| 0U, // LDUMAXAB |
| 0U, // LDUMAXAH |
| 0U, // LDUMAXALB |
| 0U, // LDUMAXALH |
| 0U, // LDUMAXALW |
| 0U, // LDUMAXALX |
| 0U, // LDUMAXAW |
| 0U, // LDUMAXAX |
| 0U, // LDUMAXB |
| 0U, // LDUMAXH |
| 0U, // LDUMAXLB |
| 0U, // LDUMAXLH |
| 0U, // LDUMAXLW |
| 0U, // LDUMAXLX |
| 0U, // LDUMAXW |
| 0U, // LDUMAXX |
| 0U, // LDUMINAB |
| 0U, // LDUMINAH |
| 0U, // LDUMINALB |
| 0U, // LDUMINALH |
| 0U, // LDUMINALW |
| 0U, // LDUMINALX |
| 0U, // LDUMINAW |
| 0U, // LDUMINAX |
| 0U, // LDUMINB |
| 0U, // LDUMINH |
| 0U, // LDUMINLB |
| 0U, // LDUMINLH |
| 0U, // LDUMINLW |
| 0U, // LDUMINLX |
| 0U, // LDUMINW |
| 0U, // LDUMINX |
| 114949U, // LDURBBi |
| 114949U, // LDURBi |
| 114949U, // LDURDi |
| 114949U, // LDURHHi |
| 114949U, // LDURHi |
| 114949U, // LDURQi |
| 114949U, // LDURSBWi |
| 114949U, // LDURSBXi |
| 114949U, // LDURSHWi |
| 114949U, // LDURSHXi |
| 114949U, // LDURSWi |
| 114949U, // LDURSi |
| 114949U, // LDURWi |
| 114949U, // LDURXi |
| 114955U, // LDXPW |
| 114955U, // LDXPX |
| 27U, // LDXRB |
| 27U, // LDXRH |
| 27U, // LDXRW |
| 27U, // LDXRX |
| 0U, // LOADgot |
| 74560U, // LSLR_ZPmZ_B |
| 598912U, // LSLR_ZPmZ_D |
| 1131465U, // LSLR_ZPmZ_H |
| 1647616U, // LSLR_ZPmZ_S |
| 261U, // LSLVWr |
| 261U, // LSLVXr |
| 598848U, // LSL_WIDE_ZPmZ_B |
| 99273U, // LSL_WIDE_ZPmZ_H |
| 599040U, // LSL_WIDE_ZPmZ_S |
| 901U, // LSL_WIDE_ZZZ_B |
| 10U, // LSL_WIDE_ZZZ_H |
| 901U, // LSL_WIDE_ZZZ_S |
| 2171712U, // LSL_ZPmI_B |
| 2171776U, // LSL_ZPmI_D |
| 91081U, // LSL_ZPmI_H |
| 2171904U, // LSL_ZPmI_S |
| 74560U, // LSL_ZPmZ_B |
| 598912U, // LSL_ZPmZ_D |
| 1131465U, // LSL_ZPmZ_H |
| 1647616U, // LSL_ZPmZ_S |
| 261U, // LSL_ZZI_B |
| 261U, // LSL_ZZI_D |
| 11U, // LSL_ZZI_H |
| 261U, // LSL_ZZI_S |
| 74560U, // LSRR_ZPmZ_B |
| 598912U, // LSRR_ZPmZ_D |
| 1131465U, // LSRR_ZPmZ_H |
| 1647616U, // LSRR_ZPmZ_S |
| 261U, // LSRVWr |
| 261U, // LSRVXr |
| 598848U, // LSR_WIDE_ZPmZ_B |
| 99273U, // LSR_WIDE_ZPmZ_H |
| 599040U, // LSR_WIDE_ZPmZ_S |
| 901U, // LSR_WIDE_ZZZ_B |
| 10U, // LSR_WIDE_ZZZ_H |
| 901U, // LSR_WIDE_ZZZ_S |
| 2171712U, // LSR_ZPmI_B |
| 2171776U, // LSR_ZPmI_D |
| 91081U, // LSR_ZPmI_H |
| 2171904U, // LSR_ZPmI_S |
| 74560U, // LSR_ZPmZ_B |
| 598912U, // LSR_ZPmZ_D |
| 1131465U, // LSR_ZPmZ_H |
| 1647616U, // LSR_ZPmZ_S |
| 261U, // LSR_ZZI_B |
| 261U, // LSR_ZZI_D |
| 11U, // LSR_ZZI_H |
| 261U, // LSR_ZZI_S |
| 2171141U, // MADDWrrr |
| 2171141U, // MADDXrrr |
| 19472384U, // MAD_ZPmZZ_B |
| 6889536U, // MAD_ZPmZZ_D |
| 1246144U, // MAD_ZPmZZ_H |
| 7413952U, // MAD_ZPmZZ_S |
| 19472384U, // MLA_ZPmZZ_B |
| 6889536U, // MLA_ZPmZZ_D |
| 1246144U, // MLA_ZPmZZ_H |
| 7413952U, // MLA_ZPmZZ_S |
| 33159U, // MLAv16i8 |
| 41351U, // MLAv2i32 |
| 9126279U, // MLAv2i32_indexed |
| 49544U, // MLAv4i16 |
| 9118088U, // MLAv4i16_indexed |
| 16774U, // MLAv4i32 |
| 9126278U, // MLAv4i32_indexed |
| 24966U, // MLAv8i16 |
| 9118086U, // MLAv8i16_indexed |
| 57736U, // MLAv8i8 |
| 19472384U, // MLS_ZPmZZ_B |
| 6889536U, // MLS_ZPmZZ_D |
| 1246144U, // MLS_ZPmZZ_H |
| 7413952U, // MLS_ZPmZZ_S |
| 33159U, // MLSv16i8 |
| 41351U, // MLSv2i32 |
| 9126279U, // MLSv2i32_indexed |
| 49544U, // MLSv4i16 |
| 9118088U, // MLSv4i16_indexed |
| 16774U, // MLSv4i32 |
| 9126278U, // MLSv4i32_indexed |
| 24966U, // MLSv8i16 |
| 9118086U, // MLSv8i16_indexed |
| 57736U, // MLSv8i8 |
| 0U, // MOVID |
| 1U, // MOVIv16b_ns |
| 0U, // MOVIv2d_ns |
| 28U, // MOVIv2i32 |
| 28U, // MOVIv2s_msl |
| 28U, // MOVIv4i16 |
| 28U, // MOVIv4i32 |
| 28U, // MOVIv4s_msl |
| 1U, // MOVIv8b_ns |
| 28U, // MOVIv8i16 |
| 0U, // MOVKWi |
| 0U, // MOVKXi |
| 28U, // MOVNWi |
| 28U, // MOVNXi |
| 0U, // MOVPRFX_ZPmZ_B |
| 64U, // MOVPRFX_ZPmZ_D |
| 128U, // MOVPRFX_ZPmZ_H |
| 192U, // MOVPRFX_ZPmZ_S |
| 842U, // MOVPRFX_ZPzZ_B |
| 906U, // MOVPRFX_ZPzZ_D |
| 137U, // MOVPRFX_ZPzZ_H |
| 1034U, // MOVPRFX_ZPzZ_S |
| 1U, // MOVPRFX_ZZ |
| 28U, // MOVZWi |
| 28U, // MOVZXi |
| 0U, // MOVaddr |
| 0U, // MOVaddrBA |
| 0U, // MOVaddrCP |
| 0U, // MOVaddrEXT |
| 0U, // MOVaddrJT |
| 0U, // MOVaddrTLS |
| 0U, // MOVbaseTLS |
| 0U, // MOVi32imm |
| 0U, // MOVi64imm |
| 0U, // MRS |
| 19472384U, // MSB_ZPmZZ_B |
| 6889536U, // MSB_ZPmZZ_D |
| 1246144U, // MSB_ZPmZZ_H |
| 7413952U, // MSB_ZPmZZ_S |
| 0U, // MSR |
| 0U, // MSRpstateImm1 |
| 0U, // MSRpstateImm4 |
| 2171141U, // MSUBWrrr |
| 2171141U, // MSUBXrrr |
| 261U, // MUL_ZI_B |
| 261U, // MUL_ZI_D |
| 11U, // MUL_ZI_H |
| 261U, // MUL_ZI_S |
| 74560U, // MUL_ZPmZ_B |
| 598912U, // MUL_ZPmZ_D |
| 1131465U, // MUL_ZPmZ_H |
| 1647616U, // MUL_ZPmZ_S |
| 33095U, // MULv16i8 |
| 41287U, // MULv2i32 |
| 10174791U, // MULv2i32_indexed |
| 49480U, // MULv4i16 |
| 10166600U, // MULv4i16_indexed |
| 16710U, // MULv4i32 |
| 10174790U, // MULv4i32_indexed |
| 24902U, // MULv8i16 |
| 10166598U, // MULv8i16_indexed |
| 57672U, // MULv8i8 |
| 28U, // MVNIv2i32 |
| 28U, // MVNIv2s_msl |
| 28U, // MVNIv4i16 |
| 28U, // MVNIv4i32 |
| 28U, // MVNIv4s_msl |
| 28U, // MVNIv8i16 |
| 74570U, // NANDS_PPzPP |
| 74570U, // NAND_PPzPP |
| 0U, // NEG_ZPmZ_B |
| 64U, // NEG_ZPmZ_D |
| 128U, // NEG_ZPmZ_H |
| 192U, // NEG_ZPmZ_S |
| 1U, // NEGv16i8 |
| 1U, // NEGv1i64 |
| 2U, // NEGv2i32 |
| 2U, // NEGv2i64 |
| 3U, // NEGv4i16 |
| 3U, // NEGv4i32 |
| 4U, // NEGv8i16 |
| 4U, // NEGv8i8 |
| 74570U, // NORS_PPzPP |
| 74570U, // NOR_PPzPP |
| 0U, // NOT_ZPmZ_B |
| 64U, // NOT_ZPmZ_D |
| 128U, // NOT_ZPmZ_H |
| 192U, // NOT_ZPmZ_S |
| 1U, // NOTv16i8 |
| 4U, // NOTv8i8 |
| 74570U, // ORNS_PPzPP |
| 0U, // ORNWrr |
| 517U, // ORNWrs |
| 0U, // ORNXrr |
| 517U, // ORNXrs |
| 74570U, // ORN_PPzPP |
| 33095U, // ORNv16i8 |
| 57672U, // ORNv8i8 |
| 74570U, // ORRS_PPzPP |
| 2117U, // ORRWri |
| 0U, // ORRWrr |
| 517U, // ORRWrs |
| 2181U, // ORRXri |
| 0U, // ORRXrr |
| 517U, // ORRXrs |
| 74570U, // ORR_PPzPP |
| 2181U, // ORR_ZI |
| 74560U, // ORR_ZPmZ_B |
| 598912U, // ORR_ZPmZ_D |
| 1131465U, // ORR_ZPmZ_H |
| 1647616U, // ORR_ZPmZ_S |
| 901U, // ORR_ZZZ |
| 33095U, // ORRv16i8 |
| 0U, // ORRv2i32 |
| 0U, // ORRv4i16 |
| 0U, // ORRv4i32 |
| 0U, // ORRv8i16 |
| 57672U, // ORRv8i8 |
| 837U, // ORV_VPZ_B |
| 901U, // ORV_VPZ_D |
| 2245U, // ORV_VPZ_H |
| 1029U, // ORV_VPZ_S |
| 1U, // PACDA |
| 1U, // PACDB |
| 0U, // PACDZA |
| 0U, // PACDZB |
| 261U, // PACGA |
| 1U, // PACIA |
| 0U, // PACIA1716 |
| 0U, // PACIASP |
| 0U, // PACIAZ |
| 1U, // PACIB |
| 0U, // PACIB1716 |
| 0U, // PACIBSP |
| 0U, // PACIBZ |
| 0U, // PACIZA |
| 0U, // PACIZB |
| 0U, // PFALSE |
| 33095U, // PMULLv16i8 |
| 0U, // PMULLv1i64 |
| 0U, // PMULLv2i64 |
| 57672U, // PMULLv8i8 |
| 33095U, // PMULv16i8 |
| 57672U, // PMULv8i8 |
| 837U, // PNEXT_B |
| 901U, // PNEXT_D |
| 137U, // PNEXT_H |
| 1029U, // PNEXT_S |
| 27U, // PRFB_D_PZI |
| 29U, // PRFB_D_SCALED |
| 29U, // PRFB_D_SXTW_SCALED |
| 30U, // PRFB_D_UXTW_SCALED |
| 5329U, // PRFB_PRI |
| 30U, // PRFB_PRR |
| 27U, // PRFB_S_PZI |
| 31U, // PRFB_S_SXTW_SCALED |
| 31U, // PRFB_S_UXTW_SCALED |
| 0U, // PRFD_D_PZI |
| 32U, // PRFD_D_SCALED |
| 32U, // PRFD_D_SXTW_SCALED |
| 33U, // PRFD_D_UXTW_SCALED |
| 5329U, // PRFD_PRI |
| 33U, // PRFD_PRR |
| 0U, // PRFD_S_PZI |
| 34U, // PRFD_S_SXTW_SCALED |
| 34U, // PRFD_S_UXTW_SCALED |
| 0U, // PRFH_D_PZI |
| 35U, // PRFH_D_SCALED |
| 35U, // PRFH_D_SXTW_SCALED |
| 36U, // PRFH_D_UXTW_SCALED |
| 5329U, // PRFH_PRI |
| 36U, // PRFH_PRR |
| 0U, // PRFH_S_PZI |
| 37U, // PRFH_S_SXTW_SCALED |
| 37U, // PRFH_S_UXTW_SCALED |
| 0U, // PRFMl |
| 15278341U, // PRFMroW |
| 15802629U, // PRFMroX |
| 5061U, // PRFMui |
| 38U, // PRFS_PRR |
| 114949U, // PRFUMi |
| 0U, // PRFW_D_PZI |
| 38U, // PRFW_D_SCALED |
| 39U, // PRFW_D_SXTW_SCALED |
| 39U, // PRFW_D_UXTW_SCALED |
| 5329U, // PRFW_PRI |
| 0U, // PRFW_S_PZI |
| 40U, // PRFW_S_SXTW_SCALED |
| 40U, // PRFW_S_UXTW_SCALED |
| 1U, // PTEST_PP |
| 1U, // PTRUES_B |
| 1U, // PTRUES_D |
| 0U, // PTRUES_H |
| 1U, // PTRUES_S |
| 1U, // PTRUE_B |
| 1U, // PTRUE_D |
| 0U, // PTRUE_H |
| 1U, // PTRUE_S |
| 0U, // PUNPKHI_PP |
| 0U, // PUNPKLO_PP |
| 8517U, // RADDHNv2i64_v2i32 |
| 8581U, // RADDHNv2i64_v4i32 |
| 16710U, // RADDHNv4i32_v4i16 |
| 16774U, // RADDHNv4i32_v8i16 |
| 24966U, // RADDHNv8i16_v16i8 |
| 24902U, // RADDHNv8i16_v8i8 |
| 8517U, // RAX1 |
| 1U, // RBITWr |
| 1U, // RBITXr |
| 0U, // RBIT_ZPmZ_B |
| 64U, // RBIT_ZPmZ_D |
| 128U, // RBIT_ZPmZ_H |
| 192U, // RBIT_ZPmZ_S |
| 1U, // RBITv16i8 |
| 4U, // RBITv8i8 |
| 41U, // RDFFRS_PPz |
| 0U, // RDFFR_P |
| 41U, // RDFFR_PPz |
| 1U, // RDVLI_XI |
| 0U, // RET |
| 0U, // RETAA |
| 0U, // RETAB |
| 0U, // RET_ReallyLR |
| 1U, // REV16Wr |
| 1U, // REV16Xr |
| 1U, // REV16v16i8 |
| 4U, // REV16v8i8 |
| 1U, // REV32Xr |
| 1U, // REV32v16i8 |
| 3U, // REV32v4i16 |
| 4U, // REV32v8i16 |
| 4U, // REV32v8i8 |
| 1U, // REV64v16i8 |
| 2U, // REV64v2i32 |
| 3U, // REV64v4i16 |
| 3U, // REV64v4i32 |
| 4U, // REV64v8i16 |
| 4U, // REV64v8i8 |
| 64U, // REVB_ZPmZ_D |
| 128U, // REVB_ZPmZ_H |
| 192U, // REVB_ZPmZ_S |
| 64U, // REVH_ZPmZ_D |
| 192U, // REVH_ZPmZ_S |
| 64U, // REVW_ZPmZ_D |
| 1U, // REVWr |
| 1U, // REVXr |
| 1U, // REV_PP_B |
| 1U, // REV_PP_D |
| 0U, // REV_PP_H |
| 1U, // REV_PP_S |
| 1U, // REV_ZZ_B |
| 1U, // REV_ZZ_D |
| 0U, // REV_ZZ_H |
| 1U, // REV_ZZ_S |
| 261U, // RMIF |
| 261U, // RORVWr |
| 261U, // RORVXr |
| 2310U, // RSHRNv16i8_shift |
| 261U, // RSHRNv2i32_shift |
| 262U, // RSHRNv4i16_shift |
| 2309U, // RSHRNv4i32_shift |
| 2310U, // RSHRNv8i16_shift |
| 262U, // RSHRNv8i8_shift |
| 8517U, // RSUBHNv2i64_v2i32 |
| 8581U, // RSUBHNv2i64_v4i32 |
| 16710U, // RSUBHNv4i32_v4i16 |
| 16774U, // RSUBHNv4i32_v8i16 |
| 24966U, // RSUBHNv8i16_v16i8 |
| 24902U, // RSUBHNv8i16_v8i8 |
| 33159U, // SABALv16i8_v8i16 |
| 41351U, // SABALv2i32_v2i64 |
| 49544U, // SABALv4i16_v4i32 |
| 16774U, // SABALv4i32_v2i64 |
| 24966U, // SABALv8i16_v4i32 |
| 57736U, // SABALv8i8_v8i16 |
| 33159U, // SABAv16i8 |
| 41351U, // SABAv2i32 |
| 49544U, // SABAv4i16 |
| 16774U, // SABAv4i32 |
| 24966U, // SABAv8i16 |
| 57736U, // SABAv8i8 |
| 33095U, // SABDLv16i8_v8i16 |
| 41287U, // SABDLv2i32_v2i64 |
| 49480U, // SABDLv4i16_v4i32 |
| 16710U, // SABDLv4i32_v2i64 |
| 24902U, // SABDLv8i16_v4i32 |
| 57672U, // SABDLv8i8_v8i16 |
| 74560U, // SABD_ZPmZ_B |
| 598912U, // SABD_ZPmZ_D |
| 1131465U, // SABD_ZPmZ_H |
| 1647616U, // SABD_ZPmZ_S |
| 33095U, // SABDv16i8 |
| 41287U, // SABDv2i32 |
| 49480U, // SABDv4i16 |
| 16710U, // SABDv4i32 |
| 24902U, // SABDv8i16 |
| 57672U, // SABDv8i8 |
| 1U, // SADALPv16i8_v8i16 |
| 2U, // SADALPv2i32_v1i64 |
| 3U, // SADALPv4i16_v2i32 |
| 3U, // SADALPv4i32_v2i64 |
| 4U, // SADALPv8i16_v4i32 |
| 4U, // SADALPv8i8_v4i16 |
| 1U, // SADDLPv16i8_v8i16 |
| 2U, // SADDLPv2i32_v1i64 |
| 3U, // SADDLPv4i16_v2i32 |
| 3U, // SADDLPv4i32_v2i64 |
| 4U, // SADDLPv8i16_v4i32 |
| 4U, // SADDLPv8i8_v4i16 |
| 1U, // SADDLVv16i8v |
| 3U, // SADDLVv4i16v |
| 3U, // SADDLVv4i32v |
| 4U, // SADDLVv8i16v |
| 4U, // SADDLVv8i8v |
| 33095U, // SADDLv16i8_v8i16 |
| 41287U, // SADDLv2i32_v2i64 |
| 49480U, // SADDLv4i16_v4i32 |
| 16710U, // SADDLv4i32_v2i64 |
| 24902U, // SADDLv8i16_v4i32 |
| 57672U, // SADDLv8i8_v8i16 |
| 837U, // SADDV_VPZ_B |
| 2245U, // SADDV_VPZ_H |
| 1029U, // SADDV_VPZ_S |
| 33094U, // SADDWv16i8_v8i16 |
| 41285U, // SADDWv2i32_v2i64 |
| 49478U, // SADDWv4i16_v4i32 |
| 16709U, // SADDWv4i32_v2i64 |
| 24902U, // SADDWv8i16_v4i32 |
| 57670U, // SADDWv8i8_v8i16 |
| 261U, // SBCSWr |
| 261U, // SBCSXr |
| 261U, // SBCWr |
| 261U, // SBCXr |
| 2171141U, // SBFMWri |
| 2171141U, // SBFMXri |
| 261U, // SCVTFSWDri |
| 261U, // SCVTFSWHri |
| 261U, // SCVTFSWSri |
| 261U, // SCVTFSXDri |
| 261U, // SCVTFSXHri |
| 261U, // SCVTFSXSri |
| 1U, // SCVTFUWDri |
| 1U, // SCVTFUWHri |
| 1U, // SCVTFUWSri |
| 1U, // SCVTFUXDri |
| 1U, // SCVTFUXHri |
| 1U, // SCVTFUXSri |
| 64U, // SCVTF_ZPmZ_DtoD |
| 153U, // SCVTF_ZPmZ_DtoH |
| 64U, // SCVTF_ZPmZ_DtoS |
| 128U, // SCVTF_ZPmZ_HtoH |
| 192U, // SCVTF_ZPmZ_StoD |
| 152U, // SCVTF_ZPmZ_StoH |
| 192U, // SCVTF_ZPmZ_StoS |
| 261U, // SCVTFd |
| 261U, // SCVTFh |
| 261U, // SCVTFs |
| 1U, // SCVTFv1i16 |
| 1U, // SCVTFv1i32 |
| 1U, // SCVTFv1i64 |
| 2U, // SCVTFv2f32 |
| 2U, // SCVTFv2f64 |
| 263U, // SCVTFv2i32_shift |
| 261U, // SCVTFv2i64_shift |
| 3U, // SCVTFv4f16 |
| 3U, // SCVTFv4f32 |
| 264U, // SCVTFv4i16_shift |
| 262U, // SCVTFv4i32_shift |
| 4U, // SCVTFv8f16 |
| 262U, // SCVTFv8i16_shift |
| 598912U, // SDIVR_ZPmZ_D |
| 1647616U, // SDIVR_ZPmZ_S |
| 261U, // SDIVWr |
| 261U, // SDIVXr |
| 598912U, // SDIV_ZPmZ_D |
| 1647616U, // SDIV_ZPmZ_S |
| 41U, // SDOT_ZZZI_D |
| 41U, // SDOT_ZZZI_S |
| 1U, // SDOT_ZZZ_D |
| 1U, // SDOT_ZZZ_S |
| 278919U, // SDOTlanev16i8 |
| 278920U, // SDOTlanev8i8 |
| 33159U, // SDOTv16i8 |
| 57736U, // SDOTv8i8 |
| 74565U, // SEL_PPPP |
| 74565U, // SEL_ZPZZ_B |
| 598917U, // SEL_ZPZZ_D |
| 1131465U, // SEL_ZPZZ_H |
| 1647621U, // SEL_ZPZZ_S |
| 0U, // SETF16 |
| 0U, // SETF8 |
| 0U, // SETFFR |
| 16773U, // SHA1Crrr |
| 1U, // SHA1Hrr |
| 16773U, // SHA1Mrrr |
| 16773U, // SHA1Prrr |
| 16774U, // SHA1SU0rrr |
| 3U, // SHA1SU1rr |
| 16773U, // SHA256H2rrr |
| 16773U, // SHA256Hrrr |
| 3U, // SHA256SU0rr |
| 16774U, // SHA256SU1rrr |
| 8581U, // SHA512H |
| 8581U, // SHA512H2 |
| 2U, // SHA512SU0 |
| 8581U, // SHA512SU1 |
| 33095U, // SHADDv16i8 |
| 41287U, // SHADDv2i32 |
| 49480U, // SHADDv4i16 |
| 16710U, // SHADDv4i32 |
| 24902U, // SHADDv8i16 |
| 57672U, // SHADDv8i8 |
| 42U, // SHLLv16i8 |
| 42U, // SHLLv2i32 |
| 43U, // SHLLv4i16 |
| 43U, // SHLLv4i32 |
| 44U, // SHLLv8i16 |
| 44U, // SHLLv8i8 |
| 261U, // SHLd |
| 263U, // SHLv16i8_shift |
| 263U, // SHLv2i32_shift |
| 261U, // SHLv2i64_shift |
| 264U, // SHLv4i16_shift |
| 262U, // SHLv4i32_shift |
| 262U, // SHLv8i16_shift |
| 264U, // SHLv8i8_shift |
| 2310U, // SHRNv16i8_shift |
| 261U, // SHRNv2i32_shift |
| 262U, // SHRNv4i16_shift |
| 2309U, // SHRNv4i32_shift |
| 2310U, // SHRNv8i16_shift |
| 262U, // SHRNv8i8_shift |
| 33095U, // SHSUBv16i8 |
| 41287U, // SHSUBv2i32 |
| 49480U, // SHSUBv4i16 |
| 16710U, // SHSUBv4i32 |
| 24902U, // SHSUBv8i16 |
| 57672U, // SHSUBv8i8 |
| 2309U, // SLId |
| 2311U, // SLIv16i8_shift |
| 2311U, // SLIv2i32_shift |
| 2309U, // SLIv2i64_shift |
| 2312U, // SLIv4i16_shift |
| 2310U, // SLIv4i32_shift |
| 2310U, // SLIv8i16_shift |
| 2312U, // SLIv8i8_shift |
| 16774U, // SM3PARTW1 |
| 16774U, // SM3PARTW2 |
| 204120390U, // SM3SS1 |
| 9126278U, // SM3TT1A |
| 9126278U, // SM3TT1B |
| 9126278U, // SM3TT2A |
| 9126278U, // SM3TT2B |
| 3U, // SM4E |
| 16710U, // SM4ENCKEY |
| 2171141U, // SMADDLrrr |
| 33095U, // SMAXPv16i8 |
| 41287U, // SMAXPv2i32 |
| 49480U, // SMAXPv4i16 |
| 16710U, // SMAXPv4i32 |
| 24902U, // SMAXPv8i16 |
| 57672U, // SMAXPv8i8 |
| 837U, // SMAXV_VPZ_B |
| 901U, // SMAXV_VPZ_D |
| 2245U, // SMAXV_VPZ_H |
| 1029U, // SMAXV_VPZ_S |
| 1U, // SMAXVv16i8v |
| 3U, // SMAXVv4i16v |
| 3U, // SMAXVv4i32v |
| 4U, // SMAXVv8i16v |
| 4U, // SMAXVv8i8v |
| 261U, // SMAX_ZI_B |
| 261U, // SMAX_ZI_D |
| 11U, // SMAX_ZI_H |
| 261U, // SMAX_ZI_S |
| 74560U, // SMAX_ZPmZ_B |
| 598912U, // SMAX_ZPmZ_D |
| 1131465U, // SMAX_ZPmZ_H |
| 1647616U, // SMAX_ZPmZ_S |
| 33095U, // SMAXv16i8 |
| 41287U, // SMAXv2i32 |
| 49480U, // SMAXv4i16 |
| 16710U, // SMAXv4i32 |
| 24902U, // SMAXv8i16 |
| 57672U, // SMAXv8i8 |
| 0U, // SMC |
| 33095U, // SMINPv16i8 |
| 41287U, // SMINPv2i32 |
| 49480U, // SMINPv4i16 |
| 16710U, // SMINPv4i32 |
| 24902U, // SMINPv8i16 |
| 57672U, // SMINPv8i8 |
| 837U, // SMINV_VPZ_B |
| 901U, // SMINV_VPZ_D |
| 2245U, // SMINV_VPZ_H |
| 1029U, // SMINV_VPZ_S |
| 1U, // SMINVv16i8v |
| 3U, // SMINVv4i16v |
| 3U, // SMINVv4i32v |
| 4U, // SMINVv8i16v |
| 4U, // SMINVv8i8v |
| 261U, // SMIN_ZI_B |
| 261U, // SMIN_ZI_D |
| 11U, // SMIN_ZI_H |
| 261U, // SMIN_ZI_S |
| 74560U, // SMIN_ZPmZ_B |
| 598912U, // SMIN_ZPmZ_D |
| 1131465U, // SMIN_ZPmZ_H |
| 1647616U, // SMIN_ZPmZ_S |
| 33095U, // SMINv16i8 |
| 41287U, // SMINv2i32 |
| 49480U, // SMINv4i16 |
| 16710U, // SMINv4i32 |
| 24902U, // SMINv8i16 |
| 57672U, // SMINv8i8 |
| 33159U, // SMLALv16i8_v8i16 |
| 9126279U, // SMLALv2i32_indexed |
| 41351U, // SMLALv2i32_v2i64 |
| 9118088U, // SMLALv4i16_indexed |
| 49544U, // SMLALv4i16_v4i32 |
| 9126278U, // SMLALv4i32_indexed |
| 16774U, // SMLALv4i32_v2i64 |
| 9118086U, // SMLALv8i16_indexed |
| 24966U, // SMLALv8i16_v4i32 |
| 57736U, // SMLALv8i8_v8i16 |
| 33159U, // SMLSLv16i8_v8i16 |
| 9126279U, // SMLSLv2i32_indexed |
| 41351U, // SMLSLv2i32_v2i64 |
| 9118088U, // SMLSLv4i16_indexed |
| 49544U, // SMLSLv4i16_v4i32 |
| 9126278U, // SMLSLv4i32_indexed |
| 16774U, // SMLSLv4i32_v2i64 |
| 9118086U, // SMLSLv8i16_indexed |
| 24966U, // SMLSLv8i16_v4i32 |
| 57736U, // SMLSLv8i8_v8i16 |
| 2770U, // SMOVvi16to32 |
| 2770U, // SMOVvi16to64 |
| 2770U, // SMOVvi32to64 |
| 2771U, // SMOVvi8to32 |
| 2771U, // SMOVvi8to64 |
| 2171141U, // SMSUBLrrr |
| 74560U, // SMULH_ZPmZ_B |
| 598912U, // SMULH_ZPmZ_D |
| 1131465U, // SMULH_ZPmZ_H |
| 1647616U, // SMULH_ZPmZ_S |
| 261U, // SMULHrr |
| 33095U, // SMULLv16i8_v8i16 |
| 10174791U, // SMULLv2i32_indexed |
| 41287U, // SMULLv2i32_v2i64 |
| 10166600U, // SMULLv4i16_indexed |
| 49480U, // SMULLv4i16_v4i32 |
| 10174790U, // SMULLv4i32_indexed |
| 16710U, // SMULLv4i32_v2i64 |
| 10166598U, // SMULLv8i16_indexed |
| 24902U, // SMULLv8i16_v4i32 |
| 57672U, // SMULLv8i8_v8i16 |
| 74565U, // SPLICE_ZPZ_B |
| 598917U, // SPLICE_ZPZ_D |
| 1131465U, // SPLICE_ZPZ_H |
| 1647621U, // SPLICE_ZPZ_S |
| 1U, // SQABSv16i8 |
| 1U, // SQABSv1i16 |
| 1U, // SQABSv1i32 |
| 1U, // SQABSv1i64 |
| 1U, // SQABSv1i8 |
| 2U, // SQABSv2i32 |
| 2U, // SQABSv2i64 |
| 3U, // SQABSv4i16 |
| 3U, // SQABSv4i32 |
| 4U, // SQABSv8i16 |
| 4U, // SQABSv8i8 |
| 645U, // SQADD_ZI_B |
| 709U, // SQADD_ZI_D |
| 9U, // SQADD_ZI_H |
| 773U, // SQADD_ZI_S |
| 837U, // SQADD_ZZZ_B |
| 901U, // SQADD_ZZZ_D |
| 137U, // SQADD_ZZZ_H |
| 1029U, // SQADD_ZZZ_S |
| 33095U, // SQADDv16i8 |
| 261U, // SQADDv1i16 |
| 261U, // SQADDv1i32 |
| 261U, // SQADDv1i64 |
| 261U, // SQADDv1i8 |
| 41287U, // SQADDv2i32 |
| 8517U, // SQADDv2i64 |
| 49480U, // SQADDv4i16 |
| 16710U, // SQADDv4i32 |
| 24902U, // SQADDv8i16 |
| 57672U, // SQADDv8i8 |
| 0U, // SQDECB_XPiI |
| 0U, // SQDECB_XPiWdI |
| 0U, // SQDECD_XPiI |
| 0U, // SQDECD_XPiWdI |
| 0U, // SQDECD_ZPiI |
| 0U, // SQDECH_XPiI |
| 0U, // SQDECH_XPiWdI |
| 0U, // SQDECH_ZPiI |
| 5381U, // SQDECP_XPWd_B |
| 5381U, // SQDECP_XPWd_D |
| 5381U, // SQDECP_XPWd_H |
| 5381U, // SQDECP_XPWd_S |
| 1U, // SQDECP_XP_B |
| 1U, // SQDECP_XP_D |
| 1U, // SQDECP_XP_H |
| 1U, // SQDECP_XP_S |
| 1U, // SQDECP_ZP_D |
| 0U, // SQDECP_ZP_H |
| 1U, // SQDECP_ZP_S |
| 0U, // SQDECW_XPiI |
| 0U, // SQDECW_XPiWdI |
| 0U, // SQDECW_ZPiI |
| 2309U, // SQDMLALi16 |
| 2309U, // SQDMLALi32 |
| 9118085U, // SQDMLALv1i32_indexed |
| 9126277U, // SQDMLALv1i64_indexed |
| 9126279U, // SQDMLALv2i32_indexed |
| 41351U, // SQDMLALv2i32_v2i64 |
| 9118088U, // SQDMLALv4i16_indexed |
| 49544U, // SQDMLALv4i16_v4i32 |
| 9126278U, // SQDMLALv4i32_indexed |
| 16774U, // SQDMLALv4i32_v2i64 |
| 9118086U, // SQDMLALv8i16_indexed |
| 24966U, // SQDMLALv8i16_v4i32 |
| 2309U, // SQDMLSLi16 |
| 2309U, // SQDMLSLi32 |
| 9118085U, // SQDMLSLv1i32_indexed |
| 9126277U, // SQDMLSLv1i64_indexed |
| 9126279U, // SQDMLSLv2i32_indexed |
| 41351U, // SQDMLSLv2i32_v2i64 |
| 9118088U, // SQDMLSLv4i16_indexed |
| 49544U, // SQDMLSLv4i16_v4i32 |
| 9126278U, // SQDMLSLv4i32_indexed |
| 16774U, // SQDMLSLv4i32_v2i64 |
| 9118086U, // SQDMLSLv8i16_indexed |
| 24966U, // SQDMLSLv8i16_v4i32 |
| 261U, // SQDMULHv1i16 |
| 10166597U, // SQDMULHv1i16_indexed |
| 261U, // SQDMULHv1i32 |
| 10174789U, // SQDMULHv1i32_indexed |
| 41287U, // SQDMULHv2i32 |
| 10174791U, // SQDMULHv2i32_indexed |
| 49480U, // SQDMULHv4i16 |
| 10166600U, // SQDMULHv4i16_indexed |
| 16710U, // SQDMULHv4i32 |
| 10174790U, // SQDMULHv4i32_indexed |
| 24902U, // SQDMULHv8i16 |
| 10166598U, // SQDMULHv8i16_indexed |
| 261U, // SQDMULLi16 |
| 261U, // SQDMULLi32 |
| 10166597U, // SQDMULLv1i32_indexed |
| 10174789U, // SQDMULLv1i64_indexed |
| 10174791U, // SQDMULLv2i32_indexed |
| 41287U, // SQDMULLv2i32_v2i64 |
| 10166600U, // SQDMULLv4i16_indexed |
| 49480U, // SQDMULLv4i16_v4i32 |
| 10174790U, // SQDMULLv4i32_indexed |
| 16710U, // SQDMULLv4i32_v2i64 |
| 10166598U, // SQDMULLv8i16_indexed |
| 24902U, // SQDMULLv8i16_v4i32 |
| 0U, // SQINCB_XPiI |
| 0U, // SQINCB_XPiWdI |
| 0U, // SQINCD_XPiI |
| 0U, // SQINCD_XPiWdI |
| 0U, // SQINCD_ZPiI |
| 0U, // SQINCH_XPiI |
| 0U, // SQINCH_XPiWdI |
| 0U, // SQINCH_ZPiI |
| 5381U, // SQINCP_XPWd_B |
| 5381U, // SQINCP_XPWd_D |
| 5381U, // SQINCP_XPWd_H |
| 5381U, // SQINCP_XPWd_S |
| 1U, // SQINCP_XP_B |
| 1U, // SQINCP_XP_D |
| 1U, // SQINCP_XP_H |
| 1U, // SQINCP_XP_S |
| 1U, // SQINCP_ZP_D |
| 0U, // SQINCP_ZP_H |
| 1U, // SQINCP_ZP_S |
| 0U, // SQINCW_XPiI |
| 0U, // SQINCW_XPiWdI |
| 0U, // SQINCW_ZPiI |
| 1U, // SQNEGv16i8 |
| 1U, // SQNEGv1i16 |
| 1U, // SQNEGv1i32 |
| 1U, // SQNEGv1i64 |
| 1U, // SQNEGv1i8 |
| 2U, // SQNEGv2i32 |
| 2U, // SQNEGv2i64 |
| 3U, // SQNEGv4i16 |
| 3U, // SQNEGv4i32 |
| 4U, // SQNEGv8i16 |
| 4U, // SQNEGv8i8 |
| 9118085U, // SQRDMLAHi16_indexed |
| 9126277U, // SQRDMLAHi32_indexed |
| 2309U, // SQRDMLAHv1i16 |
| 2309U, // SQRDMLAHv1i32 |
| 41351U, // SQRDMLAHv2i32 |
| 9126279U, // SQRDMLAHv2i32_indexed |
| 49544U, // SQRDMLAHv4i16 |
| 9118088U, // SQRDMLAHv4i16_indexed |
| 16774U, // SQRDMLAHv4i32 |
| 9126278U, // SQRDMLAHv4i32_indexed |
| 24966U, // SQRDMLAHv8i16 |
| 9118086U, // SQRDMLAHv8i16_indexed |
| 9118085U, // SQRDMLSHi16_indexed |
| 9126277U, // SQRDMLSHi32_indexed |
| 2309U, // SQRDMLSHv1i16 |
| 2309U, // SQRDMLSHv1i32 |
| 41351U, // SQRDMLSHv2i32 |
| 9126279U, // SQRDMLSHv2i32_indexed |
| 49544U, // SQRDMLSHv4i16 |
| 9118088U, // SQRDMLSHv4i16_indexed |
| 16774U, // SQRDMLSHv4i32 |
| 9126278U, // SQRDMLSHv4i32_indexed |
| 24966U, // SQRDMLSHv8i16 |
| 9118086U, // SQRDMLSHv8i16_indexed |
| 261U, // SQRDMULHv1i16 |
| 10166597U, // SQRDMULHv1i16_indexed |
| 261U, // SQRDMULHv1i32 |
| 10174789U, // SQRDMULHv1i32_indexed |
| 41287U, // SQRDMULHv2i32 |
| 10174791U, // SQRDMULHv2i32_indexed |
| 49480U, // SQRDMULHv4i16 |
| 10166600U, // SQRDMULHv4i16_indexed |
| 16710U, // SQRDMULHv4i32 |
| 10174790U, // SQRDMULHv4i32_indexed |
| 24902U, // SQRDMULHv8i16 |
| 10166598U, // SQRDMULHv8i16_indexed |
| 33095U, // SQRSHLv16i8 |
| 261U, // SQRSHLv1i16 |
| 261U, // SQRSHLv1i32 |
| 261U, // SQRSHLv1i64 |
| 261U, // SQRSHLv1i8 |
| 41287U, // SQRSHLv2i32 |
| 8517U, // SQRSHLv2i64 |
| 49480U, // SQRSHLv4i16 |
| 16710U, // SQRSHLv4i32 |
| 24902U, // SQRSHLv8i16 |
| 57672U, // SQRSHLv8i8 |
| 261U, // SQRSHRNb |
| 261U, // SQRSHRNh |
| 261U, // SQRSHRNs |
| 2310U, // SQRSHRNv16i8_shift |
| 261U, // SQRSHRNv2i32_shift |
| 262U, // SQRSHRNv4i16_shift |
| 2309U, // SQRSHRNv4i32_shift |
| 2310U, // SQRSHRNv8i16_shift |
| 262U, // SQRSHRNv8i8_shift |
| 261U, // SQRSHRUNb |
| 261U, // SQRSHRUNh |
| 261U, // SQRSHRUNs |
| 2310U, // SQRSHRUNv16i8_shift |
| 261U, // SQRSHRUNv2i32_shift |
| 262U, // SQRSHRUNv4i16_shift |
| 2309U, // SQRSHRUNv4i32_shift |
| 2310U, // SQRSHRUNv8i16_shift |
| 262U, // SQRSHRUNv8i8_shift |
| 261U, // SQSHLUb |
| 261U, // SQSHLUd |
| 261U, // SQSHLUh |
| 261U, // SQSHLUs |
| 263U, // SQSHLUv16i8_shift |
| 263U, // SQSHLUv2i32_shift |
| 261U, // SQSHLUv2i64_shift |
| 264U, // SQSHLUv4i16_shift |
| 262U, // SQSHLUv4i32_shift |
| 262U, // SQSHLUv8i16_shift |
| 264U, // SQSHLUv8i8_shift |
| 261U, // SQSHLb |
| 261U, // SQSHLd |
| 261U, // SQSHLh |
| 261U, // SQSHLs |
| 33095U, // SQSHLv16i8 |
| 263U, // SQSHLv16i8_shift |
| 261U, // SQSHLv1i16 |
| 261U, // SQSHLv1i32 |
| 261U, // SQSHLv1i64 |
| 261U, // SQSHLv1i8 |
| 41287U, // SQSHLv2i32 |
| 263U, // SQSHLv2i32_shift |
| 8517U, // SQSHLv2i64 |
| 261U, // SQSHLv2i64_shift |
| 49480U, // SQSHLv4i16 |
| 264U, // SQSHLv4i16_shift |
| 16710U, // SQSHLv4i32 |
| 262U, // SQSHLv4i32_shift |
| 24902U, // SQSHLv8i16 |
| 262U, // SQSHLv8i16_shift |
| 57672U, // SQSHLv8i8 |
| 264U, // SQSHLv8i8_shift |
| 261U, // SQSHRNb |
| 261U, // SQSHRNh |
| 261U, // SQSHRNs |
| 2310U, // SQSHRNv16i8_shift |
| 261U, // SQSHRNv2i32_shift |
| 262U, // SQSHRNv4i16_shift |
| 2309U, // SQSHRNv4i32_shift |
| 2310U, // SQSHRNv8i16_shift |
| 262U, // SQSHRNv8i8_shift |
| 261U, // SQSHRUNb |
| 261U, // SQSHRUNh |
| 261U, // SQSHRUNs |
| 2310U, // SQSHRUNv16i8_shift |
| 261U, // SQSHRUNv2i32_shift |
| 262U, // SQSHRUNv4i16_shift |
| 2309U, // SQSHRUNv4i32_shift |
| 2310U, // SQSHRUNv8i16_shift |
| 262U, // SQSHRUNv8i8_shift |
| 645U, // SQSUB_ZI_B |
| 709U, // SQSUB_ZI_D |
| 9U, // SQSUB_ZI_H |
| 773U, // SQSUB_ZI_S |
| 837U, // SQSUB_ZZZ_B |
| 901U, // SQSUB_ZZZ_D |
| 137U, // SQSUB_ZZZ_H |
| 1029U, // SQSUB_ZZZ_S |
| 33095U, // SQSUBv16i8 |
| 261U, // SQSUBv1i16 |
| 261U, // SQSUBv1i32 |
| 261U, // SQSUBv1i64 |
| 261U, // SQSUBv1i8 |
| 41287U, // SQSUBv2i32 |
| 8517U, // SQSUBv2i64 |
| 49480U, // SQSUBv4i16 |
| 16710U, // SQSUBv4i32 |
| 24902U, // SQSUBv8i16 |
| 57672U, // SQSUBv8i8 |
| 4U, // SQXTNv16i8 |
| 1U, // SQXTNv1i16 |
| 1U, // SQXTNv1i32 |
| 1U, // SQXTNv1i8 |
| 2U, // SQXTNv2i32 |
| 3U, // SQXTNv4i16 |
| 2U, // SQXTNv4i32 |
| 3U, // SQXTNv8i16 |
| 4U, // SQXTNv8i8 |
| 4U, // SQXTUNv16i8 |
| 1U, // SQXTUNv1i16 |
| 1U, // SQXTUNv1i32 |
| 1U, // SQXTUNv1i8 |
| 2U, // SQXTUNv2i32 |
| 3U, // SQXTUNv4i16 |
| 2U, // SQXTUNv4i32 |
| 3U, // SQXTUNv8i16 |
| 4U, // SQXTUNv8i8 |
| 33095U, // SRHADDv16i8 |
| 41287U, // SRHADDv2i32 |
| 49480U, // SRHADDv4i16 |
| 16710U, // SRHADDv4i32 |
| 24902U, // SRHADDv8i16 |
| 57672U, // SRHADDv8i8 |
| 2309U, // SRId |
| 2311U, // SRIv16i8_shift |
| 2311U, // SRIv2i32_shift |
| 2309U, // SRIv2i64_shift |
| 2312U, // SRIv4i16_shift |
| 2310U, // SRIv4i32_shift |
| 2310U, // SRIv8i16_shift |
| 2312U, // SRIv8i8_shift |
| 33095U, // SRSHLv16i8 |
| 261U, // SRSHLv1i64 |
| 41287U, // SRSHLv2i32 |
| 8517U, // SRSHLv2i64 |
| 49480U, // SRSHLv4i16 |
| 16710U, // SRSHLv4i32 |
| 24902U, // SRSHLv8i16 |
| 57672U, // SRSHLv8i8 |
| 261U, // SRSHRd |
| 263U, // SRSHRv16i8_shift |
| 263U, // SRSHRv2i32_shift |
| 261U, // SRSHRv2i64_shift |
| 264U, // SRSHRv4i16_shift |
| 262U, // SRSHRv4i32_shift |
| 262U, // SRSHRv8i16_shift |
| 264U, // SRSHRv8i8_shift |
| 2309U, // SRSRAd |
| 2311U, // SRSRAv16i8_shift |
| 2311U, // SRSRAv2i32_shift |
| 2309U, // SRSRAv2i64_shift |
| 2312U, // SRSRAv4i16_shift |
| 2310U, // SRSRAv4i32_shift |
| 2310U, // SRSRAv8i16_shift |
| 2312U, // SRSRAv8i8_shift |
| 263U, // SSHLLv16i8_shift |
| 263U, // SSHLLv2i32_shift |
| 264U, // SSHLLv4i16_shift |
| 262U, // SSHLLv4i32_shift |
| 262U, // SSHLLv8i16_shift |
| 264U, // SSHLLv8i8_shift |
| 33095U, // SSHLv16i8 |
| 261U, // SSHLv1i64 |
| 41287U, // SSHLv2i32 |
| 8517U, // SSHLv2i64 |
| 49480U, // SSHLv4i16 |
| 16710U, // SSHLv4i32 |
| 24902U, // SSHLv8i16 |
| 57672U, // SSHLv8i8 |
| 261U, // SSHRd |
| 263U, // SSHRv16i8_shift |
| 263U, // SSHRv2i32_shift |
| 261U, // SSHRv2i64_shift |
| 264U, // SSHRv4i16_shift |
| 262U, // SSHRv4i32_shift |
| 262U, // SSHRv8i16_shift |
| 264U, // SSHRv8i8_shift |
| 2309U, // SSRAd |
| 2311U, // SSRAv16i8_shift |
| 2311U, // SSRAv2i32_shift |
| 2309U, // SSRAv2i64_shift |
| 2312U, // SSRAv4i16_shift |
| 2310U, // SSRAv4i32_shift |
| 2310U, // SSRAv8i16_shift |
| 2312U, // SSRAv8i8_shift |
| 3205U, // SST1B_D |
| 3153U, // SST1B_D_IMM |
| 3269U, // SST1B_D_SXTW |
| 3333U, // SST1B_D_UXTW |
| 3153U, // SST1B_S_IMM |
| 3397U, // SST1B_S_SXTW |
| 3461U, // SST1B_S_UXTW |
| 3205U, // SST1D |
| 26U, // SST1D_IMM |
| 3525U, // SST1D_SCALED |
| 3269U, // SST1D_SXTW |
| 3589U, // SST1D_SXTW_SCALED |
| 3333U, // SST1D_UXTW |
| 3653U, // SST1D_UXTW_SCALED |
| 3205U, // SST1H_D |
| 26U, // SST1H_D_IMM |
| 3717U, // SST1H_D_SCALED |
| 3269U, // SST1H_D_SXTW |
| 3781U, // SST1H_D_SXTW_SCALED |
| 3333U, // SST1H_D_UXTW |
| 3845U, // SST1H_D_UXTW_SCALED |
| 26U, // SST1H_S_IMM |
| 3397U, // SST1H_S_SXTW |
| 3909U, // SST1H_S_SXTW_SCALED |
| 3461U, // SST1H_S_UXTW |
| 3973U, // SST1H_S_UXTW_SCALED |
| 3205U, // SST1W_D |
| 27U, // SST1W_D_IMM |
| 4037U, // SST1W_D_SCALED |
| 3269U, // SST1W_D_SXTW |
| 4101U, // SST1W_D_SXTW_SCALED |
| 3333U, // SST1W_D_UXTW |
| 4165U, // SST1W_D_UXTW_SCALED |
| 27U, // SST1W_IMM |
| 3397U, // SST1W_SXTW |
| 4229U, // SST1W_SXTW_SCALED |
| 3461U, // SST1W_UXTW |
| 4293U, // SST1W_UXTW_SCALED |
| 33095U, // SSUBLv16i8_v8i16 |
| 41287U, // SSUBLv2i32_v2i64 |
| 49480U, // SSUBLv4i16_v4i32 |
| 16710U, // SSUBLv4i32_v2i64 |
| 24902U, // SSUBLv8i16_v4i32 |
| 57672U, // SSUBLv8i8_v8i16 |
| 33094U, // SSUBWv16i8_v8i16 |
| 41285U, // SSUBWv2i32_v2i64 |
| 49478U, // SSUBWv4i16_v4i32 |
| 16709U, // SSUBWv4i32_v2i64 |
| 24902U, // SSUBWv8i16_v4i32 |
| 57670U, // SSUBWv8i8_v8i16 |
| 4357U, // ST1B |
| 4357U, // ST1B_D |
| 256261U, // ST1B_D_IMM |
| 4357U, // ST1B_H |
| 256261U, // ST1B_H_IMM |
| 256261U, // ST1B_IMM |
| 4357U, // ST1B_S |
| 256261U, // ST1B_S_IMM |
| 4421U, // ST1D |
| 256261U, // ST1D_IMM |
| 0U, // ST1Fourv16b |
| 0U, // ST1Fourv16b_POST |
| 0U, // ST1Fourv1d |
| 0U, // ST1Fourv1d_POST |
| 0U, // ST1Fourv2d |
| 0U, // ST1Fourv2d_POST |
| 0U, // ST1Fourv2s |
| 0U, // ST1Fourv2s_POST |
| 0U, // ST1Fourv4h |
| 0U, // ST1Fourv4h_POST |
| 0U, // ST1Fourv4s |
| 0U, // ST1Fourv4s_POST |
| 0U, // ST1Fourv8b |
| 0U, // ST1Fourv8b_POST |
| 0U, // ST1Fourv8h |
| 0U, // ST1Fourv8h_POST |
| 4485U, // ST1H |
| 4485U, // ST1H_D |
| 256261U, // ST1H_D_IMM |
| 256261U, // ST1H_IMM |
| 4485U, // ST1H_S |
| 256261U, // ST1H_S_IMM |
| 0U, // ST1Onev16b |
| 0U, // ST1Onev16b_POST |
| 0U, // ST1Onev1d |
| 0U, // ST1Onev1d_POST |
| 0U, // ST1Onev2d |
| 0U, // ST1Onev2d_POST |
| 0U, // ST1Onev2s |
| 0U, // ST1Onev2s_POST |
| 0U, // ST1Onev4h |
| 0U, // ST1Onev4h_POST |
| 0U, // ST1Onev4s |
| 0U, // ST1Onev4s_POST |
| 0U, // ST1Onev8b |
| 0U, // ST1Onev8b_POST |
| 0U, // ST1Onev8h |
| 0U, // ST1Onev8h_POST |
| 0U, // ST1Threev16b |
| 0U, // ST1Threev16b_POST |
| 0U, // ST1Threev1d |
| 0U, // ST1Threev1d_POST |
| 0U, // ST1Threev2d |
| 0U, // ST1Threev2d_POST |
| 0U, // ST1Threev2s |
| 0U, // ST1Threev2s_POST |
| 0U, // ST1Threev4h |
| 0U, // ST1Threev4h_POST |
| 0U, // ST1Threev4s |
| 0U, // ST1Threev4s_POST |
| 0U, // ST1Threev8b |
| 0U, // ST1Threev8b_POST |
| 0U, // ST1Threev8h |
| 0U, // ST1Threev8h_POST |
| 0U, // ST1Twov16b |
| 0U, // ST1Twov16b_POST |
| 0U, // ST1Twov1d |
| 0U, // ST1Twov1d_POST |
| 0U, // ST1Twov2d |
| 0U, // ST1Twov2d_POST |
| 0U, // ST1Twov2s |
| 0U, // ST1Twov2s_POST |
| 0U, // ST1Twov4h |
| 0U, // ST1Twov4h_POST |
| 0U, // ST1Twov4s |
| 0U, // ST1Twov4s_POST |
| 0U, // ST1Twov8b |
| 0U, // ST1Twov8b_POST |
| 0U, // ST1Twov8h |
| 0U, // ST1Twov8h_POST |
| 4741U, // ST1W |
| 4741U, // ST1W_D |
| 256261U, // ST1W_D_IMM |
| 256261U, // ST1W_IMM |
| 0U, // ST1i16 |
| 0U, // ST1i16_POST |
| 0U, // ST1i32 |
| 0U, // ST1i32_POST |
| 0U, // ST1i64 |
| 0U, // ST1i64_POST |
| 0U, // ST1i8 |
| 0U, // ST1i8_POST |
| 4357U, // ST2B |
| 258565U, // ST2B_IMM |
| 4421U, // ST2D |
| 258565U, // ST2D_IMM |
| 4485U, // ST2H |
| 258565U, // ST2H_IMM |
| 0U, // ST2Twov16b |
| 0U, // ST2Twov16b_POST |
| 0U, // ST2Twov2d |
| 0U, // ST2Twov2d_POST |
| 0U, // ST2Twov2s |
| 0U, // ST2Twov2s_POST |
| 0U, // ST2Twov4h |
| 0U, // ST2Twov4h_POST |
| 0U, // ST2Twov4s |
| 0U, // ST2Twov4s_POST |
| 0U, // ST2Twov8b |
| 0U, // ST2Twov8b_POST |
| 0U, // ST2Twov8h |
| 0U, // ST2Twov8h_POST |
| 4741U, // ST2W |
| 258565U, // ST2W_IMM |
| 0U, // ST2i16 |
| 0U, // ST2i16_POST |
| 0U, // ST2i32 |
| 0U, // ST2i32_POST |
| 0U, // ST2i64 |
| 0U, // ST2i64_POST |
| 0U, // ST2i8 |
| 0U, // ST2i8_POST |
| 4357U, // ST3B |
| 4869U, // ST3B_IMM |
| 4421U, // ST3D |
| 4869U, // ST3D_IMM |
| 4485U, // ST3H |
| 4869U, // ST3H_IMM |
| 0U, // ST3Threev16b |
| 0U, // ST3Threev16b_POST |
| 0U, // ST3Threev2d |
| 0U, // ST3Threev2d_POST |
| 0U, // ST3Threev2s |
| 0U, // ST3Threev2s_POST |
| 0U, // ST3Threev4h |
| 0U, // ST3Threev4h_POST |
| 0U, // ST3Threev4s |
| 0U, // ST3Threev4s_POST |
| 0U, // ST3Threev8b |
| 0U, // ST3Threev8b_POST |
| 0U, // ST3Threev8h |
| 0U, // ST3Threev8h_POST |
| 4741U, // ST3W |
| 4869U, // ST3W_IMM |
| 0U, // ST3i16 |
| 0U, // ST3i16_POST |
| 0U, // ST3i32 |
| 0U, // ST3i32_POST |
| 0U, // ST3i64 |
| 0U, // ST3i64_POST |
| 0U, // ST3i8 |
| 0U, // ST3i8_POST |
| 4357U, // ST4B |
| 258757U, // ST4B_IMM |
| 4421U, // ST4D |
| 258757U, // ST4D_IMM |
| 0U, // ST4Fourv16b |
| 0U, // ST4Fourv16b_POST |
| 0U, // ST4Fourv2d |
| 0U, // ST4Fourv2d_POST |
| 0U, // ST4Fourv2s |
| 0U, // ST4Fourv2s_POST |
| 0U, // ST4Fourv4h |
| 0U, // ST4Fourv4h_POST |
| 0U, // ST4Fourv4s |
| 0U, // ST4Fourv4s_POST |
| 0U, // ST4Fourv8b |
| 0U, // ST4Fourv8b_POST |
| 0U, // ST4Fourv8h |
| 0U, // ST4Fourv8h_POST |
| 4485U, // ST4H |
| 258757U, // ST4H_IMM |
| 4741U, // ST4W |
| 258757U, // ST4W_IMM |
| 0U, // ST4i16 |
| 0U, // ST4i16_POST |
| 0U, // ST4i32 |
| 0U, // ST4i32_POST |
| 0U, // ST4i64 |
| 0U, // ST4i64_POST |
| 0U, // ST4i8 |
| 0U, // ST4i8_POST |
| 27U, // STLLRB |
| 27U, // STLLRH |
| 27U, // STLLRW |
| 27U, // STLLRX |
| 27U, // STLRB |
| 27U, // STLRH |
| 27U, // STLRW |
| 27U, // STLRX |
| 114949U, // STLURBi |
| 114949U, // STLURHi |
| 114949U, // STLURWi |
| 114949U, // STLURXi |
| 286981U, // STLXPW |
| 286981U, // STLXPX |
| 114955U, // STLXRB |
| 114955U, // STLXRH |
| 114955U, // STLXRW |
| 114955U, // STLXRX |
| 11084043U, // STNPDi |
| 11608331U, // STNPQi |
| 12132619U, // STNPSi |
| 12132619U, // STNPWi |
| 11084043U, // STNPXi |
| 256261U, // STNT1B_ZRI |
| 4357U, // STNT1B_ZRR |
| 256261U, // STNT1D_ZRI |
| 4421U, // STNT1D_ZRR |
| 256261U, // STNT1H_ZRI |
| 4485U, // STNT1H_ZRR |
| 256261U, // STNT1W_ZRI |
| 4741U, // STNT1W_ZRR |
| 11084043U, // STPDi |
| 12847371U, // STPDpost |
| 180431115U, // STPDpre |
| 11608331U, // STPQi |
| 13371659U, // STPQpost |
| 180955403U, // STPQpre |
| 12132619U, // STPSi |
| 13895947U, // STPSpost |
| 181479691U, // STPSpre |
| 12132619U, // STPWi |
| 13895947U, // STPWpost |
| 181479691U, // STPWpre |
| 11084043U, // STPXi |
| 12847371U, // STPXpost |
| 180431115U, // STPXpre |
| 28U, // STRBBpost |
| 272645U, // STRBBpre |
| 14229765U, // STRBBroW |
| 14754053U, // STRBBroX |
| 4997U, // STRBBui |
| 28U, // STRBpost |
| 272645U, // STRBpre |
| 14229765U, // STRBroW |
| 14754053U, // STRBroX |
| 4997U, // STRBui |
| 28U, // STRDpost |
| 272645U, // STRDpre |
| 15278341U, // STRDroW |
| 15802629U, // STRDroX |
| 5061U, // STRDui |
| 28U, // STRHHpost |
| 272645U, // STRHHpre |
| 16326917U, // STRHHroW |
| 16851205U, // STRHHroX |
| 5125U, // STRHHui |
| 28U, // STRHpost |
| 272645U, // STRHpre |
| 16326917U, // STRHroW |
| 16851205U, // STRHroX |
| 5125U, // STRHui |
| 28U, // STRQpost |
| 272645U, // STRQpre |
| 17375493U, // STRQroW |
| 17899781U, // STRQroX |
| 5189U, // STRQui |
| 28U, // STRSpost |
| 272645U, // STRSpre |
| 18424069U, // STRSroW |
| 18948357U, // STRSroX |
| 5253U, // STRSui |
| 28U, // STRWpost |
| 272645U, // STRWpre |
| 18424069U, // STRWroW |
| 18948357U, // STRWroX |
| 5253U, // STRWui |
| 28U, // STRXpost |
| 272645U, // STRXpre |
| 15278341U, // STRXroW |
| 15802629U, // STRXroX |
| 5061U, // STRXui |
| 254213U, // STR_PXI |
| 254213U, // STR_ZXI |
| 114949U, // STTRBi |
| 114949U, // STTRHi |
| 114949U, // STTRWi |
| 114949U, // STTRXi |
| 114949U, // STURBBi |
| 114949U, // STURBi |
| 114949U, // STURDi |
| 114949U, // STURHHi |
| 114949U, // STURHi |
| 114949U, // STURQi |
| 114949U, // STURSi |
| 114949U, // STURWi |
| 114949U, // STURXi |
| 286981U, // STXPW |
| 286981U, // STXPX |
| 114955U, // STXRB |
| 114955U, // STXRH |
| 114955U, // STXRW |
| 114955U, // STXRX |
| 8517U, // SUBHNv2i64_v2i32 |
| 8581U, // SUBHNv2i64_v4i32 |
| 16710U, // SUBHNv4i32_v4i16 |
| 16774U, // SUBHNv4i32_v8i16 |
| 24966U, // SUBHNv8i16_v16i8 |
| 24902U, // SUBHNv8i16_v8i8 |
| 645U, // SUBR_ZI_B |
| 709U, // SUBR_ZI_D |
| 9U, // SUBR_ZI_H |
| 773U, // SUBR_ZI_S |
| 74560U, // SUBR_ZPmZ_B |
| 598912U, // SUBR_ZPmZ_D |
| 1131465U, // SUBR_ZPmZ_H |
| 1647616U, // SUBR_ZPmZ_S |
| 453U, // SUBSWri |
| 0U, // SUBSWrr |
| 517U, // SUBSWrs |
| 581U, // SUBSWrx |
| 453U, // SUBSXri |
| 0U, // SUBSXrr |
| 517U, // SUBSXrs |
| 581U, // SUBSXrx |
| 65797U, // SUBSXrx64 |
| 453U, // SUBWri |
| 0U, // SUBWrr |
| 517U, // SUBWrs |
| 581U, // SUBWrx |
| 453U, // SUBXri |
| 0U, // SUBXrr |
| 517U, // SUBXrs |
| 581U, // SUBXrx |
| 65797U, // SUBXrx64 |
| 645U, // SUB_ZI_B |
| 709U, // SUB_ZI_D |
| 9U, // SUB_ZI_H |
| 773U, // SUB_ZI_S |
| 74560U, // SUB_ZPmZ_B |
| 598912U, // SUB_ZPmZ_D |
| 1131465U, // SUB_ZPmZ_H |
| 1647616U, // SUB_ZPmZ_S |
| 837U, // SUB_ZZZ_B |
| 901U, // SUB_ZZZ_D |
| 137U, // SUB_ZZZ_H |
| 1029U, // SUB_ZZZ_S |
| 33095U, // SUBv16i8 |
| 261U, // SUBv1i64 |
| 41287U, // SUBv2i32 |
| 8517U, // SUBv2i64 |
| 49480U, // SUBv4i16 |
| 16710U, // SUBv4i32 |
| 24902U, // SUBv8i16 |
| 57672U, // SUBv8i8 |
| 1U, // SUNPKHI_ZZ_D |
| 0U, // SUNPKHI_ZZ_H |
| 1U, // SUNPKHI_ZZ_S |
| 1U, // SUNPKLO_ZZ_D |
| 0U, // SUNPKLO_ZZ_H |
| 1U, // SUNPKLO_ZZ_S |
| 1U, // SUQADDv16i8 |
| 1U, // SUQADDv1i16 |
| 1U, // SUQADDv1i32 |
| 1U, // SUQADDv1i64 |
| 1U, // SUQADDv1i8 |
| 2U, // SUQADDv2i32 |
| 2U, // SUQADDv2i64 |
| 3U, // SUQADDv4i16 |
| 3U, // SUQADDv4i32 |
| 4U, // SUQADDv8i16 |
| 4U, // SUQADDv8i8 |
| 0U, // SVC |
| 0U, // SWPAB |
| 0U, // SWPAH |
| 0U, // SWPALB |
| 0U, // SWPALH |
| 0U, // SWPALW |
| 0U, // SWPALX |
| 0U, // SWPAW |
| 0U, // SWPAX |
| 0U, // SWPB |
| 0U, // SWPH |
| 0U, // SWPLB |
| 0U, // SWPLH |
| 0U, // SWPLW |
| 0U, // SWPLX |
| 0U, // SWPW |
| 0U, // SWPX |
| 64U, // SXTB_ZPmZ_D |
| 128U, // SXTB_ZPmZ_H |
| 192U, // SXTB_ZPmZ_S |
| 64U, // SXTH_ZPmZ_D |
| 192U, // SXTH_ZPmZ_S |
| 64U, // SXTW_ZPmZ_D |
| 5445U, // SYSLxt |
| 0U, // SYSxt |
| 0U, // TBL_ZZZ_B |
| 0U, // TBL_ZZZ_D |
| 0U, // TBL_ZZZ_H |
| 0U, // TBL_ZZZ_S |
| 1U, // TBLv16i8Four |
| 1U, // TBLv16i8One |
| 1U, // TBLv16i8Three |
| 1U, // TBLv16i8Two |
| 4U, // TBLv8i8Four |
| 4U, // TBLv8i8One |
| 4U, // TBLv8i8Three |
| 4U, // TBLv8i8Two |
| 5509U, // TBNZW |
| 5509U, // TBNZX |
| 1U, // TBXv16i8Four |
| 1U, // TBXv16i8One |
| 1U, // TBXv16i8Three |
| 1U, // TBXv16i8Two |
| 4U, // TBXv8i8Four |
| 4U, // TBXv8i8One |
| 4U, // TBXv8i8Three |
| 4U, // TBXv8i8Two |
| 5509U, // TBZW |
| 5509U, // TBZX |
| 0U, // TCRETURNdi |
| 0U, // TCRETURNri |
| 0U, // TLSDESCCALL |
| 0U, // TLSDESC_CALLSEQ |
| 837U, // TRN1_PPP_B |
| 901U, // TRN1_PPP_D |
| 137U, // TRN1_PPP_H |
| 1029U, // TRN1_PPP_S |
| 837U, // TRN1_ZZZ_B |
| 901U, // TRN1_ZZZ_D |
| 137U, // TRN1_ZZZ_H |
| 1029U, // TRN1_ZZZ_S |
| 33095U, // TRN1v16i8 |
| 41287U, // TRN1v2i32 |
| 8517U, // TRN1v2i64 |
| 49480U, // TRN1v4i16 |
| 16710U, // TRN1v4i32 |
| 24902U, // TRN1v8i16 |
| 57672U, // TRN1v8i8 |
| 837U, // TRN2_PPP_B |
| 901U, // TRN2_PPP_D |
| 137U, // TRN2_PPP_H |
| 1029U, // TRN2_PPP_S |
| 837U, // TRN2_ZZZ_B |
| 901U, // TRN2_ZZZ_D |
| 137U, // TRN2_ZZZ_H |
| 1029U, // TRN2_ZZZ_S |
| 33095U, // TRN2v16i8 |
| 41287U, // TRN2v2i32 |
| 8517U, // TRN2v2i64 |
| 49480U, // TRN2v4i16 |
| 16710U, // TRN2v4i32 |
| 24902U, // TRN2v8i16 |
| 57672U, // TRN2v8i8 |
| 0U, // TSB |
| 33159U, // UABALv16i8_v8i16 |
| 41351U, // UABALv2i32_v2i64 |
| 49544U, // UABALv4i16_v4i32 |
| 16774U, // UABALv4i32_v2i64 |
| 24966U, // UABALv8i16_v4i32 |
| 57736U, // UABALv8i8_v8i16 |
| 33159U, // UABAv16i8 |
| 41351U, // UABAv2i32 |
| 49544U, // UABAv4i16 |
| 16774U, // UABAv4i32 |
| 24966U, // UABAv8i16 |
| 57736U, // UABAv8i8 |
| 33095U, // UABDLv16i8_v8i16 |
| 41287U, // UABDLv2i32_v2i64 |
| 49480U, // UABDLv4i16_v4i32 |
| 16710U, // UABDLv4i32_v2i64 |
| 24902U, // UABDLv8i16_v4i32 |
| 57672U, // UABDLv8i8_v8i16 |
| 74560U, // UABD_ZPmZ_B |
| 598912U, // UABD_ZPmZ_D |
| 1131465U, // UABD_ZPmZ_H |
| 1647616U, // UABD_ZPmZ_S |
| 33095U, // UABDv16i8 |
| 41287U, // UABDv2i32 |
| 49480U, // UABDv4i16 |
| 16710U, // UABDv4i32 |
| 24902U, // UABDv8i16 |
| 57672U, // UABDv8i8 |
| 1U, // UADALPv16i8_v8i16 |
| 2U, // UADALPv2i32_v1i64 |
| 3U, // UADALPv4i16_v2i32 |
| 3U, // UADALPv4i32_v2i64 |
| 4U, // UADALPv8i16_v4i32 |
| 4U, // UADALPv8i8_v4i16 |
| 1U, // UADDLPv16i8_v8i16 |
| 2U, // UADDLPv2i32_v1i64 |
| 3U, // UADDLPv4i16_v2i32 |
| 3U, // UADDLPv4i32_v2i64 |
| 4U, // UADDLPv8i16_v4i32 |
| 4U, // UADDLPv8i8_v4i16 |
| 1U, // UADDLVv16i8v |
| 3U, // UADDLVv4i16v |
| 3U, // UADDLVv4i32v |
| 4U, // UADDLVv8i16v |
| 4U, // UADDLVv8i8v |
| 33095U, // UADDLv16i8_v8i16 |
| 41287U, // UADDLv2i32_v2i64 |
| 49480U, // UADDLv4i16_v4i32 |
| 16710U, // UADDLv4i32_v2i64 |
| 24902U, // UADDLv8i16_v4i32 |
| 57672U, // UADDLv8i8_v8i16 |
| 837U, // UADDV_VPZ_B |
| 901U, // UADDV_VPZ_D |
| 2245U, // UADDV_VPZ_H |
| 1029U, // UADDV_VPZ_S |
| 33094U, // UADDWv16i8_v8i16 |
| 41285U, // UADDWv2i32_v2i64 |
| 49478U, // UADDWv4i16_v4i32 |
| 16709U, // UADDWv4i32_v2i64 |
| 24902U, // UADDWv8i16_v4i32 |
| 57670U, // UADDWv8i8_v8i16 |
| 2171141U, // UBFMWri |
| 2171141U, // UBFMXri |
| 261U, // UCVTFSWDri |
| 261U, // UCVTFSWHri |
| 261U, // UCVTFSWSri |
| 261U, // UCVTFSXDri |
| 261U, // UCVTFSXHri |
| 261U, // UCVTFSXSri |
| 1U, // UCVTFUWDri |
| 1U, // UCVTFUWHri |
| 1U, // UCVTFUWSri |
| 1U, // UCVTFUXDri |
| 1U, // UCVTFUXHri |
| 1U, // UCVTFUXSri |
| 64U, // UCVTF_ZPmZ_DtoD |
| 153U, // UCVTF_ZPmZ_DtoH |
| 64U, // UCVTF_ZPmZ_DtoS |
| 128U, // UCVTF_ZPmZ_HtoH |
| 192U, // UCVTF_ZPmZ_StoD |
| 152U, // UCVTF_ZPmZ_StoH |
| 192U, // UCVTF_ZPmZ_StoS |
| 261U, // UCVTFd |
| 261U, // UCVTFh |
| 261U, // UCVTFs |
| 1U, // UCVTFv1i16 |
| 1U, // UCVTFv1i32 |
| 1U, // UCVTFv1i64 |
| 2U, // UCVTFv2f32 |
| 2U, // UCVTFv2f64 |
| 263U, // UCVTFv2i32_shift |
| 261U, // UCVTFv2i64_shift |
| 3U, // UCVTFv4f16 |
| 3U, // UCVTFv4f32 |
| 264U, // UCVTFv4i16_shift |
| 262U, // UCVTFv4i32_shift |
| 4U, // UCVTFv8f16 |
| 262U, // UCVTFv8i16_shift |
| 598912U, // UDIVR_ZPmZ_D |
| 1647616U, // UDIVR_ZPmZ_S |
| 261U, // UDIVWr |
| 261U, // UDIVXr |
| 598912U, // UDIV_ZPmZ_D |
| 1647616U, // UDIV_ZPmZ_S |
| 41U, // UDOT_ZZZI_D |
| 41U, // UDOT_ZZZI_S |
| 1U, // UDOT_ZZZ_D |
| 1U, // UDOT_ZZZ_S |
| 278919U, // UDOTlanev16i8 |
| 278920U, // UDOTlanev8i8 |
| 33159U, // UDOTv16i8 |
| 57736U, // UDOTv8i8 |
| 33095U, // UHADDv16i8 |
| 41287U, // UHADDv2i32 |
| 49480U, // UHADDv4i16 |
| 16710U, // UHADDv4i32 |
| 24902U, // UHADDv8i16 |
| 57672U, // UHADDv8i8 |
| 33095U, // UHSUBv16i8 |
| 41287U, // UHSUBv2i32 |
| 49480U, // UHSUBv4i16 |
| 16710U, // UHSUBv4i32 |
| 24902U, // UHSUBv8i16 |
| 57672U, // UHSUBv8i8 |
| 2171141U, // UMADDLrrr |
| 33095U, // UMAXPv16i8 |
| 41287U, // UMAXPv2i32 |
| 49480U, // UMAXPv4i16 |
| 16710U, // UMAXPv4i32 |
| 24902U, // UMAXPv8i16 |
| 57672U, // UMAXPv8i8 |
| 837U, // UMAXV_VPZ_B |
| 901U, // UMAXV_VPZ_D |
| 2245U, // UMAXV_VPZ_H |
| 1029U, // UMAXV_VPZ_S |
| 1U, // UMAXVv16i8v |
| 3U, // UMAXVv4i16v |
| 3U, // UMAXVv4i32v |
| 4U, // UMAXVv8i16v |
| 4U, // UMAXVv8i8v |
| 5573U, // UMAX_ZI_B |
| 5573U, // UMAX_ZI_D |
| 45U, // UMAX_ZI_H |
| 5573U, // UMAX_ZI_S |
| 74560U, // UMAX_ZPmZ_B |
| 598912U, // UMAX_ZPmZ_D |
| 1131465U, // UMAX_ZPmZ_H |
| 1647616U, // UMAX_ZPmZ_S |
| 33095U, // UMAXv16i8 |
| 41287U, // UMAXv2i32 |
| 49480U, // UMAXv4i16 |
| 16710U, // UMAXv4i32 |
| 24902U, // UMAXv8i16 |
| 57672U, // UMAXv8i8 |
| 33095U, // UMINPv16i8 |
| 41287U, // UMINPv2i32 |
| 49480U, // UMINPv4i16 |
| 16710U, // UMINPv4i32 |
| 24902U, // UMINPv8i16 |
| 57672U, // UMINPv8i8 |
| 837U, // UMINV_VPZ_B |
| 901U, // UMINV_VPZ_D |
| 2245U, // UMINV_VPZ_H |
| 1029U, // UMINV_VPZ_S |
| 1U, // UMINVv16i8v |
| 3U, // UMINVv4i16v |
| 3U, // UMINVv4i32v |
| 4U, // UMINVv8i16v |
| 4U, // UMINVv8i8v |
| 5573U, // UMIN_ZI_B |
| 5573U, // UMIN_ZI_D |
| 45U, // UMIN_ZI_H |
| 5573U, // UMIN_ZI_S |
| 74560U, // UMIN_ZPmZ_B |
| 598912U, // UMIN_ZPmZ_D |
| 1131465U, // UMIN_ZPmZ_H |
| 1647616U, // UMIN_ZPmZ_S |
| 33095U, // UMINv16i8 |
| 41287U, // UMINv2i32 |
| 49480U, // UMINv4i16 |
| 16710U, // UMINv4i32 |
| 24902U, // UMINv8i16 |
| 57672U, // UMINv8i8 |
| 33159U, // UMLALv16i8_v8i16 |
| 9126279U, // UMLALv2i32_indexed |
| 41351U, // UMLALv2i32_v2i64 |
| 9118088U, // UMLALv4i16_indexed |
| 49544U, // UMLALv4i16_v4i32 |
| 9126278U, // UMLALv4i32_indexed |
| 16774U, // UMLALv4i32_v2i64 |
| 9118086U, // UMLALv8i16_indexed |
| 24966U, // UMLALv8i16_v4i32 |
| 57736U, // UMLALv8i8_v8i16 |
| 33159U, // UMLSLv16i8_v8i16 |
| 9126279U, // UMLSLv2i32_indexed |
| 41351U, // UMLSLv2i32_v2i64 |
| 9118088U, // UMLSLv4i16_indexed |
| 49544U, // UMLSLv4i16_v4i32 |
| 9126278U, // UMLSLv4i32_indexed |
| 16774U, // UMLSLv4i32_v2i64 |
| 9118086U, // UMLSLv8i16_indexed |
| 24966U, // UMLSLv8i16_v4i32 |
| 57736U, // UMLSLv8i8_v8i16 |
| 2770U, // UMOVvi16 |
| 2770U, // UMOVvi32 |
| 2771U, // UMOVvi64 |
| 2771U, // UMOVvi8 |
| 2171141U, // UMSUBLrrr |
| 74560U, // UMULH_ZPmZ_B |
| 598912U, // UMULH_ZPmZ_D |
| 1131465U, // UMULH_ZPmZ_H |
| 1647616U, // UMULH_ZPmZ_S |
| 261U, // UMULHrr |
| 33095U, // UMULLv16i8_v8i16 |
| 10174791U, // UMULLv2i32_indexed |
| 41287U, // UMULLv2i32_v2i64 |
| 10166600U, // UMULLv4i16_indexed |
| 49480U, // UMULLv4i16_v4i32 |
| 10174790U, // UMULLv4i32_indexed |
| 16710U, // UMULLv4i32_v2i64 |
| 10166598U, // UMULLv8i16_indexed |
| 24902U, // UMULLv8i16_v4i32 |
| 57672U, // UMULLv8i8_v8i16 |
| 645U, // UQADD_ZI_B |
| 709U, // UQADD_ZI_D |
| 9U, // UQADD_ZI_H |
| 773U, // UQADD_ZI_S |
| 837U, // UQADD_ZZZ_B |
| 901U, // UQADD_ZZZ_D |
| 137U, // UQADD_ZZZ_H |
| 1029U, // UQADD_ZZZ_S |
| 33095U, // UQADDv16i8 |
| 261U, // UQADDv1i16 |
| 261U, // UQADDv1i32 |
| 261U, // UQADDv1i64 |
| 261U, // UQADDv1i8 |
| 41287U, // UQADDv2i32 |
| 8517U, // UQADDv2i64 |
| 49480U, // UQADDv4i16 |
| 16710U, // UQADDv4i32 |
| 24902U, // UQADDv8i16 |
| 57672U, // UQADDv8i8 |
| 0U, // UQDECB_WPiI |
| 0U, // UQDECB_XPiI |
| 0U, // UQDECD_WPiI |
| 0U, // UQDECD_XPiI |
| 0U, // UQDECD_ZPiI |
| 0U, // UQDECH_WPiI |
| 0U, // UQDECH_XPiI |
| 0U, // UQDECH_ZPiI |
| 1U, // UQDECP_WP_B |
| 1U, // UQDECP_WP_D |
| 1U, // UQDECP_WP_H |
| 1U, // UQDECP_WP_S |
| 1U, // UQDECP_XP_B |
| 1U, // UQDECP_XP_D |
| 1U, // UQDECP_XP_H |
| 1U, // UQDECP_XP_S |
| 1U, // UQDECP_ZP_D |
| 0U, // UQDECP_ZP_H |
| 1U, // UQDECP_ZP_S |
| 0U, // UQDECW_WPiI |
| 0U, // UQDECW_XPiI |
| 0U, // UQDECW_ZPiI |
| 0U, // UQINCB_WPiI |
| 0U, // UQINCB_XPiI |
| 0U, // UQINCD_WPiI |
| 0U, // UQINCD_XPiI |
| 0U, // UQINCD_ZPiI |
| 0U, // UQINCH_WPiI |
| 0U, // UQINCH_XPiI |
| 0U, // UQINCH_ZPiI |
| 1U, // UQINCP_WP_B |
| 1U, // UQINCP_WP_D |
| 1U, // UQINCP_WP_H |
| 1U, // UQINCP_WP_S |
| 1U, // UQINCP_XP_B |
| 1U, // UQINCP_XP_D |
| 1U, // UQINCP_XP_H |
| 1U, // UQINCP_XP_S |
| 1U, // UQINCP_ZP_D |
| 0U, // UQINCP_ZP_H |
| 1U, // UQINCP_ZP_S |
| 0U, // UQINCW_WPiI |
| 0U, // UQINCW_XPiI |
| 0U, // UQINCW_ZPiI |
| 33095U, // UQRSHLv16i8 |
| 261U, // UQRSHLv1i16 |
| 261U, // UQRSHLv1i32 |
| 261U, // UQRSHLv1i64 |
| 261U, // UQRSHLv1i8 |
| 41287U, // UQRSHLv2i32 |
| 8517U, // UQRSHLv2i64 |
| 49480U, // UQRSHLv4i16 |
| 16710U, // UQRSHLv4i32 |
| 24902U, // UQRSHLv8i16 |
| 57672U, // UQRSHLv8i8 |
| 261U, // UQRSHRNb |
| 261U, // UQRSHRNh |
| 261U, // UQRSHRNs |
| 2310U, // UQRSHRNv16i8_shift |
| 261U, // UQRSHRNv2i32_shift |
| 262U, // UQRSHRNv4i16_shift |
| 2309U, // UQRSHRNv4i32_shift |
| 2310U, // UQRSHRNv8i16_shift |
| 262U, // UQRSHRNv8i8_shift |
| 261U, // UQSHLb |
| 261U, // UQSHLd |
| 261U, // UQSHLh |
| 261U, // UQSHLs |
| 33095U, // UQSHLv16i8 |
| 263U, // UQSHLv16i8_shift |
| 261U, // UQSHLv1i16 |
| 261U, // UQSHLv1i32 |
| 261U, // UQSHLv1i64 |
| 261U, // UQSHLv1i8 |
| 41287U, // UQSHLv2i32 |
| 263U, // UQSHLv2i32_shift |
| 8517U, // UQSHLv2i64 |
| 261U, // UQSHLv2i64_shift |
| 49480U, // UQSHLv4i16 |
| 264U, // UQSHLv4i16_shift |
| 16710U, // UQSHLv4i32 |
| 262U, // UQSHLv4i32_shift |
| 24902U, // UQSHLv8i16 |
| 262U, // UQSHLv8i16_shift |
| 57672U, // UQSHLv8i8 |
| 264U, // UQSHLv8i8_shift |
| 261U, // UQSHRNb |
| 261U, // UQSHRNh |
| 261U, // UQSHRNs |
| 2310U, // UQSHRNv16i8_shift |
| 261U, // UQSHRNv2i32_shift |
| 262U, // UQSHRNv4i16_shift |
| 2309U, // UQSHRNv4i32_shift |
| 2310U, // UQSHRNv8i16_shift |
| 262U, // UQSHRNv8i8_shift |
| 645U, // UQSUB_ZI_B |
| 709U, // UQSUB_ZI_D |
| 9U, // UQSUB_ZI_H |
| 773U, // UQSUB_ZI_S |
| 837U, // UQSUB_ZZZ_B |
| 901U, // UQSUB_ZZZ_D |
| 137U, // UQSUB_ZZZ_H |
| 1029U, // UQSUB_ZZZ_S |
| 33095U, // UQSUBv16i8 |
| 261U, // UQSUBv1i16 |
| 261U, // UQSUBv1i32 |
| 261U, // UQSUBv1i64 |
| 261U, // UQSUBv1i8 |
| 41287U, // UQSUBv2i32 |
| 8517U, // UQSUBv2i64 |
| 49480U, // UQSUBv4i16 |
| 16710U, // UQSUBv4i32 |
| 24902U, // UQSUBv8i16 |
| 57672U, // UQSUBv8i8 |
| 4U, // UQXTNv16i8 |
| 1U, // UQXTNv1i16 |
| 1U, // UQXTNv1i32 |
| 1U, // UQXTNv1i8 |
| 2U, // UQXTNv2i32 |
| 3U, // UQXTNv4i16 |
| 2U, // UQXTNv4i32 |
| 3U, // UQXTNv8i16 |
| 4U, // UQXTNv8i8 |
| 2U, // URECPEv2i32 |
| 3U, // URECPEv4i32 |
| 33095U, // URHADDv16i8 |
| 41287U, // URHADDv2i32 |
| 49480U, // URHADDv4i16 |
| 16710U, // URHADDv4i32 |
| 24902U, // URHADDv8i16 |
| 57672U, // URHADDv8i8 |
| 33095U, // URSHLv16i8 |
| 261U, // URSHLv1i64 |
| 41287U, // URSHLv2i32 |
| 8517U, // URSHLv2i64 |
| 49480U, // URSHLv4i16 |
| 16710U, // URSHLv4i32 |
| 24902U, // URSHLv8i16 |
| 57672U, // URSHLv8i8 |
| 261U, // URSHRd |
| 263U, // URSHRv16i8_shift |
| 263U, // URSHRv2i32_shift |
| 261U, // URSHRv2i64_shift |
| 264U, // URSHRv4i16_shift |
| 262U, // URSHRv4i32_shift |
| 262U, // URSHRv8i16_shift |
| 264U, // URSHRv8i8_shift |
| 2U, // URSQRTEv2i32 |
| 3U, // URSQRTEv4i32 |
| 2309U, // URSRAd |
| 2311U, // URSRAv16i8_shift |
| 2311U, // URSRAv2i32_shift |
| 2309U, // URSRAv2i64_shift |
| 2312U, // URSRAv4i16_shift |
| 2310U, // URSRAv4i32_shift |
| 2310U, // URSRAv8i16_shift |
| 2312U, // URSRAv8i8_shift |
| 263U, // USHLLv16i8_shift |
| 263U, // USHLLv2i32_shift |
| 264U, // USHLLv4i16_shift |
| 262U, // USHLLv4i32_shift |
| 262U, // USHLLv8i16_shift |
| 264U, // USHLLv8i8_shift |
| 33095U, // USHLv16i8 |
| 261U, // USHLv1i64 |
| 41287U, // USHLv2i32 |
| 8517U, // USHLv2i64 |
| 49480U, // USHLv4i16 |
| 16710U, // USHLv4i32 |
| 24902U, // USHLv8i16 |
| 57672U, // USHLv8i8 |
| 261U, // USHRd |
| 263U, // USHRv16i8_shift |
| 263U, // USHRv2i32_shift |
| 261U, // USHRv2i64_shift |
| 264U, // USHRv4i16_shift |
| 262U, // USHRv4i32_shift |
| 262U, // USHRv8i16_shift |
| 264U, // USHRv8i8_shift |
| 1U, // USQADDv16i8 |
| 1U, // USQADDv1i16 |
| 1U, // USQADDv1i32 |
| 1U, // USQADDv1i64 |
| 1U, // USQADDv1i8 |
| 2U, // USQADDv2i32 |
| 2U, // USQADDv2i64 |
| 3U, // USQADDv4i16 |
| 3U, // USQADDv4i32 |
| 4U, // USQADDv8i16 |
| 4U, // USQADDv8i8 |
| 2309U, // USRAd |
| 2311U, // USRAv16i8_shift |
| 2311U, // USRAv2i32_shift |
| 2309U, // USRAv2i64_shift |
| 2312U, // USRAv4i16_shift |
| 2310U, // USRAv4i32_shift |
| 2310U, // USRAv8i16_shift |
| 2312U, // USRAv8i8_shift |
| 33095U, // USUBLv16i8_v8i16 |
| 41287U, // USUBLv2i32_v2i64 |
| 49480U, // USUBLv4i16_v4i32 |
| 16710U, // USUBLv4i32_v2i64 |
| 24902U, // USUBLv8i16_v4i32 |
| 57672U, // USUBLv8i8_v8i16 |
| 33094U, // USUBWv16i8_v8i16 |
| 41285U, // USUBWv2i32_v2i64 |
| 49478U, // USUBWv4i16_v4i32 |
| 16709U, // USUBWv4i32_v2i64 |
| 24902U, // USUBWv8i16_v4i32 |
| 57670U, // USUBWv8i8_v8i16 |
| 1U, // UUNPKHI_ZZ_D |
| 0U, // UUNPKHI_ZZ_H |
| 1U, // UUNPKHI_ZZ_S |
| 1U, // UUNPKLO_ZZ_D |
| 0U, // UUNPKLO_ZZ_H |
| 1U, // UUNPKLO_ZZ_S |
| 64U, // UXTB_ZPmZ_D |
| 128U, // UXTB_ZPmZ_H |
| 192U, // UXTB_ZPmZ_S |
| 64U, // UXTH_ZPmZ_D |
| 192U, // UXTH_ZPmZ_S |
| 64U, // UXTW_ZPmZ_D |
| 837U, // UZP1_PPP_B |
| 901U, // UZP1_PPP_D |
| 137U, // UZP1_PPP_H |
| 1029U, // UZP1_PPP_S |
| 837U, // UZP1_ZZZ_B |
| 901U, // UZP1_ZZZ_D |
| 137U, // UZP1_ZZZ_H |
| 1029U, // UZP1_ZZZ_S |
| 33095U, // UZP1v16i8 |
| 41287U, // UZP1v2i32 |
| 8517U, // UZP1v2i64 |
| 49480U, // UZP1v4i16 |
| 16710U, // UZP1v4i32 |
| 24902U, // UZP1v8i16 |
| 57672U, // UZP1v8i8 |
| 837U, // UZP2_PPP_B |
| 901U, // UZP2_PPP_D |
| 137U, // UZP2_PPP_H |
| 1029U, // UZP2_PPP_S |
| 837U, // UZP2_ZZZ_B |
| 901U, // UZP2_ZZZ_D |
| 137U, // UZP2_ZZZ_H |
| 1029U, // UZP2_ZZZ_S |
| 33095U, // UZP2v16i8 |
| 41287U, // UZP2v2i32 |
| 8517U, // UZP2v2i64 |
| 49480U, // UZP2v4i16 |
| 16710U, // UZP2v4i32 |
| 24902U, // UZP2v8i16 |
| 57672U, // UZP2v8i8 |
| 261U, // WHILELE_PWW_B |
| 261U, // WHILELE_PWW_D |
| 11U, // WHILELE_PWW_H |
| 261U, // WHILELE_PWW_S |
| 261U, // WHILELE_PXX_B |
| 261U, // WHILELE_PXX_D |
| 11U, // WHILELE_PXX_H |
| 261U, // WHILELE_PXX_S |
| 261U, // WHILELO_PWW_B |
| 261U, // WHILELO_PWW_D |
| 11U, // WHILELO_PWW_H |
| 261U, // WHILELO_PWW_S |
| 261U, // WHILELO_PXX_B |
| 261U, // WHILELO_PXX_D |
| 11U, // WHILELO_PXX_H |
| 261U, // WHILELO_PXX_S |
| 261U, // WHILELS_PWW_B |
| 261U, // WHILELS_PWW_D |
| 11U, // WHILELS_PWW_H |
| 261U, // WHILELS_PWW_S |
| 261U, // WHILELS_PXX_B |
| 261U, // WHILELS_PXX_D |
| 11U, // WHILELS_PXX_H |
| 261U, // WHILELS_PXX_S |
| 261U, // WHILELT_PWW_B |
| 261U, // WHILELT_PWW_D |
| 11U, // WHILELT_PWW_H |
| 261U, // WHILELT_PWW_S |
| 261U, // WHILELT_PXX_B |
| 261U, // WHILELT_PXX_D |
| 11U, // WHILELT_PXX_H |
| 261U, // WHILELT_PXX_S |
| 0U, // WRFFR |
| 2253125U, // XAR |
| 0U, // XPACD |
| 0U, // XPACI |
| 0U, // XPACLRI |
| 4U, // XTNv16i8 |
| 2U, // XTNv2i32 |
| 3U, // XTNv4i16 |
| 2U, // XTNv4i32 |
| 3U, // XTNv8i16 |
| 4U, // XTNv8i8 |
| 837U, // ZIP1_PPP_B |
| 901U, // ZIP1_PPP_D |
| 137U, // ZIP1_PPP_H |
| 1029U, // ZIP1_PPP_S |
| 837U, // ZIP1_ZZZ_B |
| 901U, // ZIP1_ZZZ_D |
| 137U, // ZIP1_ZZZ_H |
| 1029U, // ZIP1_ZZZ_S |
| 33095U, // ZIP1v16i8 |
| 41287U, // ZIP1v2i32 |
| 8517U, // ZIP1v2i64 |
| 49480U, // ZIP1v4i16 |
| 16710U, // ZIP1v4i32 |
| 24902U, // ZIP1v8i16 |
| 57672U, // ZIP1v8i8 |
| 837U, // ZIP2_PPP_B |
| 901U, // ZIP2_PPP_D |
| 137U, // ZIP2_PPP_H |
| 1029U, // ZIP2_PPP_S |
| 837U, // ZIP2_ZZZ_B |
| 901U, // ZIP2_ZZZ_D |
| 137U, // ZIP2_ZZZ_H |
| 1029U, // ZIP2_ZZZ_S |
| 33095U, // ZIP2v16i8 |
| 41287U, // ZIP2v2i32 |
| 8517U, // ZIP2v2i64 |
| 49480U, // ZIP2v4i16 |
| 16710U, // ZIP2v4i32 |
| 24902U, // ZIP2v8i16 |
| 57672U, // ZIP2v8i8 |
| 837U, // anonymous_1349 |
| }; |
| |
| O << "\t"; |
| |
| // Emit the opcode for the instruction. |
| uint64_t Bits = 0; |
| Bits |= (uint64_t)OpInfo0[MI->getOpcode()] << 0; |
| Bits |= (uint64_t)OpInfo1[MI->getOpcode()] << 32; |
| assert(Bits != 0 && "Cannot print this instruction."); |
| O << AsmStrs+(Bits & 8191)-1; |
| |
| |
| // Fragment 0 encoded into 6 bits for 54 unique commands. |
| switch ((Bits >> 13) & 63) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... |
| return; |
| break; |
| case 1: |
| // ABS_ZPmZ_B, ADD_ZI_B, ADD_ZPmZ_B, ADD_ZZZ_B, ANDS_PPzPP, AND_PPzPP, AN... |
| printSVERegOp<'b'>(MI, 0, STI, O); |
| break; |
| case 2: |
| // ABS_ZPmZ_D, ADD_ZI_D, ADD_ZPmZ_D, ADD_ZZZ_D, ADR_LSL_ZZZ_D_0, ADR_LSL_... |
| printSVERegOp<'d'>(MI, 0, STI, O); |
| break; |
| case 3: |
| // ABS_ZPmZ_H, ADD_ZI_H, ADD_ZPmZ_H, ADD_ZZZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ... |
| printSVERegOp<'h'>(MI, 0, STI, O); |
| O << ", "; |
| break; |
| case 4: |
| // ABS_ZPmZ_S, ADD_ZI_S, ADD_ZPmZ_S, ADD_ZZZ_S, ADR_LSL_ZZZ_S_0, ADR_LSL_... |
| printSVERegOp<'s'>(MI, 0, STI, O); |
| break; |
| case 5: |
| // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... |
| printVRegOperand(MI, 0, STI, O); |
| break; |
| case 6: |
| // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPL_XXI, ADDPv2i64p, ADDSWri... |
| printOperand(MI, 0, STI, O); |
| break; |
| case 7: |
| // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... |
| printVRegOperand(MI, 1, STI, O); |
| break; |
| case 8: |
| // B, BL |
| printAlignedLabel(MI, 0, STI, O); |
| return; |
| break; |
| case 9: |
| // BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, SMC, SVC |
| printImmHex(MI, 0, STI, O); |
| return; |
| break; |
| case 10: |
| // Bcc |
| printCondCode(MI, 0, STI, O); |
| O << "\t"; |
| printAlignedLabel(MI, 1, STI, O); |
| return; |
| break; |
| case 11: |
| // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH... |
| printOperand(MI, 1, STI, O); |
| break; |
| case 12: |
| // CASPALW, CASPAW, CASPLW, CASPW |
| printGPRSeqPairsClassOperand<32>(MI, 1, STI, O); |
| O << ", "; |
| printGPRSeqPairsClassOperand<32>(MI, 2, STI, O); |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 13: |
| // CASPALX, CASPAX, CASPLX, CASPX |
| printGPRSeqPairsClassOperand<64>(MI, 1, STI, O); |
| O << ", "; |
| printGPRSeqPairsClassOperand<64>(MI, 2, STI, O); |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 14: |
| // DMB, DSB, ISB, TSB |
| printBarrierOption(MI, 0, STI, O); |
| return; |
| break; |
| case 15: |
| // DUP_ZZI_Q |
| printSVERegOp<'q'>(MI, 0, STI, O); |
| O << ", "; |
| printSVERegOp<'q'>(MI, 1, STI, O); |
| printVectorIndex(MI, 2, STI, O); |
| return; |
| break; |
| case 16: |
| // GLD1B_D_IMM_REAL, GLD1B_D_REAL, GLD1B_D_SXTW_REAL, GLD1B_D_UXTW_REAL, ... |
| printTypedVectorList<0,'d'>(MI, 0, STI, O); |
| O << ", "; |
| printSVERegOp<>(MI, 1, STI, O); |
| break; |
| case 17: |
| // GLD1B_S_IMM_REAL, GLD1B_S_SXTW_REAL, GLD1B_S_UXTW_REAL, GLD1H_S_IMM_RE... |
| printTypedVectorList<0,'s'>(MI, 0, STI, O); |
| O << ", "; |
| printSVERegOp<>(MI, 1, STI, O); |
| break; |
| case 18: |
| // HINT |
| printImm(MI, 0, STI, O); |
| return; |
| break; |
| case 19: |
| // LD1B, LD1B_IMM_REAL, LD1RB_IMM, LD1RQ_B, LD1RQ_B_IMM, LD2B, LD2B_IMM, ... |
| printTypedVectorList<0,'b'>(MI, 0, STI, O); |
| O << ", "; |
| printSVERegOp<>(MI, 1, STI, O); |
| break; |
| case 20: |
| // LD1B_H, LD1B_H_IMM_REAL, LD1H, LD1H_IMM_REAL, LD1RB_H_IMM, LD1RH_IMM, ... |
| printTypedVectorList<0,'h'>(MI, 0, STI, O); |
| O << ", "; |
| printSVERegOp<>(MI, 1, STI, O); |
| break; |
| case 21: |
| // LD1Fourv16b, LD1Onev16b, LD1Rv16b, LD1Threev16b, LD1Twov16b, LD2Rv16b,... |
| printTypedVectorList<16, 'b'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 22: |
| // LD1Fourv16b_POST, LD1Onev16b_POST, LD1Rv16b_POST, LD1Threev16b_POST, L... |
| printTypedVectorList<16, 'b'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 23: |
| // LD1Fourv1d, LD1Onev1d, LD1Rv1d, LD1Threev1d, LD1Twov1d, LD2Rv1d, LD3Rv... |
| printTypedVectorList<1, 'd'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 24: |
| // LD1Fourv1d_POST, LD1Onev1d_POST, LD1Rv1d_POST, LD1Threev1d_POST, LD1Tw... |
| printTypedVectorList<1, 'd'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 25: |
| // LD1Fourv2d, LD1Onev2d, LD1Rv2d, LD1Threev2d, LD1Twov2d, LD2Rv2d, LD2Tw... |
| printTypedVectorList<2, 'd'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 26: |
| // LD1Fourv2d_POST, LD1Onev2d_POST, LD1Rv2d_POST, LD1Threev2d_POST, LD1Tw... |
| printTypedVectorList<2, 'd'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 27: |
| // LD1Fourv2s, LD1Onev2s, LD1Rv2s, LD1Threev2s, LD1Twov2s, LD2Rv2s, LD2Tw... |
| printTypedVectorList<2, 's'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 28: |
| // LD1Fourv2s_POST, LD1Onev2s_POST, LD1Rv2s_POST, LD1Threev2s_POST, LD1Tw... |
| printTypedVectorList<2, 's'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 29: |
| // LD1Fourv4h, LD1Onev4h, LD1Rv4h, LD1Threev4h, LD1Twov4h, LD2Rv4h, LD2Tw... |
| printTypedVectorList<4, 'h'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 30: |
| // LD1Fourv4h_POST, LD1Onev4h_POST, LD1Rv4h_POST, LD1Threev4h_POST, LD1Tw... |
| printTypedVectorList<4, 'h'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 31: |
| // LD1Fourv4s, LD1Onev4s, LD1Rv4s, LD1Threev4s, LD1Twov4s, LD2Rv4s, LD2Tw... |
| printTypedVectorList<4, 's'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 32: |
| // LD1Fourv4s_POST, LD1Onev4s_POST, LD1Rv4s_POST, LD1Threev4s_POST, LD1Tw... |
| printTypedVectorList<4, 's'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 33: |
| // LD1Fourv8b, LD1Onev8b, LD1Rv8b, LD1Threev8b, LD1Twov8b, LD2Rv8b, LD2Tw... |
| printTypedVectorList<8, 'b'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 34: |
| // LD1Fourv8b_POST, LD1Onev8b_POST, LD1Rv8b_POST, LD1Threev8b_POST, LD1Tw... |
| printTypedVectorList<8, 'b'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 35: |
| // LD1Fourv8h, LD1Onev8h, LD1Rv8h, LD1Threev8h, LD1Twov8h, LD2Rv8h, LD2Tw... |
| printTypedVectorList<8, 'h'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 36: |
| // LD1Fourv8h_POST, LD1Onev8h_POST, LD1Rv8h_POST, LD1Threev8h_POST, LD1Tw... |
| printTypedVectorList<8, 'h'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 37: |
| // LD1i16, LD2i16, LD3i16, LD4i16, ST1i16_POST, ST2i16_POST, ST3i16_POST,... |
| printTypedVectorList<0, 'h'>(MI, 1, STI, O); |
| printVectorIndex(MI, 2, STI, O); |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| break; |
| case 38: |
| // LD1i16_POST, LD2i16_POST, LD3i16_POST, LD4i16_POST |
| printTypedVectorList<0, 'h'>(MI, 2, STI, O); |
| printVectorIndex(MI, 3, STI, O); |
| O << ", ["; |
| printOperand(MI, 4, STI, O); |
| O << "], "; |
| break; |
| case 39: |
| // LD1i32, LD2i32, LD3i32, LD4i32, ST1i32_POST, ST2i32_POST, ST3i32_POST,... |
| printTypedVectorList<0, 's'>(MI, 1, STI, O); |
| printVectorIndex(MI, 2, STI, O); |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| break; |
| case 40: |
| // LD1i32_POST, LD2i32_POST, LD3i32_POST, LD4i32_POST |
| printTypedVectorList<0, 's'>(MI, 2, STI, O); |
| printVectorIndex(MI, 3, STI, O); |
| O << ", ["; |
| printOperand(MI, 4, STI, O); |
| O << "], "; |
| break; |
| case 41: |
| // LD1i64, LD2i64, LD3i64, LD4i64, ST1i64_POST, ST2i64_POST, ST3i64_POST,... |
| printTypedVectorList<0, 'd'>(MI, 1, STI, O); |
| printVectorIndex(MI, 2, STI, O); |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| break; |
| case 42: |
| // LD1i64_POST, LD2i64_POST, LD3i64_POST, LD4i64_POST |
| printTypedVectorList<0, 'd'>(MI, 2, STI, O); |
| printVectorIndex(MI, 3, STI, O); |
| O << ", ["; |
| printOperand(MI, 4, STI, O); |
| O << "], "; |
| break; |
| case 43: |
| // LD1i8, LD2i8, LD3i8, LD4i8, ST1i8_POST, ST2i8_POST, ST3i8_POST, ST4i8_... |
| printTypedVectorList<0, 'b'>(MI, 1, STI, O); |
| printVectorIndex(MI, 2, STI, O); |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| break; |
| case 44: |
| // LD1i8_POST, LD2i8_POST, LD3i8_POST, LD4i8_POST |
| printTypedVectorList<0, 'b'>(MI, 2, STI, O); |
| printVectorIndex(MI, 3, STI, O); |
| O << ", ["; |
| printOperand(MI, 4, STI, O); |
| O << "], "; |
| break; |
| case 45: |
| // LDR_PXI, LDR_ZXI, MOVPRFX_ZZ, PTEST_PP, STR_PXI, STR_ZXI |
| printSVERegOp<>(MI, 0, STI, O); |
| break; |
| case 46: |
| // MSR |
| printMSRSystemRegister(MI, 0, STI, O); |
| O << ", "; |
| printOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 47: |
| // MSRpstateImm1, MSRpstateImm4 |
| printSystemPStateField(MI, 0, STI, O); |
| O << ", "; |
| printOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 48: |
| // PRFB_D_PZI, PRFB_D_SCALED, PRFB_D_SXTW_SCALED, PRFB_D_UXTW_SCALED, PRF... |
| printPrefetchOp<true>(MI, 0, STI, O); |
| O << ", "; |
| printSVERegOp<>(MI, 1, STI, O); |
| O << ", ["; |
| break; |
| case 49: |
| // PRFMl, PRFMroW, PRFMroX, PRFMui, PRFUMi |
| printPrefetchOp(MI, 0, STI, O); |
| break; |
| case 50: |
| // ST1i16, ST2i16, ST3i16, ST4i16 |
| printTypedVectorList<0, 'h'>(MI, 0, STI, O); |
| printVectorIndex(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 51: |
| // ST1i32, ST2i32, ST3i32, ST4i32 |
| printTypedVectorList<0, 's'>(MI, 0, STI, O); |
| printVectorIndex(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 52: |
| // ST1i64, ST2i64, ST3i64, ST4i64 |
| printTypedVectorList<0, 'd'>(MI, 0, STI, O); |
| printVectorIndex(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 53: |
| // ST1i8, ST2i8, ST3i8, ST4i8 |
| printTypedVectorList<0, 'b'>(MI, 0, STI, O); |
| printVectorIndex(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| } |
| |
| |
| // Fragment 1 encoded into 6 bits for 56 unique commands. |
| switch ((Bits >> 19) & 63) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, ABSv1i64, ADCSWr, ADCSXr, ADCWr, A... |
| O << ", "; |
| break; |
| case 1: |
| // ABS_ZPmZ_H, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPmZ_H, CNT_ZPmZ_H, CPY_ZPmI_... |
| printSVERegOp<>(MI, 2, STI, O); |
| break; |
| case 2: |
| // ABSv16i8, ADDHNv8i16_v16i8, ADDPv16i8, ADDv16i8, AESDrr, AESErr, AESIM... |
| O << ".16b, "; |
| break; |
| case 3: |
| // ABSv2i32, ADDHNv2i64_v2i32, ADDPv2i32, ADDv2i32, BICv2i32, CLSv2i32, C... |
| O << ".2s, "; |
| break; |
| case 4: |
| // ABSv2i64, ADDPv2i64, ADDv2i64, CMEQv2i64, CMEQv2i64rz, CMGEv2i64, CMGE... |
| O << ".2d, "; |
| break; |
| case 5: |
| // ABSv4i16, ADDHNv4i32_v4i16, ADDPv4i16, ADDv4i16, BICv4i16, CLSv4i16, C... |
| O << ".4h, "; |
| break; |
| case 6: |
| // ABSv4i32, ADDHNv2i64_v4i32, ADDPv4i32, ADDv4i32, BICv4i32, CLSv4i32, C... |
| O << ".4s, "; |
| break; |
| case 7: |
| // ABSv8i16, ADDHNv4i32_v8i16, ADDPv8i16, ADDv8i16, BICv8i16, CLSv8i16, C... |
| O << ".8h, "; |
| break; |
| case 8: |
| // ABSv8i8, ADDHNv8i16_v8i8, ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8... |
| O << ".8b, "; |
| break; |
| case 9: |
| // ADD_ZI_H, ADD_ZZZ_H, ASR_WIDE_ZZZ_H, ASR_ZZI_H, DUP_ZZI_H, FADD_ZZZ_H,... |
| printSVERegOp<'h'>(MI, 1, STI, O); |
| break; |
| case 10: |
| // ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WIDE_ZPmZ_H, ASR... |
| printSVERegOp<>(MI, 1, STI, O); |
| break; |
| case 11: |
| // ADR_LSL_ZZZ_D_0, ADR_LSL_ZZZ_D_1, ADR_LSL_ZZZ_D_2, ADR_LSL_ZZZ_D_3, AD... |
| O << ", ["; |
| break; |
| case 12: |
| // AUTDZA, AUTDZB, AUTIZA, AUTIZB, BLR, BLRAAZ, BLRABZ, BR, BRAAZ, BRABZ,... |
| return; |
| break; |
| case 13: |
| // DECH_ZPiI, INCH_ZPiI, SQDECH_ZPiI, SQINCH_ZPiI, UQDECH_ZPiI, UQINCH_ZP... |
| printSVEPattern(MI, 2, STI, O); |
| O << ", mul "; |
| printOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 14: |
| // DUP_ZI_H |
| printImm8OptLsl<int16_t>(MI, 1, STI, O); |
| return; |
| break; |
| case 15: |
| // DUP_ZR_H, INDEX_II_H, INDEX_IR_H, INDEX_RI_H, INDEX_RR_H, WHILELE_PWW_... |
| printOperand(MI, 1, STI, O); |
| break; |
| case 16: |
| // FCMLA_ZZZI_H, FMLA_ZZZI_H, FMLS_ZZZI_H |
| printSVERegOp<'h'>(MI, 2, STI, O); |
| O << ", "; |
| printSVERegOp<'h'>(MI, 3, STI, O); |
| printVectorIndex(MI, 4, STI, O); |
| break; |
| case 17: |
| // FCMPDri, FCMPEDri, FCMPEHri, FCMPESri, FCMPHri, FCMPSri |
| O << ", #0.0"; |
| return; |
| break; |
| case 18: |
| // FDUP_ZI_H |
| printFPImmOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 19: |
| // FMOVXDHighr, INSvi64gpr, INSvi64lane |
| O << ".d"; |
| printVectorIndex(MI, 2, STI, O); |
| O << ", "; |
| break; |
| case 20: |
| // GLD1B_D_IMM_REAL, GLD1B_D_REAL, GLD1B_D_SXTW_REAL, GLD1B_D_UXTW_REAL, ... |
| O << "/z, ["; |
| break; |
| case 21: |
| // INSR_ZR_H, INSR_ZV_H, PRFB_D_SCALED, PRFB_D_SXTW_SCALED, PRFB_D_UXTW_S... |
| printOperand(MI, 2, STI, O); |
| break; |
| case 22: |
| // INSvi16gpr, INSvi16lane |
| O << ".h"; |
| printVectorIndex(MI, 2, STI, O); |
| O << ", "; |
| break; |
| case 23: |
| // INSvi32gpr, INSvi32lane |
| O << ".s"; |
| printVectorIndex(MI, 2, STI, O); |
| O << ", "; |
| break; |
| case 24: |
| // INSvi8gpr, INSvi8lane |
| O << ".b"; |
| printVectorIndex(MI, 2, STI, O); |
| O << ", "; |
| break; |
| case 25: |
| // LD1Fourv16b_POST, LD1Fourv2d_POST, LD1Fourv4s_POST, LD1Fourv8h_POST, L... |
| printPostIncOperand<64>(MI, 3, STI, O); |
| return; |
| break; |
| case 26: |
| // LD1Fourv1d_POST, LD1Fourv2s_POST, LD1Fourv4h_POST, LD1Fourv8b_POST, LD... |
| printPostIncOperand<32>(MI, 3, STI, O); |
| return; |
| break; |
| case 27: |
| // LD1Onev16b_POST, LD1Onev2d_POST, LD1Onev4s_POST, LD1Onev8h_POST, LD1Tw... |
| printPostIncOperand<16>(MI, 3, STI, O); |
| return; |
| break; |
| case 28: |
| // LD1Onev1d_POST, LD1Onev2s_POST, LD1Onev4h_POST, LD1Onev8b_POST, LD1Rv1... |
| printPostIncOperand<8>(MI, 3, STI, O); |
| return; |
| break; |
| case 29: |
| // LD1Rv16b_POST, LD1Rv8b_POST |
| printPostIncOperand<1>(MI, 3, STI, O); |
| return; |
| break; |
| case 30: |
| // LD1Rv2s_POST, LD1Rv4s_POST, LD2Rv4h_POST, LD2Rv8h_POST, LD4Rv16b_POST,... |
| printPostIncOperand<4>(MI, 3, STI, O); |
| return; |
| break; |
| case 31: |
| // LD1Rv4h_POST, LD1Rv8h_POST, LD2Rv16b_POST, LD2Rv8b_POST |
| printPostIncOperand<2>(MI, 3, STI, O); |
| return; |
| break; |
| case 32: |
| // LD1Threev16b_POST, LD1Threev2d_POST, LD1Threev4s_POST, LD1Threev8h_POS... |
| printPostIncOperand<48>(MI, 3, STI, O); |
| return; |
| break; |
| case 33: |
| // LD1Threev1d_POST, LD1Threev2s_POST, LD1Threev4h_POST, LD1Threev8b_POST... |
| printPostIncOperand<24>(MI, 3, STI, O); |
| return; |
| break; |
| case 34: |
| // LD1i16, LD1i32, LD1i64, LD1i8, LD2i16, LD2i32, LD2i64, LD2i8, LD3i16, ... |
| O << ']'; |
| return; |
| break; |
| case 35: |
| // LD1i16_POST, LD2i8_POST |
| printPostIncOperand<2>(MI, 5, STI, O); |
| return; |
| break; |
| case 36: |
| // LD1i32_POST, LD2i16_POST, LD4i8_POST |
| printPostIncOperand<4>(MI, 5, STI, O); |
| return; |
| break; |
| case 37: |
| // LD1i64_POST, LD2i32_POST, LD4i16_POST |
| printPostIncOperand<8>(MI, 5, STI, O); |
| return; |
| break; |
| case 38: |
| // LD1i8_POST |
| printPostIncOperand<1>(MI, 5, STI, O); |
| return; |
| break; |
| case 39: |
| // LD2i64_POST, LD4i32_POST |
| printPostIncOperand<16>(MI, 5, STI, O); |
| return; |
| break; |
| case 40: |
| // LD3Rv16b_POST, LD3Rv8b_POST |
| printPostIncOperand<3>(MI, 3, STI, O); |
| return; |
| break; |
| case 41: |
| // LD3Rv2s_POST, LD3Rv4s_POST |
| printPostIncOperand<12>(MI, 3, STI, O); |
| return; |
| break; |
| case 42: |
| // LD3Rv4h_POST, LD3Rv8h_POST |
| printPostIncOperand<6>(MI, 3, STI, O); |
| return; |
| break; |
| case 43: |
| // LD3i16_POST |
| printPostIncOperand<6>(MI, 5, STI, O); |
| return; |
| break; |
| case 44: |
| // LD3i32_POST |
| printPostIncOperand<12>(MI, 5, STI, O); |
| return; |
| break; |
| case 45: |
| // LD3i64_POST |
| printPostIncOperand<24>(MI, 5, STI, O); |
| return; |
| break; |
| case 46: |
| // LD3i8_POST |
| printPostIncOperand<3>(MI, 5, STI, O); |
| return; |
| break; |
| case 47: |
| // LD4i64_POST |
| printPostIncOperand<32>(MI, 5, STI, O); |
| return; |
| break; |
| case 48: |
| // PMULLv1i64, PMULLv2i64 |
| O << ".1q, "; |
| printVRegOperand(MI, 1, STI, O); |
| break; |
| case 49: |
| // PRFB_D_PZI, PRFD_D_PZI, PRFH_D_PZI, PRFW_D_PZI |
| printSVERegOp<'d'>(MI, 2, STI, O); |
| O << ", "; |
| break; |
| case 50: |
| // PRFB_S_PZI, PRFD_S_PZI, PRFH_S_PZI, PRFW_S_PZI |
| printSVERegOp<'s'>(MI, 2, STI, O); |
| O << ", "; |
| break; |
| case 51: |
| // PTRUES_H, PTRUE_H |
| printSVEPattern(MI, 1, STI, O); |
| return; |
| break; |
| case 52: |
| // PUNPKHI_PP, PUNPKLO_PP, SUNPKHI_ZZ_H, SUNPKLO_ZZ_H, UUNPKHI_ZZ_H, UUNP... |
| printSVERegOp<'b'>(MI, 1, STI, O); |
| return; |
| break; |
| case 53: |
| // SADALPv2i32_v1i64, SADDLPv2i32_v1i64, UADALPv2i32_v1i64, UADDLPv2i32_v... |
| O << ".1d, "; |
| break; |
| case 54: |
| // ST1i16_POST, ST1i32_POST, ST1i64_POST, ST1i8_POST, ST2i16_POST, ST2i32... |
| O << "], "; |
| break; |
| case 55: |
| // TBL_ZZZ_H |
| printTypedVectorList<0,'h'>(MI, 1, STI, O); |
| O << ", "; |
| printSVERegOp<'h'>(MI, 2, STI, O); |
| return; |
| break; |
| } |
| |
| |
| // Fragment 2 encoded into 6 bits for 57 unique commands. |
| switch ((Bits >> 25) & 63) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, BRKA_PPmP, BRKB_PPmP, CLS_ZPmZ_B, ... |
| printSVERegOp<>(MI, 2, STI, O); |
| break; |
| case 1: |
| // ABS_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WIDE... |
| O << "/m, "; |
| break; |
| case 2: |
| // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... |
| printVRegOperand(MI, 1, STI, O); |
| break; |
| case 3: |
| // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPL_XXI, ADDSWri, ADDSWrs, A... |
| printOperand(MI, 1, STI, O); |
| break; |
| case 4: |
| // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... |
| printVRegOperand(MI, 2, STI, O); |
| break; |
| case 5: |
| // ADD_ZI_B, ADD_ZZZ_B, ASR_WIDE_ZZZ_B, ASR_ZZI_B, DECP_XP_B, DUP_ZZI_B, ... |
| printSVERegOp<'b'>(MI, 1, STI, O); |
| break; |
| case 6: |
| // ADD_ZI_D, ADD_ZZZ_D, ADR_LSL_ZZZ_D_0, ADR_LSL_ZZZ_D_1, ADR_LSL_ZZZ_D_2... |
| printSVERegOp<'d'>(MI, 1, STI, O); |
| break; |
| case 7: |
| // ADD_ZI_H, ADD_ZZZ_H, ASR_WIDE_ZZZ_H, ASR_ZZI_H, CLASTA_ZPZ_H, CLASTB_Z... |
| O << ", "; |
| break; |
| case 8: |
| // ADD_ZI_S, ADD_ZZZ_S, ADR_LSL_ZZZ_S_0, ADR_LSL_ZZZ_S_1, ADR_LSL_ZZZ_S_2... |
| printSVERegOp<'s'>(MI, 1, STI, O); |
| break; |
| case 9: |
| // ADD_ZPmZ_B, ADD_ZPmZ_D, ADD_ZPmZ_S, ANDS_PPzPP, ANDV_VPZ_B, ANDV_VPZ_D... |
| printSVERegOp<>(MI, 1, STI, O); |
| break; |
| case 10: |
| // ADRP |
| printAdrpLabel(MI, 1, STI, O); |
| return; |
| break; |
| case 11: |
| // BFMWri, BFMXri, CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, C... |
| printOperand(MI, 2, STI, O); |
| break; |
| case 12: |
| // BICv2i32, BICv4i16, BICv4i32, BICv8i16, MOVKWi, MOVKXi, ORRv2i32, ORRv... |
| printImm(MI, 2, STI, O); |
| printShifter(MI, 3, STI, O); |
| return; |
| break; |
| case 13: |
| // CBNZW, CBNZX, CBZW, CBZX, LDRDl, LDRQl, LDRSWl, LDRSl, LDRWl, LDRXl, P... |
| printAlignedLabel(MI, 1, STI, O); |
| return; |
| break; |
| case 14: |
| // CMPEQ_PPzZI_H, CMPEQ_PPzZZ_H, CMPEQ_WIDE_PPzZZ_H, CMPGE_PPzZI_H, CMPGE... |
| O << "/z, "; |
| break; |
| case 15: |
| // CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI, PTRUES_B, PTRUES_D, PTRUES... |
| printSVEPattern(MI, 1, STI, O); |
| break; |
| case 16: |
| // DECB_XPiI, DECD_XPiI, DECD_ZPiI, DECH_XPiI, DECW_XPiI, DECW_ZPiI, INCB... |
| printSVEPattern(MI, 2, STI, O); |
| O << ", mul "; |
| printOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 17: |
| // DECP_XP_H, INCP_XP_H, SQDECP_XPWd_H, SQDECP_XP_H, SQINCP_XPWd_H, SQINC... |
| printSVERegOp<'h'>(MI, 1, STI, O); |
| break; |
| case 18: |
| // DECP_ZP_H, DUP_ZR_H, FEXPA_ZZ_H, FMLA_ZZZI_H, FMLS_ZZZI_H, FRECPE_ZZ_H... |
| return; |
| break; |
| case 19: |
| // DUPM_ZI |
| printLogicalImm<int64_t>(MI, 1, STI, O); |
| return; |
| break; |
| case 20: |
| // DUP_ZI_B |
| printImm8OptLsl<int8_t>(MI, 1, STI, O); |
| return; |
| break; |
| case 21: |
| // DUP_ZI_D |
| printImm8OptLsl<int64_t>(MI, 1, STI, O); |
| return; |
| break; |
| case 22: |
| // DUP_ZI_S |
| printImm8OptLsl<int32_t>(MI, 1, STI, O); |
| return; |
| break; |
| case 23: |
| // DUP_ZZI_H |
| printVectorIndex(MI, 2, STI, O); |
| return; |
| break; |
| case 24: |
| // FCMLA_ZZZI_S, FMLA_ZZZI_S, FMLS_ZZZI_S, GLD1B_S_IMM_REAL, GLD1H_S_IMM_... |
| printSVERegOp<'s'>(MI, 2, STI, O); |
| O << ", "; |
| break; |
| case 25: |
| // FDUP_ZI_D, FDUP_ZI_S, FMOVDi, FMOVHi, FMOVSi, FMOVv2f32_ns, FMOVv2f64_... |
| printFPImmOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 26: |
| // FMLA_ZZZI_D, FMLS_ZZZI_D, GLD1B_D_IMM_REAL, GLD1D_IMM_REAL, GLD1H_D_IM... |
| printSVERegOp<'d'>(MI, 2, STI, O); |
| O << ", "; |
| break; |
| case 27: |
| // INSvi16gpr, INSvi32gpr, INSvi64gpr, INSvi8gpr, PRFB_D_PZI, PRFB_S_PZI |
| printOperand(MI, 3, STI, O); |
| break; |
| case 28: |
| // INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane |
| printVRegOperand(MI, 3, STI, O); |
| break; |
| case 29: |
| // LDADDAB, LDADDAH, LDADDALB, LDADDALH, LDADDALW, LDADDALX, LDADDAW, LDA... |
| printOperand(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 30: |
| // MOVID, MOVIv2d_ns |
| printSIMDType10Operand(MI, 1, STI, O); |
| return; |
| break; |
| case 31: |
| // MOVIv16b_ns, MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl... |
| printImm(MI, 1, STI, O); |
| break; |
| case 32: |
| // MRS |
| printMRSSystemRegister(MI, 1, STI, O); |
| return; |
| break; |
| case 33: |
| // PMULLv1i64 |
| O << ".1d, "; |
| printVRegOperand(MI, 2, STI, O); |
| O << ".1d"; |
| return; |
| break; |
| case 34: |
| // PMULLv2i64 |
| O << ".2d, "; |
| printVRegOperand(MI, 2, STI, O); |
| O << ".2d"; |
| return; |
| break; |
| case 35: |
| // PRFD_D_PZI, PRFD_S_PZI |
| printImmScale<8>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 36: |
| // PRFH_D_PZI, PRFH_S_PZI |
| printImmScale<2>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 37: |
| // PRFW_D_PZI, PRFW_S_PZI |
| printImmScale<4>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 38: |
| // SDOT_ZZZI_D, SDOT_ZZZ_D, UDOT_ZZZI_D, UDOT_ZZZ_D |
| printSVERegOp<'h'>(MI, 2, STI, O); |
| O << ", "; |
| printSVERegOp<'h'>(MI, 3, STI, O); |
| break; |
| case 39: |
| // SDOT_ZZZI_S, SDOT_ZZZ_S, UDOT_ZZZI_S, UDOT_ZZZ_S |
| printSVERegOp<'b'>(MI, 2, STI, O); |
| O << ", "; |
| printSVERegOp<'b'>(MI, 3, STI, O); |
| break; |
| case 40: |
| // SQDECB_XPiWdI, SQDECD_XPiWdI, SQDECH_XPiWdI, SQDECW_XPiWdI, SQINCB_XPi... |
| printGPR64as32(MI, 1, STI, O); |
| O << ", "; |
| printSVEPattern(MI, 2, STI, O); |
| O << ", mul "; |
| printOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 41: |
| // ST1i16_POST, ST2i8_POST |
| printPostIncOperand<2>(MI, 4, STI, O); |
| return; |
| break; |
| case 42: |
| // ST1i32_POST, ST2i16_POST, ST4i8_POST |
| printPostIncOperand<4>(MI, 4, STI, O); |
| return; |
| break; |
| case 43: |
| // ST1i64_POST, ST2i32_POST, ST4i16_POST |
| printPostIncOperand<8>(MI, 4, STI, O); |
| return; |
| break; |
| case 44: |
| // ST1i8_POST |
| printPostIncOperand<1>(MI, 4, STI, O); |
| return; |
| break; |
| case 45: |
| // ST2i64_POST, ST4i32_POST |
| printPostIncOperand<16>(MI, 4, STI, O); |
| return; |
| break; |
| case 46: |
| // ST3i16_POST |
| printPostIncOperand<6>(MI, 4, STI, O); |
| return; |
| break; |
| case 47: |
| // ST3i32_POST |
| printPostIncOperand<12>(MI, 4, STI, O); |
| return; |
| break; |
| case 48: |
| // ST3i64_POST |
| printPostIncOperand<24>(MI, 4, STI, O); |
| return; |
| break; |
| case 49: |
| // ST3i8_POST |
| printPostIncOperand<3>(MI, 4, STI, O); |
| return; |
| break; |
| case 50: |
| // ST4i64_POST |
| printPostIncOperand<32>(MI, 4, STI, O); |
| return; |
| break; |
| case 51: |
| // SYSxt |
| printSysCROperand(MI, 1, STI, O); |
| O << ", "; |
| printSysCROperand(MI, 2, STI, O); |
| O << ", "; |
| printOperand(MI, 3, STI, O); |
| O << ", "; |
| printOperand(MI, 4, STI, O); |
| return; |
| break; |
| case 52: |
| // TBL_ZZZ_B |
| printTypedVectorList<0,'b'>(MI, 1, STI, O); |
| O << ", "; |
| printSVERegOp<'b'>(MI, 2, STI, O); |
| return; |
| break; |
| case 53: |
| // TBL_ZZZ_D |
| printTypedVectorList<0,'d'>(MI, 1, STI, O); |
| O << ", "; |
| printSVERegOp<'d'>(MI, 2, STI, O); |
| return; |
| break; |
| case 54: |
| // TBL_ZZZ_S |
| printTypedVectorList<0,'s'>(MI, 1, STI, O); |
| O << ", "; |
| printSVERegOp<'s'>(MI, 2, STI, O); |
| return; |
| break; |
| case 55: |
| // TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16i8Two, TBLv8i8Four, TB... |
| printTypedVectorList<16, 'b'>(MI, 1, STI, O); |
| O << ", "; |
| printVRegOperand(MI, 2, STI, O); |
| break; |
| case 56: |
| // TBXv16i8Four, TBXv16i8One, TBXv16i8Three, TBXv16i8Two, TBXv8i8Four, TB... |
| printTypedVectorList<16, 'b'>(MI, 2, STI, O); |
| O << ", "; |
| printVRegOperand(MI, 3, STI, O); |
| break; |
| } |
| |
| |
| // Fragment 3 encoded into 7 bits for 91 unique commands. |
| switch ((Bits >> 31) & 127) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_D, ADD_ZPmZ_S... |
| O << "/m, "; |
| break; |
| case 1: |
| // ABS_ZPmZ_H, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPmZ_H, CNT_ZPmZ_H, FABS_ZPmZ... |
| printSVERegOp<'h'>(MI, 3, STI, O); |
| break; |
| case 2: |
| // ABSv16i8, ADDVv16i8v, AESDrr, AESErr, AESIMCrr, AESMCrr, CLSv16i8, CLZ... |
| O << ".16b"; |
| return; |
| break; |
| case 3: |
| // ABSv1i64, ADR, AUTDA, AUTDB, AUTIA, AUTIB, BLRAA, BLRAB, BRAA, BRAB, C... |
| return; |
| break; |
| case 4: |
| // ABSv2i32, CLSv2i32, CLZv2i32, FABSv2f32, FADDPv2i32p, FCVTASv2f32, FCV... |
| O << ".2s"; |
| return; |
| break; |
| case 5: |
| // ABSv2i64, ADDPv2i64p, FABSv2f64, FADDPv2i64p, FCVTASv2f64, FCVTAUv2f64... |
| O << ".2d"; |
| return; |
| break; |
| case 6: |
| // ABSv4i16, ADDVv4i16v, CLSv4i16, CLZv4i16, FABSv4f16, FCVTASv4f16, FCVT... |
| O << ".4h"; |
| return; |
| break; |
| case 7: |
| // ABSv4i32, ADDVv4i32v, CLSv4i32, CLZv4i32, FABSv4f32, FCVTASv4f32, FCVT... |
| O << ".4s"; |
| return; |
| break; |
| case 8: |
| // ABSv8i16, ADDVv8i16v, CLSv8i16, CLZv8i16, FABSv8f16, FCVTASv8f16, FCVT... |
| O << ".8h"; |
| return; |
| break; |
| case 9: |
| // ABSv8i8, ADDVv8i8v, CLSv8i8, CLZv8i8, CNTv8i8, NEGv8i8, NOTv8i8, RBITv... |
| O << ".8b"; |
| return; |
| break; |
| case 10: |
| // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPL_XXI, ADDSWri, ADDSWrs, ADDSWrx, AD... |
| O << ", "; |
| break; |
| case 11: |
| // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM... |
| O << ".2d, "; |
| break; |
| case 12: |
| // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM... |
| O << ".4s, "; |
| break; |
| case 13: |
| // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, CMEQv8i16, CMG... |
| O << ".8h, "; |
| break; |
| case 14: |
| // ADDPv16i8, ADDv16i8, ANDv16i8, BCAX, BICv16i8, BIFv16i8, BITv16i8, BSL... |
| O << ".16b, "; |
| break; |
| case 15: |
| // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv... |
| O << ".2s, "; |
| break; |
| case 16: |
| // ADDPv4i16, ADDv4i16, CMEQv4i16, CMGEv4i16, CMGTv4i16, CMHIv4i16, CMHSv... |
| O << ".4h, "; |
| break; |
| case 17: |
| // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8... |
| O << ".8b, "; |
| break; |
| case 18: |
| // ADD_ZI_H, SQADD_ZI_H, SQSUB_ZI_H, SUBR_ZI_H, SUB_ZI_H, UQADD_ZI_H, UQS... |
| printImm8OptLsl<uint16_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 19: |
| // ADD_ZPmZ_H, ADD_ZZZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WIDE_... |
| printSVERegOp<'h'>(MI, 2, STI, O); |
| break; |
| case 20: |
| // ANDS_PPzPP, AND_PPzPP, BICS_PPzPP, BIC_PPzPP, BRKAS_PPzP, BRKA_PPzP, B... |
| O << "/z, "; |
| break; |
| case 21: |
| // ASR_WIDE_ZZZ_H, LSL_WIDE_ZZZ_H, LSR_WIDE_ZZZ_H |
| printSVERegOp<'d'>(MI, 2, STI, O); |
| return; |
| break; |
| case 22: |
| // ASR_ZZI_H, INDEX_II_H, INDEX_IR_H, INDEX_RI_H, INDEX_RR_H, LSL_ZZI_H, ... |
| printOperand(MI, 2, STI, O); |
| return; |
| break; |
| case 23: |
| // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH... |
| O << ", ["; |
| break; |
| case 24: |
| // CMEQv16i8rz, CMGEv16i8rz, CMGTv16i8rz, CMLEv16i8rz, CMLTv16i8rz |
| O << ".16b, #0"; |
| return; |
| break; |
| case 25: |
| // CMEQv1i64rz, CMGEv1i64rz, CMGTv1i64rz, CMLEv1i64rz, CMLTv1i64rz |
| O << ", #0"; |
| return; |
| break; |
| case 26: |
| // CMEQv2i32rz, CMGEv2i32rz, CMGTv2i32rz, CMLEv2i32rz, CMLTv2i32rz |
| O << ".2s, #0"; |
| return; |
| break; |
| case 27: |
| // CMEQv2i64rz, CMGEv2i64rz, CMGTv2i64rz, CMLEv2i64rz, CMLTv2i64rz |
| O << ".2d, #0"; |
| return; |
| break; |
| case 28: |
| // CMEQv4i16rz, CMGEv4i16rz, CMGTv4i16rz, CMLEv4i16rz, CMLTv4i16rz |
| O << ".4h, #0"; |
| return; |
| break; |
| case 29: |
| // CMEQv4i32rz, CMGEv4i32rz, CMGTv4i32rz, CMLEv4i32rz, CMLTv4i32rz |
| O << ".4s, #0"; |
| return; |
| break; |
| case 30: |
| // CMEQv8i16rz, CMGEv8i16rz, CMGTv8i16rz, CMLEv8i16rz, CMLTv8i16rz |
| O << ".8h, #0"; |
| return; |
| break; |
| case 31: |
| // CMEQv8i8rz, CMGEv8i8rz, CMGTv8i8rz, CMLEv8i8rz, CMLTv8i8rz |
| O << ".8b, #0"; |
| return; |
| break; |
| case 32: |
| // CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI |
| O << ", mul "; |
| printOperand(MI, 2, STI, O); |
| return; |
| break; |
| case 33: |
| // CPY_ZPmI_H |
| printImm8OptLsl<int16_t>(MI, 3, STI, O); |
| return; |
| break; |
| case 34: |
| // CPY_ZPmR_H, CPY_ZPmV_H, GLD1B_D_IMM_REAL, GLD1B_S_IMM_REAL, GLD1SB_D_I... |
| printOperand(MI, 3, STI, O); |
| break; |
| case 35: |
| // CPY_ZPzI_H |
| printImm8OptLsl<int16_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 36: |
| // CPYi16, DUPv4i16lane, DUPv8i16lane, INSvi16lane, SMOVvi16to32, SMOVvi1... |
| O << ".h"; |
| break; |
| case 37: |
| // CPYi32, DUPv2i32lane, DUPv4i32lane, INSvi32lane, SMOVvi32to64, UMOVvi3... |
| O << ".s"; |
| break; |
| case 38: |
| // CPYi64, DUPv2i64lane, FMOVDXHighr, INSvi64lane, UMOVvi64 |
| O << ".d"; |
| break; |
| case 39: |
| // CPYi8, DUPv16i8lane, DUPv8i8lane, INSvi8lane, SMOVvi8to32, SMOVvi8to64... |
| O << ".b"; |
| break; |
| case 40: |
| // DUP_ZZI_B, DUP_ZZI_D, DUP_ZZI_S |
| printVectorIndex(MI, 2, STI, O); |
| return; |
| break; |
| case 41: |
| // FADDPv2i16p, FMAXNMPv2i16p, FMAXPv2i16p, FMINNMPv2i16p, FMINPv2i16p |
| O << ".2h"; |
| return; |
| break; |
| case 42: |
| // FCMEQv1i16rz, FCMEQv1i32rz, FCMEQv1i64rz, FCMGEv1i16rz, FCMGEv1i32rz, ... |
| O << ", #0.0"; |
| return; |
| break; |
| case 43: |
| // FCMEQv2i32rz, FCMGEv2i32rz, FCMGTv2i32rz, FCMLEv2i32rz, FCMLTv2i32rz |
| O << ".2s, #0.0"; |
| return; |
| break; |
| case 44: |
| // FCMEQv2i64rz, FCMGEv2i64rz, FCMGTv2i64rz, FCMLEv2i64rz, FCMLTv2i64rz |
| O << ".2d, #0.0"; |
| return; |
| break; |
| case 45: |
| // FCMEQv4i16rz, FCMGEv4i16rz, FCMGTv4i16rz, FCMLEv4i16rz, FCMLTv4i16rz |
| O << ".4h, #0.0"; |
| return; |
| break; |
| case 46: |
| // FCMEQv4i32rz, FCMGEv4i32rz, FCMGTv4i32rz, FCMLEv4i32rz, FCMLTv4i32rz |
| O << ".4s, #0.0"; |
| return; |
| break; |
| case 47: |
| // FCMEQv8i16rz, FCMGEv8i16rz, FCMGTv8i16rz, FCMLEv8i16rz, FCMLTv8i16rz |
| O << ".8h, #0.0"; |
| return; |
| break; |
| case 48: |
| // FCMLA_ZZZI_H |
| printComplexRotationOp<90, 0>(MI, 5, STI, O); |
| return; |
| break; |
| case 49: |
| // FCMLA_ZZZI_S, FCVT_ZPmZ_StoH, FMLA_ZZZI_S, FMLS_ZZZI_S, SCVTF_ZPmZ_Sto... |
| printSVERegOp<'s'>(MI, 3, STI, O); |
| break; |
| case 50: |
| // FCPY_ZPmI_H |
| printFPImmOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 51: |
| // FCVT_ZPmZ_DtoH, FMLA_ZZZI_D, FMLS_ZZZI_D, SCVTF_ZPmZ_DtoH, UCVTF_ZPmZ_... |
| printSVERegOp<'d'>(MI, 3, STI, O); |
| break; |
| case 52: |
| // GLD1D_IMM_REAL, GLDFF1D_IMM_REAL, SST1D_IMM |
| printImmScale<8>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 53: |
| // GLD1H_D_IMM_REAL, GLD1H_S_IMM_REAL, GLD1SH_D_IMM_REAL, GLD1SH_S_IMM_RE... |
| printImmScale<2>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 54: |
| // GLD1SW_D_IMM_REAL, GLD1W_D_IMM_REAL, GLD1W_IMM_REAL, GLDFF1SW_D_IMM_RE... |
| printImmScale<4>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 55: |
| // LDAPRB, LDAPRH, LDAPRW, LDAPRX, LDARB, LDARH, LDARW, LDARX, LDAXRB, LD... |
| O << ']'; |
| return; |
| break; |
| case 56: |
| // LDRBBpost, LDRBpost, LDRDpost, LDRHHpost, LDRHpost, LDRQpost, LDRSBWpo... |
| O << "], "; |
| printOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 57: |
| // MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl, MOVIv8i16, ... |
| printShifter(MI, 2, STI, O); |
| return; |
| break; |
| case 58: |
| // PRFB_D_SCALED |
| printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 59: |
| // PRFB_D_SXTW_SCALED |
| printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 60: |
| // PRFB_D_UXTW_SCALED |
| printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 61: |
| // PRFB_PRR |
| printRegWithShiftExtend<false, 8, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 62: |
| // PRFB_S_SXTW_SCALED |
| printRegWithShiftExtend<true, 8, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 63: |
| // PRFB_S_UXTW_SCALED |
| printRegWithShiftExtend<false, 8, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 64: |
| // PRFD_D_SCALED |
| printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 65: |
| // PRFD_D_SXTW_SCALED |
| printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 66: |
| // PRFD_D_UXTW_SCALED |
| printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 67: |
| // PRFD_PRR |
| printRegWithShiftExtend<false, 64, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 68: |
| // PRFD_S_SXTW_SCALED |
| printRegWithShiftExtend<true, 64, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 69: |
| // PRFD_S_UXTW_SCALED |
| printRegWithShiftExtend<false, 64, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 70: |
| // PRFH_D_SCALED |
| printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 71: |
| // PRFH_D_SXTW_SCALED |
| printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 72: |
| // PRFH_D_UXTW_SCALED |
| printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 73: |
| // PRFH_PRR |
| printRegWithShiftExtend<false, 16, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 74: |
| // PRFH_S_SXTW_SCALED |
| printRegWithShiftExtend<true, 16, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 75: |
| // PRFH_S_UXTW_SCALED |
| printRegWithShiftExtend<false, 16, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 76: |
| // PRFS_PRR |
| printRegWithShiftExtend<false, 32, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 77: |
| // PRFW_D_SCALED |
| printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 78: |
| // PRFW_D_SXTW_SCALED |
| printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 79: |
| // PRFW_D_UXTW_SCALED |
| printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 80: |
| // PRFW_S_SXTW_SCALED |
| printRegWithShiftExtend<true, 32, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 81: |
| // PRFW_S_UXTW_SCALED |
| printRegWithShiftExtend<false, 32, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 82: |
| // RDFFRS_PPz, RDFFR_PPz |
| O << "/z"; |
| return; |
| break; |
| case 83: |
| // SDOT_ZZZI_D, SDOT_ZZZI_S, UDOT_ZZZI_D, UDOT_ZZZI_S |
| printVectorIndex(MI, 4, STI, O); |
| return; |
| break; |
| case 84: |
| // SHLLv16i8 |
| O << ".16b, #8"; |
| return; |
| break; |
| case 85: |
| // SHLLv2i32 |
| O << ".2s, #32"; |
| return; |
| break; |
| case 86: |
| // SHLLv4i16 |
| O << ".4h, #16"; |
| return; |
| break; |
| case 87: |
| // SHLLv4i32 |
| O << ".4s, #32"; |
| return; |
| break; |
| case 88: |
| // SHLLv8i16 |
| O << ".8h, #16"; |
| return; |
| break; |
| case 89: |
| // SHLLv8i8 |
| O << ".8b, #8"; |
| return; |
| break; |
| case 90: |
| // UMAX_ZI_H, UMIN_ZI_H |
| printImm(MI, 2, STI, O); |
| return; |
| break; |
| } |
| |
| |
| // Fragment 4 encoded into 7 bits for 88 unique commands. |
| switch ((Bits >> 38) & 127) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // ABS_ZPmZ_B, BRKA_PPmP, BRKB_PPmP, CLS_ZPmZ_B, CLZ_ZPmZ_B, CNOT_ZPmZ_B,... |
| printSVERegOp<'b'>(MI, 3, STI, O); |
| break; |
| case 1: |
| // ABS_ZPmZ_D, CLS_ZPmZ_D, CLZ_ZPmZ_D, CNOT_ZPmZ_D, CNT_ZPmZ_D, FABS_ZPmZ... |
| printSVERegOp<'d'>(MI, 3, STI, O); |
| break; |
| case 2: |
| // ABS_ZPmZ_H, ADD_ZZZ_H, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPmZ_H, CNT_ZPmZ_H... |
| return; |
| break; |
| case 3: |
| // ABS_ZPmZ_S, CLS_ZPmZ_S, CLZ_ZPmZ_S, CNOT_ZPmZ_S, CNT_ZPmZ_S, FABS_ZPmZ... |
| printSVERegOp<'s'>(MI, 3, STI, O); |
| break; |
| case 4: |
| // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPL_XXI, ADDSXrx64, ADDVL_XXI, ADDXrx6... |
| printOperand(MI, 2, STI, O); |
| break; |
| case 5: |
| // ADDHNv2i64_v2i32, ADDHNv4i32_v4i16, ADDHNv8i16_v8i8, ADDPv16i8, ADDPv2... |
| printVRegOperand(MI, 2, STI, O); |
| break; |
| case 6: |
| // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, BITv16i8, BITv8i... |
| printVRegOperand(MI, 3, STI, O); |
| break; |
| case 7: |
| // ADDSWri, ADDSXri, ADDWri, ADDXri, SUBSWri, SUBSXri, SUBWri, SUBXri |
| printAddSubImm(MI, 2, STI, O); |
| return; |
| break; |
| case 8: |
| // ADDSWrs, ADDSXrs, ADDWrs, ADDXrs, ANDSWrs, ANDSXrs, ANDWrs, ANDXrs, BI... |
| printShiftedRegister(MI, 2, STI, O); |
| return; |
| break; |
| case 9: |
| // ADDSWrx, ADDSXrx, ADDWrx, ADDXrx, SUBSWrx, SUBSXrx, SUBWrx, SUBXrx |
| printExtendedRegister(MI, 2, STI, O); |
| return; |
| break; |
| case 10: |
| // ADD_ZI_B, SQADD_ZI_B, SQSUB_ZI_B, SUBR_ZI_B, SUB_ZI_B, UQADD_ZI_B, UQS... |
| printImm8OptLsl<uint8_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 11: |
| // ADD_ZI_D, SQADD_ZI_D, SQSUB_ZI_D, SUBR_ZI_D, SUB_ZI_D, UQADD_ZI_D, UQS... |
| printImm8OptLsl<uint64_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 12: |
| // ADD_ZI_S, SQADD_ZI_S, SQSUB_ZI_S, SUBR_ZI_S, SUB_ZI_S, UQADD_ZI_S, UQS... |
| printImm8OptLsl<uint32_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 13: |
| // ADD_ZPmZ_B, ADD_ZZZ_B, ANDS_PPzPP, ANDV_VPZ_B, AND_PPzPP, AND_ZPmZ_B, ... |
| printSVERegOp<'b'>(MI, 2, STI, O); |
| break; |
| case 14: |
| // ADD_ZPmZ_D, ADD_ZZZ_D, ANDV_VPZ_D, AND_ZPmZ_D, AND_ZZZ, ASRD_ZPmI_D, A... |
| printSVERegOp<'d'>(MI, 2, STI, O); |
| break; |
| case 15: |
| // ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WIDE_ZPmZ_H, ASR... |
| O << ", "; |
| break; |
| case 16: |
| // ADD_ZPmZ_S, ADD_ZZZ_S, ANDV_VPZ_S, AND_ZPmZ_S, ASRD_ZPmI_S, ASRR_ZPmZ_... |
| printSVERegOp<'s'>(MI, 2, STI, O); |
| break; |
| case 17: |
| // ADR_LSL_ZZZ_D_0 |
| printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 18: |
| // ADR_LSL_ZZZ_D_1 |
| printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 19: |
| // ADR_LSL_ZZZ_D_2 |
| printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 20: |
| // ADR_LSL_ZZZ_D_3 |
| printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 21: |
| // ADR_LSL_ZZZ_S_0 |
| printRegWithShiftExtend<false, 8, 'x', 's'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 22: |
| // ADR_LSL_ZZZ_S_1 |
| printRegWithShiftExtend<false, 16, 'x', 's'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 23: |
| // ADR_LSL_ZZZ_S_2 |
| printRegWithShiftExtend<false, 32, 'x', 's'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 24: |
| // ADR_LSL_ZZZ_S_3 |
| printRegWithShiftExtend<false, 64, 'x', 's'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 25: |
| // ADR_SXTW_ZZZ_D_0 |
| printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 26: |
| // ADR_SXTW_ZZZ_D_1 |
| printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 27: |
| // ADR_SXTW_ZZZ_D_2 |
| printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 28: |
| // ADR_SXTW_ZZZ_D_3 |
| printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 29: |
| // ADR_UXTW_ZZZ_D_0 |
| printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 30: |
| // ADR_UXTW_ZZZ_D_1 |
| printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 31: |
| // ADR_UXTW_ZZZ_D_2 |
| printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 32: |
| // ADR_UXTW_ZZZ_D_3 |
| printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 33: |
| // ANDSWri, ANDWri, EORWri, ORRWri |
| printLogicalImm<int32_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 34: |
| // ANDSXri, ANDXri, AND_ZI, EORXri, EOR_ZI, ORRXri, ORR_ZI |
| printLogicalImm<int64_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 35: |
| // ANDV_VPZ_H, CNTP_XPP_H, EORV_VPZ_H, FADDV_VPZ_H, FMAXNMV_VPZ_H, FMAXV_... |
| printSVERegOp<'h'>(MI, 2, STI, O); |
| return; |
| break; |
| case 36: |
| // BFMWri, BFMXri, CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, C... |
| printOperand(MI, 3, STI, O); |
| break; |
| case 37: |
| // CPY_ZPmI_B |
| printImm8OptLsl<int8_t>(MI, 3, STI, O); |
| return; |
| break; |
| case 38: |
| // CPY_ZPmI_D |
| printImm8OptLsl<int64_t>(MI, 3, STI, O); |
| return; |
| break; |
| case 39: |
| // CPY_ZPmI_S |
| printImm8OptLsl<int32_t>(MI, 3, STI, O); |
| return; |
| break; |
| case 40: |
| // CPY_ZPzI_B |
| printImm8OptLsl<int8_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 41: |
| // CPY_ZPzI_D |
| printImm8OptLsl<int64_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 42: |
| // CPY_ZPzI_S |
| printImm8OptLsl<int32_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 43: |
| // CPYi16, CPYi32, CPYi64, CPYi8, DUPv16i8lane, DUPv2i32lane, DUPv2i64lan... |
| printVectorIndex(MI, 2, STI, O); |
| return; |
| break; |
| case 44: |
| // FCMEQ_PPzZ0_H, FCMGE_PPzZ0_H, FCMGT_PPzZ0_H, FCMLE_PPzZ0_H, FCMLT_PPzZ... |
| O << ", #0.0"; |
| return; |
| break; |
| case 45: |
| // FCMLA_ZZZI_S, FMLA_ZZZI_D, FMLA_ZZZI_S, FMLS_ZZZI_D, FMLS_ZZZI_S, INSv... |
| printVectorIndex(MI, 4, STI, O); |
| break; |
| case 46: |
| // FCPY_ZPmI_D, FCPY_ZPmI_S |
| printFPImmOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 47: |
| // FCVTZS_ZPmZ_HtoD, FCVTZS_ZPmZ_HtoS, FCVTZU_ZPmZ_HtoD, FCVTZU_ZPmZ_HtoS... |
| printSVERegOp<'h'>(MI, 3, STI, O); |
| return; |
| break; |
| case 48: |
| // FMUL_ZZZI_H |
| printVectorIndex(MI, 3, STI, O); |
| return; |
| break; |
| case 49: |
| // GLD1B_D_IMM_REAL, GLD1B_S_IMM_REAL, GLD1SB_D_IMM_REAL, GLD1SB_S_IMM_RE... |
| O << ']'; |
| return; |
| break; |
| case 50: |
| // GLD1B_D_REAL, GLD1D_REAL, GLD1H_D_REAL, GLD1SB_D_REAL, GLD1SH_D_REAL, ... |
| printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 51: |
| // GLD1B_D_SXTW_REAL, GLD1D_SXTW_REAL, GLD1H_D_SXTW_REAL, GLD1SB_D_SXTW_R... |
| printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 52: |
| // GLD1B_D_UXTW_REAL, GLD1D_UXTW_REAL, GLD1H_D_UXTW_REAL, GLD1SB_D_UXTW_R... |
| printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 53: |
| // GLD1B_S_SXTW_REAL, GLD1H_S_SXTW_REAL, GLD1SB_S_SXTW_REAL, GLD1SH_S_SXT... |
| printRegWithShiftExtend<true, 8, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 54: |
| // GLD1B_S_UXTW_REAL, GLD1H_S_UXTW_REAL, GLD1SB_S_UXTW_REAL, GLD1SH_S_UXT... |
| printRegWithShiftExtend<false, 8, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 55: |
| // GLD1D_SCALED_REAL, GLDFF1D_SCALED_REAL, SST1D_SCALED |
| printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 56: |
| // GLD1D_SXTW_SCALED_REAL, GLDFF1D_SXTW_SCALED_REAL, SST1D_SXTW_SCALED |
| printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 57: |
| // GLD1D_UXTW_SCALED_REAL, GLDFF1D_UXTW_SCALED_REAL, SST1D_UXTW_SCALED |
| printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 58: |
| // GLD1H_D_SCALED_REAL, GLD1SH_D_SCALED_REAL, GLDFF1H_D_SCALED_REAL, GLDF... |
| printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 59: |
| // GLD1H_D_SXTW_SCALED_REAL, GLD1SH_D_SXTW_SCALED_REAL, GLDFF1H_D_SXTW_SC... |
| printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 60: |
| // GLD1H_D_UXTW_SCALED_REAL, GLD1SH_D_UXTW_SCALED_REAL, GLDFF1H_D_UXTW_SC... |
| printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 61: |
| // GLD1H_S_SXTW_SCALED_REAL, GLD1SH_S_SXTW_SCALED_REAL, GLDFF1H_S_SXTW_SC... |
| printRegWithShiftExtend<true, 16, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 62: |
| // GLD1H_S_UXTW_SCALED_REAL, GLD1SH_S_UXTW_SCALED_REAL, GLDFF1H_S_UXTW_SC... |
| printRegWithShiftExtend<false, 16, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 63: |
| // GLD1SW_D_SCALED_REAL, GLD1W_D_SCALED_REAL, GLDFF1SW_D_SCALED_REAL, GLD... |
| printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 64: |
| // GLD1SW_D_SXTW_SCALED_REAL, GLD1W_D_SXTW_SCALED_REAL, GLDFF1SW_D_SXTW_S... |
| printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 65: |
| // GLD1SW_D_UXTW_SCALED_REAL, GLD1W_D_UXTW_SCALED_REAL, GLDFF1SW_D_UXTW_S... |
| printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 66: |
| // GLD1W_SXTW_SCALED_REAL, GLDFF1W_SXTW_SCALED_REAL, SST1W_SXTW_SCALED |
| printRegWithShiftExtend<true, 32, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 67: |
| // GLD1W_UXTW_SCALED_REAL, GLDFF1W_UXTW_SCALED_REAL, SST1W_UXTW_SCALED |
| printRegWithShiftExtend<false, 32, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 68: |
| // LD1B, LD1B_D, LD1B_H, LD1B_S, LD1RQ_B, LD1SB_D, LD1SB_H, LD1SB_S, LD2B... |
| printRegWithShiftExtend<false, 8, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 69: |
| // LD1D, LD1RQ_D, LD2D, LD3D, LD4D, LDFF1D_REAL, LDNT1D_ZRR, ST1D, ST2D, ... |
| printRegWithShiftExtend<false, 64, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 70: |
| // LD1H, LD1H_D, LD1H_S, LD1RQ_H, LD1SH_D, LD1SH_S, LD2H, LD3H, LD4H, LDF... |
| printRegWithShiftExtend<false, 16, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 71: |
| // LD1RD_IMM, LDRAAwriteback, LDRABwriteback |
| printImmScale<8>(MI, 3, STI, O); |
| break; |
| case 72: |
| // LD1RH_D_IMM, LD1RH_IMM, LD1RH_S_IMM, LD1RSH_D_IMM, LD1RSH_S_IMM, LD2B_... |
| printImmScale<2>(MI, 3, STI, O); |
| break; |
| case 73: |
| // LD1RQ_B_IMM, LD1RQ_D_IMM, LD1RQ_H_IMM, LD1RQ_W_IMM |
| printImmScale<16>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 74: |
| // LD1RQ_W, LD1SW_D, LD1W, LD1W_D, LD2W, LD3W, LD4W, LDFF1SW_D_REAL, LDFF... |
| printRegWithShiftExtend<false, 32, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 75: |
| // LD1RSW_IMM, LD1RW_D_IMM, LD1RW_IMM, LD4B_IMM, LD4D_IMM, LD4H_IMM, LD4W... |
| printImmScale<4>(MI, 3, STI, O); |
| break; |
| case 76: |
| // LD3B_IMM, LD3D_IMM, LD3H_IMM, LD3W_IMM, ST3B_IMM, ST3D_IMM, ST3H_IMM, ... |
| printImmScale<3>(MI, 3, STI, O); |
| O << ", mul vl]"; |
| return; |
| break; |
| case 77: |
| // LDRAAindexed, LDRABindexed |
| printImmScale<8>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 78: |
| // LDRBBui, LDRBui, LDRSBWui, LDRSBXui, STRBBui, STRBui |
| printUImm12Offset<1>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 79: |
| // LDRDui, LDRXui, PRFMui, STRDui, STRXui |
| printUImm12Offset<8>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 80: |
| // LDRHHui, LDRHui, LDRSHWui, LDRSHXui, STRHHui, STRHui |
| printUImm12Offset<2>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 81: |
| // LDRQui, STRQui |
| printUImm12Offset<16>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 82: |
| // LDRSWui, LDRSui, LDRWui, STRSui, STRWui |
| printUImm12Offset<4>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 83: |
| // PRFB_PRI, PRFD_PRI, PRFH_PRI, PRFW_PRI |
| O << ", mul vl]"; |
| return; |
| break; |
| case 84: |
| // SQDECP_XPWd_B, SQDECP_XPWd_D, SQDECP_XPWd_H, SQDECP_XPWd_S, SQINCP_XPW... |
| printGPR64as32(MI, 2, STI, O); |
| return; |
| break; |
| case 85: |
| // SYSLxt |
| printSysCROperand(MI, 2, STI, O); |
| O << ", "; |
| printSysCROperand(MI, 3, STI, O); |
| O << ", "; |
| printOperand(MI, 4, STI, O); |
| return; |
| break; |
| case 86: |
| // TBNZW, TBNZX, TBZW, TBZX |
| printAlignedLabel(MI, 2, STI, O); |
| return; |
| break; |
| case 87: |
| // UMAX_ZI_B, UMAX_ZI_D, UMAX_ZI_S, UMIN_ZI_B, UMIN_ZI_D, UMIN_ZI_S |
| printImm(MI, 2, STI, O); |
| return; |
| break; |
| } |
| |
| |
| // Fragment 5 encoded into 6 bits for 36 unique commands. |
| switch ((Bits >> 45) & 63) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDP... |
| return; |
| break; |
| case 1: |
| // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM... |
| O << ".2d"; |
| return; |
| break; |
| case 2: |
| // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM... |
| O << ".4s"; |
| return; |
| break; |
| case 3: |
| // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, CMEQv8i16, CMG... |
| O << ".8h"; |
| return; |
| break; |
| case 4: |
| // ADDPv16i8, ADDv16i8, ANDv16i8, BICv16i8, BIFv16i8, BITv16i8, BSLv16i8,... |
| O << ".16b"; |
| return; |
| break; |
| case 5: |
| // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv... |
| O << ".2s"; |
| return; |
| break; |
| case 6: |
| // ADDPv4i16, ADDv4i16, CMEQv4i16, CMGEv4i16, CMGTv4i16, CMHIv4i16, CMHSv... |
| O << ".4h"; |
| return; |
| break; |
| case 7: |
| // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8... |
| O << ".8b"; |
| return; |
| break; |
| case 8: |
| // ADDSXrx64, ADDXrx64, SUBSXrx64, SUBXrx64 |
| printArithExtend(MI, 3, STI, O); |
| return; |
| break; |
| case 9: |
| // ADD_ZPmZ_B, ADD_ZPmZ_D, ADD_ZPmZ_S, ANDS_PPzPP, AND_PPzPP, AND_ZPmZ_B,... |
| O << ", "; |
| break; |
| case 10: |
| // ADD_ZPmZ_H, AND_ZPmZ_H, ASRR_ZPmZ_H, ASR_ZPmZ_H, BIC_ZPmZ_H, CLASTA_ZP... |
| printSVERegOp<'h'>(MI, 3, STI, O); |
| break; |
| case 11: |
| // ASRD_ZPmI_H, ASR_ZPmI_H, CMPEQ_PPzZI_H, CMPGE_PPzZI_H, CMPGT_PPzZI_H, ... |
| printOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 12: |
| // ASR_WIDE_ZPmZ_H, CMPEQ_WIDE_PPzZZ_H, CMPGE_WIDE_PPzZZ_H, CMPGT_WIDE_PP... |
| printSVERegOp<'d'>(MI, 3, STI, O); |
| return; |
| break; |
| case 13: |
| // BCAX, EOR3, EXTv16i8 |
| O << ".16b, "; |
| break; |
| case 14: |
| // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH... |
| O << ']'; |
| return; |
| break; |
| case 15: |
| // CMPHI_PPzZI_H, CMPHS_PPzZI_H, CMPLO_PPzZI_H, CMPLS_PPzZI_H |
| printImm(MI, 3, STI, O); |
| return; |
| break; |
| case 16: |
| // EXTv8i8 |
| O << ".8b, "; |
| printOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 17: |
| // FADD_ZPmI_H, FSUBR_ZPmI_H, FSUB_ZPmI_H |
| printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::one>(MI, 3, STI, O); |
| return; |
| break; |
| case 18: |
| // FCADDv2f32, FCMLAv2f32 |
| O << ".2s, "; |
| break; |
| case 19: |
| // FCADDv2f64, FCMLAv2f64, XAR |
| O << ".2d, "; |
| break; |
| case 20: |
| // FCADDv4f16, FCMLAv4f16 |
| O << ".4h, "; |
| break; |
| case 21: |
| // FCADDv4f32, FCMLAv4f32, SM3SS1 |
| O << ".4s, "; |
| break; |
| case 22: |
| // FCADDv8f16, FCMLAv8f16 |
| O << ".8h, "; |
| break; |
| case 23: |
| // FCMEQ_PPzZ0_D, FCMEQ_PPzZ0_S, FCMGE_PPzZ0_D, FCMGE_PPzZ0_S, FCMGT_PPzZ... |
| O << ", #0.0"; |
| return; |
| break; |
| case 24: |
| // FCMLA_ZPmZZ_H, FMAD_ZPmZZ_H, FMLA_ZPmZZ_H, FMLS_ZPmZZ_H, FMSB_ZPmZZ_H,... |
| printSVERegOp<'h'>(MI, 4, STI, O); |
| break; |
| case 25: |
| // FCMLAv4f16_indexed, FCMLAv8f16_indexed, FMLAv1i16_indexed, FMLAv4i16_i... |
| O << ".h"; |
| break; |
| case 26: |
| // FCMLAv4f32_indexed, FMLAv1i32_indexed, FMLAv2i32_indexed, FMLAv4i32_in... |
| O << ".s"; |
| break; |
| case 27: |
| // FMAXNM_ZPmI_H, FMAX_ZPmI_H, FMINNM_ZPmI_H, FMIN_ZPmI_H |
| printExactFPImm<AArch64ExactFPImm::zero, AArch64ExactFPImm::one>(MI, 3, STI, O); |
| return; |
| break; |
| case 28: |
| // FMLAv1i64_indexed, FMLAv2i64_indexed, FMLSv1i64_indexed, FMLSv2i64_ind... |
| O << ".d"; |
| break; |
| case 29: |
| // FMUL_ZPmI_H |
| printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::two>(MI, 3, STI, O); |
| return; |
| break; |
| case 30: |
| // FMUL_ZZZI_D, FMUL_ZZZI_S |
| printVectorIndex(MI, 3, STI, O); |
| return; |
| break; |
| case 31: |
| // LD1B_D_IMM_REAL, LD1B_H_IMM_REAL, LD1B_IMM_REAL, LD1B_S_IMM_REAL, LD1D... |
| O << ", mul vl]"; |
| return; |
| break; |
| case 32: |
| // LDPDpost, LDPQpost, LDPSWpost, LDPSpost, LDPWpost, LDPXpost, STPDpost,... |
| O << "], "; |
| break; |
| case 33: |
| // LDRAAwriteback, LDRABwriteback, LDRBBpre, LDRBpre, LDRDpre, LDRHHpre, ... |
| O << "]!"; |
| return; |
| break; |
| case 34: |
| // SDOTlanev16i8, SDOTlanev8i8, UDOTlanev16i8, UDOTlanev8i8 |
| O << ".4b"; |
| printVectorIndex(MI, 4, STI, O); |
| return; |
| break; |
| case 35: |
| // STLXPW, STLXPX, STXPW, STXPX |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| } |
| |
| |
| // Fragment 6 encoded into 6 bits for 38 unique commands. |
| switch ((Bits >> 51) & 63) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // ADD_ZPmZ_B, ANDS_PPzPP, AND_PPzPP, AND_ZPmZ_B, ASRR_ZPmZ_B, ASR_ZPmZ_B... |
| printSVERegOp<'b'>(MI, 3, STI, O); |
| return; |
| break; |
| case 1: |
| // ADD_ZPmZ_D, AND_ZPmZ_D, ASRR_ZPmZ_D, ASR_WIDE_ZPmZ_B, ASR_WIDE_ZPmZ_S,... |
| printSVERegOp<'d'>(MI, 3, STI, O); |
| break; |
| case 2: |
| // ADD_ZPmZ_H, AND_ZPmZ_H, ASRR_ZPmZ_H, ASR_ZPmZ_H, BIC_ZPmZ_H, CLASTA_ZP... |
| return; |
| break; |
| case 3: |
| // ADD_ZPmZ_S, AND_ZPmZ_S, ASRR_ZPmZ_S, ASR_ZPmZ_S, BIC_ZPmZ_S, CLASTA_RP... |
| printSVERegOp<'s'>(MI, 3, STI, O); |
| break; |
| case 4: |
| // ASRD_ZPmI_B, ASRD_ZPmI_D, ASRD_ZPmI_S, ASR_ZPmI_B, ASR_ZPmI_D, ASR_ZPm... |
| printOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 5: |
| // BCAX, EOR3, SM3SS1 |
| printVRegOperand(MI, 3, STI, O); |
| break; |
| case 6: |
| // BFMWri, BFMXri |
| printOperand(MI, 4, STI, O); |
| return; |
| break; |
| case 7: |
| // CCMNWi, CCMNWr, CCMNXi, CCMNXr, CCMPWi, CCMPWr, CCMPXi, CCMPXr, CSELWr... |
| printCondCode(MI, 3, STI, O); |
| return; |
| break; |
| case 8: |
| // CLASTA_RPZ_H, CLASTA_VPZ_H, CLASTB_RPZ_H, CLASTB_VPZ_H, FADDA_VPZ_H |
| printSVERegOp<'h'>(MI, 3, STI, O); |
| return; |
| break; |
| case 9: |
| // CMPHI_PPzZI_B, CMPHI_PPzZI_D, CMPHI_PPzZI_S, CMPHS_PPzZI_B, CMPHS_PPzZ... |
| printImm(MI, 3, STI, O); |
| return; |
| break; |
| case 10: |
| // FADD_ZPmI_D, FADD_ZPmI_S, FSUBR_ZPmI_D, FSUBR_ZPmI_S, FSUB_ZPmI_D, FSU... |
| printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::one>(MI, 3, STI, O); |
| return; |
| break; |
| case 11: |
| // FCADD_ZPmZ_H, FCMLA_ZPmZZ_H |
| O << ", "; |
| break; |
| case 12: |
| // FCADDv2f32, FCADDv2f64, FCADDv4f16, FCADDv4f32, FCADDv8f16 |
| printComplexRotationOp<180, 90>(MI, 3, STI, O); |
| return; |
| break; |
| case 13: |
| // FCMLA_ZPmZZ_D, FMAD_ZPmZZ_D, FMLA_ZPmZZ_D, FMLS_ZPmZZ_D, FMSB_ZPmZZ_D,... |
| printSVERegOp<'d'>(MI, 4, STI, O); |
| break; |
| case 14: |
| // FCMLA_ZPmZZ_S, FMAD_ZPmZZ_S, FMLA_ZPmZZ_S, FMLS_ZPmZZ_S, FMSB_ZPmZZ_S,... |
| printSVERegOp<'s'>(MI, 4, STI, O); |
| break; |
| case 15: |
| // FCMLA_ZZZI_S |
| printComplexRotationOp<90, 0>(MI, 5, STI, O); |
| return; |
| break; |
| case 16: |
| // FCMLAv2f32, FCMLAv2f64, FCMLAv4f16, FCMLAv4f32, FCMLAv8f16 |
| printComplexRotationOp<90, 0>(MI, 4, STI, O); |
| return; |
| break; |
| case 17: |
| // FCMLAv4f16_indexed, FCMLAv4f32_indexed, FCMLAv8f16_indexed, FMLAv1i16_... |
| printVectorIndex(MI, 4, STI, O); |
| break; |
| case 18: |
| // FMAXNM_ZPmI_D, FMAXNM_ZPmI_S, FMAX_ZPmI_D, FMAX_ZPmI_S, FMINNM_ZPmI_D,... |
| printExactFPImm<AArch64ExactFPImm::zero, AArch64ExactFPImm::one>(MI, 3, STI, O); |
| return; |
| break; |
| case 19: |
| // FMULXv1i16_indexed, FMULXv1i32_indexed, FMULXv1i64_indexed, FMULXv2i32... |
| printVectorIndex(MI, 3, STI, O); |
| return; |
| break; |
| case 20: |
| // FMUL_ZPmI_D, FMUL_ZPmI_S |
| printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::two>(MI, 3, STI, O); |
| return; |
| break; |
| case 21: |
| // LDNPDi, LDNPXi, LDPDi, LDPXi, STNPDi, STNPXi, STPDi, STPXi |
| printImmScale<8>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 22: |
| // LDNPQi, LDPQi, STNPQi, STPQi |
| printImmScale<16>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 23: |
| // LDNPSi, LDNPWi, LDPSWi, LDPSi, LDPWi, STNPSi, STNPWi, STPSi, STPWi |
| printImmScale<4>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 24: |
| // LDPDpost, LDPDpre, LDPXpost, LDPXpre, STPDpost, STPDpre, STPXpost, STP... |
| printImmScale<8>(MI, 4, STI, O); |
| break; |
| case 25: |
| // LDPQpost, LDPQpre, STPQpost, STPQpre |
| printImmScale<16>(MI, 4, STI, O); |
| break; |
| case 26: |
| // LDPSWpost, LDPSWpre, LDPSpost, LDPSpre, LDPWpost, LDPWpre, STPSpost, S... |
| printImmScale<4>(MI, 4, STI, O); |
| break; |
| case 27: |
| // LDRBBroW, LDRBroW, LDRSBWroW, LDRSBXroW, STRBBroW, STRBroW |
| printMemExtend<'w', 8>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 28: |
| // LDRBBroX, LDRBroX, LDRSBWroX, LDRSBXroX, STRBBroX, STRBroX |
| printMemExtend<'x', 8>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 29: |
| // LDRDroW, LDRXroW, PRFMroW, STRDroW, STRXroW |
| printMemExtend<'w', 64>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 30: |
| // LDRDroX, LDRXroX, PRFMroX, STRDroX, STRXroX |
| printMemExtend<'x', 64>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 31: |
| // LDRHHroW, LDRHroW, LDRSHWroW, LDRSHXroW, STRHHroW, STRHroW |
| printMemExtend<'w', 16>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 32: |
| // LDRHHroX, LDRHroX, LDRSHWroX, LDRSHXroX, STRHHroX, STRHroX |
| printMemExtend<'x', 16>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 33: |
| // LDRQroW, STRQroW |
| printMemExtend<'w', 128>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 34: |
| // LDRQroX, STRQroX |
| printMemExtend<'x', 128>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 35: |
| // LDRSWroW, LDRSroW, LDRWroW, STRSroW, STRWroW |
| printMemExtend<'w', 32>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 36: |
| // LDRSWroX, LDRSroX, LDRWroX, STRSroX, STRWroX |
| printMemExtend<'x', 32>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 37: |
| // MAD_ZPmZZ_B, MLA_ZPmZZ_B, MLS_ZPmZZ_B, MSB_ZPmZZ_B |
| printSVERegOp<'b'>(MI, 4, STI, O); |
| return; |
| break; |
| } |
| |
| |
| // Fragment 7 encoded into 3 bits for 7 unique commands. |
| switch ((Bits >> 57) & 7) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // ADD_ZPmZ_D, ADD_ZPmZ_S, AND_ZPmZ_D, AND_ZPmZ_S, ASRR_ZPmZ_D, ASRR_ZPmZ... |
| return; |
| break; |
| case 1: |
| // BCAX, EOR3 |
| O << ".16b"; |
| return; |
| break; |
| case 2: |
| // FCADD_ZPmZ_D, FCADD_ZPmZ_S, FCMLA_ZPmZZ_D, FCMLA_ZPmZZ_S, FCMLAv4f16_i... |
| O << ", "; |
| break; |
| case 3: |
| // FCADD_ZPmZ_H |
| printComplexRotationOp<180, 90>(MI, 4, STI, O); |
| return; |
| break; |
| case 4: |
| // FCMLA_ZPmZZ_H |
| printComplexRotationOp<90, 0>(MI, 5, STI, O); |
| return; |
| break; |
| case 5: |
| // LDPDpre, LDPQpre, LDPSWpre, LDPSpre, LDPWpre, LDPXpre, STPDpre, STPQpr... |
| O << "]!"; |
| return; |
| break; |
| case 6: |
| // SM3SS1 |
| O << ".4s"; |
| return; |
| break; |
| } |
| |
| |
| // Fragment 8 encoded into 1 bits for 2 unique commands. |
| if ((Bits >> 60) & 1) { |
| // FCMLA_ZPmZZ_D, FCMLA_ZPmZZ_S, FCMLAv4f16_indexed, FCMLAv4f32_indexed, ... |
| printComplexRotationOp<90, 0>(MI, 5, STI, O); |
| return; |
| } else { |
| // FCADD_ZPmZ_D, FCADD_ZPmZ_S |
| printComplexRotationOp<180, 90>(MI, 4, STI, O); |
| return; |
| } |
| |
| } |
| |
| |
| /// getRegisterName - This method is automatically generated by tblgen |
| /// from the register set description. This returns the assembler name |
| /// for the specified register. |
| const char *AArch64InstPrinter:: |
| getRegisterName(unsigned RegNo, unsigned AltIdx) { |
| assert(RegNo && RegNo < 661 && "Invalid register number!"); |
| |
| static const char AsmStrsNoRegAltName[] = { |
| /* 0 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0, |
| /* 13 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0, |
| /* 26 */ 'W', '9', '_', 'W', '1', '0', 0, |
| /* 33 */ 'X', '9', '_', 'X', '1', '0', 0, |
| /* 40 */ 'Z', '7', '_', 'Z', '8', '_', 'Z', '9', '_', 'Z', '1', '0', 0, |
| /* 53 */ 'b', '1', '0', 0, |
| /* 57 */ 'd', '1', '0', 0, |
| /* 61 */ 'h', '1', '0', 0, |
| /* 65 */ 'p', '1', '0', 0, |
| /* 69 */ 'q', '1', '0', 0, |
| /* 73 */ 's', '1', '0', 0, |
| /* 77 */ 'w', '1', '0', 0, |
| /* 81 */ 'x', '1', '0', 0, |
| /* 85 */ 'z', '1', '0', 0, |
| /* 89 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0, |
| /* 105 */ 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', 0, |
| /* 121 */ 'W', '1', '9', '_', 'W', '2', '0', 0, |
| /* 129 */ 'X', '1', '9', '_', 'X', '2', '0', 0, |
| /* 137 */ 'Z', '1', '7', '_', 'Z', '1', '8', '_', 'Z', '1', '9', '_', 'Z', '2', '0', 0, |
| /* 153 */ 'b', '2', '0', 0, |
| /* 157 */ 'd', '2', '0', 0, |
| /* 161 */ 'h', '2', '0', 0, |
| /* 165 */ 'q', '2', '0', 0, |
| /* 169 */ 's', '2', '0', 0, |
| /* 173 */ 'w', '2', '0', 0, |
| /* 177 */ 'x', '2', '0', 0, |
| /* 181 */ 'z', '2', '0', 0, |
| /* 185 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0, |
| /* 201 */ 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', 0, |
| /* 217 */ 'W', '2', '9', '_', 'W', '3', '0', 0, |
| /* 225 */ 'Z', '2', '7', '_', 'Z', '2', '8', '_', 'Z', '2', '9', '_', 'Z', '3', '0', 0, |
| /* 241 */ 'b', '3', '0', 0, |
| /* 245 */ 'd', '3', '0', 0, |
| /* 249 */ 'h', '3', '0', 0, |
| /* 253 */ 'q', '3', '0', 0, |
| /* 257 */ 's', '3', '0', 0, |
| /* 261 */ 'w', '3', '0', 0, |
| /* 265 */ 'x', '3', '0', 0, |
| /* 269 */ 'z', '3', '0', 0, |
| /* 273 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', 0, |
| /* 288 */ 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', 0, |
| /* 303 */ 'W', 'Z', 'R', '_', 'W', '0', 0, |
| /* 310 */ 'X', 'Z', 'R', '_', 'X', '0', 0, |
| /* 317 */ 'Z', '2', '9', '_', 'Z', '3', '0', '_', 'Z', '3', '1', '_', 'Z', '0', 0, |
| /* 332 */ 'b', '0', 0, |
| /* 335 */ 'd', '0', 0, |
| /* 338 */ 'h', '0', 0, |
| /* 341 */ 'p', '0', 0, |
| /* 344 */ 'q', '0', 0, |
| /* 347 */ 's', '0', 0, |
| /* 350 */ 'w', '0', 0, |
| /* 353 */ 'x', '0', 0, |
| /* 356 */ 'z', '0', 0, |
| /* 359 */ 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0, |
| /* 373 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0, |
| /* 387 */ 'W', '1', '0', '_', 'W', '1', '1', 0, |
| /* 395 */ 'X', '1', '0', '_', 'X', '1', '1', 0, |
| /* 403 */ 'Z', '8', '_', 'Z', '9', '_', 'Z', '1', '0', '_', 'Z', '1', '1', 0, |
| /* 417 */ 'b', '1', '1', 0, |
| /* 421 */ 'd', '1', '1', 0, |
| /* 425 */ 'h', '1', '1', 0, |
| /* 429 */ 'p', '1', '1', 0, |
| /* 433 */ 'q', '1', '1', 0, |
| /* 437 */ 's', '1', '1', 0, |
| /* 441 */ 'w', '1', '1', 0, |
| /* 445 */ 'x', '1', '1', 0, |
| /* 449 */ 'z', '1', '1', 0, |
| /* 453 */ 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0, |
| /* 469 */ 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', 0, |
| /* 485 */ 'W', '2', '0', '_', 'W', '2', '1', 0, |
| /* 493 */ 'X', '2', '0', '_', 'X', '2', '1', 0, |
| /* 501 */ 'Z', '1', '8', '_', 'Z', '1', '9', '_', 'Z', '2', '0', '_', 'Z', '2', '1', 0, |
| /* 517 */ 'b', '2', '1', 0, |
| /* 521 */ 'd', '2', '1', 0, |
| /* 525 */ 'h', '2', '1', 0, |
| /* 529 */ 'q', '2', '1', 0, |
| /* 533 */ 's', '2', '1', 0, |
| /* 537 */ 'w', '2', '1', 0, |
| /* 541 */ 'x', '2', '1', 0, |
| /* 545 */ 'z', '2', '1', 0, |
| /* 549 */ 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0, |
| /* 565 */ 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', 0, |
| /* 581 */ 'Z', '2', '8', '_', 'Z', '2', '9', '_', 'Z', '3', '0', '_', 'Z', '3', '1', 0, |
| /* 597 */ 'b', '3', '1', 0, |
| /* 601 */ 'd', '3', '1', 0, |
| /* 605 */ 'h', '3', '1', 0, |
| /* 609 */ 'q', '3', '1', 0, |
| /* 613 */ 's', '3', '1', 0, |
| /* 617 */ 'z', '3', '1', 0, |
| /* 621 */ 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', 0, |
| /* 635 */ 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', 0, |
| /* 649 */ 'W', '0', '_', 'W', '1', 0, |
| /* 655 */ 'X', '0', '_', 'X', '1', 0, |
| /* 661 */ 'Z', '3', '0', '_', 'Z', '3', '1', '_', 'Z', '0', '_', 'Z', '1', 0, |
| /* 675 */ 'b', '1', 0, |
| /* 678 */ 'd', '1', 0, |
| /* 681 */ 'h', '1', 0, |
| /* 684 */ 'p', '1', 0, |
| /* 687 */ 'q', '1', 0, |
| /* 690 */ 's', '1', 0, |
| /* 693 */ 'w', '1', 0, |
| /* 696 */ 'x', '1', 0, |
| /* 699 */ 'z', '1', 0, |
| /* 702 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0, |
| /* 717 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0, |
| /* 732 */ 'W', '1', '1', '_', 'W', '1', '2', 0, |
| /* 740 */ 'X', '1', '1', '_', 'X', '1', '2', 0, |
| /* 748 */ 'Z', '9', '_', 'Z', '1', '0', '_', 'Z', '1', '1', '_', 'Z', '1', '2', 0, |
| /* 763 */ 'b', '1', '2', 0, |
| /* 767 */ 'd', '1', '2', 0, |
| /* 771 */ 'h', '1', '2', 0, |
| /* 775 */ 'p', '1', '2', 0, |
| /* 779 */ 'q', '1', '2', 0, |
| /* 783 */ 's', '1', '2', 0, |
| /* 787 */ 'w', '1', '2', 0, |
| /* 791 */ 'x', '1', '2', 0, |
| /* 795 */ 'z', '1', '2', 0, |
| /* 799 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0, |
| /* 815 */ 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', 0, |
| /* 831 */ 'W', '2', '1', '_', 'W', '2', '2', 0, |
| /* 839 */ 'X', '2', '1', '_', 'X', '2', '2', 0, |
| /* 847 */ 'Z', '1', '9', '_', 'Z', '2', '0', '_', 'Z', '2', '1', '_', 'Z', '2', '2', 0, |
| /* 863 */ 'b', '2', '2', 0, |
| /* 867 */ 'd', '2', '2', 0, |
| /* 871 */ 'h', '2', '2', 0, |
| /* 875 */ 'q', '2', '2', 0, |
| /* 879 */ 's', '2', '2', 0, |
| /* 883 */ 'w', '2', '2', 0, |
| /* 887 */ 'x', '2', '2', 0, |
| /* 891 */ 'z', '2', '2', 0, |
| /* 895 */ 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', '_', 'D', '2', 0, |
| /* 908 */ 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', 0, |
| /* 921 */ 'W', '1', '_', 'W', '2', 0, |
| /* 927 */ 'X', '1', '_', 'X', '2', 0, |
| /* 933 */ 'Z', '3', '1', '_', 'Z', '0', '_', 'Z', '1', '_', 'Z', '2', 0, |
| /* 946 */ 'b', '2', 0, |
| /* 949 */ 'd', '2', 0, |
| /* 952 */ 'h', '2', 0, |
| /* 955 */ 'p', '2', 0, |
| /* 958 */ 'q', '2', 0, |
| /* 961 */ 's', '2', 0, |
| /* 964 */ 'w', '2', 0, |
| /* 967 */ 'x', '2', 0, |
| /* 970 */ 'z', '2', 0, |
| /* 973 */ 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0, |
| /* 989 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0, |
| /* 1005 */ 'W', '1', '2', '_', 'W', '1', '3', 0, |
| /* 1013 */ 'X', '1', '2', '_', 'X', '1', '3', 0, |
| /* 1021 */ 'Z', '1', '0', '_', 'Z', '1', '1', '_', 'Z', '1', '2', '_', 'Z', '1', '3', 0, |
| /* 1037 */ 'b', '1', '3', 0, |
| /* 1041 */ 'd', '1', '3', 0, |
| /* 1045 */ 'h', '1', '3', 0, |
| /* 1049 */ 'p', '1', '3', 0, |
| /* 1053 */ 'q', '1', '3', 0, |
| /* 1057 */ 's', '1', '3', 0, |
| /* 1061 */ 'w', '1', '3', 0, |
| /* 1065 */ 'x', '1', '3', 0, |
| /* 1069 */ 'z', '1', '3', 0, |
| /* 1073 */ 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0, |
| /* 1089 */ 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', 0, |
| /* 1105 */ 'W', '2', '2', '_', 'W', '2', '3', 0, |
| /* 1113 */ 'X', '2', '2', '_', 'X', '2', '3', 0, |
| /* 1121 */ 'Z', '2', '0', '_', 'Z', '2', '1', '_', 'Z', '2', '2', '_', 'Z', '2', '3', 0, |
| /* 1137 */ 'b', '2', '3', 0, |
| /* 1141 */ 'd', '2', '3', 0, |
| /* 1145 */ 'h', '2', '3', 0, |
| /* 1149 */ 'q', '2', '3', 0, |
| /* 1153 */ 's', '2', '3', 0, |
| /* 1157 */ 'w', '2', '3', 0, |
| /* 1161 */ 'x', '2', '3', 0, |
| /* 1165 */ 'z', '2', '3', 0, |
| /* 1169 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', '_', 'D', '3', 0, |
| /* 1181 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0, |
| /* 1193 */ 'W', '2', '_', 'W', '3', 0, |
| /* 1199 */ 'X', '2', '_', 'X', '3', 0, |
| /* 1205 */ 'Z', '0', '_', 'Z', '1', '_', 'Z', '2', '_', 'Z', '3', 0, |
| /* 1217 */ 'b', '3', 0, |
| /* 1220 */ 'd', '3', 0, |
| /* 1223 */ 'h', '3', 0, |
| /* 1226 */ 'p', '3', 0, |
| /* 1229 */ 'q', '3', 0, |
| /* 1232 */ 's', '3', 0, |
| /* 1235 */ 'w', '3', 0, |
| /* 1238 */ 'x', '3', 0, |
| /* 1241 */ 'z', '3', 0, |
| /* 1244 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0, |
| /* 1260 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0, |
| /* 1276 */ 'W', '1', '3', '_', 'W', '1', '4', 0, |
| /* 1284 */ 'X', '1', '3', '_', 'X', '1', '4', 0, |
| /* 1292 */ 'Z', '1', '1', '_', 'Z', '1', '2', '_', 'Z', '1', '3', '_', 'Z', '1', '4', 0, |
| /* 1308 */ 'b', '1', '4', 0, |
| /* 1312 */ 'd', '1', '4', 0, |
| /* 1316 */ 'h', '1', '4', 0, |
| /* 1320 */ 'p', '1', '4', 0, |
| /* 1324 */ 'q', '1', '4', 0, |
| /* 1328 */ 's', '1', '4', 0, |
| /* 1332 */ 'w', '1', '4', 0, |
| /* 1336 */ 'x', '1', '4', 0, |
| /* 1340 */ 'z', '1', '4', 0, |
| /* 1344 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0, |
| /* 1360 */ 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', 0, |
| /* 1376 */ 'W', '2', '3', '_', 'W', '2', '4', 0, |
| /* 1384 */ 'X', '2', '3', '_', 'X', '2', '4', 0, |
| /* 1392 */ 'Z', '2', '1', '_', 'Z', '2', '2', '_', 'Z', '2', '3', '_', 'Z', '2', '4', 0, |
| /* 1408 */ 'b', '2', '4', 0, |
| /* 1412 */ 'd', '2', '4', 0, |
| /* 1416 */ 'h', '2', '4', 0, |
| /* 1420 */ 'q', '2', '4', 0, |
| /* 1424 */ 's', '2', '4', 0, |
| /* 1428 */ 'w', '2', '4', 0, |
| /* 1432 */ 'x', '2', '4', 0, |
| /* 1436 */ 'z', '2', '4', 0, |
| /* 1440 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0, |
| /* 1452 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0, |
| /* 1464 */ 'W', '3', '_', 'W', '4', 0, |
| /* 1470 */ 'X', '3', '_', 'X', '4', 0, |
| /* 1476 */ 'Z', '1', '_', 'Z', '2', '_', 'Z', '3', '_', 'Z', '4', 0, |
| /* 1488 */ 'b', '4', 0, |
| /* 1491 */ 'd', '4', 0, |
| /* 1494 */ 'h', '4', 0, |
| /* 1497 */ 'p', '4', 0, |
| /* 1500 */ 'q', '4', 0, |
| /* 1503 */ 's', '4', 0, |
| /* 1506 */ 'w', '4', 0, |
| /* 1509 */ 'x', '4', 0, |
| /* 1512 */ 'z', '4', 0, |
| /* 1515 */ 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0, |
| /* 1531 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0, |
| /* 1547 */ 'W', '1', '4', '_', 'W', '1', '5', 0, |
| /* 1555 */ 'X', '1', '4', '_', 'X', '1', '5', 0, |
| /* 1563 */ 'Z', '1', '2', '_', 'Z', '1', '3', '_', 'Z', '1', '4', '_', 'Z', '1', '5', 0, |
| /* 1579 */ 'b', '1', '5', 0, |
| /* 1583 */ 'd', '1', '5', 0, |
| /* 1587 */ 'h', '1', '5', 0, |
| /* 1591 */ 'p', '1', '5', 0, |
| /* 1595 */ 'q', '1', '5', 0, |
| /* 1599 */ 's', '1', '5', 0, |
| /* 1603 */ 'w', '1', '5', 0, |
| /* 1607 */ 'x', '1', '5', 0, |
| /* 1611 */ 'z', '1', '5', 0, |
| /* 1615 */ 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0, |
| /* 1631 */ 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', 0, |
| /* 1647 */ 'W', '2', '4', '_', 'W', '2', '5', 0, |
| /* 1655 */ 'X', '2', '4', '_', 'X', '2', '5', 0, |
| /* 1663 */ 'Z', '2', '2', '_', 'Z', '2', '3', '_', 'Z', '2', '4', '_', 'Z', '2', '5', 0, |
| /* 1679 */ 'b', '2', '5', 0, |
| /* 1683 */ 'd', '2', '5', 0, |
| /* 1687 */ 'h', '2', '5', 0, |
| /* 1691 */ 'q', '2', '5', 0, |
| /* 1695 */ 's', '2', '5', 0, |
| /* 1699 */ 'w', '2', '5', 0, |
| /* 1703 */ 'x', '2', '5', 0, |
| /* 1707 */ 'z', '2', '5', 0, |
| /* 1711 */ 'D', '2', '_', 'D', '3', '_', 'D', '4', '_', 'D', '5', 0, |
| /* 1723 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0, |
| /* 1735 */ 'W', '4', '_', 'W', '5', 0, |
| /* 1741 */ 'X', '4', '_', 'X', '5', 0, |
| /* 1747 */ 'Z', '2', '_', 'Z', '3', '_', 'Z', '4', '_', 'Z', '5', 0, |
| /* 1759 */ 'b', '5', 0, |
| /* 1762 */ 'd', '5', 0, |
| /* 1765 */ 'h', '5', 0, |
| /* 1768 */ 'p', '5', 0, |
| /* 1771 */ 'q', '5', 0, |
| /* 1774 */ 's', '5', 0, |
| /* 1777 */ 'w', '5', 0, |
| /* 1780 */ 'x', '5', 0, |
| /* 1783 */ 'z', '5', 0, |
| /* 1786 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0, |
| /* 1802 */ 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', 0, |
| /* 1818 */ 'W', '1', '5', '_', 'W', '1', '6', 0, |
| /* 1826 */ 'X', '1', '5', '_', 'X', '1', '6', 0, |
| /* 1834 */ 'Z', '1', '3', '_', 'Z', '1', '4', '_', 'Z', '1', '5', '_', 'Z', '1', '6', 0, |
| /* 1850 */ 'b', '1', '6', 0, |
| /* 1854 */ 'd', '1', '6', 0, |
| /* 1858 */ 'h', '1', '6', 0, |
| /* 1862 */ 'q', '1', '6', 0, |
| /* 1866 */ 's', '1', '6', 0, |
| /* 1870 */ 'w', '1', '6', 0, |
| /* 1874 */ 'x', '1', '6', 0, |
| /* 1878 */ 'z', '1', '6', 0, |
| /* 1882 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0, |
| /* 1898 */ 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', 0, |
| /* 1914 */ 'W', '2', '5', '_', 'W', '2', '6', 0, |
| /* 1922 */ 'X', '2', '5', '_', 'X', '2', '6', 0, |
| /* 1930 */ 'Z', '2', '3', '_', 'Z', '2', '4', '_', 'Z', '2', '5', '_', 'Z', '2', '6', 0, |
| /* 1946 */ 'b', '2', '6', 0, |
| /* 1950 */ 'd', '2', '6', 0, |
| /* 1954 */ 'h', '2', '6', 0, |
| /* 1958 */ 'q', '2', '6', 0, |
| /* 1962 */ 's', '2', '6', 0, |
| /* 1966 */ 'w', '2', '6', 0, |
| /* 1970 */ 'x', '2', '6', 0, |
| /* 1974 */ 'z', '2', '6', 0, |
| /* 1978 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0, |
| /* 1990 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0, |
| /* 2002 */ 'W', '5', '_', 'W', '6', 0, |
| /* 2008 */ 'X', '5', '_', 'X', '6', 0, |
| /* 2014 */ 'Z', '3', '_', 'Z', '4', '_', 'Z', '5', '_', 'Z', '6', 0, |
| /* 2026 */ 'b', '6', 0, |
| /* 2029 */ 'd', '6', 0, |
| /* 2032 */ 'h', '6', 0, |
| /* 2035 */ 'p', '6', 0, |
| /* 2038 */ 'q', '6', 0, |
| /* 2041 */ 's', '6', 0, |
| /* 2044 */ 'w', '6', 0, |
| /* 2047 */ 'x', '6', 0, |
| /* 2050 */ 'z', '6', 0, |
| /* 2053 */ 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0, |
| /* 2069 */ 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', 0, |
| /* 2085 */ 'W', '1', '6', '_', 'W', '1', '7', 0, |
| /* 2093 */ 'X', '1', '6', '_', 'X', '1', '7', 0, |
| /* 2101 */ 'Z', '1', '4', '_', 'Z', '1', '5', '_', 'Z', '1', '6', '_', 'Z', '1', '7', 0, |
| /* 2117 */ 'b', '1', '7', 0, |
| /* 2121 */ 'd', '1', '7', 0, |
| /* 2125 */ 'h', '1', '7', 0, |
| /* 2129 */ 'q', '1', '7', 0, |
| /* 2133 */ 's', '1', '7', 0, |
| /* 2137 */ 'w', '1', '7', 0, |
| /* 2141 */ 'x', '1', '7', 0, |
| /* 2145 */ 'z', '1', '7', 0, |
| /* 2149 */ 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0, |
| /* 2165 */ 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', 0, |
| /* 2181 */ 'W', '2', '6', '_', 'W', '2', '7', 0, |
| /* 2189 */ 'X', '2', '6', '_', 'X', '2', '7', 0, |
| /* 2197 */ 'Z', '2', '4', '_', 'Z', '2', '5', '_', 'Z', '2', '6', '_', 'Z', '2', '7', 0, |
| /* 2213 */ 'b', '2', '7', 0, |
| /* 2217 */ 'd', '2', '7', 0, |
| /* 2221 */ 'h', '2', '7', 0, |
| /* 2225 */ 'q', '2', '7', 0, |
| /* 2229 */ 's', '2', '7', 0, |
| /* 2233 */ 'w', '2', '7', 0, |
| /* 2237 */ 'x', '2', '7', 0, |
| /* 2241 */ 'z', '2', '7', 0, |
| /* 2245 */ 'D', '4', '_', 'D', '5', '_', 'D', '6', '_', 'D', '7', 0, |
| /* 2257 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0, |
| /* 2269 */ 'W', '6', '_', 'W', '7', 0, |
| /* 2275 */ 'X', '6', '_', 'X', '7', 0, |
| /* 2281 */ 'Z', '4', '_', 'Z', '5', '_', 'Z', '6', '_', 'Z', '7', 0, |
| /* 2293 */ 'b', '7', 0, |
| /* 2296 */ 'd', '7', 0, |
| /* 2299 */ 'h', '7', 0, |
| /* 2302 */ 'p', '7', 0, |
| /* 2305 */ 'q', '7', 0, |
| /* 2308 */ 's', '7', 0, |
| /* 2311 */ 'w', '7', 0, |
| /* 2314 */ 'x', '7', 0, |
| /* 2317 */ 'z', '7', 0, |
| /* 2320 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0, |
| /* 2336 */ 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', 0, |
| /* 2352 */ 'W', '1', '7', '_', 'W', '1', '8', 0, |
| /* 2360 */ 'X', '1', '7', '_', 'X', '1', '8', 0, |
| /* 2368 */ 'Z', '1', '5', '_', 'Z', '1', '6', '_', 'Z', '1', '7', '_', 'Z', '1', '8', 0, |
| /* 2384 */ 'b', '1', '8', 0, |
| /* 2388 */ 'd', '1', '8', 0, |
| /* 2392 */ 'h', '1', '8', 0, |
| /* 2396 */ 'q', '1', '8', 0, |
| /* 2400 */ 's', '1', '8', 0, |
| /* 2404 */ 'w', '1', '8', 0, |
| /* 2408 */ 'x', '1', '8', 0, |
| /* 2412 */ 'z', '1', '8', 0, |
| /* 2416 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0, |
| /* 2432 */ 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', 0, |
| /* 2448 */ 'W', '2', '7', '_', 'W', '2', '8', 0, |
| /* 2456 */ 'X', '2', '7', '_', 'X', '2', '8', 0, |
| /* 2464 */ 'Z', '2', '5', '_', 'Z', '2', '6', '_', 'Z', '2', '7', '_', 'Z', '2', '8', 0, |
| /* 2480 */ 'b', '2', '8', 0, |
| /* 2484 */ 'd', '2', '8', 0, |
| /* 2488 */ 'h', '2', '8', 0, |
| /* 2492 */ 'q', '2', '8', 0, |
| /* 2496 */ 's', '2', '8', 0, |
| /* 2500 */ 'w', '2', '8', 0, |
| /* 2504 */ 'x', '2', '8', 0, |
| /* 2508 */ 'z', '2', '8', 0, |
| /* 2512 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0, |
| /* 2524 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0, |
| /* 2536 */ 'W', '7', '_', 'W', '8', 0, |
| /* 2542 */ 'X', '7', '_', 'X', '8', 0, |
| /* 2548 */ 'Z', '5', '_', 'Z', '6', '_', 'Z', '7', '_', 'Z', '8', 0, |
| /* 2560 */ 'b', '8', 0, |
| /* 2563 */ 'd', '8', 0, |
| /* 2566 */ 'h', '8', 0, |
| /* 2569 */ 'p', '8', 0, |
| /* 2572 */ 'q', '8', 0, |
| /* 2575 */ 's', '8', 0, |
| /* 2578 */ 'w', '8', 0, |
| /* 2581 */ 'x', '8', 0, |
| /* 2584 */ 'z', '8', 0, |
| /* 2587 */ 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0, |
| /* 2603 */ 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', 0, |
| /* 2619 */ 'W', '1', '8', '_', 'W', '1', '9', 0, |
| /* 2627 */ 'X', '1', '8', '_', 'X', '1', '9', 0, |
| /* 2635 */ 'Z', '1', '6', '_', 'Z', '1', '7', '_', 'Z', '1', '8', '_', 'Z', '1', '9', 0, |
| /* 2651 */ 'b', '1', '9', 0, |
| /* 2655 */ 'd', '1', '9', 0, |
| /* 2659 */ 'h', '1', '9', 0, |
| /* 2663 */ 'q', '1', '9', 0, |
| /* 2667 */ 's', '1', '9', 0, |
| /* 2671 */ 'w', '1', '9', 0, |
| /* 2675 */ 'x', '1', '9', 0, |
| /* 2679 */ 'z', '1', '9', 0, |
| /* 2683 */ 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0, |
| /* 2699 */ 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', 0, |
| /* 2715 */ 'W', '2', '8', '_', 'W', '2', '9', 0, |
| /* 2723 */ 'Z', '2', '6', '_', 'Z', '2', '7', '_', 'Z', '2', '8', '_', 'Z', '2', '9', 0, |
| /* 2739 */ 'b', '2', '9', 0, |
| /* 2743 */ 'd', '2', '9', 0, |
| /* 2747 */ 'h', '2', '9', 0, |
| /* 2751 */ 'q', '2', '9', 0, |
| /* 2755 */ 's', '2', '9', 0, |
| /* 2759 */ 'w', '2', '9', 0, |
| /* 2763 */ 'x', '2', '9', 0, |
| /* 2767 */ 'z', '2', '9', 0, |
| /* 2771 */ 'D', '6', '_', 'D', '7', '_', 'D', '8', '_', 'D', '9', 0, |
| /* 2783 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0, |
| /* 2795 */ 'W', '8', '_', 'W', '9', 0, |
| /* 2801 */ 'X', '8', '_', 'X', '9', 0, |
| /* 2807 */ 'Z', '6', '_', 'Z', '7', '_', 'Z', '8', '_', 'Z', '9', 0, |
| /* 2819 */ 'b', '9', 0, |
| /* 2822 */ 'd', '9', 0, |
| /* 2825 */ 'h', '9', 0, |
| /* 2828 */ 'p', '9', 0, |
| /* 2831 */ 'q', '9', 0, |
| /* 2834 */ 's', '9', 0, |
| /* 2837 */ 'w', '9', 0, |
| /* 2840 */ 'x', '9', 0, |
| /* 2843 */ 'z', '9', 0, |
| /* 2846 */ 'X', '2', '8', '_', 'F', 'P', 0, |
| /* 2853 */ 'F', 'P', '_', 'L', 'R', 0, |
| /* 2859 */ 'W', '3', '0', '_', 'W', 'Z', 'R', 0, |
| /* 2867 */ 'L', 'R', '_', 'X', 'Z', 'R', 0, |
| /* 2874 */ 'z', '1', '0', '_', 'h', 'i', 0, |
| /* 2881 */ 'z', '2', '0', '_', 'h', 'i', 0, |
| /* 2888 */ 'z', '3', '0', '_', 'h', 'i', 0, |
| /* 2895 */ 'z', '0', '_', 'h', 'i', 0, |
| /* 2901 */ 'z', '1', '1', '_', 'h', 'i', 0, |
| /* 2908 */ 'z', '2', '1', '_', 'h', 'i', 0, |
| /* 2915 */ 'z', '3', '1', '_', 'h', 'i', 0, |
| /* 2922 */ 'z', '1', '_', 'h', 'i', 0, |
| /* 2928 */ 'z', '1', '2', '_', 'h', 'i', 0, |
| /* 2935 */ 'z', '2', '2', '_', 'h', 'i', 0, |
| /* 2942 */ 'z', '2', '_', 'h', 'i', 0, |
| /* 2948 */ 'z', '1', '3', '_', 'h', 'i', 0, |
| /* 2955 */ 'z', '2', '3', '_', 'h', 'i', 0, |
| /* 2962 */ 'z', '3', '_', 'h', 'i', 0, |
| /* 2968 */ 'z', '1', '4', '_', 'h', 'i', 0, |
| /* 2975 */ 'z', '2', '4', '_', 'h', 'i', 0, |
| /* 2982 */ 'z', '4', '_', 'h', 'i', 0, |
| /* 2988 */ 'z', '1', '5', '_', 'h', 'i', 0, |
| /* 2995 */ 'z', '2', '5', '_', 'h', 'i', 0, |
| /* 3002 */ 'z', '5', '_', 'h', 'i', 0, |
| /* 3008 */ 'z', '1', '6', '_', 'h', 'i', 0, |
| /* 3015 */ 'z', '2', '6', '_', 'h', 'i', 0, |
| /* 3022 */ 'z', '6', '_', 'h', 'i', 0, |
| /* 3028 */ 'z', '1', '7', '_', 'h', 'i', 0, |
| /* 3035 */ 'z', '2', '7', '_', 'h', 'i', 0, |
| /* 3042 */ 'z', '7', '_', 'h', 'i', 0, |
| /* 3048 */ 'z', '1', '8', '_', 'h', 'i', 0, |
| /* 3055 */ 'z', '2', '8', '_', 'h', 'i', 0, |
| /* 3062 */ 'z', '8', '_', 'h', 'i', 0, |
| /* 3068 */ 'z', '1', '9', '_', 'h', 'i', 0, |
| /* 3075 */ 'z', '2', '9', '_', 'h', 'i', 0, |
| /* 3082 */ 'z', '9', '_', 'h', 'i', 0, |
| /* 3088 */ 'w', 's', 'p', 0, |
| /* 3092 */ 'f', 'f', 'r', 0, |
| /* 3096 */ 'w', 'z', 'r', 0, |
| /* 3100 */ 'x', 'z', 'r', 0, |
| /* 3104 */ 'n', 'z', 'c', 'v', 0, |
| }; |
| |
| static const uint16_t RegAsmOffsetNoRegAltName[] = { |
| 3092, 2763, 265, 3104, 3089, 3088, 3096, 3100, 332, 675, 946, 1217, 1488, 1759, |
| 2026, 2293, 2560, 2819, 53, 417, 763, 1037, 1308, 1579, 1850, 2117, 2384, 2651, |
| 153, 517, 863, 1137, 1408, 1679, 1946, 2213, 2480, 2739, 241, 597, 335, 678, |
| 949, 1220, 1491, 1762, 2029, 2296, 2563, 2822, 57, 421, 767, 1041, 1312, 1583, |
| 1854, 2121, 2388, 2655, 157, 521, 867, 1141, 1412, 1683, 1950, 2217, 2484, 2743, |
| 245, 601, 338, 681, 952, 1223, 1494, 1765, 2032, 2299, 2566, 2825, 61, 425, |
| 771, 1045, 1316, 1587, 1858, 2125, 2392, 2659, 161, 525, 871, 1145, 1416, 1687, |
| 1954, 2221, 2488, 2747, 249, 605, 341, 684, 955, 1226, 1497, 1768, 2035, 2302, |
| 2569, 2828, 65, 429, 775, 1049, 1320, 1591, 344, 687, 958, 1229, 1500, 1771, |
| 2038, 2305, 2572, 2831, 69, 433, 779, 1053, 1324, 1595, 1862, 2129, 2396, 2663, |
| 165, 529, 875, 1149, 1420, 1691, 1958, 2225, 2492, 2751, 253, 609, 347, 690, |
| 961, 1232, 1503, 1774, 2041, 2308, 2575, 2834, 73, 437, 783, 1057, 1328, 1599, |
| 1866, 2133, 2400, 2667, 169, 533, 879, 1153, 1424, 1695, 1962, 2229, 2496, 2755, |
| 257, 613, 350, 693, 964, 1235, 1506, 1777, 2044, 2311, 2578, 2837, 77, 441, |
| 787, 1061, 1332, 1603, 1870, 2137, 2404, 2671, 173, 537, 883, 1157, 1428, 1699, |
| 1966, 2233, 2500, 2759, 261, 353, 696, 967, 1238, 1509, 1780, 2047, 2314, 2581, |
| 2840, 81, 445, 791, 1065, 1336, 1607, 1874, 2141, 2408, 2675, 177, 541, 887, |
| 1161, 1432, 1703, 1970, 2237, 2504, 356, 699, 970, 1241, 1512, 1783, 2050, 2317, |
| 2584, 2843, 85, 449, 795, 1069, 1340, 1611, 1878, 2145, 2412, 2679, 181, 545, |
| 891, 1165, 1436, 1707, 1974, 2241, 2508, 2767, 269, 617, 2895, 2922, 2942, 2962, |
| 2982, 3002, 3022, 3042, 3062, 3082, 2874, 2901, 2928, 2948, 2968, 2988, 3008, 3028, |
| 3048, 3068, 2881, 2908, 2935, 2955, 2975, 2995, 3015, 3035, 3055, 3075, 2888, 2915, |
| 629, 902, 1175, 1446, 1717, 1984, 2251, 2518, 2777, 6, 365, 709, 981, 1252, |
| 1523, 1794, 2061, 2328, 2595, 97, 461, 807, 1081, 1352, 1623, 1890, 2157, 2424, |
| 2691, 193, 557, 281, 1169, 1440, 1711, 1978, 2245, 2512, 2771, 0, 359, 702, |
| 973, 1244, 1515, 1786, 2053, 2320, 2587, 89, 453, 799, 1073, 1344, 1615, 1882, |
| 2149, 2416, 2683, 185, 549, 273, 621, 895, 899, 1172, 1443, 1714, 1981, 2248, |
| 2515, 2774, 3, 362, 705, 977, 1248, 1519, 1790, 2057, 2324, 2591, 93, 457, |
| 803, 1077, 1348, 1619, 1886, 2153, 2420, 2687, 189, 553, 277, 625, 643, 915, |
| 1187, 1458, 1729, 1996, 2263, 2530, 2789, 19, 379, 724, 997, 1268, 1539, 1810, |
| 2077, 2344, 2611, 113, 477, 823, 1097, 1368, 1639, 1906, 2173, 2440, 2707, 209, |
| 573, 296, 1181, 1452, 1723, 1990, 2257, 2524, 2783, 13, 373, 717, 989, 1260, |
| 1531, 1802, 2069, 2336, 2603, 105, 469, 815, 1089, 1360, 1631, 1898, 2165, 2432, |
| 2699, 201, 565, 288, 635, 908, 912, 1184, 1455, 1726, 1993, 2260, 2527, 2786, |
| 16, 376, 720, 993, 1264, 1535, 1806, 2073, 2340, 2607, 109, 473, 819, 1093, |
| 1364, 1635, 1902, 2169, 2436, 2703, 205, 569, 292, 639, 303, 2859, 649, 921, |
| 1193, 1464, 1735, 2002, 2269, 2536, 2795, 26, 387, 732, 1005, 1276, 1547, 1818, |
| 2085, 2352, 2619, 121, 485, 831, 1105, 1376, 1647, 1914, 2181, 2448, 2715, 217, |
| 2853, 2867, 310, 2846, 655, 927, 1199, 1470, 1741, 2008, 2275, 2542, 2801, 33, |
| 395, 740, 1013, 1284, 1555, 1826, 2093, 2360, 2627, 129, 493, 839, 1113, 1384, |
| 1655, 1922, 2189, 2456, 669, 940, 1211, 1482, 1753, 2020, 2287, 2554, 2813, 46, |
| 409, 755, 1029, 1300, 1571, 1842, 2109, 2376, 2643, 145, 509, 855, 1129, 1400, |
| 1671, 1938, 2205, 2472, 2731, 233, 589, 325, 1205, 1476, 1747, 2014, 2281, 2548, |
| 2807, 40, 403, 748, 1021, 1292, 1563, 1834, 2101, 2368, 2635, 137, 501, 847, |
| 1121, 1392, 1663, 1930, 2197, 2464, 2723, 225, 581, 317, 661, 933, 937, 1208, |
| 1479, 1750, 2017, 2284, 2551, 2810, 43, 406, 751, 1025, 1296, 1567, 1838, 2105, |
| 2372, 2639, 141, 505, 851, 1125, 1396, 1667, 1934, 2201, 2468, 2727, 229, 585, |
| 321, 665, |
| }; |
| |
| static const char AsmStrsvlist1[] = { |
| /* 0 */ 0, |
| }; |
| |
| static const uint8_t RegAsmOffsetvlist1[] = { |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, |
| }; |
| |
| static const char AsmStrsvreg[] = { |
| /* 0 */ 'v', '1', '0', 0, |
| /* 4 */ 'v', '2', '0', 0, |
| /* 8 */ 'v', '3', '0', 0, |
| /* 12 */ 'v', '0', 0, |
| /* 15 */ 'v', '1', '1', 0, |
| /* 19 */ 'v', '2', '1', 0, |
| /* 23 */ 'v', '3', '1', 0, |
| /* 27 */ 'v', '1', 0, |
| /* 30 */ 'v', '1', '2', 0, |
| /* 34 */ 'v', '2', '2', 0, |
| /* 38 */ 'v', '2', 0, |
| /* 41 */ 'v', '1', '3', 0, |
| /* 45 */ 'v', '2', '3', 0, |
| /* 49 */ 'v', '3', 0, |
| /* 52 */ 'v', '1', '4', 0, |
| /* 56 */ 'v', '2', '4', 0, |
| /* 60 */ 'v', '4', 0, |
| /* 63 */ 'v', '1', '5', 0, |
| /* 67 */ 'v', '2', '5', 0, |
| /* 71 */ 'v', '5', 0, |
| /* 74 */ 'v', '1', '6', 0, |
| /* 78 */ 'v', '2', '6', 0, |
| /* 82 */ 'v', '6', 0, |
| /* 85 */ 'v', '1', '7', 0, |
| /* 89 */ 'v', '2', '7', 0, |
| /* 93 */ 'v', '7', 0, |
| /* 96 */ 'v', '1', '8', 0, |
| /* 100 */ 'v', '2', '8', 0, |
| /* 104 */ 'v', '8', 0, |
| /* 107 */ 'v', '1', '9', 0, |
| /* 111 */ 'v', '2', '9', 0, |
| /* 115 */ 'v', '9', 0, |
| }; |
| |
| static const uint8_t RegAsmOffsetvreg[] = { |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 12, 27, |
| 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, |
| 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, |
| 8, 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, |
| 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, |
| 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, |
| 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, |
| 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, |
| 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, |
| 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, |
| 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, |
| 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, |
| 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, |
| 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, |
| 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, |
| 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, |
| 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, |
| 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, |
| 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, |
| }; |
| |
| switch(AltIdx) { |
| default: llvm_unreachable("Invalid register alt name index!"); |
| case AArch64::NoRegAltName: |
| assert(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) && |
| "Invalid alt name index for register!"); |
| return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]; |
| case AArch64::vlist1: |
| assert(*(AsmStrsvlist1+RegAsmOffsetvlist1[RegNo-1]) && |
| "Invalid alt name index for register!"); |
| return AsmStrsvlist1+RegAsmOffsetvlist1[RegNo-1]; |
| case AArch64::vreg: |
| assert(*(AsmStrsvreg+RegAsmOffsetvreg[RegNo-1]) && |
| "Invalid alt name index for register!"); |
| return AsmStrsvreg+RegAsmOffsetvreg[RegNo-1]; |
| } |
| } |
| |
| #ifdef PRINT_ALIAS_INSTR |
| #undef PRINT_ALIAS_INSTR |
| |
| static bool AArch64InstPrinterValidateMCOperand(const MCOperand &MCOp, |
| const MCSubtargetInfo &STI, |
| unsigned PredicateIndex); |
| bool AArch64InstPrinter::printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &OS) { |
| const char *AsmString; |
| switch (MI->getOpcode()) { |
| default: return false; |
| case AArch64::ADDSWri: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg())) { |
| // (ADDSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) |
| AsmString = "cmn $\x02, $\xFF\x03\x01"; |
| break; |
| } |
| return false; |
| case AArch64::ADDSWrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "cmn $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) |
| AsmString = "cmn $\x02, $\x03$\xFF\x04\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ADDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "adds $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ADDSWrx: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 16) { |
| // (ADDSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) |
| AsmString = "cmn $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (ADDSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) |
| AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 16) { |
| // (ADDSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) |
| AsmString = "adds $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ADDSXri: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg())) { |
| // (ADDSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) |
| AsmString = "cmn $\x02, $\xFF\x03\x01"; |
| break; |
| } |
| return false; |
| case AArch64::ADDSXrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "cmn $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) |
| AsmString = "cmn $\x02, $\x03$\xFF\x04\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ADDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "adds $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ADDSXrx: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (ADDSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) |
| AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ADDSXrx64: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 24) { |
| // (ADDSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) |
| AsmString = "cmn $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (ADDSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) |
| AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 24) { |
| // (ADDSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) |
| AsmString = "adds $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ADDWri: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0) |
| AsmString = "mov $\x01, $\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0) |
| AsmString = "mov $\x01, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64::ADDWrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ADDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "add $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ADDWrx: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 16) { |
| // (ADDWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) |
| AsmString = "add $\x01, $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 16) { |
| // (ADDWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) |
| AsmString = "add $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ADDXri: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64sponlyRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0) |
| AsmString = "mov $\x01, $\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0) |
| AsmString = "mov $\x01, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64::ADDXrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ADDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "add $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ADDXrx64: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64sponlyRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 24) { |
| // (ADDXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) |
| AsmString = "add $\x01, $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 24) { |
| // (ADDXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) |
| AsmString = "add $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ANDSWri: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg())) { |
| // (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2) |
| AsmString = "tst $\x02, $\xFF\x03\x04"; |
| break; |
| } |
| return false; |
| case AArch64::ANDSWrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "tst $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh) |
| AsmString = "tst $\x02, $\x03$\xFF\x04\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ANDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "ands $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ANDSXri: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg())) { |
| // (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2) |
| AsmString = "tst $\x02, $\xFF\x03\x05"; |
| break; |
| } |
| return false; |
| case AArch64::ANDSXrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "tst $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh) |
| AsmString = "tst $\x02, $\x03$\xFF\x04\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ANDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "ands $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ANDS_PPzPP: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MI->getOperand(3).getReg() == MI->getOperand(2).getReg() && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ANDS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) |
| AsmString = "movs $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06"; |
| break; |
| } |
| return false; |
| case AArch64::ANDWrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ANDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "and $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ANDXrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ANDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "and $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::AND_PPzPP: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MI->getOperand(3).getReg() == MI->getOperand(2).getReg() && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (AND_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) |
| AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06"; |
| break; |
| } |
| return false; |
| case AArch64::AND_ZI: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64InstPrinterValidateMCOperand(MI->getOperand(2), STI, 1) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (AND_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) |
| AsmString = "and $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64InstPrinterValidateMCOperand(MI->getOperand(2), STI, 2) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (AND_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) |
| AsmString = "and $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64InstPrinterValidateMCOperand(MI->getOperand(2), STI, 3) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (AND_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) |
| AsmString = "and $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04"; |
| break; |
| } |
| return false; |
| case AArch64::BICSWrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (BICSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "bics $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::BICSXrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (BICSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "bics $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::BICWrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (BICWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "bic $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::BICXrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (BICXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "bic $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::CLREX: |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).isImm() && |
| MI->getOperand(0).getImm() == 15) { |
| // (CLREX 15) |
| AsmString = "clrex"; |
| break; |
| } |
| return false; |
| case AArch64::CNTB_XPiI: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 31 && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CNTB_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "cntb $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CNTB_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) |
| AsmString = "cntb $\x01, $\xFF\x02\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::CNTD_XPiI: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 31 && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CNTD_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "cntd $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CNTD_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) |
| AsmString = "cntd $\x01, $\xFF\x02\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::CNTH_XPiI: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 31 && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CNTH_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "cnth $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CNTH_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) |
| AsmString = "cnth $\x01, $\xFF\x02\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::CNTW_XPiI: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 31 && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CNTW_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "cntw $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CNTW_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) |
| AsmString = "cntw $\x01, $\xFF\x02\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPmI_B: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPmI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) |
| AsmString = "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\xFF\x04\x0F"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPmI_D: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) |
| AsmString = "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x11"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPmI_H: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) |
| AsmString = "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x12"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPmI_S: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) |
| AsmString = "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x13"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPmR_B: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPmR_B ZPR8:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) |
| AsmString = "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPmR_D: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPmR_D ZPR64:$Zd, PPR3bAny:$Pg, GPR64sp:$Rn) |
| AsmString = "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPmR_H: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPmR_H ZPR16:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) |
| AsmString = "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPmR_S: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPmR_S ZPR32:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) |
| AsmString = "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPmV_B: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPmV_B ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn) |
| AsmString = "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPmV_D: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPmV_D ZPR64:$Zd, PPR3bAny:$Pg, FPR64:$Vn) |
| AsmString = "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPmV_H: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::FPR16RegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPmV_H ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn) |
| AsmString = "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPmV_S: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPmV_S ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn) |
| AsmString = "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPzI_B: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPzI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) |
| AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x0F"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPzI_D: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPzI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) |
| AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x07/z, $\xFF\x03\x11"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPzI_H: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPzI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) |
| AsmString = "mov $\xFF\x01\x09, $\xFF\x02\x07/z, $\xFF\x03\x12"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPzI_S: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPzI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) |
| AsmString = "mov $\xFF\x01\x0B, $\xFF\x02\x07/z, $\xFF\x03\x13"; |
| break; |
| } |
| return false; |
| case AArch64::CSINCWr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::WZR && |
| MI->getOperand(2).getReg() == AArch64::WZR && |
| AArch64InstPrinterValidateMCOperand(MI->getOperand(3), STI, 4)) { |
| // (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) |
| AsmString = "cset $\x01, $\xFF\x04\x14"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MI->getOperand(2).getReg() == MI->getOperand(1).getReg() && |
| AArch64InstPrinterValidateMCOperand(MI->getOperand(3), STI, 4)) { |
| // (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) |
| AsmString = "cinc $\x01, $\x02, $\xFF\x04\x14"; |
| break; |
| } |
| return false; |
| case AArch64::CSINCXr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::XZR && |
| MI->getOperand(2).getReg() == AArch64::XZR && |
| AArch64InstPrinterValidateMCOperand(MI->getOperand(3), STI, 4)) { |
| // (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) |
| AsmString = "cset $\x01, $\xFF\x04\x14"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MI->getOperand(2).getReg() == MI->getOperand(1).getReg() && |
| AArch64InstPrinterValidateMCOperand(MI->getOperand(3), STI, 4)) { |
| // (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) |
| AsmString = "cinc $\x01, $\x02, $\xFF\x04\x14"; |
| break; |
| } |
| return false; |
| case AArch64::CSINVWr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::WZR && |
| MI->getOperand(2).getReg() == AArch64::WZR && |
| AArch64InstPrinterValidateMCOperand(MI->getOperand(3), STI, 4)) { |
| // (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) |
| AsmString = "csetm $\x01, $\xFF\x04\x14"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MI->getOperand(2).getReg() == MI->getOperand(1).getReg() && |
| AArch64InstPrinterValidateMCOperand(MI->getOperand(3), STI, 4)) { |
| // (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) |
| AsmString = "cinv $\x01, $\x02, $\xFF\x04\x14"; |
| break; |
| } |
| return false; |
| case AArch64::CSINVXr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::XZR && |
| MI->getOperand(2).getReg() == AArch64::XZR && |
| AArch64InstPrinterValidateMCOperand(MI->getOperand(3), STI, 4)) { |
| // (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) |
| AsmString = "csetm $\x01, $\xFF\x04\x14"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MI->getOperand(2).getReg() == MI->getOperand(1).getReg() && |
| AArch64InstPrinterValidateMCOperand(MI->getOperand(3), STI, 4)) { |
| // (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) |
| AsmString = "cinv $\x01, $\x02, $\xFF\x04\x14"; |
| break; |
| } |
| return false; |
| case AArch64::CSNEGWr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MI->getOperand(2).getReg() == MI->getOperand(1).getReg() && |
| AArch64InstPrinterValidateMCOperand(MI->getOperand(3), STI, 4)) { |
| // (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) |
| AsmString = "cneg $\x01, $\x02, $\xFF\x04\x14"; |
| break; |
| } |
| return false; |
| case AArch64::CSNEGXr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MI->getOperand(2).getReg() == MI->getOperand(1).getReg() && |
| AArch64InstPrinterValidateMCOperand(MI->getOperand(3), STI, 4)) { |
| // (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) |
| AsmString = "cneg $\x01, $\x02, $\xFF\x04\x14"; |
| break; |
| } |
| return false; |
| case AArch64::DCPS1: |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).isImm() && |
| MI->getOperand(0).getImm() == 0) { |
| // (DCPS1 0) |
| AsmString = "dcps1"; |
| break; |
| } |
| return false; |
| case AArch64::DCPS2: |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).isImm() && |
| MI->getOperand(0).getImm() == 0) { |
| // (DCPS2 0) |
| AsmString = "dcps2"; |
| break; |
| } |
| return false; |
| case AArch64::DCPS3: |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).isImm() && |
| MI->getOperand(0).getImm() == 0) { |
| // (DCPS3 0) |
| AsmString = "dcps3"; |
| break; |
| } |
| return false; |
| case AArch64::DECB_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "decb $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "decb $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::DECD_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "decd $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "decd $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::DECD_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "decd $\xFF\x01\x10"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "decd $\xFF\x01\x10, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::DECH_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "dech $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "dech $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::DECH_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "dech $\xFF\x01\x09"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "dech $\xFF\x01\x09, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::DECW_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "decw $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "decw $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::DECW_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "decw $\xFF\x01\x0B"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "decw $\xFF\x01\x0B, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::DUPM_ZI: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64InstPrinterValidateMCOperand(MI->getOperand(1), STI, 5) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUPM_ZI ZPR16:$Zd, sve_preferred_logical_imm16:$imm) |
| AsmString = "mov $\xFF\x01\x09, $\xFF\x02\x15"; |
| break; |
| } |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64InstPrinterValidateMCOperand(MI->getOperand(1), STI, 6) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUPM_ZI ZPR32:$Zd, sve_preferred_logical_imm32:$imm) |
| AsmString = "mov $\xFF\x01\x0B, $\xFF\x02\x16"; |
| break; |
| } |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64InstPrinterValidateMCOperand(MI->getOperand(1), STI, 7) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUPM_ZI ZPR64:$Zd, sve_preferred_logical_imm64:$imm) |
| AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x17"; |
| break; |
| } |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64InstPrinterValidateMCOperand(MI->getOperand(1), STI, 1) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUPM_ZI ZPR8:$Zd, sve_logical_imm8:$imm) |
| AsmString = "dupm $\xFF\x01\x06, $\xFF\x02\x08"; |
| break; |
| } |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64InstPrinterValidateMCOperand(MI->getOperand(1), STI, 2) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUPM_ZI ZPR16:$Zd, sve_logical_imm16:$imm) |
| AsmString = "dupm $\xFF\x01\x09, $\xFF\x02\x0A"; |
| break; |
| } |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64InstPrinterValidateMCOperand(MI->getOperand(1), STI, 3) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUPM_ZI ZPR32:$Zd, sve_logical_imm32:$imm) |
| AsmString = "dupm $\xFF\x01\x0B, $\xFF\x02\x04"; |
| break; |
| } |
| return false; |
| case AArch64::DUP_ZI_B: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZI_B ZPR8:$Zd, cpy_imm8_opt_lsl_i8:$imm) |
| AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x0F"; |
| break; |
| } |
| return false; |
| case AArch64::DUP_ZI_D: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZI_D ZPR64:$Zd, cpy_imm8_opt_lsl_i64:$imm) |
| AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x11"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 0 && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZI_D ZPR64:$Zd, 0, 0) |
| AsmString = "fmov $\xFF\x01\x10, #0.0"; |
| break; |
| } |
| return false; |
| case AArch64::DUP_ZI_H: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZI_H ZPR16:$Zd, cpy_imm8_opt_lsl_i16:$imm) |
| AsmString = "mov $\xFF\x01\x09, $\xFF\x02\x12"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 0 && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZI_H ZPR16:$Zd, 0, 0) |
| AsmString = "fmov $\xFF\x01\x09, #0.0"; |
| break; |
| } |
| return false; |
| case AArch64::DUP_ZI_S: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZI_S ZPR32:$Zd, cpy_imm8_opt_lsl_i32:$imm) |
| AsmString = "mov $\xFF\x01\x0B, $\xFF\x02\x13"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 0 && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZI_S ZPR32:$Zd, 0, 0) |
| AsmString = "fmov $\xFF\x01\x0B, #0.0"; |
| break; |
| } |
| return false; |
| case AArch64::DUP_ZR_B: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZR_B ZPR8:$Zd, GPR32sp:$Rn) |
| AsmString = "mov $\xFF\x01\x06, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64::DUP_ZR_D: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZR_D ZPR64:$Zd, GPR64sp:$Rn) |
| AsmString = "mov $\xFF\x01\x10, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64::DUP_ZR_H: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZR_H ZPR16:$Zd, GPR32sp:$Rn) |
| AsmString = "mov $\xFF\x01\x09, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64::DUP_ZR_S: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZR_S ZPR32:$Zd, GPR32sp:$Rn) |
| AsmString = "mov $\xFF\x01\x0B, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64::DUP_ZZI_B: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZZI_B ZPR8:$Zd, FPR8asZPR:$Bn, 0) |
| AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x18"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZZI_B ZPR8:$Zd, ZPR8:$Zn, sve_elm_idx_extdup_b:$idx) |
| AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x06$\xFF\x03\x19"; |
| break; |
| } |
| return false; |
| case AArch64::DUP_ZZI_D: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZZI_D ZPR64:$Zd, FPR64asZPR:$Dn, 0) |
| AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x1A"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZZI_D ZPR64:$Zd, ZPR64:$Zn, sve_elm_idx_extdup_d:$idx) |
| AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x10$\xFF\x03\x19"; |
| break; |
| } |
| return false; |
| case AArch64::DUP_ZZI_H: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZZI_H ZPR16:$Zd, FPR16asZPR:$Hn, 0) |
| AsmString = "mov $\xFF\x01\x09, $\xFF\x02\x1B"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZZI_H ZPR16:$Zd, ZPR16:$Zn, sve_elm_idx_extdup_h:$idx) |
| AsmString = "mov $\xFF\x01\x09, $\xFF\x02\x09$\xFF\x03\x19"; |
| break; |
| } |
| return false; |
| case AArch64::DUP_ZZI_Q: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZZI_Q ZPR128:$Zd, FPR128asZPR:$Qn, 0) |
| AsmString = "mov $\xFF\x01\x1C, $\xFF\x02\x1D"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZZI_Q ZPR128:$Zd, ZPR128:$Zn, sve_elm_idx_extdup_q:$idx) |
| AsmString = "mov $\xFF\x01\x1C, $\xFF\x02\x1C$\xFF\x03\x19"; |
| break; |
| } |
| return false; |
| case AArch64::DUP_ZZI_S: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZZI_S ZPR32:$Zd, FPR32asZPR:$Sn, 0) |
| AsmString = "mov $\xFF\x01\x0B, $\xFF\x02\x1E"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZZI_S ZPR32:$Zd, ZPR32:$Zn, sve_elm_idx_extdup_s:$idx) |
| AsmString = "mov $\xFF\x01\x0B, $\xFF\x02\x0B$\xFF\x03\x19"; |
| break; |
| } |
| return false; |
| case AArch64::EONWrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (EONWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "eon $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::EONXrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (EONXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "eon $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::EORS_PPzPP: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MI->getOperand(3).getReg() == MI->getOperand(1).getReg() && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (EORS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) |
| AsmString = "nots $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06"; |
| break; |
| } |
| return false; |
| case AArch64::EORWrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (EORWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "eor $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::EORXrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (EORXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "eor $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::EOR_PPzPP: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MI->getOperand(3).getReg() == MI->getOperand(1).getReg() && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (EOR_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) |
| AsmString = "not $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06"; |
| break; |
| } |
| return false; |
| case AArch64::EOR_ZI: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64InstPrinterValidateMCOperand(MI->getOperand(2), STI, 1) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (EOR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) |
| AsmString = "eor $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64InstPrinterValidateMCOperand(MI->getOperand(2), STI, 2) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (EOR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) |
| AsmString = "eor $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64InstPrinterValidateMCOperand(MI->getOperand(2), STI, 3) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (EOR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) |
| AsmString = "eor $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04"; |
| break; |
| } |
| return false; |
| case AArch64::EXTRWrri: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MI->getOperand(2).getReg() == MI->getOperand(1).getReg()) { |
| // (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift) |
| AsmString = "ror $\x01, $\x02, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::EXTRXrri: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MI->getOperand(2).getReg() == MI->getOperand(1).getReg()) { |
| // (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift) |
| AsmString = "ror $\x01, $\x02, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::FCPY_ZPmI_D: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (FCPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, fpimm64:$imm8) |
| AsmString = "fmov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x1F"; |
| break; |
| } |
| return false; |
| case AArch64::FCPY_ZPmI_H: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (FCPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, fpimm16:$imm8) |
| AsmString = "fmov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x1F"; |
| break; |
| } |
| return false; |
| case AArch64::FCPY_ZPmI_S: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (FCPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, fpimm32:$imm8) |
| AsmString = "fmov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x1F"; |
| break; |
| } |
| return false; |
| case AArch64::FDUP_ZI_D: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (FDUP_ZI_D ZPR64:$Zd, fpimm64:$imm8) |
| AsmString = "fmov $\xFF\x01\x10, $\xFF\x02\x1F"; |
| break; |
| } |
| return false; |
| case AArch64::FDUP_ZI_H: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (FDUP_ZI_H ZPR16:$Zd, fpimm16:$imm8) |
| AsmString = "fmov $\xFF\x01\x09, $\xFF\x02\x1F"; |
| break; |
| } |
| return false; |
| case AArch64::FDUP_ZI_S: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (FDUP_ZI_S ZPR32:$Zd, fpimm32:$imm8) |
| AsmString = "fmov $\xFF\x01\x0B, $\xFF\x02\x1F"; |
| break; |
| } |
| return false; |
| case AArch64::GLD1B_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLD1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ld1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLD1B_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLD1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "ld1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::GLD1D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLD1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ld1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLD1H_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLD1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ld1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLD1H_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLD1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "ld1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::GLD1SB_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLD1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ld1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLD1SB_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLD1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "ld1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::GLD1SH_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLD1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ld1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLD1SH_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLD1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "ld1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::GLD1SW_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLD1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ld1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLD1W_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLD1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ld1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLD1W_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLD1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "ld1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::GLDFF1B_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLDFF1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ldff1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLDFF1B_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLDFF1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "ldff1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::GLDFF1D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLDFF1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ldff1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLDFF1H_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLDFF1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ldff1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLDFF1H_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLDFF1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "ldff1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::GLDFF1SB_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLDFF1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ldff1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLDFF1SB_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLDFF1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "ldff1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::GLDFF1SH_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLDFF1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ldff1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLDFF1SH_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLDFF1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "ldff1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::GLDFF1SW_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLDFF1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ldff1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLDFF1W_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLDFF1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ldff1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLDFF1W_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLDFF1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "ldff1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::HINT: |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).isImm() && |
| MI->getOperand(0).getImm() == 0) { |
| // (HINT { 0, 0, 0 }) |
| AsmString = "nop"; |
| break; |
| } |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).isImm() && |
| MI->getOperand(0).getImm() == 1) { |
| // (HINT { 0, 0, 1 }) |
| AsmString = "yield"; |
| break; |
| } |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).isImm() && |
| MI->getOperand(0).getImm() == 2) { |
| // (HINT { 0, 1, 0 }) |
| AsmString = "wfe"; |
| break; |
| } |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).isImm() && |
| MI->getOperand(0).getImm() == 3) { |
| // (HINT { 0, 1, 1 }) |
| AsmString = "wfi"; |
| break; |
| } |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).isImm() && |
| MI->getOperand(0).getImm() == 4) { |
| // (HINT { 1, 0, 0 }) |
| AsmString = "sev"; |
| break; |
| } |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).isImm() && |
| MI->getOperand(0).getImm() == 5) { |
| // (HINT { 1, 0, 1 }) |
| AsmString = "sevl"; |
| break; |
| } |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).isImm() && |
| MI->getOperand(0).getImm() == 16 && |
| STI.getFeatureBits()[AArch64::FeatureRAS]) { |
| // (HINT { 1, 0, 0, 0, 0 }) |
| AsmString = "esb"; |
| break; |
| } |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).isImm() && |
| MI->getOperand(0).getImm() == 20) { |
| // (HINT 20) |
| AsmString = "csdb"; |
| break; |
| } |
| if (MI->getNumOperands() == 1 && |
| AArch64InstPrinterValidateMCOperand(MI->getOperand(0), STI, 8) && |
| STI.getFeatureBits()[AArch64::FeatureSPE]) { |
| // (HINT psbhint_op:$op) |
| AsmString = "psb $\xFF\x01\x22"; |
| break; |
| } |
| return false; |
| case AArch64::INCB_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "incb $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "incb $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::INCD_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "incd $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "incd $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::INCD_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "incd $\xFF\x01\x10"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "incd $\xFF\x01\x10, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::INCH_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "inch $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "inch $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::INCH_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "inch $\xFF\x01\x09"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "inch $\xFF\x01\x09, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::INCW_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "incw $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "incw $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::INCW_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "incw $\xFF\x01\x0B"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "incw $\xFF\x01\x0B, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::INSvi16gpr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (INSvi16gpr V128:$dst, VectorIndexH:$idx, GPR32:$src) |
| AsmString = "mov $\xFF\x01\x0C.h$\xFF\x03\x19, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::INSvi16lane: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (INSvi16lane V128:$dst, VectorIndexH:$idx, V128:$src, VectorIndexH:$idx2) |
| AsmString = "mov $\xFF\x01\x0C.h$\xFF\x03\x19, $\xFF\x04\x0C.h$\xFF\x05\x19"; |
| break; |
| } |
| return false; |
| case AArch64::INSvi32gpr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (INSvi32gpr V128:$dst, VectorIndexS:$idx, GPR32:$src) |
| AsmString = "mov $\xFF\x01\x0C.s$\xFF\x03\x19, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::INSvi32lane: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (INSvi32lane V128:$dst, VectorIndexS:$idx, V128:$src, VectorIndexS:$idx2) |
| AsmString = "mov $\xFF\x01\x0C.s$\xFF\x03\x19, $\xFF\x04\x0C.s$\xFF\x05\x19"; |
| break; |
| } |
| return false; |
| case AArch64::INSvi64gpr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (INSvi64gpr V128:$dst, VectorIndexD:$idx, GPR64:$src) |
| AsmString = "mov $\xFF\x01\x0C.d$\xFF\x03\x19, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::INSvi64lane: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (INSvi64lane V128:$dst, VectorIndexD:$idx, V128:$src, VectorIndexD:$idx2) |
| AsmString = "mov $\xFF\x01\x0C.d$\xFF\x03\x19, $\xFF\x04\x0C.d$\xFF\x05\x19"; |
| break; |
| } |
| return false; |
| case AArch64::INSvi8gpr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (INSvi8gpr V128:$dst, VectorIndexB:$idx, GPR32:$src) |
| AsmString = "mov $\xFF\x01\x0C.b$\xFF\x03\x19, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::INSvi8lane: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (INSvi8lane V128:$dst, VectorIndexB:$idx, V128:$src, VectorIndexB:$idx2) |
| AsmString = "mov $\xFF\x01\x0C.b$\xFF\x03\x19, $\xFF\x04\x0C.b$\xFF\x05\x19"; |
| break; |
| } |
| return false; |
| case AArch64::ISB: |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).isImm() && |
| MI->getOperand(0).getImm() == 15) { |
| // (ISB 15) |
| AsmString = "isb"; |
| break; |
| } |
| return false; |
| case AArch64::LD1B_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1B_H_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1B_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1B_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1B_IMM_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1B_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Fourv16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x25, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Fourv1d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x26, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Fourv2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x27, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Fourv2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x28, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Fourv4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x29, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Fourv4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x2A, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Fourv8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x2B, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Fourv8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x2C, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::LD1H_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1H_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1H_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Onev16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x25, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Onev1d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x26, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Onev2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x27, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Onev2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x28, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Onev4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x29, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Onev4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x2A, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Onev8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x2B, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Onev8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x2C, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RB_D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RB_H_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RB_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RB_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RB_S_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RD_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RD_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rd $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RH_D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RH_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RH_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RH_S_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RQ_B_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RQ_B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rqb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RQ_D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RQ_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rqd $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RQ_H_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RQ_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rqh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RQ_W_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RQ_W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rqw $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RSB_D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RSB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rsb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RSB_H_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RSB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rsb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RSB_S_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RSB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rsb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RSH_D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RSH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rsh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RSH_S_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RSH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rsh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RSW_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RSW_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rsw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RW_D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RW_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RW_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rw $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Rv16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Rv16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) |
| AsmString = "ld1r $\xFF\x02\x25, [$\x01], #1"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Rv1d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Rv1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) |
| AsmString = "ld1r $\xFF\x02\x26, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Rv2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Rv2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) |
| AsmString = "ld1r $\xFF\x02\x27, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Rv2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Rv2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) |
| AsmString = "ld1r $\xFF\x02\x28, [$\x01], #4"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Rv4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Rv4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) |
| AsmString = "ld1r $\xFF\x02\x29, [$\x01], #2"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Rv4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Rv4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) |
| AsmString = "ld1r $\xFF\x02\x2A, [$\x01], #4"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Rv8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Rv8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) |
| AsmString = "ld1r $\xFF\x02\x2B, [$\x01], #1"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Rv8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Rv8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) |
| AsmString = "ld1r $\xFF\x02\x2C, [$\x01], #2"; |
| break; |
| } |
| return false; |
| case AArch64::LD1SB_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1SB_H_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1SB_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1SB_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1SH_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1SH_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1SW_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Threev16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x25, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Threev1d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x26, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Threev2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x27, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Threev2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x28, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Threev4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x29, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Threev4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x2A, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Threev8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x2B, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Threev8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x2C, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Twov16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x25, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Twov1d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x26, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Twov2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x27, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Twov2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x28, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Twov4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x29, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Twov4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x2A, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Twov8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x2B, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Twov8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x2C, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD1W_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1W_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1i16_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) |
| AsmString = "ld1 $\xFF\x02\x2D$\xFF\x04\x19, [$\x01], #2"; |
| break; |
| } |
| return false; |
| case AArch64::LD1i32_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) |
| AsmString = "ld1 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #4"; |
| break; |
| } |
| return false; |
| case AArch64::LD1i64_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) |
| AsmString = "ld1 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::LD1i8_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) |
| AsmString = "ld1 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #1"; |
| break; |
| } |
| return false; |
| case AArch64::LD2B_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR2RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld2b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD2D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR2RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld2d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD2H_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR2RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld2h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Rv16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Rv16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) |
| AsmString = "ld2r $\xFF\x02\x25, [$\x01], #2"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Rv1d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Rv1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) |
| AsmString = "ld2r $\xFF\x02\x26, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Rv2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Rv2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) |
| AsmString = "ld2r $\xFF\x02\x27, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Rv2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Rv2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) |
| AsmString = "ld2r $\xFF\x02\x28, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Rv4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Rv4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) |
| AsmString = "ld2r $\xFF\x02\x29, [$\x01], #4"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Rv4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Rv4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) |
| AsmString = "ld2r $\xFF\x02\x2A, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Rv8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Rv8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) |
| AsmString = "ld2r $\xFF\x02\x2B, [$\x01], #2"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Rv8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Rv8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) |
| AsmString = "ld2r $\xFF\x02\x2C, [$\x01], #4"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Twov16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) |
| AsmString = "ld2 $\xFF\x02\x25, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Twov2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) |
| AsmString = "ld2 $\xFF\x02\x27, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Twov2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) |
| AsmString = "ld2 $\xFF\x02\x28, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Twov4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) |
| AsmString = "ld2 $\xFF\x02\x29, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Twov4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) |
| AsmString = "ld2 $\xFF\x02\x2A, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Twov8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) |
| AsmString = "ld2 $\xFF\x02\x2B, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Twov8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) |
| AsmString = "ld2 $\xFF\x02\x2C, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD2W_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR2RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld2w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD2i16_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) |
| AsmString = "ld2 $\xFF\x02\x2D$\xFF\x04\x19, [$\x01], #4"; |
| break; |
| } |
| return false; |
| case AArch64::LD2i32_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) |
| AsmString = "ld2 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::LD2i64_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) |
| AsmString = "ld2 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD2i8_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) |
| AsmString = "ld2 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #2"; |
| break; |
| } |
| return false; |
| case AArch64::LD3B_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR3RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld3b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD3D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR3RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld3d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD3H_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR3RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld3h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Rv16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Rv16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) |
| AsmString = "ld3r $\xFF\x02\x25, [$\x01], #3"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Rv1d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Rv1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) |
| AsmString = "ld3r $\xFF\x02\x26, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Rv2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Rv2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) |
| AsmString = "ld3r $\xFF\x02\x27, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Rv2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Rv2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) |
| AsmString = "ld3r $\xFF\x02\x28, [$\x01], #12"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Rv4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Rv4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) |
| AsmString = "ld3r $\xFF\x02\x29, [$\x01], #6"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Rv4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Rv4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) |
| AsmString = "ld3r $\xFF\x02\x2A, [$\x01], #12"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Rv8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Rv8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) |
| AsmString = "ld3r $\xFF\x02\x2B, [$\x01], #3"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Rv8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Rv8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) |
| AsmString = "ld3r $\xFF\x02\x2C, [$\x01], #6"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Threev16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) |
| AsmString = "ld3 $\xFF\x02\x25, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Threev2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) |
| AsmString = "ld3 $\xFF\x02\x27, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Threev2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) |
| AsmString = "ld3 $\xFF\x02\x28, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Threev4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) |
| AsmString = "ld3 $\xFF\x02\x29, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Threev4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) |
| AsmString = "ld3 $\xFF\x02\x2A, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Threev8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) |
| AsmString = "ld3 $\xFF\x02\x2B, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Threev8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) |
| AsmString = "ld3 $\xFF\x02\x2C, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::LD3W_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR3RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld3w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD3i16_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) |
| AsmString = "ld3 $\xFF\x02\x2D$\xFF\x04\x19, [$\x01], #6"; |
| break; |
| } |
| return false; |
| case AArch64::LD3i32_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) |
| AsmString = "ld3 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #12"; |
| break; |
| } |
| return false; |
| case AArch64::LD3i64_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) |
| AsmString = "ld3 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::LD3i8_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) |
| AsmString = "ld3 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #3"; |
| break; |
| } |
| return false; |
| case AArch64::LD4B_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld4b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD4D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld4d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Fourv16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) |
| AsmString = "ld4 $\xFF\x02\x25, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Fourv2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) |
| AsmString = "ld4 $\xFF\x02\x27, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Fourv2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) |
| AsmString = "ld4 $\xFF\x02\x28, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Fourv4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) |
| AsmString = "ld4 $\xFF\x02\x29, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Fourv4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) |
| AsmString = "ld4 $\xFF\x02\x2A, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Fourv8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) |
| AsmString = "ld4 $\xFF\x02\x2B, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Fourv8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) |
| AsmString = "ld4 $\xFF\x02\x2C, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::LD4H_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld4h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Rv16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Rv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) |
| AsmString = "ld4r $\xFF\x02\x25, [$\x01], #4"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Rv1d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Rv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) |
| AsmString = "ld4r $\xFF\x02\x26, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Rv2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Rv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) |
| AsmString = "ld4r $\xFF\x02\x27, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Rv2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Rv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) |
| AsmString = "ld4r $\xFF\x02\x28, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Rv4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Rv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) |
| AsmString = "ld4r $\xFF\x02\x29, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Rv4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Rv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) |
| AsmString = "ld4r $\xFF\x02\x2A, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Rv8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Rv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) |
| AsmString = "ld4r $\xFF\x02\x2B, [$\x01], #4"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Rv8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Rv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) |
| AsmString = "ld4r $\xFF\x02\x2C, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::LD4W_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld4w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD4i16_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) |
| AsmString = "ld4 $\xFF\x02\x2D$\xFF\x04\x19, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::LD4i32_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) |
| AsmString = "ld4 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD4i64_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) |
| AsmString = "ld4 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD4i8_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) |
| AsmString = "ld4 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #4"; |
| break; |
| } |
| return false; |
| case AArch64::LDADDB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDADDB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "staddb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDADDH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDADDH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "staddh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDADDLB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDADDLB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "staddlb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDADDLH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDADDLH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "staddlh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDADDLW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDADDLW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "staddl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDADDLX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDADDLX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "staddl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDADDW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDADDW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stadd $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDADDX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDADDX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "stadd $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDAPURBi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_4aOps]) { |
| // (LDAPURBi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldapurb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDAPURHi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_4aOps]) { |
| // (LDAPURHi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldapurh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDAPURSBWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_4aOps]) { |
| // (LDAPURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldapursb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDAPURSBXi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_4aOps]) { |
| // (LDAPURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldapursb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDAPURSHWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_4aOps]) { |
| // (LDAPURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldapursh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDAPURSHXi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_4aOps]) { |
| // (LDAPURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldapursh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDAPURSWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_4aOps]) { |
| // (LDAPURSWi GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldapursw $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDAPURXi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_4aOps]) { |
| // (LDAPURXi GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldapur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDAPURi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_4aOps]) { |
| // (LDAPURi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldapur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDCLRB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDCLRB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stclrb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDCLRH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDCLRH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stclrh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDCLRLB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDCLRLB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stclrlb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDCLRLH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDCLRLH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stclrlh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDCLRLW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDCLRLW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stclrl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDCLRLX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDCLRLX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "stclrl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDCLRW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDCLRW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stclr $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDCLRX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDCLRX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "stclr $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDEORB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDEORB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "steorb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDEORH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDEORH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "steorh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDEORLB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDEORLB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "steorlb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDEORLH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDEORLH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "steorlh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDEORLW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDEORLW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "steorl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDEORLX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDEORLX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "steorl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDEORW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDEORW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "steor $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDEORX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDEORX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "steor $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1B_D_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1B_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1B_H_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1B_H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1B_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1B_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1B_S_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1B_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1D_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1H_D_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1H_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1H_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1H_S_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1H_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1SB_D_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1SB_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1SB_H_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1SB_H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1SB_S_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1SB_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1SH_D_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1SH_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1SH_S_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1SH_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1SW_D_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1SW_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1W_D_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1W_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1W_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1W_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1B_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1B_H_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1B_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1B_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1B_IMM_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1B_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1H_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1H_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1H_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1SB_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1SB_H_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1SB_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1SB_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1SH_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1SH_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1SW_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1W_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1W_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNPDi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (LDNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "ldnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNPQi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (LDNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "ldnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNPSi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (LDNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "ldnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNPWi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (LDNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "ldnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNPXi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (LDNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "ldnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNT1B_ZRI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnt1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNT1D_ZRI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnt1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNT1H_ZRI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnt1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNT1W_ZRI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnt1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDPDi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (LDPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "ldp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDPQi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (LDPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "ldp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDPSWi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (LDPSWi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "ldpsw $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDPSi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (LDPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "ldp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDPWi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (LDPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "ldp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDPXi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (LDPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "ldp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRAAindexed: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_3aOps]) { |
| // (LDRAAindexed GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldraa $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRABindexed: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_3aOps]) { |
| // (LDRABindexed GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldrab $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRBBroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldrb $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRBBui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRBBui GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldrb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRBroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldr $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRBui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRDroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldr $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRDui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRHHroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldrh $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRHHui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRHHui GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldrh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRHroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR16RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldr $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRHui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR16RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRQroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldr $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRQui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRSBWroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRSBWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldrsb $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRSBWui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRSBWui GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldrsb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRSBXroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRSBXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldrsb $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRSBXui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRSBXui GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldrsb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRSHWroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRSHWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldrsh $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRSHWui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRSHWui GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldrsh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRSHXroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRSHXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldrsh $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRSHXui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRSHXui GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldrsh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRSWroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRSWroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldrsw $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRSWui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRSWui GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldrsw $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRSroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldr $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRSui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRWroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldr $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRWui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRWui GPR32z:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRXroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldr $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRXui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRXui GPR64z:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDR_PXI: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDR_PXI PPRAny:$Pt, GPR64sp:$Rn, 0) |
| AsmString = "ldr $\xFF\x01\x07, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDR_ZXI: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) |
| AsmString = "ldr $\xFF\x01\x07, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSETB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSETB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsetb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSETH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSETH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stseth $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSETLB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSETLB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsetlb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSETLH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSETLH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsetlh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSETLW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSETLW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsetl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSETLX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSETLX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "stsetl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSETW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSETW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stset $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSETX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSETX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "stset $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMAXB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsmaxb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMAXH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsmaxh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMAXLB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsmaxlb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMAXLH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsmaxlh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMAXLW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsmaxl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMAXLX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "stsmaxl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMAXW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsmax $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMAXX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "stsmax $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMINB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMINB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsminb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMINH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMINH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsminh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMINLB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsminlb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMINLH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsminlh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMINLW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsminl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMINLX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "stsminl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMINW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMINW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsmin $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMINX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMINX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "stsmin $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDTRBi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDTRBi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldtrb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDTRHi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDTRHi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldtrh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDTRSBWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDTRSBWi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldtrsb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDTRSBXi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDTRSBXi GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldtrsb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDTRSHWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDTRSHWi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldtrsh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDTRSHXi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDTRSHXi GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldtrsh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDTRSWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDTRSWi GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldtrsw $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDTRWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDTRWi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldtr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDTRXi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDTRXi GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldtr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMAXB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stumaxb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMAXH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stumaxh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMAXLB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stumaxlb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMAXLH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stumaxlh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMAXLW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stumaxl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMAXLX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "stumaxl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMAXW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stumax $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMAXX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "stumax $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMINB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMINB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stuminb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMINH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMINH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stuminh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMINLB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stuminlb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMINLH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stuminlh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMINLW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stuminl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMINLX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "stuminl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMINW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMINW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stumin $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMINX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMINX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "stumin $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURBBi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURBBi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldurb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURBi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURDi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURHHi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURHHi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldurh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURHi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR16RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURQi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURSBWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldursb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURSBXi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldursb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURSHWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldursh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURSHXi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldursh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURSWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURSWi GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldursw $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURSi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURWi GPR32z:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURXi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURXi GPR64z:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::MADDWrrr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::WZR) { |
| // (MADDWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) |
| AsmString = "mul $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::MADDXrrr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR) { |
| // (MADDXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) |
| AsmString = "mul $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::MSUBWrrr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::WZR) { |
| // (MSUBWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) |
| AsmString = "mneg $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::MSUBXrrr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR) { |
| // (MSUBXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) |
| AsmString = "mneg $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::NOTv16i8: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg())) { |
| // (NOTv16i8 V128:$Vd, V128:$Vn) |
| AsmString = "mvn $\xFF\x01\x0C.16b, $\xFF\x02\x0C.16b"; |
| break; |
| } |
| return false; |
| case AArch64::NOTv8i8: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg())) { |
| // (NOTv8i8 V64:$Vd, V64:$Vn) |
| AsmString = "mvn $\xFF\x01\x0C.8b, $\xFF\x02\x0C.8b"; |
| break; |
| } |
| return false; |
| case AArch64::ORNWrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::WZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0) |
| AsmString = "mvn $\x01, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::WZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh) |
| AsmString = "mvn $\x01, $\x03$\xFF\x04\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ORNWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "orn $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ORNXrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::XZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0) |
| AsmString = "mvn $\x01, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::XZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh) |
| AsmString = "mvn $\x01, $\x03$\xFF\x04\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ORNXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "orn $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ORRS_PPzPP: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MI->getOperand(2).getReg() == MI->getOperand(1).getReg() && |
| MI->getOperand(3).isReg() && |
| MI->getOperand(3).getReg() == MI->getOperand(1).getReg() && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ORRS_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) |
| AsmString = "movs $\xFF\x01\x06, $\xFF\x02\x06"; |
| break; |
| } |
| return false; |
| case AArch64::ORRWrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::WZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0) |
| AsmString = "mov $\x01, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ORRWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "orr $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ORRXrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::XZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0) |
| AsmString = "mov $\x01, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ORRXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "orr $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ORR_PPzPP: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MI->getOperand(2).getReg() == MI->getOperand(1).getReg() && |
| MI->getOperand(3).isReg() && |
| MI->getOperand(3).getReg() == MI->getOperand(1).getReg() && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ORR_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) |
| AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x06"; |
| break; |
| } |
| return false; |
| case AArch64::ORR_ZI: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64InstPrinterValidateMCOperand(MI->getOperand(2), STI, 1) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ORR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) |
| AsmString = "orr $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64InstPrinterValidateMCOperand(MI->getOperand(2), STI, 2) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ORR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) |
| AsmString = "orr $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64InstPrinterValidateMCOperand(MI->getOperand(2), STI, 3) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ORR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) |
| AsmString = "orr $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04"; |
| break; |
| } |
| return false; |
| case AArch64::ORR_ZZZ: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MI->getOperand(2).getReg() == MI->getOperand(1).getReg() && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn) |
| AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x10"; |
| break; |
| } |
| return false; |
| case AArch64::ORRv16i8: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MI->getOperand(2).getReg() == MI->getOperand(1).getReg()) { |
| // (ORRv16i8 V128:$dst, V128:$src, V128:$src) |
| AsmString = "mov $\xFF\x01\x0C.16b, $\xFF\x02\x0C.16b"; |
| break; |
| } |
| return false; |
| case AArch64::ORRv8i8: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MI->getOperand(2).getReg() == MI->getOperand(1).getReg()) { |
| // (ORRv8i8 V64:$dst, V64:$src, V64:$src) |
| AsmString = "mov $\xFF\x01\x0C.8b, $\xFF\x02\x0C.8b"; |
| break; |
| } |
| return false; |
| case AArch64::PRFB_D_PZI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PRFB_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "prfb $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFB_PRI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PRFB_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "prfb $\xFF\x01\x32, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFB_S_PZI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PRFB_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "prfb $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFD_D_PZI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PRFD_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "prfd $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFD_PRI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PRFD_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "prfd $\xFF\x01\x32, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFD_S_PZI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PRFD_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "prfd $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFH_D_PZI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PRFH_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "prfh $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFH_PRI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PRFH_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "prfh $\xFF\x01\x32, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFH_S_PZI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PRFH_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "prfh $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFMroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (PRFMroX prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "prfm $\xFF\x01\x33, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFMui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (PRFMui prfop:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "prfm $\xFF\x01\x33, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFUMi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (PRFUMi prfop:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "prfum $\xFF\x01\x33, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFW_D_PZI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PRFW_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "prfw $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFW_PRI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PRFW_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "prfw $\xFF\x01\x32, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFW_S_PZI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PRFW_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "prfw $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::PTRUES_B: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 31 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PTRUES_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) |
| AsmString = "ptrues $\xFF\x01\x06"; |
| break; |
| } |
| return false; |
| case AArch64::PTRUES_D: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 31 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PTRUES_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) |
| AsmString = "ptrues $\xFF\x01\x10"; |
| break; |
| } |
| return false; |
| case AArch64::PTRUES_H: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 31 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PTRUES_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) |
| AsmString = "ptrues $\xFF\x01\x09"; |
| break; |
| } |
| return false; |
| case AArch64::PTRUES_S: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 31 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PTRUES_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) |
| AsmString = "ptrues $\xFF\x01\x0B"; |
| break; |
| } |
| return false; |
| case AArch64::PTRUE_B: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 31 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PTRUE_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) |
| AsmString = "ptrue $\xFF\x01\x06"; |
| break; |
| } |
| return false; |
| case AArch64::PTRUE_D: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 31 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PTRUE_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) |
| AsmString = "ptrue $\xFF\x01\x10"; |
| break; |
| } |
| return false; |
| case AArch64::PTRUE_H: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 31 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PTRUE_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) |
| AsmString = "ptrue $\xFF\x01\x09"; |
| break; |
| } |
| return false; |
| case AArch64::PTRUE_S: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 31 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PTRUE_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) |
| AsmString = "ptrue $\xFF\x01\x0B"; |
| break; |
| } |
| return false; |
| case AArch64::RET: |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).getReg() == AArch64::LR) { |
| // (RET LR) |
| AsmString = "ret"; |
| break; |
| } |
| return false; |
| case AArch64::SBCSWr: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::WZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (SBCSWr GPR32:$dst, WZR, GPR32:$src) |
| AsmString = "ngcs $\x01, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SBCSXr: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::XZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (SBCSXr GPR64:$dst, XZR, GPR64:$src) |
| AsmString = "ngcs $\x01, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SBCWr: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::WZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (SBCWr GPR32:$dst, WZR, GPR32:$src) |
| AsmString = "ngc $\x01, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SBCXr: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::XZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (SBCXr GPR64:$dst, XZR, GPR64:$src) |
| AsmString = "ngc $\x01, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SBFMWri: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 31) { |
| // (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) |
| AsmString = "asr $\x01, $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 7) { |
| // (SBFMWri GPR32:$dst, GPR32:$src, 0, 7) |
| AsmString = "sxtb $\x01, $\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 15) { |
| // (SBFMWri GPR32:$dst, GPR32:$src, 0, 15) |
| AsmString = "sxth $\x01, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64::SBFMXri: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 63) { |
| // (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) |
| AsmString = "asr $\x01, $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 7) { |
| // (SBFMXri GPR64:$dst, GPR64:$src, 0, 7) |
| AsmString = "sxtb $\x01, $\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 15) { |
| // (SBFMXri GPR64:$dst, GPR64:$src, 0, 15) |
| AsmString = "sxth $\x01, $\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 31) { |
| // (SBFMXri GPR64:$dst, GPR64:$src, 0, 31) |
| AsmString = "sxtw $\x01, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64::SEL_PPPP: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MI->getOperand(3).getReg() == MI->getOperand(0).getReg() && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SEL_PPPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pd) |
| AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x07/m, $\xFF\x03\x06"; |
| break; |
| } |
| return false; |
| case AArch64::SEL_ZPZZ_B: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MI->getOperand(3).getReg() == MI->getOperand(0).getReg() && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SEL_ZPZZ_B ZPR8:$Zd, PPRAny:$Pg, ZPR8:$Zn, ZPR8:$Zd) |
| AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x07/m, $\xFF\x03\x06"; |
| break; |
| } |
| return false; |
| case AArch64::SEL_ZPZZ_D: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MI->getOperand(3).getReg() == MI->getOperand(0).getReg() && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SEL_ZPZZ_D ZPR64:$Zd, PPRAny:$Pg, ZPR64:$Zn, ZPR64:$Zd) |
| AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x07/m, $\xFF\x03\x10"; |
| break; |
| } |
| return false; |
| case AArch64::SEL_ZPZZ_H: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MI->getOperand(3).getReg() == MI->getOperand(0).getReg() && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SEL_ZPZZ_H ZPR16:$Zd, PPRAny:$Pg, ZPR16:$Zn, ZPR16:$Zd) |
| AsmString = "mov $\xFF\x01\x09, $\xFF\x02\x07/m, $\xFF\x03\x09"; |
| break; |
| } |
| return false; |
| case AArch64::SEL_ZPZZ_S: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MI->getOperand(3).getReg() == MI->getOperand(0).getReg() && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SEL_ZPZZ_S ZPR32:$Zd, PPRAny:$Pg, ZPR32:$Zn, ZPR32:$Zd) |
| AsmString = "mov $\xFF\x01\x0B, $\xFF\x02\x07/m, $\xFF\x03\x0B"; |
| break; |
| } |
| return false; |
| case AArch64::SMADDLrrr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR) { |
| // (SMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) |
| AsmString = "smull $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SMSUBLrrr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR) { |
| // (SMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) |
| AsmString = "smnegl $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SQDECB_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqdecb $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqdecb $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQDECB_XPiWdI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqdecb $\x01, $\xFF\x02\x34"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqdecb $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQDECD_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqdecd $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqdecd $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQDECD_XPiWdI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqdecd $\x01, $\xFF\x02\x34"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqdecd $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQDECD_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqdecd $\xFF\x01\x10"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqdecd $\xFF\x01\x10, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQDECH_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqdech $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqdech $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQDECH_XPiWdI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqdech $\x01, $\xFF\x02\x34"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqdech $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQDECH_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqdech $\xFF\x01\x09"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqdech $\xFF\x01\x09, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQDECW_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqdecw $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqdecw $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQDECW_XPiWdI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqdecw $\x01, $\xFF\x02\x34"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqdecw $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQDECW_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqdecw $\xFF\x01\x0B"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqdecw $\xFF\x01\x0B, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQINCB_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqincb $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqincb $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQINCB_XPiWdI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqincb $\x01, $\xFF\x02\x34"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqincb $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQINCD_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqincd $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqincd $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQINCD_XPiWdI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqincd $\x01, $\xFF\x02\x34"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqincd $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQINCD_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqincd $\xFF\x01\x10"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqincd $\xFF\x01\x10, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQINCH_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqinch $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqinch $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQINCH_XPiWdI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqinch $\x01, $\xFF\x02\x34"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqinch $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQINCH_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqinch $\xFF\x01\x09"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqinch $\xFF\x01\x09, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQINCW_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqincw $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqincw $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQINCW_XPiWdI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqincw $\x01, $\xFF\x02\x34"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqincw $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQINCW_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqincw $\xFF\x01\x0B"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqincw $\xFF\x01\x0B, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SST1B_D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "st1b $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::SST1B_S_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "st1b $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::SST1D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "st1d $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::SST1H_D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "st1h $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::SST1H_S_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "st1h $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::SST1W_D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "st1w $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::SST1W_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "st1w $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::ST1B_D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st1b $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST1B_H_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST1B_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st1b $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST1B_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST1B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st1b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST1B_S_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st1b $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST1D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st1d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Fourv16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x25, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Fourv1d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x26, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Fourv2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x27, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Fourv2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x28, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Fourv4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x29, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Fourv4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x2A, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Fourv8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x2B, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Fourv8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x2C, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::ST1H_D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st1h $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST1H_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST1H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st1h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST1H_S_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st1h $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Onev16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x25, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Onev1d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x26, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Onev2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x27, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Onev2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x28, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Onev4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x29, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Onev4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x2A, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Onev8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x2B, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Onev8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x2C, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Threev16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x25, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Threev1d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x26, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Threev2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x27, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Threev2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x28, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Threev4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x29, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Threev4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x2A, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Threev8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x2B, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Threev8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x2C, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Twov16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x25, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Twov1d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x26, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Twov2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x27, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Twov2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x28, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Twov4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x29, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Twov4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x2A, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Twov8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x2B, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Twov8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x2C, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST1W_D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st1w $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST1W_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st1w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST1i16_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) |
| AsmString = "st1 $\xFF\x02\x2D$\xFF\x03\x19, [$\x01], #2"; |
| break; |
| } |
| return false; |
| case AArch64::ST1i32_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) |
| AsmString = "st1 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #4"; |
| break; |
| } |
| return false; |
| case AArch64::ST1i64_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) |
| AsmString = "st1 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::ST1i8_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) |
| AsmString = "st1 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #1"; |
| break; |
| } |
| return false; |
| case AArch64::ST2B_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR2RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st2b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST2D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR2RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st2d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST2H_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR2RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st2h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST2Twov16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) |
| AsmString = "st2 $\xFF\x02\x25, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST2Twov2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) |
| AsmString = "st2 $\xFF\x02\x27, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST2Twov2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) |
| AsmString = "st2 $\xFF\x02\x28, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::ST2Twov4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) |
| AsmString = "st2 $\xFF\x02\x29, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::ST2Twov4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) |
| AsmString = "st2 $\xFF\x02\x2A, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST2Twov8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) |
| AsmString = "st2 $\xFF\x02\x2B, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::ST2Twov8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) |
| AsmString = "st2 $\xFF\x02\x2C, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST2W_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR2RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st2w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST2i16_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) |
| AsmString = "st2 $\xFF\x02\x2D$\xFF\x03\x19, [$\x01], #4"; |
| break; |
| } |
| return false; |
| case AArch64::ST2i32_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) |
| AsmString = "st2 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::ST2i64_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) |
| AsmString = "st2 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::ST2i8_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) |
| AsmString = "st2 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #2"; |
| break; |
| } |
| return false; |
| case AArch64::ST3B_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR3RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st3b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST3D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR3RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st3d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST3H_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR3RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st3h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST3Threev16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) |
| AsmString = "st3 $\xFF\x02\x25, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::ST3Threev2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) |
| AsmString = "st3 $\xFF\x02\x27, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::ST3Threev2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) |
| AsmString = "st3 $\xFF\x02\x28, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::ST3Threev4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) |
| AsmString = "st3 $\xFF\x02\x29, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::ST3Threev4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) |
| AsmString = "st3 $\xFF\x02\x2A, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::ST3Threev8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) |
| AsmString = "st3 $\xFF\x02\x2B, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::ST3Threev8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) |
| AsmString = "st3 $\xFF\x02\x2C, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::ST3W_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR3RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st3w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST3i16_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) |
| AsmString = "st3 $\xFF\x02\x2D$\xFF\x03\x19, [$\x01], #6"; |
| break; |
| } |
| return false; |
| case AArch64::ST3i32_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) |
| AsmString = "st3 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #12"; |
| break; |
| } |
| return false; |
| case AArch64::ST3i64_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) |
| AsmString = "st3 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::ST3i8_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) |
| AsmString = "st3 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #3"; |
| break; |
| } |
| return false; |
| case AArch64::ST4B_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st4b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST4D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st4d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST4Fourv16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) |
| AsmString = "st4 $\xFF\x02\x25, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::ST4Fourv2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) |
| AsmString = "st4 $\xFF\x02\x27, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::ST4Fourv2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) |
| AsmString = "st4 $\xFF\x02\x28, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST4Fourv4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) |
| AsmString = "st4 $\xFF\x02\x29, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST4Fourv4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) |
| AsmString = "st4 $\xFF\x02\x2A, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::ST4Fourv8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) |
| AsmString = "st4 $\xFF\x02\x2B, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST4Fourv8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) |
| AsmString = "st4 $\xFF\x02\x2C, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::ST4H_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st4h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST4W_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st4w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST4i16_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) |
| AsmString = "st4 $\xFF\x02\x2D$\xFF\x03\x19, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::ST4i32_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) |
| AsmString = "st4 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::ST4i64_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) |
| AsmString = "st4 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST4i8_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) |
| AsmString = "st4 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #4"; |
| break; |
| } |
| return false; |
| case AArch64::STLURBi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_4aOps]) { |
| // (STLURBi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "stlurb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STLURHi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_4aOps]) { |
| // (STLURHi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "stlurh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STLURWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_4aOps]) { |
| // (STLURWi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "stlur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STLURXi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_4aOps]) { |
| // (STLURXi GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "stlur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STNPDi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (STNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "stnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STNPQi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (STNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "stnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STNPSi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (STNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "stnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STNPWi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (STNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "stnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STNPXi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (STNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "stnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STNT1B_ZRI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (STNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "stnt1b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STNT1D_ZRI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (STNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "stnt1d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STNT1H_ZRI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (STNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "stnt1h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STNT1W_ZRI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (STNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "stnt1w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STPDi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (STPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "stp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STPQi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (STPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "stp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STPSi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (STPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "stp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STPWi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (STPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "stp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STPXi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (STPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "stp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STRBBroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (STRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "strb $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STRBBui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STRBBui GPR32z:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "strb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STRBroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (STRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "str $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STRBui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "str $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STRDroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (STRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "str $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STRDui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "str $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STRHHroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (STRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "strh $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STRHHui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STRHHui GPR32z:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "strh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STRHroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR16RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (STRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "str $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STRHui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR16RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "str $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STRQroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (STRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "str $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STRQui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "str $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STRSroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (STRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "str $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STRSui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "str $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STRWroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (STRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "str $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STRWui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STRWui GPR32z:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "str $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STRXroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (STRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "str $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STRXui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STRXui GPR64z:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "str $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STR_PXI: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (STR_PXI PPRAny:$Pt, GPR64sp:$Rn, 0) |
| AsmString = "str $\xFF\x01\x07, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STR_ZXI: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (STR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) |
| AsmString = "str $\xFF\x01\x07, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STTRBi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STTRBi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "sttrb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STTRHi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STTRHi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "sttrh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STTRWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STTRWi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "sttr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STTRXi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STTRXi GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "sttr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STURBBi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STURBBi GPR32z:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "sturb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STURBi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "stur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STURDi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "stur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STURHHi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STURHHi GPR32z:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "sturh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STURHi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR16RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "stur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STURQi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "stur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STURSi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "stur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STURWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STURWi GPR32z:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "stur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STURXi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STURXi GPR64z:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "stur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::SUBSWri: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg())) { |
| // (SUBSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) |
| AsmString = "cmp $\x02, $\xFF\x03\x01"; |
| break; |
| } |
| return false; |
| case AArch64::SUBSWrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "cmp $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) |
| AsmString = "cmp $\x02, $\x03$\xFF\x04\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::WZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0) |
| AsmString = "negs $\x01, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::WZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) |
| AsmString = "negs $\x01, $\x03$\xFF\x04\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (SUBSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "subs $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SUBSWrx: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 16) { |
| // (SUBSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) |
| AsmString = "cmp $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (SUBSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) |
| AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 16) { |
| // (SUBSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) |
| AsmString = "subs $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SUBSXri: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg())) { |
| // (SUBSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) |
| AsmString = "cmp $\x02, $\xFF\x03\x01"; |
| break; |
| } |
| return false; |
| case AArch64::SUBSXrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "cmp $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) |
| AsmString = "cmp $\x02, $\x03$\xFF\x04\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::XZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0) |
| AsmString = "negs $\x01, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::XZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) |
| AsmString = "negs $\x01, $\x03$\xFF\x04\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (SUBSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "subs $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SUBSXrx: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (SUBSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) |
| AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SUBSXrx64: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 24) { |
| // (SUBSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) |
| AsmString = "cmp $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (SUBSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) |
| AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 24) { |
| // (SUBSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) |
| AsmString = "subs $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SUBWrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::WZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0) |
| AsmString = "neg $\x01, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::WZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) |
| AsmString = "neg $\x01, $\x03$\xFF\x04\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (SUBWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "sub $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SUBWrx: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 16) { |
| // (SUBWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) |
| AsmString = "sub $\x01, $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 16) { |
| // (SUBWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) |
| AsmString = "sub $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SUBXrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::XZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0) |
| AsmString = "neg $\x01, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::XZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) |
| AsmString = "neg $\x01, $\x03$\xFF\x04\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (SUBXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "sub $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SUBXrx64: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64sponlyRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 24) { |
| // (SUBXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) |
| AsmString = "sub $\x01, $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 24) { |
| // (SUBXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) |
| AsmString = "sub $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SYSxt: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(4).getReg() == AArch64::XZR) { |
| // (SYSxt imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR) |
| AsmString = "sys $\x01, $\xFF\x02\x35, $\xFF\x03\x35, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::UBFMWri: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 31) { |
| // (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) |
| AsmString = "lsr $\x01, $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 7) { |
| // (UBFMWri GPR32:$dst, GPR32:$src, 0, 7) |
| AsmString = "uxtb $\x01, $\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 15) { |
| // (UBFMWri GPR32:$dst, GPR32:$src, 0, 15) |
| AsmString = "uxth $\x01, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64::UBFMXri: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 63) { |
| // (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) |
| AsmString = "lsr $\x01, $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 7) { |
| // (UBFMXri GPR64:$dst, GPR64:$src, 0, 7) |
| AsmString = "uxtb $\x01, $\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 15) { |
| // (UBFMXri GPR64:$dst, GPR64:$src, 0, 15) |
| AsmString = "uxth $\x01, $\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 31) { |
| // (UBFMXri GPR64:$dst, GPR64:$src, 0, 31) |
| AsmString = "uxtw $\x01, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64::UMADDLrrr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR) { |
| // (UMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) |
| AsmString = "umull $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::UMOVvi32: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (UMOVvi32 GPR32:$dst, V128:$src, VectorIndexS:$idx) |
| AsmString = "mov $\x01, $\xFF\x02\x0C.s$\xFF\x03\x19"; |
| break; |
| } |
| return false; |
| case AArch64::UMOVvi64: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (UMOVvi64 GPR64:$dst, V128:$src, VectorIndexD:$idx) |
| AsmString = "mov $\x01, $\xFF\x02\x0C.d$\xFF\x03\x19"; |
| break; |
| } |
| return false; |
| case AArch64::UMSUBLrrr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR) { |
| // (UMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) |
| AsmString = "umnegl $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::UQDECB_WPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqdecb $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqdecb $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQDECB_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqdecb $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqdecb $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQDECD_WPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqdecd $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqdecd $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQDECD_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqdecd $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqdecd $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQDECD_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqdecd $\xFF\x01\x10"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqdecd $\xFF\x01\x10, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQDECH_WPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqdech $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqdech $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQDECH_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqdech $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqdech $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQDECH_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqdech $\xFF\x01\x09"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqdech $\xFF\x01\x09, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQDECW_WPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqdecw $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqdecw $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQDECW_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqdecw $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqdecw $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQDECW_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqdecw $\xFF\x01\x0B"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqdecw $\xFF\x01\x0B, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQINCB_WPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqincb $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqincb $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQINCB_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqincb $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqincb $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQINCD_WPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqincd $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqincd $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQINCD_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqincd $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqincd $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQINCD_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqincd $\xFF\x01\x10"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqincd $\xFF\x01\x10, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQINCH_WPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqinch $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqinch $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQINCH_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqinch $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqinch $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQINCH_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqinch $\xFF\x01\x09"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqinch $\xFF\x01\x09, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQINCW_WPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqincw $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqincw $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQINCW_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqincw $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqincw $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQINCW_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqincw $\xFF\x01\x0B"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqincw $\xFF\x01\x0B, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| } |
| |
| unsigned I = 0; |
| while (AsmString[I] != ' ' && AsmString[I] != '\t' && |
| AsmString[I] != '$' && AsmString[I] != '\0') |
| ++I; |
| OS << '\t' << StringRef(AsmString, I); |
| if (AsmString[I] != '\0') { |
| if (AsmString[I] == ' ' || AsmString[I] == '\t') { |
| OS << '\t'; |
| ++I; |
| } |
| do { |
| if (AsmString[I] == '$') { |
| ++I; |
| if (AsmString[I] == (char)0xff) { |
| ++I; |
| int OpIdx = AsmString[I++] - 1; |
| int PrintMethodIdx = AsmString[I++] - 1; |
| printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, STI, OS); |
| } else |
| printOperand(MI, unsigned(AsmString[I++]) - 1, STI, OS); |
| } else { |
| OS << AsmString[I++]; |
| } |
| } while (AsmString[I] != '\0'); |
| } |
| |
| return true; |
| } |
| |
| void AArch64InstPrinter::printCustomAliasOperand( |
| const MCInst *MI, unsigned OpIdx, |
| unsigned PrintMethodIdx, |
| const MCSubtargetInfo &STI, |
| raw_ostream &OS) { |
| switch (PrintMethodIdx) { |
| default: |
| llvm_unreachable("Unknown PrintMethod kind"); |
| break; |
| case 0: |
| printAddSubImm(MI, OpIdx, STI, OS); |
| break; |
| case 1: |
| printShifter(MI, OpIdx, STI, OS); |
| break; |
| case 2: |
| printArithExtend(MI, OpIdx, STI, OS); |
| break; |
| case 3: |
| printLogicalImm<int32_t>(MI, OpIdx, STI, OS); |
| break; |
| case 4: |
| printLogicalImm<int64_t>(MI, OpIdx, STI, OS); |
| break; |
| case 5: |
| printSVERegOp<'b'>(MI, OpIdx, STI, OS); |
| break; |
| case 6: |
| printSVERegOp<>(MI, OpIdx, STI, OS); |
| break; |
| case 7: |
| printLogicalImm<int8_t>(MI, OpIdx, STI, OS); |
| break; |
| case 8: |
| printSVERegOp<'h'>(MI, OpIdx, STI, OS); |
| break; |
| case 9: |
| printLogicalImm<int16_t>(MI, OpIdx, STI, OS); |
| break; |
| case 10: |
| printSVERegOp<'s'>(MI, OpIdx, STI, OS); |
| break; |
| case 11: |
| printVRegOperand(MI, OpIdx, STI, OS); |
| break; |
| case 12: |
| printImm(MI, OpIdx, STI, OS); |
| break; |
| case 13: |
| printSVEPattern(MI, OpIdx, STI, OS); |
| break; |
| case 14: |
| printImm8OptLsl<int8_t>(MI, OpIdx, STI, OS); |
| break; |
| case 15: |
| printSVERegOp<'d'>(MI, OpIdx, STI, OS); |
| break; |
| case 16: |
| printImm8OptLsl<int64_t>(MI, OpIdx, STI, OS); |
| break; |
| case 17: |
| printImm8OptLsl<int16_t>(MI, OpIdx, STI, OS); |
| break; |
| case 18: |
| printImm8OptLsl<int32_t>(MI, OpIdx, STI, OS); |
| break; |
| case 19: |
| printInverseCondCode(MI, OpIdx, STI, OS); |
| break; |
| case 20: |
| printSVELogicalImm<int16_t>(MI, OpIdx, STI, OS); |
| break; |
| case 21: |
| printSVELogicalImm<int32_t>(MI, OpIdx, STI, OS); |
| break; |
| case 22: |
| printSVELogicalImm<int64_t>(MI, OpIdx, STI, OS); |
| break; |
| case 23: |
| printZPRasFPR<8>(MI, OpIdx, STI, OS); |
| break; |
| case 24: |
| printVectorIndex(MI, OpIdx, STI, OS); |
| break; |
| case 25: |
| printZPRasFPR<64>(MI, OpIdx, STI, OS); |
| break; |
| case 26: |
| printZPRasFPR<16>(MI, OpIdx, STI, OS); |
| break; |
| case 27: |
| printSVERegOp<'q'>(MI, OpIdx, STI, OS); |
| break; |
| case 28: |
| printZPRasFPR<128>(MI, OpIdx, STI, OS); |
| break; |
| case 29: |
| printZPRasFPR<32>(MI, OpIdx, STI, OS); |
| break; |
| case 30: |
| printFPImmOperand(MI, OpIdx, STI, OS); |
| break; |
| case 31: |
| printTypedVectorList<0,'d'>(MI, OpIdx, STI, OS); |
| break; |
| case 32: |
| printTypedVectorList<0,'s'>(MI, OpIdx, STI, OS); |
| break; |
| case 33: |
| printPSBHintOp(MI, OpIdx, STI, OS); |
| break; |
| case 34: |
| printTypedVectorList<0,'h'>(MI, OpIdx, STI, OS); |
| break; |
| case 35: |
| printTypedVectorList<0,'b'>(MI, OpIdx, STI, OS); |
| break; |
| case 36: |
| printTypedVectorList<16, 'b'>(MI, OpIdx, STI, OS); |
| break; |
| case 37: |
| printTypedVectorList<1, 'd'>(MI, OpIdx, STI, OS); |
| break; |
| case 38: |
| printTypedVectorList<2, 'd'>(MI, OpIdx, STI, OS); |
| break; |
| case 39: |
| printTypedVectorList<2, 's'>(MI, OpIdx, STI, OS); |
| break; |
| case 40: |
| printTypedVectorList<4, 'h'>(MI, OpIdx, STI, OS); |
| break; |
| case 41: |
| printTypedVectorList<4, 's'>(MI, OpIdx, STI, OS); |
| break; |
| case 42: |
| printTypedVectorList<8, 'b'>(MI, OpIdx, STI, OS); |
| break; |
| case 43: |
| printTypedVectorList<8, 'h'>(MI, OpIdx, STI, OS); |
| break; |
| case 44: |
| printTypedVectorList<0, 'h'>(MI, OpIdx, STI, OS); |
| break; |
| case 45: |
| printTypedVectorList<0, 's'>(MI, OpIdx, STI, OS); |
| break; |
| case 46: |
| printTypedVectorList<0, 'd'>(MI, OpIdx, STI, OS); |
| break; |
| case 47: |
| printTypedVectorList<0, 'b'>(MI, OpIdx, STI, OS); |
| break; |
| case 48: |
| printImmHex(MI, OpIdx, STI, OS); |
| break; |
| case 49: |
| printPrefetchOp<true>(MI, OpIdx, STI, OS); |
| break; |
| case 50: |
| printPrefetchOp(MI, OpIdx, STI, OS); |
| break; |
| case 51: |
| printGPR64as32(MI, OpIdx, STI, OS); |
| break; |
| case 52: |
| printSysCROperand(MI, OpIdx, STI, OS); |
| break; |
| } |
| } |
| |
| static bool AArch64InstPrinterValidateMCOperand(const MCOperand &MCOp, |
| const MCSubtargetInfo &STI, |
| unsigned PredicateIndex) { |
| switch (PredicateIndex) { |
| default: |
| llvm_unreachable("Unknown MCOperandPredicate kind"); |
| break; |
| case 1: { |
| |
| if (!MCOp.isImm()) |
| return false; |
| int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); |
| return AArch64_AM::isSVEMaskOfIdenticalElements<int8_t>(Val); |
| |
| } |
| case 2: { |
| |
| if (!MCOp.isImm()) |
| return false; |
| int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); |
| return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val); |
| |
| } |
| case 3: { |
| |
| if (!MCOp.isImm()) |
| return false; |
| int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); |
| return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Val); |
| |
| } |
| case 4: { |
| |
| return MCOp.isImm() && |
| MCOp.getImm() != AArch64CC::AL && |
| MCOp.getImm() != AArch64CC::NV; |
| |
| } |
| case 5: { |
| |
| if (!MCOp.isImm()) |
| return false; |
| int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); |
| return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val) && |
| AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val); |
| |
| } |
| case 6: { |
| |
| if (!MCOp.isImm()) |
| return false; |
| int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); |
| return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Val) && |
| AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val); |
| |
| } |
| case 7: { |
| |
| if (!MCOp.isImm()) |
| return false; |
| int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); |
| return AArch64_AM::isSVEMaskOfIdenticalElements<int64_t>(Val) && |
| AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val); |
| |
| } |
| case 8: { |
| |
| // Check, if operand is valid, to fix exhaustive aliasing in disassembly. |
| // "psb" is an alias to "hint" only for certain values of CRm:Op2 fields. |
| if (!MCOp.isImm()) |
| return false; |
| return AArch64PSBHint::lookupPSBByEncoding(MCOp.getImm()) != nullptr; |
| |
| } |
| } |
| } |
| |
| #endif // PRINT_ALIAS_INSTR |
