Subzero ARM: do lowerIcmp, lowerBr, and a bit of lowerCall.
Allow instructions to be predicated and use that in lower icmp
and branch. Tracking the predicate for almost every instruction
is a bit overkill, but technically possible. Add that to most of
the instruction constructors except ret and call for now.
This doesn't yet do compare + branch fusing, but it does handle
the branch fallthrough to avoid branching twice.
I can't yet test 8bit and 16bit, since those come from "trunc"
and "trunc" is not lowered yet (or load, which also isn't
handled yet).
Adds basic "call(void)" lowering, just to get the call markers
showing up in tests.
64bit.pnacl.ll no longer explodes with liveness consistency errors,
so risk running that and backfill some of the 64bit arith tests.
BUG= https://code.google.com/p/nativeclient/issues/detail?id=4076
R=stichnot@chromium.org
Review URL: https://codereview.chromium.org/1151663004
diff --git a/src/IceTargetLoweringARM32.def b/src/IceTargetLoweringARM32.def
index baeec2c..a004cb6 100644
--- a/src/IceTargetLoweringARM32.def
+++ b/src/IceTargetLoweringARM32.def
@@ -15,6 +15,19 @@
#ifndef SUBZERO_SRC_ICETARGETLOWERINGARM32_DEF
#define SUBZERO_SRC_ICETARGETLOWERINGARM32_DEF
-// TODO(jvoung): Fill out comparison tables, etc. for 32/64-bit compares.
+// Patterns for lowering icmp.
+#define ICMPARM32_TABLE \
+ /* val, is_signed, swapped64, C_32, C1_64, C2_64 */ \
+ X(Eq, false, false, EQ, EQ, NE) \
+ X(Ne, false, false, NE, NE, EQ) \
+ X(Ugt, false, false, HI, HI, LS) \
+ X(Uge, false, false, CS, CS, CC) \
+ X(Ult, false, false, CC, CC, CS) \
+ X(Ule, false, false, LS, LS, HI) \
+ X(Sgt, true, true, GT, LT, GE) \
+ X(Sge, true, false, GE, GE, LT) \
+ X(Slt, true, false, LT, LT, GE) \
+ X(Sle, true, true, LE, GE, LT) \
+//#define X(val, is_signed, swapped64, C_32, C1_64, C2_64)
#endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_DEF
