Subzero ARM: do lowerIcmp, lowerBr, and a bit of lowerCall.

Allow instructions to be predicated and use that in lower icmp
and branch. Tracking the predicate for almost every instruction
is a bit overkill, but technically possible. Add that to most of
the instruction constructors except ret and call for now.

This doesn't yet do compare + branch fusing, but it does handle
the branch fallthrough to avoid branching twice.

I can't yet test 8bit and 16bit, since those come from "trunc"
and "trunc" is not lowered yet (or load, which also isn't
handled yet).

Adds basic "call(void)" lowering, just to get the call markers
showing up in tests.

64bit.pnacl.ll no longer explodes with liveness consistency errors,
so risk running that and backfill some of the 64bit arith tests.

BUG= https://code.google.com/p/nativeclient/issues/detail?id=4076
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/1151663004

src/IceInstARM32.def

diff --git a/src/IceInstARM32.def b/src/IceInstARM32.def
index c314305..d381e1b 100644
--- a/src/IceInstARM32.def
+++ b/src/IceInstARM32.def
@@ -91,4 +91,27 @@
   X(RRX, "rrx")                                                         \
 //#define X(tag, emit)
 
+// Attributes for the condition code 4-bit encoding (that is independent
+// of the APSR's NZCV fields). For example, EQ is 0, but corresponds to
+// Z = 1, and NE is 1, but corresponds to Z = 0.
+#define ICEINSTARM32COND_TABLE                                          \
+  /* enum value, encoding, opposite, emit */                            \
+  X(EQ, 0, NE, "eq") /* equal */                                        \
+  X(NE, 1, EQ, "ne") /* not equal */                                    \
+  X(CS, 2, CC, "cs") /* carry set/unsigned (AKA hs: higher or same) */  \
+  X(CC, 3, CS, "cc") /* carry clear/unsigned (AKA lo: lower) */         \
+  X(MI, 4, PL, "mi") /* minus/negative */                               \
+  X(PL, 5, MI, "pl") /* plus/positive or zero */                        \
+  X(VS, 6, VC, "vs") /* overflow (float unordered) */                   \
+  X(VC, 7, VS, "vc") /* no overflow (float not unordered) */            \
+  X(HI, 8, LS, "hi") /* unsigned higher */                              \
+  X(LS, 9, HI, "ls") /* unsigned lower or same */                       \
+  X(GE, 10, LT, "ge") /* signed greater than or equal */                \
+  X(LT, 11, GE, "lt") /* signed less than */                            \
+  X(GT, 12, LE, "gt") /* signed greater than */                         \
+  X(LE, 13, GT, "le") /* signed less than or equal */                   \
+  X(AL, 14, kNone, "") /* always (unconditional) */                     \
+  X(kNone, 15, kNone, "??") /* special condition / none */              \
+//#define(tag, encode, opp, emit)
+
 #endif // SUBZERO_SRC_ICEINSTARM32_DEF