Subzero: Make -reg-use and -reg-exclude specific to register class.
The main feature here is that when listing a register via the -reg-use or -reg-exclude option, we can limit the effect to a single register class, instead of applying it across all register classes. Example:
pnacl-sz -reg-use i32:eax,i32:ecx,i32:edx -reg-exclude f32:xmm0
Note that without the register class prefix, behavior is the same as before, specifically that the restriction applies to all register classes.
This requires a few high-level changes:
1. We need a mechanism to name *all* register classes, not just the standard ones that map to IceType values.
2. While we're at it, give standard types a more usable name, e.g. "v4i32" instead of "<4 x i32>".
3. Since we've commandeered ":" as the class/register token separator, we change ARM i64 register pair names from e.g. "r0:r1" to "r0r1".
The motivation is that for register allocator torture testing, we'd like to drastically restrict the registers available to e.g. the extensively-used i32 register class, while not overly restricting the seldom-used i32to8 register class (which reflects the set of i32 registers that may trivially truncate to i8).
BUG= none
R=kschimpf@google.com
Review URL: https://codereview.chromium.org/1614273002 .
diff --git a/src/IceTypes.def b/src/IceTypes.def
index 0d4ec86..a1a2552 100644
--- a/src/IceTypes.def
+++ b/src/IceTypes.def
@@ -26,7 +26,7 @@
#define TARGETARCH_TABLE \
/* enum value, printable string, is_elf64, e_machine, e_flags */ \
X(Target_X8632, "x86-32", false, EM_386, 0) \
- X(Target_X8664, "x86-64", true, EM_X86_64, 0) \
+ X(Target_X8664, "x86-64", true, EM_X86_64, 0) \
X(Target_ARM32, "arm32", false, EM_ARM, EF_ARM_EABI_VER5) \
X(Target_ARM64, "arm64", true, EM_AARCH64, 0) \
X(Target_MIPS32,"mips32", false, EM_MIPS, 0) \
@@ -34,23 +34,24 @@
#define ICETYPE_TABLE \
/* enum value, log_2(size), align, # elts, element type, */ \
- /* printable string (size and alignment in bytes) */ \
- X(void, -1, 0, 1, void, "void") \
- X(i1, 0, 1, 1, i1, "i1") \
- X(i8, 0, 1, 1, i8, "i8") \
- X(i16, 1, 1, 1, i16, "i16") \
- X(i32, 2, 1, 1, i32, "i32") \
- X(i64, 3, 1, 1, i64, "i64") \
- X(f32, 2, 4, 1, f32, "float") \
- X(f64, 3, 8, 1, f64, "double") \
- X(v4i1, 4, 1, 4, i1, "<4 x i1>") \
- X(v8i1, 4, 1, 8, i1, "<8 x i1>") \
- X(v16i1, 4, 1, 16, i1, "<16 x i1>") \
- X(v16i8, 4, 1, 16, i8, "<16 x i8>") \
- X(v8i16, 4, 2, 8, i16, "<8 x i16>") \
- X(v4i32, 4, 4, 4, i32, "<4 x i32>") \
- X(v4f32, 4, 4, 4, f32, "<4 x float>") \
-//#define X(tag, sizeLog2, align, elts, elty, str)
+ /* printable string (size and alignment in bytes), */ \
+ /* register class string */ \
+ X(void, -1, 0, 1, void, "void", "void") \
+ X(i1, 0, 1, 1, i1, "i1", "i1") \
+ X(i8, 0, 1, 1, i8, "i8", "i8") \
+ X(i16, 1, 1, 1, i16, "i16", "i16") \
+ X(i32, 2, 1, 1, i32, "i32", "i32") \
+ X(i64, 3, 1, 1, i64, "i64", "i64") \
+ X(f32, 2, 4, 1, f32, "float", "f32") \
+ X(f64, 3, 8, 1, f64, "double", "f64") \
+ X(v4i1, 4, 1, 4, i1, "<4 x i1>", "v4i1") \
+ X(v8i1, 4, 1, 8, i1, "<8 x i1>", "v8ii") \
+ X(v16i1, 4, 1, 16, i1, "<16 x i1>", "v16i1") \
+ X(v16i8, 4, 1, 16, i8, "<16 x i8>", "v16i8") \
+ X(v8i16, 4, 2, 8, i16, "<8 x i16>", "v8i16") \
+ X(v4i32, 4, 4, 4, i32, "<4 x i32>", "v4i32") \
+ X(v4f32, 4, 4, 4, f32, "<4 x float>", "v4f32") \
+//#define X(tag, sizeLog2, align, elts, elty, str, rcstr)
// Dictionary:
// V - Is vector type.
